Low power event driven pixel with passive differential detection circuitry and reset control circuit therefor

Abstract

A low-power event-driven pixel (and reset control circuit therefor) with a passive differential detection circuit is disclosed herein. In one embodiment, the event-driven pixel includes a photosensor, a photocurrent / voltage converter, and a differential circuit. The differential circuit includes a source follower transistor and a switched capacitor filter, the switched capacitor filter having an input coupled to the photocurrent / voltage converter and an output coupled to the gate of the source follower transistor. The switched capacitor filter includes: a first capacitor coupled between the input and output of the switched capacitor filter; a second capacitor having a first plate coupled to the output of the switched capacitor filter; and a reset transistor coupled between a reference voltage and the output of the switched capacitor filter. The differential circuit is configured to generate a differential signal indicating whether the event-driven pixel has detected an event in an external scene.

Description

Technical Field

[0001] The present invention relates generally to image sensors. For example, several embodiments of the present technology relate to event-driven pixels, including low-power event-driven pixels with passive differential detection circuitry and reset control circuits therefor. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. In integrating image sensors into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and the like (e.g., resolution, power consumption, dynamic range, etc.) of the image sensors in as many ways as possible, both through device architecture design as well as image acquisition processing.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges upon absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and the image light is read out from the column bit line as an analog image signal and converted into a digital value to provide information representing the external scene. Summary of the invention

[0004] An embodiment of the present invention provides an event-driven pixel, which includes: a light sensor configured to generate a photocurrent in response to incident light received from an external scene; a photocurrent / voltage converter coupled to the light sensor to convert the photocurrent into a first voltage; and a differential circuit coupled to the photocurrent / voltage converter in an AC manner, wherein the differential circuit includes a source follower transistor and a switched capacitor filter, the switched capacitor filter having an input coupled to the photocurrent / voltage converter and an output coupled to the gate of the source follower transistor, wherein the switched capacitor filter includes: (a) a first capacitor coupled between the input of the switched capacitor filter and the gate of the photocurrent / voltage converter; between the output of the switched capacitor filter, (b) a second capacitor having a first plate coupled to the output of the switched capacitor filter, and (c) a reset transistor coupled between a reference voltage and the output of the switched capacitor filter, and wherein the differential circuit is configured to sample a reference light level based at least in part on the reference voltage and the first voltage at a first time, and is configured to generate a differential signal based at least in part on a second voltage at the gate of the source follower transistor, wherein the second voltage is based at least in part on the reference light level and the first voltage at a second time, and wherein the differential signal indicates whether the event-driven pixel has detected an event in the external scene.

[0005] Another embodiment of the present invention provides a method for operating an event-driven pixel, the method comprising: utilizing a light sensor to generate a photocurrent in response to receiving incident light from an external scene; converting the photocurrent into a first voltage; generating a differential signal, wherein generating the differential signal comprises: using a capacitive voltage divider of a differential circuit of the event-driven pixel and sampling a reference light level based at least in part on the first voltage at a first time, and using the capacitive voltage divider to generate a second voltage at a gate of a source follower transistor of the differential circuit, wherein the second voltage is based at least in part on (i) the first voltage at a second time and (ii) the reference light level, wherein the differential signal is at least in part based on the second voltage, and wherein the magnitude of the differential signal indicates whether the event-driven pixel has detected an event in the external scene; and outputting the differential signal onto a column line in response to assertion of a row select signal.

[0006] Yet another embodiment of the present invention provides an imaging system, comprising: an event-driven pixel, comprising: a photodetector configured to generate a photocurrent in response to incident light received from an external scene, a photocurrent / voltage converter coupled to the photodetector to convert the photocurrent into a voltage, and a differential circuit coupled to the photocurrent / voltage converter and configured to generate a differential signal based at least in part on the voltage, wherein the differential circuit comprises: a capacitive voltage divider having: (a) a first capacitor coupled to an output of the photocurrent / voltage converter, and (b) a second capacitor coupled to the first capacitor opposite to the output of the photocurrent / voltage converter; a source follower transistor having a gate coupled to a node located between the first capacitor and the second capacitor; a reset transistor a transistor coupled between a reference voltage and the node and having a gate configured to receive a reset signal; and a row select transistor coupled between the source follower transistor and a column line and configured to output the differential signal onto the column line in response to assertion of a row select signal; a threshold comparison circuit coupled to the differential circuit via the column line, wherein the threshold comparison circuit is configured to compare the differential signal with one or more thresholds; and a control circuit coupled to the threshold comparison circuit and to the event-driven pixel, wherein the control circuit is configured to, when the differential signal exceeds a threshold value among the one or more threshold values, (i) register that the event-driven pixel has detected an event in the external scene, and (ii) initiate a reset of the differential circuit so that the node is set to the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present technology are described below with reference to the following figures, throughout which like or similar reference symbols are used to refer to like or similar components unless otherwise specified.

[0008] Figure 1 and 2 is a partially schematic block diagram of imaging systems including event-driven pixels, each configured in accordance with various embodiments of the present technology.

[0009] Figure 3 and 4 is a partial schematic diagram of a reset control circuit configured in accordance with various embodiments of the present technology.

[0010] Figure 5 is a timing diagram illustrating a method of operating an event-driven pixel according to various embodiments of the present technology.

[0011] Figure 6 is a partial schematic diagram of another event-driven pixel configured according to various embodiments of the present technology.

[0012] Fig. 7A is a partial schematic diagram of a MOS varactor circuit configured in accordance with various embodiments of the present technology.

[0013] Figure 7B is a diagram illustrating the operation of various embodiments of the present technology Fig. 7A Timing diagram of the MOS varactor circuit method.

[0014] Figure 8 is available in Fig. 7A Partial schematic of a three-terminal device used in a MOS varactor circuit.

[0015] Figures 9 to 12 is a partial schematic diagram of a photocurrent / voltage converter coupled to a photosensor, each configured in accordance with various embodiments of the present technology.

[0016] A skilled artisan will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding various aspects of the present technology, the dimensions of some of the elements in the various figures may be exaggerated relative to other elements. In addition, common and well-understood elements or methods that are useful or necessary in commercially feasible embodiments are generally not depicted in the figures or generally not described in detail below to avoid unnecessarily obscuring the description of various aspects of the present technology. DETAILED DESCRIPTION

[0017] The present invention relates to event-driven sensors. For example, several embodiments of the present technology are directed to event-driven pixels, including low-power event-driven pixels with passive differential detection circuitry, and / or to event-driven pixels with reset control circuitry. In the following description, specific details are set forth to provide a thorough understanding of various aspects of the present technology. However, those skilled in the relevant art will recognize that the systems, devices, and techniques described herein may be practiced without one or more of the specific details set forth herein, or may be practiced using other methods, components, materials, etc.

[0018] References throughout this specification to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example or embodiment is included in at least one example or embodiment of the present technology. Therefore, the phrases "for example," "as an example," or "an embodiment" used herein do not necessarily all refer to the same example or embodiment, and are not necessarily limited to the particular example or embodiment discussed. In addition, the features, structures, or characteristics of the present technology described herein may be combined in any suitable manner to provide further examples or embodiments of the present technology.

[0019] Spatially relative terms (e.g., "below," "below," "above," "below," "above," "upper," "top," "bottom," "left," "right," "middle," "middle," and the like) may be used herein for ease of description to describe the relationship of one element or feature relative to one or more other elements or features as illustrated in the various figures. It should be understood that the spatially relative terms are intended to cover different orientations of the device or system when in use or operation in addition to the orientation depicted in the figures. For example, if the device or system illustrated in the figures is rotated, turned, or flipped about a horizontal axis, then the element or feature described as being "below" or "below" or "below" one or more other elements or features may be oriented "above" the one or more other elements or features at that time. Therefore, the exemplary terms "below" and "below" are non-limiting and may cover both above and below orientations. The device or system may be oriented in other ways than those illustrated in the figures (e.g., rotated 90 degrees about a vertical axis, or in other orientations) in addition or alternatively, and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when an element is referred to as being “between” two other elements, it can be the only element between the two other elements, or one or more intervening elements may also be present.

[0020] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they belong, unless otherwise specifically defined herein or the context of their use would clearly imply otherwise. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0021] A. Overview

[0022] Active pixel sensors typically employ a pixel array with a globally defined integration time. Thus, pixels in an array of an active pixel sensor typically have the same integration time, and each pixel in the array is typically converted into a digital signal regardless of its content (e.g., whether or not changes have occurred in the external scene captured by the pixel since the last time the pixel was read out).

[0023] In contrast, an event-driven sensor (e.g., an event vision sensor or a dynamic vision sensor) reads out a pixel and / or converts the corresponding pixel signal into a digital signal only when the pixel captures a change (e.g., an event) in an external scene. In other words, pixels of the event-driven sensor that do not detect a change in the external scene are not read out, and / or the pixel signals corresponding to such pixels are not converted into digital signals. Therefore, each pixel of the event-driven sensor can be independent of other pixels of the event-driven sensor, and only the pixels that detect a change in the external scene need to be read out, and / or have their corresponding pixel signals converted into digital signals and / or recorded (thereby saving power).

[0024] Many event-driven pixels include local amplifiers and comparators for event threshold detection. The amplifier and comparator circuits of each event-driven pixel typically require a DC bias current of the order of nanoamperes, which can result in a power consumption of several milliwatts in a megapixel event-driven sensor, regardless of whether any events occur in the external scene. In other words, the current power consumption of many event-driven pixels makes such event-driven pixels unsuitable for use with battery-powered, always-on event-driven sensors, where a power consumption of less than milliwatts of the event-driven sensor is desirable (e.g., to achieve extended battery life).

[0025] Some event-driven pixels (a) measure the voltage generated based on the photocurrent output from the photosensor without amplification in the output stage, and (b) include a common-source gm stage to compensate for the lack of signal amplification in the output stage. The use of a common-source gm stage is expected to result in excessive non-uniformity, increased nonlinearity, challenges in properly setting the operating point for all event-driven pixels of the event-driven sensor, and / or challenges in calibrating the event-driven pixels. In addition, since signal amplification occurs only after the output stage, the noise performance of event-driven pixels using a common-source gm stage is expected to be inferior to that of the event-driven sensors described above.

[0026] To address these concerns, several event-driven pixels of the present technology each include: (a) a photosensor configured to generate a photocurrent in response to incident light received from an external scene; (b) a photocurrent / voltage converter coupled to the photosensor to convert the photocurrent into a voltage; and (c) a passive differential circuit coupled to the photocurrent / voltage converter and configured to generate a differential signal or an analog signal level (e.g., a differential voltage relative to a reset time) based at least in part on the voltage. The use of a passive differential circuit can reduce power consumption of event-driven pixels. In some embodiments, the passive differential circuit of the present technology can be AC-coupled. In these and other embodiments, the differential circuit can include a source follower buffer or transistor. In particular, compared to event-driven pixels that employ a common-source amplifier to reintroduce gain, it is expected that the inclusion of a source follower buffer in the differential circuit will (a) produce improved uniformity and / or linearity, and / or (b) improve the dynamic response of the event-driven pixel. In these and other embodiments, event-driven pixels of the present techniques may include event threshold detection on column levels to (a) reduce static power consumption of event-driven pixels and / or (b) implement frame-based readout of event-driven pixels.

[0027] In these and other embodiments, the photocurrent / voltage converter of the present technology may include an amplifier. The amplifier of the photocurrent / voltage converter may be employed to increase the response speed to changes in the voltage output from the photocurrent / voltage converter. In other words, the amplifier may be employed in low latency applications to increase the speed at which the differential circuit of the event-driven pixel generates an analog signal level based on the voltage output from the photocurrent / voltage converter. In some embodiments, the amplifier of the photocurrent / voltage converter may be configured to receive an enable signal that is used to selectively enable (or disable) the amplifier in order to save power. For example, the amplifier of the photocurrent / voltage converter may be powered off when the event-driven pixel does not output an analog signal level (e.g., when a frame is not being read out), thereby reducing the power consumption of the event-driven pixel.

[0028] In these and further embodiments, the event-driven pixel of the present technology includes a reset control circuit. The reset control circuit can be configured to (a) initialize the event-driven pixel in response to assertion of a global reset signal, and / or (b) reset the event-driven pixel when an analog signal level is read out from the event-driven pixel (e.g., in response to assertion of a row select signal) and the analog signal level indicates that an event has occurred within an external scene (e.g., resulting in assertion of a confirmation signal). In some embodiments, the event-driven pixel of the present technology can utilize capacitor matching between several capacitors of the differential circuit to reduce, minimize, or eliminate gain errors of the differential circuit. Therefore, it is expected that the event-driven pixel of the present technology is suitable for use with battery-powered always-on event-driven sensors while avoiding several of the challenges discussed above and observed in many event-driven pixels.

[0029] B. Selected implementations of low power event driven pixels, reset control circuits, and associated systems, devices, and methods example

[0030] Figure 1 1 is a partial schematic block diagram of an imaging system 100 configured in accordance with various embodiments of the present technology. As shown, the imaging system 100 includes an event-driven pixel 120 and a threshold comparison circuit 108. In other embodiments of the present technology, the threshold comparison circuit 108 may be incorporated into the event-driven pixel 120.

[0031] Figure 1 The event-driven pixel 120 includes a light sensor 102, a photocurrent / voltage converter 104, a differential circuit 106, and a reset control circuit 110. The light sensor 102 Figure 1 1 is illustrated as a photodiode having an anode coupled to ground (eg, a negative power supply rail or another reference voltage) and a cathode coupled to the photocurrent / voltage converter 104. In operation, Figure 1 The light sensor 102 is configured to photogenerate a charge or photocurrent in response to incident light 114 received from an external scene. In other embodiments of the present technology, the light sensor 102 may be another suitable type of light sensor or photodetector (e.g., a metal semiconductor metal (MSM) photodetector, a phototransistor, a photoconductive detector, or a phototube).

[0032] Figure 1A photocurrent / voltage converter 104 is coupled to the photosensor 102 and is configured to convert a photocurrent generated by the photosensor 102 into a voltage. A differential circuit 106 is coupled to the photocurrent / voltage converter 104. Based on the voltage received from the photocurrent / voltage converter 104, the differential circuit 106 is configured to (a) sample a reference signal or voltage when the event-driven pixel 120 is reset, and (b) generate a differential signal or voltage (e.g., an analog signal level) relative to the reference signal (e.g., relative to the last time the event-driven pixel 120 was reset). When the row select signal rsel(m) is asserted, the differential circuit 106 may output the differential signal onto a bit line or column line 107. More specifically, the differential circuit 106 may output the differential signal to a threshold comparison circuit 108 via the column line 107.

[0033] In some embodiments, the photocurrent / voltage converter 104 may be configured to receive an enable signal EN. Fig.11 and 12 Discussed in more detail, enable signal EN may be used to selectively enable (e.g., power on, such as turning on, enabling current flow, or forcing into a higher power mode or state) or disable (e.g., power off, such as cutting off, disabling current flow, or forcing into a lower power mode or state) one or more amplifiers of photocurrent / voltage converter 104. Disabling the amplifiers is expected to reduce power consumption of event-driven pixels 120, thereby reducing power consumption of imaging system 100 and / or an image sensor (not shown) incorporating imaging system 100.

[0034] The reset control circuit 110 controls the reset of the event-driven pixel 120. More specifically, the reset control circuit 110 receives a global reset signal GRST, a row selection signal rsel(m), and an acknowledgement signal col_ack(n). Figures 2 to 6 Discussed in more detail, based on the assertion of the global reset signal GRST, the row select signal rsel(m) and / or the acknowledgement signal col_ack(n), the reset control circuit is configured to (a) generate a reset signal RST and (b) initiate sampling of a new reference signal in the differential circuit 106 in response to the assertion of the reset signal RST.

[0035] Threshold comparison circuit 108 is coupled to the output of difference circuit 106. In the illustrated embodiment, threshold comparison circuit 108 is a circuit peripheral to event-driven pixel 120 and is coupled to event-driven pixel 120 via column line 107. Placing threshold comparison circuit 108 on column line 107 so that threshold comparison circuit 108 is shared among event-driven pixel 120 and other event-driven pixels (not shown) coupled to column line 107 is expected to reduce static power consumption compared to event-driven pixels incorporating dedicated threshold comparison circuits.

[0036] In operation, the threshold comparison circuit 108 is configured to detect events occurring within the external scene. More specifically, when an event occurs in the external scene, the event is indicated as a rapid or sudden change in intensity or brightness in the incident light 114 received by the light sensor 102. In other words, if the external scene is static so that no events occur, the brightness of the incident light 114 remains substantially unchanged. As such, the photocurrent generated by the light sensor 102 remains substantially constant. However, if an event (e.g., movement) occurs within the external scene, the event is indicated as an asynchronous rapid or sudden change in the brightness of the incident light 114 received by the light sensor 102. The brightness change may be from darker to brighter or from brighter to darker. Therefore, there may be an asynchronous change in the photocurrent generated by the light sensor 102, which in turn may cause the differential signal generated by the differential circuit 106 to change. Thus, the threshold comparison circuit 108 may be configured to receive the differential signal from the differential circuit 106, compare the differential signal to one or more thresholds or quantities, and detect an event occurring in the external scene based on the comparison. For example, when the magnitude of the differential signal output by the differential circuit 106 exceeds the magnitude of the threshold, the threshold comparison circuit 108 may detect that an event has occurred in the external scene.

[0037] When the threshold comparison circuit 108 detects an event, the confirmation signal col_ack(n) may be asserted to prompt the reset control circuit 110 to (a) assert the reset signal RST to reset the event-driven pixel 120, and (b) start sampling a new reference voltage in the differential circuit 106. Additionally or alternatively, the threshold comparison circuit 108 may output event information (e.g., the location where the event was detected, such as the xy coordinates of the photosensor 102 in the pixel array used to detect the event; the polarity of the photocurrent change for the event (e.g., brighter or darker); and / or the time when the event occurred) for recording. On the other hand, when the threshold comparison circuit 108 does not detect an event, the confirmation signal col_ack(n) may remain unasserted so that (without the assertion of the global reset signal GRST) the event-driven pixel 120 is not reset by the reset control circuit 110, and the differential circuit 106 continues to generate a differential signal based on the previously sampled reference voltage.

[0038] It should be noted that the Figure 1The image sensor of the imaging system 100 does not need to record the entire conventional image, and therefore does not have the burden of having to capture all the highly redundant information of a normal image frame by frame. Alternatively, the image sensor may record only event information. In other words, outside of the threshold comparison performed by the threshold comparison circuit 108, the image sensor may ignore the frame portion of the image or video in which no event is detected, thereby achieving ultra-high frame rate and / or ultra-high speed capabilities at low data rates. In some embodiments, events may be read out synchronously or asynchronously. In these and other embodiments, event data from event-driven pixels 120 may be combined with normal image or video capture via software, an artificial intelligence (AI) network, or other suitable technology to reconstruct a high frame rate, high quality image or video using event detection.

[0039] Figure 2 FIG. 2 is a partial schematic diagram of an imaging system 200 configured in accordance with various embodiments of the present technology. The imaging system 200 may be Figure 1 As shown, the imaging system 200 includes a control circuit 215, an event-driven pixel 220, and a threshold comparison circuit 208.

[0040] Event-driven pixel 220 includes light sensor 202, photocurrent / voltage converter 204, differential circuit 206, and reset control circuit 210. Light sensor 202 includes an anode coupled to ground (e.g., a negative power supply rail or another reference voltage) and a cathode. Photocurrent / voltage converter 204 of event-driven pixel 220 is coupled to the cathode of light sensor 202 and is configured to convert the photocurrent generated by light sensor 202 into a voltage V A In some embodiments, the voltage V A is logarithmically related to the intensity of incident light received by light sensor 202 from the external scene. Figures 9 to 12 Several exemplary configurations of the photocurrent-to-voltage converter 204 are discussed in greater detail.

[0041] The differential circuit 206 of the event-driven pixel 220 is coupled to the output of the photocurrent / voltage converter 204. In the illustrated embodiment, the differential circuit 206 includes a first capacitor 222 having a capacitance C1, a second capacitor 223 having a capacitance C2, a reset transistor 225, a source follower buffer or transistor 226, and a row select transistor 227. The first capacitor 222, the second capacitor 223, the reset transistor 225, and the source follower transistor 226 are coupled to each other via a node D. More specifically, the first capacitor 222 is coupled between the output of the photocurrent / voltage converter 204 and the node D; the second capacitor 223 is coupled between ground (e.g., a negative power supply rail or another reference voltage) and the node D; the gate of the source follower transistor 226 is coupled to the node D; and the source of the reset transistor 225 is coupled to the node D. The drain of source follower transistor 226 is coupled to a supply voltage (e.g., a positive power supply rail or another reference voltage), and the source of source follower transistor 226 is coupled to the drain of row select transistor 227. In some embodiments, source follower transistor 226 is a linear source follower buffer. The source of row select transistor 227 is coupled to column line col(n), and the gate of row select transistor 227 is configured to receive a row select signal rsel(m) controlled by control circuitry 215 of imaging system 200.

[0042] Differential circuit 206 is coupled to photocurrent / voltage converter 204 in an AC manner. In operation, first capacitor 222 and second capacitor 223 of differential circuit 206 collectively function as a high pass filter configured to filter out lower frequency components from the output of light sensor 202 and / or photocurrent / voltage converter 204. Thus, event-driven pixel 220 may ignore slow or gradual changes in the photocurrent generated by light sensor 202 in response to incident light from an external scene, and may instead detect rapid or sudden changes occurring in the photocurrent generated by light sensor 202 in response to incident light. Based at least in part on voltage V A , the differential circuit 206 can generate a signal or voltage V at the node D B , the signal or voltage is applied to the gate of the source follower transistor 226, so that the source follower transistor 226 outputs a corresponding differential signal (eg, analog signal level) to the row select transistor 227. In other words, based at least in part on the voltage V at the node D B, when the row select signal rsel(m) applied to the gate of the row select transistor 227 is asserted by the control circuit 215, the source follower transistor 226 and the row select transistor 227 can output the differential signal to the column line col(n). In addition, since the first capacitor 222 and the second capacitor 223 are passive components, the differential circuit 206 consumes a small amount of power compared to differential circuits using active circuit components, making the differential circuit 206 suitable for use in low-power, battery-powered and / or always-on event-driven sensors. Therefore, the differential circuit 206 can be regarded as a low-power passive differential detection circuit.

[0043] The differential signal output from the event-driven pixel 220 onto the column line col(n) is fed into the threshold comparison circuit 208. As shown, the threshold comparison circuit 208 includes a first comparator 231 and a second comparator 232, each having an input coupled to the column line col(n) via a node O. The first comparator 231 is configured to compare the differential signal output by the event-driven pixel 220 with a first threshold, and the second comparator 232 is configured to compare the differential signal with a second threshold. In some embodiments, the first comparator 231 may be triggered when the brightness or intensity of the light incident on the light sensor 202 of the event-driven pixel 220 changes in one direction (e.g., from darker to brighter). When triggered, the first comparator 231 may assert a signal UP that may indicate that an event has occurred in the external scene. In these and other embodiments, the second comparator 232 may be triggered when the brightness or intensity of the light incident on the light sensor 202 changes in another direction (e.g., from brighter to darker). When triggered, the second comparator 232 may assert a signal DOWN which may indicate that an event has occurred in the external scenario. The signals UP and DOWN are passed to the control circuit 215, and the control circuit 215 may assert an acknowledgement signal col_ack(n) when the signal UP or the signal DOWN indicates that an event has occurred in the external scenario (e.g., when the signal UP or the signal DOWN is asserted).

[0044] Reference again Figure 2 The event drives the pixel 220, and the reset transistor 225 of the differential circuit 206 is arranged as a reset switch. More specifically, the reset transistor 225 is arranged as a switch of a switched capacitor filter formed by the first capacitor 222 and the second capacitor 223. As shown, the reset transistor 225 includes (a) a voltage coupled to a reference voltage V REF The differential circuit 206 may be configured to have a drain (e.g., a positive power supply rail or another reference voltage) and (b) a gate configured to receive a reset signal RST from the reset control circuit 210. As discussed in more detail below, the differential circuit 206 may be reset or initialized when the reset control circuit 210 asserts the reset signal RST.

[0045] like Figure 2 , the reset control circuit 210 includes a first input (input a) configured to receive a row select signal rsel(m), a second input (input b) configured to receive an acknowledgement signal col_ack(n), and a third input (input c) configured to receive a global reset signal GRST. The reset control circuit 210 further includes an output (output y) configured to apply the reset signal RST to the gate of the reset transistor 225 of the differential circuit 206. The assertion of the reset signal RST may depend at least in part on the states of the row select signal rsel(m), the acknowledgement signal col_ack(n), and the global reset signal GRST received from the control circuit 215 and input into the reset control circuit 210. For example, as discussed in more detail below, the control circuit 215 may assert the row select signal rsel(m) to read out the differential signal from the differential circuit 206, and may assert the acknowledgement signal col_ack(n) based on the differential signal when the threshold comparison circuit 208 detects that an event has occurred in an external scenario. Continuing with this example, the reset control circuit 210 may assert the reset signal RST when the row select signal rsel(m) and the acknowledge signal col_ack(n) are simultaneously asserted. As another example, the control circuit 215 may assert the global reset signal GRST to reset or initialize the event-driven pixel 220, and the reset control circuit 210 may assert the reset signal RST in response to the assertion of the global reset signal GRST.

[0046] Figure 3 and 4 The various embodiments of the present invention can be implemented as Figure 2 First, refer to the partial schematic diagram of the reset control circuit 210 of the reset control circuit 310 and the reset control circuit 410. Figure 3 , the reset control circuit 310 includes an AND logic gate 341, an OR logic gate 342, and a delay element 343. The AND logic gate 341 includes a first input configured to receive the row selection signal rsel(m) via a first input (input a) of the reset control circuit 310, and a second input configured to receive the confirmation signal col_ack(n) via a second input (input b) of the reset control circuit 310. The OR logic gate 342 includes a first input coupled to the output of the AND logic gate 341, a second input configured to receive the global reset signal GRST via a third input (input c) of the reset control circuit 310, and an output (output x) coupled to the input of the delay element 343. The delay element 343 includes an output coupled to the output (output y) of the reset control circuit 310.

[0047] In operation, the reset control circuit 310 is configured to assert the reset signal RST when (a) the global reset signal GRST is asserted or (b) the row select signal rsel(m) and the acknowledge signal col_ack(n) are both asserted. In other words, the reset control circuit 310 is configured to assert the reset signal RST whenever (a) the global reset signal GRST is asserted or (b) the differential signal is Figure 2 The event drives the differential circuit 206 of the pixel 220 to read out and the differential signal indicates that an event has occurred in the external scene, and RST is asserted. Otherwise, the reset control circuit 310 outputs the reset signal RST in an unasserted state. As discussed in more detail below, after the falling edge of the output (output x) of the "OR" logic gate 342, the delay element 343 is configured to keep the reset signal RST in an asserted state within a refractory period. In other embodiments, the reset control circuit 310 may lack or omit the delay element (for example, so that the output (output x) of the "OR" logic gate 342 is connected (for example, directly) to the output (output y) of the reset control circuit 310, and / or so that the reset signal RST is de-asserted immediately after the falling edge of the output (output x) of the "OR" logic gate 342 without a refractory period).

[0048] Reference now Figure 4 , the reset control circuit 410 includes a plurality of transistors (in Figure 4 458) and capacitor 459. The first transistor 451 to the fourth transistor 454 are arranged as a "NAND" logic gate. More specifically, the source of the first transistor 451 is coupled to ground (e.g., a negative power supply rail or another reference voltage), the drain of the first transistor 451 is coupled to the source of the second transistor 452, and the gate of the first transistor 451 is configured to receive the confirmation signal col_ack(n) via the second input (input b) of the reset control circuit 410. The drain of the second transistor 452 is coupled to the drain of the third transistor 453 and to the drain of the fourth transistor 454, and the gate of the second transistor 452 is configured to receive the row select signal rsel(m) via the first input (input a) of the reset control circuit 410. The source of the third transistor 453 is coupled to a supply voltage (e.g., a positive power supply rail or another reference voltage), the drain of the third transistor 453 is coupled to the drain of the fourth transistor 454, and the gate of the third transistor 453 is configured to receive the row select signal rsel(m) via the first input (input a) of the reset control circuit 410. The source of the fourth transistor 454 is coupled to the supply voltage, and the gate of the fourth transistor 454 is configured to receive the acknowledgement signal col_ack(n) via the second input (input b) of the reset control circuit 410.

[0049] The seventh transistor 457 of the reset control circuit 410 is arranged as a low-state active switch charging capacitor 459. In particular, the source of the seventh transistor 457 is coupled to the supply voltage, the gate of the seventh transistor 457 is coupled to the output of the "NAND" logic gate (e.g., coupled to the drain of the second transistor 452, coupled to the drain of the third transistor 453, and coupled to the drain of the fourth transistor 454), and the drain of the seventh transistor 457 is coupled to the capacitor 459 and to the output (output y) of the reset control circuit 410. The capacitor 459 is coupled between (a) ground and (b) the drain of the seventh transistor 457 and the output (output y) of the reset control circuit 410.

[0050] The fifth transistor 455 and the sixth transistor 456 of the reset control circuit 410 are arranged as pass transistors. More specifically, (a) the source of the fifth transistor 455 is coupled to the drain of the third transistor 453 and to the drain of the fourth transistor 454; (b) the drain of the fifth transistor 455 is coupled to the drain of the second transistor 452 and to the gate of the seventh transistor 457; (c) the source of the sixth transistor 456 is coupled to ground; and (d) the drain of the sixth transistor 456 is coupled to the drain of the second transistor 452, to the drain of the fifth transistor 455, and to the gate of the seventh transistor 457. The gate of the fifth transistor 455 and the gate of the sixth transistor 456 are each configured to receive a global reset signal via a third input (input c) of the reset control circuit 410.

[0051] The eighth transistor 458 is arranged as a resistive element configured to discharge the capacitor 459 when the low-state active switch is released (e.g., when the seventh transistor 457 is turned off). More specifically, the source of the eighth transistor 458 is coupled to ground; the drain of the eighth transistor 458 is coupled to the drain of the seventh transistor 457, to the capacitor 459, and to the output (output y) of the reset control circuit 410; and the gate of the eighth transistor 458 is configured to receive a programmable or trimmable bias voltage. As discussed in more detail below, the eighth transistor 458 is configured to keep the reset signal RST asserted within the hysteresis period when the seventh transistor 457 changes from on to off.

[0052] In operation, the reset control circuit 410 functions similarly to the reset control circuit 310. Specifically, when both the row selection signal rsel(m) and the confirmation signal col_ack(n) are asserted, the seventh transistor 457 is turned on via the output of the NAND logic gate (formed by the first transistor 451 to the fourth transistor 454), the capacitor 459 is charged, and the reset signal RST output from the reset control circuit 410 is asserted. In addition, when the global reset signal GRST is asserted, the seventh transistor 457 is turned on via the sixth transistor 456 acting as a pass transistor, the capacitor 459 is charged, and the reset signal RST output from the reset control circuit 410 is asserted. At all other times, the seventh transistor 457 is turned off, the capacitor 459 is discharged or remains uncharged, and the reset signal RST output from the reset control circuit 410 is not asserted.

[0053] When (a) the global reset signal is de-asserted after being asserted or (b) the row select signal rsel(m) or the confirmation signal col_ack(n) is de-asserted after both the row select signal rsel(m) and the confirmation signal col_ack(n) are jointly asserted, the capacitor 459 of the reset control circuit 410 is discharged via the eighth transistor 458. The rate at which the capacitor 459 is discharged via the eighth transistor 458 (a) depends on the programmable bias voltage applied to the gate of the eighth transistor 458 and (b) is negatively related to the length of the delay period during which the reset signal RST remains asserted after the eighth transistor 458 begins to discharge the capacitor 459. For example, a higher bias voltage can be used to discharge the capacitor 459 faster via the eighth transistor 458, and thus for a shorter delay period. Continuing with this example, a lower bias voltage can be used to discharge the capacitor 459 slower via the eighth transistor 458, and thus for a longer delay period.

[0054] It should be understood that in other embodiments of the present invention, Figure 2 The reset control circuit 210 may have Figure 2 , 3 4, and the other schematic configuration can selectively reset the event-driven pixel 220 based on the row selection signal rsel(m), the confirmation signal col_ack(n), and / or the global reset signal GRST. For example, as discussed above, in some embodiments of the present technology, the event-driven pixel 220 can be omitted. Figure 3 The delay element 343 of the reset control circuit 310 is configured so that there is no delay period after the global reset signal GRST, the confirmation signal col_ack(n) and / or the row selection signal rsel(m) are de-asserted. As another example, in some embodiments, Figure 4The reset control circuit 410 may lack a delay period after the global reset signal GRST, the confirmation signal col_ack(n) and / or the row selection signal rsel(m) are de-asserted. As a specific example, the capacitor 459 and / or the eighth transistor 458 of the reset control circuit 410 may be omitted, and / or the bias voltage applied to the gate of the eighth transistor 458 may be set so that the capacitor 459 is discharged quickly (e.g., immediately). It should be further understood that in other embodiments, the differential circuit 206, the event-driven pixel 220, the threshold comparison circuit 208 and / or the control circuit 215 may have the same Figure 2 In fact, the following description of the schematic configurations shown in FIG. Figure 6 Discuss in detail the Figure 2 Examples of alternative illustrative configurations for use in addition to or instead of the present techniques of the differential circuit 206 and / or event-driven pixel 220.

[0055] Figure 5 is a diagram illustrating the operation of various embodiments of the present technology Figure 2 A timing diagram 560 of the imaging system 200 and the method of event-driven pixel 220 is provided. Figure 2 and 5 For the sake of clarity and understanding, it is assumed that the photocurrent generated by the light sensor 202 is linear (e.g. Figure 5 ). It is also assumed that the photocurrent / voltage converter 204 converts the photocurrent generated by the light sensor 202 into a logarithmically increasing voltage V A (like Figure 5 In other embodiments, the voltage V generated by the photocurrent / voltage converter 204 is A may be another function (eg, linear, square root, etc.) of the photocurrent generated by photosensor 202 .

[0056] exist Figure 5 At time t0 shown in FIG. 1 , the control circuit 215 of the imaging system 200 implements a global reset by asserting the global reset signal GRST to initialize the event-driven pixel 220. When the global reset signal GRST is asserted, the reset control circuit 210 of the event-driven pixel 220 asserts the reset signal RST applied to the gate of the reset transistor 225. Then, the reset transistor 225 is turned on, and the voltage V at the node D is B Reaching the reference voltage V REF , and the voltage on the first capacitor 222 reaches a voltage V equal to the voltage output from the photocurrent / voltage converter 204 A With reference voltage V REF The difference between (for example, V A -V REF) voltage.

[0057] At time t1, control circuit 215 deasserts global reset signal GRST. In response, reset control circuit 210 deasserts reset signal RST, thereby turning off reset transistor 225. From time t1 to time t2, voltage V at node D B The voltage V output from the photocurrent / voltage converter 204 A proportional to the change in time t1 (e.g., V A (t)-V A The voltage V B The voltage V appears at node D as having a relative gain or attenuation depending on the capacitance C1 of the first capacitor 222 and the capacitance C2 of the second capacitor 223. For example, due to the capacitive voltage divider formed at least in part by the first capacitor 222 and the second capacitor 223, the voltage V B It appears at node D to have a relative gain or attenuation given by capacitance C1 divided by the sum of capacitance C1 and capacitance C2 (eg, C1 / (C1 + C2)).

[0058] At time t2, control circuit 215 asserts row select signal rsel(m) (e.g., as part of rolling readout of pixels in imaging system 200 to locate a pixel of imaging system 200 that has detected an event), thereby activating row select transistor 227. In turn, row select transistor 227 is activated in accordance with voltage V applied to the gate of source follower transistor 226 at time t2. B The corresponding differential signal (e.g., analog signal level) is output to the column line col(n) via the row select transistor 227. The differential signal appears at the node O between time t2 and time t3 and is fed to the first comparator 231 and the second comparator 232 of the threshold comparison circuit 208. The first comparator 231 compares the differential signal with the first threshold voltage V th-up The second comparator 232 compares the differential signal with the second threshold voltage V th-down In some embodiments, column readout of the differential signal may involve a programmable gain amplifier and / or an analog-to-digital converter.

[0059] like Figure 5 As shown in FIG. 1 , the differential signal output to the column line col(n) and appearing at the node O between time t2 and time t3 does not exceed the first threshold voltage V th-up Or the second threshold voltage V th-down. Therefore, the differential signal output between time t2 and time t3 will not trigger the first comparator 231 or the second comparator 232. As such, both the signal UP and the signal DOWN remain unasserted during this time period. Therefore, the control circuit 215 does not register an event based on the differential signal output at time t2, and the confirmation signal col_ack(n) remains unasserted. Since the confirmation signal col_ack(n) remains unasserted, the reset control circuit 210 of the event-driven pixel 220 does not reset the differential circuit 206 (for example, in the absence of an intervening assertion of the global reset signal GRST). Therefore, the voltage V at the node D B The voltage V output from the photocurrent / voltage converter 204 is A proportional to the change in time t1 (e.g., V A (t)-V A At time t3, the control circuit 215 de-asserts the row select signal rsel(m).

[0060] At time t4, control circuit 215 asserts row select signal rsel(m) (e.g., as part of rolling readout of the pixels of imaging system 200 to locate a pixel of imaging system 200 that has detected an event). Row select transistor 227 is then activated and coupled to voltage V applied to the gate of source follower transistor 226 at time t4. B The corresponding differential signal (e.g., analog signal level) is output onto the column line col(n) via the row select transistor 227 and appears at the node O between time t4 and time t5. The differential signal is fed into the first comparator 231 and the second comparator 232 of the threshold comparison circuit 208. As discussed above, column readout of the differential signal may involve a programmable gain amplifier and / or an analog-to-digital converter. Figure 5 As shown in FIG. 1 , the differential signal exceeds the first threshold voltage V th-up and does not exceed the second threshold voltage V th-down Therefore, the differential signal triggers the first comparator 231 and does not trigger the second comparator 232. As such, the first comparator 231 asserts the signal UP, while the signal DOWN output from the second comparator 232 remains unasserted.

[0061] At time t5, in response to the assertion of the signal UP, the control circuit 215 registers the event and asserts the acknowledgement signal col_ack(n). Since both the acknowledgement signal col_ack(n) and the row selection signal rsel(m) are asserted between time t5 and time t6, the reset control circuit 210 implements a partial reset of the event-driven pixel 220 by asserting the reset signal RST between time t5 and time t6. Subsequently, the asserted reset signal RST is applied to the gate of the reset transistor 225, and the differential circuit 206 of the event-driven pixel 220 is reset. More specifically, the voltage V at the node D of the differential circuit 206 is B Reset to reference voltage V REF , and the new signal (V A (t6)-V REF ) is sampled onto the first capacitor 222. The other pixels of row "m" that output differential signals indicating the occurrence of the event will also be reset at this time. At time t6, the control circuit 215 de-asserts the row selection signal rsel(m) and the confirmation signal col_ack(n). In response, the reset control circuit 210 de-asserts the reset signal RST.

[0062] like Figure 5 As shown in FIG. 1 , the photocurrent output by the light sensor 202 and the voltage V output by the photocurrent / voltage converter 204 are A decreases between time t6 and time t7. Since the voltage V at the node D B The voltage V output from the photocurrent / voltage converter 204 A is proportional to the change in time t6 (e.g., relative to the last time the differential circuit 206 was reset, or relative to V A (t)-V A (t6) changes in proportion to the change in the voltage V at the node D. B It also decreases between time t6 and time t7.

[0063] At time t7, control circuit 215 asserts row select signal rsel(m) (e.g., as part of rolling readout of the pixels of imaging system 200 to locate a pixel of imaging system 200 that has detected an event). Row select transistor 227 is then activated and coupled to voltage V applied to the gate of source follower transistor 226 at time t7. B The corresponding differential signal (e.g., analog signal level) is output onto the column line col(n) via the row select transistor 227 and appears at the node O between time t7 and time t8. The differential signal is fed into the first comparator 231 and the second comparator 232 of the threshold comparison circuit 208. As discussed above, column readout of the differential signal may involve a programmable gain amplifier and / or an analog-to-digital converter. Figure 5As shown in FIG. 1 , the differential signal exceeds the second threshold voltage V th-down and does not exceed the first threshold voltage V th-up Therefore, the differential signal triggers the second comparator 232 and does not trigger the first comparator 231. As such, the second comparator 232 asserts the signal DOWN, while the signal UP output from the first comparator 231 remains unasserted.

[0064] At time t8, in response to the assertion of the signal DOWN, the control circuit 215 registers the event and asserts the acknowledgement signal col_ack(n). Since both the acknowledgement signal col_ack(n) and the row selection signal rsel(m) are asserted between time t8 and time t9, the reset control circuit 210 implements a partial reset of the event-driven pixel 220 by asserting the reset signal RST between time t8 and time t9. Subsequently, the asserted reset signal RST is applied to the gate of the reset transistor 225, and the differential circuit 206 of the event-driven pixel 220 is reset. More specifically, the voltage V at the node D of the differential circuit 206 is B Reset to reference voltage V REF , and the new signal (V A (t9)-V REF ) is sampled onto the first capacitor 222. The other pixels of row "m" that output differential signals indicating the occurrence of the event will also be reset at this time. At time t9, the control circuit 215 de-asserts the row selection signal rsel(m) and the confirmation signal col_ack(n). Subsequently, the reset control circuit 210 de-asserts the reset signal RST.

[0065] therefore, Figure 2 The event-driven pixel 220 of the imaging system 200 of the embodiment of the present invention operates in a similar manner to the in-pixel AC-coupled correlated double sampling (CDS) pixels commonly found in global shutter sensors. However, in contrast to such pixels, the reset level is not used as a reference in the event-driven pixel 220 or in the imaging system 200. Instead, the light level corresponding to the last time the event-driven pixel 220 was reset is used as a reference. In addition, in contrast to such in-pixel AC-coupled CDS pixels, Figure 2 The reset of the event-driven pixel 220 is conditional based on (a) a global reset of the imaging system 200 and (b) the event-driven pixel 220 outputting a differential signal indicating that an event has occurred in the external scene (e.g., exceeding a first threshold voltage). Vth-up Or the second threshold voltage V th-down differential signal).

[0066] Figure 6 FIG. 6 is a partial schematic diagram of another event-driven pixel 620 configured in accordance with various embodiments of the present technology. As shown, the event-driven pixel 620 is similar to Figure 2For example, the event-driven pixel 620 includes (a) a light sensor 602, (b) a photocurrent / voltage converter 604, and (c) a differential circuit 606, the differential circuit having a first capacitor 622, a second capacitor 623, a reset transistor 625, a source follower transistor 626, and a row select transistor 627. Figure 6 Not shown, but event-driven pixel 620 may further include similar Figure 2 The reset control circuit 210 of the event-driven pixel 620 has an output coupled to the gate of the reset transistor 625. The light sensor 602, the photocurrent / voltage converter 604, the differential circuit 606 and the reset control circuit of the event-driven pixel 620 can be respectively connected to Figure 2 The light sensor 202, the photocurrent / voltage converter 204, the differential circuit 206, and the reset control circuit 210 of the event-driven pixel 620 operate similarly. Therefore, for the sake of brevity, a detailed discussion of these components of the event-driven pixel 620 is omitted here. The first reference voltage V REF1 Illustration of Figure 6 Medium and can be Figure 2 The reference voltage V illustrated in FIG. REF Or another reference voltage of the present invention.

[0067] and Figure 2 Compared with the event-driven pixel 220, Figure 6 The differential circuit 606 of the event-driven pixel 620 further includes a passive MOS varactor 670 (eg, a varactor). The varactor 670 includes a first transistor 671 and a second transistor 672. The first transistor 671 (a) is electrically coupled to a second reference voltage V REF2 and the second capacitor 623, and (b) includes a gate configured to receive the sample and hold signal S&H. The second transistor 672 (a) is electrically coupled to a third reference voltage V REF3 and the second capacitor 623, and (b) includes a gate configured to receive the signal Boost. As described in more detail below, the varactor diode 670 can be employed in the event-driven pixel 620 to provide signal amplification and reduce noise.

[0068] Now refer to Fig. 7A and 7B The characteristics of the varactor diode 670 are explained. Fig. 7A is a partially simplified schematic diagram of a MOS varactor circuit 780 configured in accordance with various embodiments of the present technology, and Figure 7B It is a graphic explanation of the operation Fig. 7A MOS varactor circuit 780 may generally correspond to Figure 6620. For example, Fig. 7A The MOS varactor circuit 780 may generally correspond to the reset transistor 625, the second capacitor 623, the first transistor 671, and the second transistor 672 of the event-driven pixel 620. Therefore, for the sake of clarity and understanding, Fig. 7A and 7B Use with Figure 6 Similar reference numerals and signals to those used in FIG.

[0069] As shown, the MOS varactor circuit 780 includes a switch 725 controlled by a reset signal RST, a switch 771 controlled by a sample and hold signal S&H, a switch 772 controlled by a signal Boost, and a MOS capacitor 723 having a drain terminal and a source terminal coupled to each other. The switch 725 selectively couples the gate of the MOS capacitor 723 to a reference voltage V REF1 Similarly, switch 771 selectively couples the source and drain terminals of MOS capacitor 723 to a reference voltage V REF2 , and switch 772 selectively couples the source and drain terminals of MOS capacitor 723 to a reference voltage V REF3 The switch 771 and the switch 772 may form at least a portion of the varactor diode 770 .

[0070] Common Reference Fig. 7A and 7B , when (i) the reset signal RST and the sample and hold signal S&H are both asserted and (ii) the signal Boost remains unasserted, the MOS varactor circuit 780 operates in a first operation phase (e.g., tracking or inversion phase) and a signal is sampled onto the MOS capacitor 723. More specifically, the drain and source terminals of the MOS capacitor 723 are biased to the reference voltage V via the switch 771. REF2 Assume (a) the reference voltage V REF2 is a low reference potential (e.g., ground, a negative power supply rail, or a reference voltage lower than V REF1 and (b) a reference voltage V REF1 is large enough to form a channel by pulling charge from the drain and source terminals of MOS capacitor 723 to cause channel inversion because the junction capacitance is at the reference voltage V REF2 , so the capacitance of MOS capacitor 723 can be defined by the gate oxide capacitance.

[0071] On the other hand, when (i) the signal Boost is asserted and (ii) the reset signal RST and the sample and hold signal S&H are not asserted, the MOS varactor circuit 780 operates in the second operation phase (e.g., amplification or accumulation phase) and the voltage at the node G increases. More specifically, the drain and source terminals of the MOS capacitor 723 are biased to the reference voltage V REF3 Assuming the reference voltage V REF3 is a high reference potential (for example, V DD , positive power supply rail or above the reference voltage V REF1 and / or V REF2 ), the channel inversion charge will be removed. In addition, although the charge at the gate (node ​​G) of MOS capacitor 723 will not change when MOS varactor circuit 780 transitions to the second operation stage, the capacitance seen by the gate (node ​​G) of MOS capacitor 723 is the series connection of the gate capacitance and the diffusion capacitance in the bulk of the semiconductor biased to ground or another low voltage. Because the series connection of these capacitances is less than the individual contribution of the gate oxide capacitance and because the charge at the gate (node ​​G) of MOS capacitor 723 remains unchanged, the voltage at node G increases to a potential given by equations 1 and 2 below:

[0072]

[0073]

[0074] The above discussion of MOS varactor circuit 780 neglects the fringing capacitance at the junction of the source and drain terminals of MOS capacitor 723, which should be kept to a minimum. Figure 8 The three-terminal device 881 illustrated in FIG. 8 may be used in some embodiments of the present technology to reduce, minimize, or eliminate fringing capacitance at the junction of the source and drain terminals.

[0075] Reference again Figure 6 , in view of the above Figures 7A to 8 When the reference signal is sampled onto the first capacitor 622, the reset signal RST applied to the gate of the reset transistor 625 and the sample and hold signal S&H applied to the gate of the first transistor 671 of the varactor 670 may be asserted together, while the signal Boost applied to the gate of the second transistor 672 of the varactor 670 may remain unasserted, so that the voltage V B is sampled onto the second capacitor 623, which is equal to the reference voltage V REF1 With reference voltage V REF2 The difference between (for example, V REF1 -V REF2 As discussed above, the reference voltage VREF2 It can be a low reference potential (e.g., ground, a negative power supply rail, or a reference voltage lower than V REF1 Then, the reset signal RST may be deasserted, thereby forming a passive voltage divider across the first capacitor 622 and the second capacitor 223, as described above with reference to Figure 2 and 5 The voltage V at the node D B Therefore, it proportionally tracks the voltage V output by the photocurrent / voltage converter 604. A , and appears at node D as having a relative gain or attenuation given by the capacitance C1 of the first capacitor 622 divided by the sum of the capacitance C1 and the capacitance C2 of the second capacitor 623 (e.g., C1 / (C1+C2)). During rolling readout of an imaging system including event-driven pixels 620, the sample and hold signal S&H may be deasserted and (in the absence of overlap) the signal Boost may be asserted to connect the bottom plate of the second capacitor 623 to the reference potential V via the second transistor 672. REF3 (For example, V DD , positive power supply rail or above the reference voltage V REF1 and / or V REF2 623). This will remove the inverted charge in the channel formed on the second capacitor 623, which will reduce the capacitance C2 of the second capacitor 623 seen by the gate of the source follower transistor 626. In turn, the gain of the passive differential circuit 606 (e.g., provided by capacitance C1 divided by the sum of capacitance C1 and capacitance C2 (e.g., C1 / (C1+C2)) is closer to 1. In this way, the event-driven pixel 620 can employ the varactor 670 to provide passive signal amplification and noise reduction by cycling the varactor 670 through inversion and accumulation phases.

[0076] Figures 9 to 12 1 and 12 are partial schematic diagrams of photocurrent / voltage converters 904, 1004, 1104, and 1204 configured according to various embodiments of the present technology. Photocurrent / voltage converters 904, 1004, 1104, and 1204 may each be configured in a Figure 2 The event driving pixel 220 is used to convert the photocurrent into a voltage and is therefore illustrated as being coupled to Figure 2 Each of the photocurrent / voltage converters 904, 1004, 1104, and 1204 can be used in other event-driven pixels of the present invention technology, including Figure 6 The event of drives pixel 620. Therefore, each of photocurrent / voltage converters 904, 1004, 1104, and 1204 can be coupled to light sensor 602 or another light sensor of the present technology.

[0077] First reference Fig. 9 , photocurrent / voltage converter 904 includes a transistor 991 having (a) a source coupled to the cathode of photosensor 202 and (b) a drain coupled to a supply voltage (e.g., a positive power supply rail or another reference voltage). The gate of transistor 991 is coupled to a bias voltage. In operation, photocurrent / voltage converter 904 is configured to convert a photocurrent output by photosensor 202 into a voltage V A , which voltage can be fed to a differential circuit (e.g., Figure 2 The differential circuit 206, Figure 6 More specifically, the photocurrent / voltage converter 904 is configured to generate a voltage V having a logarithmic or other (e.g., linear, square root, etc.) relationship to the intensity of incident light received by the light sensor 202 from the external scene. A .

[0078] Reference now Fig.10 , the photocurrent / voltage converter 1004 includes a transistor 1091 having (a) a drain coupled to a supply voltage (e.g., a positive power supply rail or another reference voltage) and (b) a gate coupled to a bias voltage. The photocurrent / voltage converter 1004 further includes a plurality of transistors 1092 stacked in series with each other (in Fig.10 1092a through nth transistor 1092n). The first transistor 1092a of the plurality of transistors includes a source coupled to a cathode of the light sensor 202, and the nth transistor 1092n of the plurality of transistors includes a drain coupled to the source of the transistor 1091 and to an output of the photocurrent / voltage converter 1004, at which the photocurrent / voltage converter 1004 generates a voltage V A .

[0079] As shown, each of the first transistor 1092a to the nth transistor 1092n includes a gate configured to receive a corresponding bias voltage. The bias voltages applied to the gates of the first transistor 1092a to the nth transistor 1092n may be the same, or at least some of the bias voltages may be different from each other. The bias voltages applied to the gates of the first transistor 1092a to the nth transistor 1092n may cause the first transistor 1092a to the nth transistor 1092n to operate in weak inversion, so that the first transistor 1092a to the nth transistor 1092n provide signal amplification. In other words, the first transistor 1092a to the nth transistor 1092n may be employed to amplify the voltage V generated at the output (node ​​A) of the photocurrent / voltage converter 1004. A .

[0080] Reference now Fig.11 , the photocurrent / voltage converter 1104 includes a transistor 1191 having (a) a source coupled to the cathode of the photosensor 202 and (b) a drain coupled to a supply voltage (e.g., a positive power supply rail or another reference voltage). The photocurrent / voltage converter 1104 further includes an amplifier 1193 having (a) an input (e.g., an inverting input) coupled to the cathode of the photosensor 202 and to the source of the transistor 1191, and (b) a voltage V coupled to (i) the photocurrent / voltage converter 1104 at which the photocurrent / voltage converter 1104 generates a voltage V A and coupled to (ii) the output of the gate of transistor 1191. In some embodiments, amplifier 1193 may be an operational amplifier and / or may include another input (not shown), such as a non-inverting input, coupled to ground (e.g., a negative power supply rail or another reference voltage).

[0081] Amplifier 1193 may be used to increase the voltage V generated at the output of photocurrent / voltage converter 1104 between the source and gate of transistor 1191. A In other words, amplifier 1193 can be used in low latency applications to improve the response speed of differential circuits (e.g., Figure 2 The differential circuit 206, Figure 6 The differential circuit 606 of the present invention or another differential circuit of the present invention) is based on the voltage V at the node D B ( Figure 2 and 6 ) generates a differential signal.

[0082] like Fig.11 As shown in FIG. 1 , amplifier 1193 may be configured to receive an enable signal EN . Enable signal EN Can be used to selectively enable or disable amplifier 1193. For example, the enable signal EN The amplifier 1193 may be selectively disabled or placed in a power-down mode when the corresponding event-driven pixel does not sample the reference signal or output the differential signal (thereby reducing the power consumption of the corresponding event-driven pixel), and may be selectively enabled or placed in a power-up mode when the corresponding event-driven pixel samples the reference signal or is expected to output the differential signal on the column line col(n) (e.g., when the row select signal rsel(m) is asserted). In some embodiments, the amplifier 1193 may require time to stabilize. In these embodiments, the enable signal EN may be asserted a given time before the differential signal is read out from the corresponding event-driven pixel onto the column line col(n).

[0083] Reference now Fig.12 , the photocurrent / voltage converter 1204 represents Fig.10 The photocurrent / voltage converter 1004 and Fig.11 More specifically, the photocurrent / voltage converter 1204 includes a transistor 1291, a plurality of transistors 1292 (in Fig.12 1292a to nth transistor 1292n), and an amplifier 1293. A plurality of transistors 1292 are stacked in series with one another. A first transistor 1292a of the plurality of transistors includes a source coupled to a cathode of the light sensor 202 and to an input (e.g., an inverting input) of the amplifier 1293. An nth transistor 1292n of the plurality of transistors includes a drain coupled to a source of the transistor 1291. The amplifier 1293 includes a photocurrent / voltage converter 1204 coupled to (i) a photocurrent / voltage converter 1204 at which the photocurrent / voltage converter 1204 generates a voltage V A 1291 includes a drain coupled to a supply voltage (e.g., a positive power supply rail or another reference voltage).

[0084] Similar to Fig.10 The first transistor 1092a to the nth transistor 1092n of the photocurrent / voltage converter 1004, Fig.12 Each of the first transistor 1292a to the nth transistor 1292n includes a gate configured to receive a corresponding bias voltage. The bias voltages applied to the gates of the first transistor 1292a to the nth transistor 1292n may be the same, or at least some of the bias voltages may be different from each other. The bias voltages applied to the gates of the first transistor 1292a to the nth transistor 1292n may cause the first transistor 1292a to the nth transistor 1292n to operate in weak inversion, so that the first transistor 1292a to the nth transistor 1292n provide signal amplification, as discussed above.

[0085] Similar to Fig.11 The amplifier 1193 of the photocurrent / voltage converter 1104, the amplifier 1293 can be used to increase the voltage V generated at the output of the photocurrent / voltage converter 1204 between the source and gate of the transistor 1191. A In other words, amplifier 1293 can be used in low latency applications to improve the response speed of a differential circuit corresponding to an event-driven pixel (e.g., Figure 2 The differential circuit 206, Figure 6 The differential circuit 606 of the present invention or another differential circuit of the present invention) is based on the voltage V at the node D B ( Figure 2 ) generates a differential signal. Additionally or alternatively, Fig.11 Consistent with the discussion of amplifier 1193 of photocurrent / voltage converter 1104, amplifier 1293 may be configured to receive enable signal EN , the enable signal is used to selectively enable or disable the amplifier 1293 (eg, to reduce the power consumption of the photocurrent / voltage converter 1204 and thus the power consumption of the corresponding event-driven pixel).

[0086] C. in conclusion

[0087] The above detailed description of the embodiments of the present technology is not intended to be exhaustive or to limit the present technology to the precise form disclosed above. Although specific embodiments and examples of the present technology are described above for illustrative purposes, various equivalent modifications may be made within the scope of the present technology as will be appreciated by those skilled in the relevant art. For example, although the steps are presented above in a given order, alternative embodiments may perform the steps in a different order. In addition, the various embodiments described herein may also be combined to provide further embodiments.

[0088] From the foregoing, it will be understood that the specific embodiments of the present technology have been described herein for the purpose of illustration, but the well-known structures and functions are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is explicitly limited to a single item that only means to exclude other items when referring to a list of two or more items, the use of "or" in this list should be interpreted as including any single item in the (a) list, all items in the (b) list, or any combination of items in the (c) list. In addition, as used herein, the phrase "and / or" as in "A and / or B" refers to only A, only B, and both A and B. In addition, throughout the text, the terms "comprise", "include", "have" and "with" are used to mean at least including the described features, so that any larger number of the same features and / or other features of additional types are not excluded. Furthermore, as used herein, the phrases "based on," "depend on," "as a result of," and "in response to" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on" or the phrase "based at least partially on." Also, the terms "connected" and "coupled" are used interchangeably herein and refer to both direct and indirect connections or couplings. For example, where the context permits, element A being "connected" or "coupled" to element B may refer to (i) A being directly "connected" or "coupled" to B and / or (ii) A being indirectly "connected" or "coupled" to B.

[0089] From the foregoing, it will also be understood that various modifications can be made without departing from the present invention or the present technology. For example, it will be understood by those of ordinary skill in the art that the various components of the present technology can be further divided into sub-component components, or the various components and functions of the present technology can be combined and integrated. In addition, the specific aspects of the present technology described in the context of the specific embodiment can also be combined or eliminated in other embodiments. In addition, although the advantages associated with those embodiments have been described in the context of the specific embodiments of the present technology, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages to be within the scope of the present technology. Therefore, the present invention and associated technologies may encompass other embodiments that are not explicitly shown or described herein.

Claims

1. An event-driven pixel, comprising: a light sensor configured to generate a photocurrent in response to incident light received from an external scene; a photocurrent / voltage converter coupled to the photosensor to convert the photocurrent into a first voltage; and a differential circuit, which is AC-coupled to the photocurrent / voltage converter, wherein the differential circuit comprises a source follower transistor and a switched capacitor filter having an input coupled to the photocurrent-to-voltage converter and an output coupled to the gate of the source follower transistor, wherein the switched capacitor filter comprises: (a) a first capacitor coupled between the input and the output of the switched capacitor filter, (b) a second capacitor having a first plate coupled to the output of the switched capacitor filter, and (c) a reset transistor coupled between a reference voltage and the output of the switched capacitor filter, and wherein the differential circuit is configured to sample a reference light level based at least in part on the reference voltage and the first voltage at a first time, and is configured to generate a differential signal based at least in part on a second voltage at the gate of the source follower transistor, wherein the second voltage is based at least in part on the reference light level and the first voltage at a second time, and wherein the differential signal indicates whether the event-driven pixel has detected an event in the external scene.

2. The event-driven pixel of claim 1, wherein a second plate of the second capacitor is coupled to ground.

3. The event-driven pixel of claim 1, further comprising a varactor diode coupled to a second plate of the second capacitor.

4. The event-driven pixel of claim 3, wherein the varactor comprises: a first transistor having a gate configured to receive a sample and hold signal, wherein the first transistor is coupled between (i) a second reference voltage and (ii) the second plate of the second capacitor; and A second transistor has a gate configured to receive a boosted signal, wherein the second transistor is coupled between (i) a third reference voltage and (ii) the second plate of the second capacitor.

5. The event-driven pixel of claim 1 , wherein: The reset transistor includes a gate configured to receive a reset signal; and The differential circuit is configured to sample the reference light level in response to assertion of the reset signal applied to the gate of the reset transistor.

6. The event-driven pixel of claim 5, further comprising a reset control circuit having an output coupled to the gate of the reset transistor, wherein the reset control circuit is configured to: initializing the differential circuit in response to assertion of a global reset signal applied to the reset control circuit; and The differential circuit is reset in response to a combination of: (a) assertion of a row select signal applied to the reset control circuit, and (b) assertion of a confirmation signal applied to the reset control circuit when the differential signal indicates that the event-driven pixel has detected the event in the external scene.

7. The event-driven pixel of claim 6, wherein the reset control circuit comprises: an AND logic gate having a first input configured to receive the row select signal and a second input configured to receive the confirmation signal; and an OR logic gate having a first input coupled to the output of the AND logic gate, a second input configured to receive the global reset signal, and an output coupled to the output of the reset control circuit.

8. The event-driven pixel of claim 6, wherein the reset control circuit comprises: a NAND logic gate having a first input configured to receive the row select signal and a second input configured to receive the confirmation signal; at least one pass transistor coupled to an output of the NAND logic gate and configured to receive the global reset signal; and an active-low switch configured to couple a supply voltage to an output of the reset control circuit based at least in part on the output of the NAND logic gate, the output of the at least one pass transistor, or a combination thereof.

9. The event-driven pixel of claim 1 , wherein: The differential circuit further includes a row select transistor coupled between the source follower transistor and a column line and configured to receive a row select signal at a gate of the row select transistor; and The event-driven pixel is configured to output the differential signal in response to assertion of the row select signal.

10. The event-driven pixel of claim 1, wherein: The photocurrent / voltage converter includes a first transistor having a drain coupled to a supply voltage, a source coupled to the photosensor, and a gate coupled to a first bias potential; and The photocurrent / voltage converter generates the first voltage between the source of the first transistor and the photosensor.

11. The event-driven pixel of claim 10, wherein: The photocurrent / voltage converter further comprises a plurality of second transistors, the plurality of second transistors being arranged in series between the light sensor and the source of the first transistor; Each of the second transistors has a gate coupled to a corresponding bias potential; and The photocurrent / voltage converter generates the first voltage between the source of the first transistor and ends of the series connection of the plurality of second transistors opposite to the photosensor.

12. The event-driven pixel of claim 1, wherein: The photocurrent / voltage converter comprises: a first transistor having a source coupled to the light sensor and a drain coupled to a supply voltage, and an amplifier having an input coupled to the photosensor and to the source of the first transistor, and an output coupled to the gate of the first transistor; and The photocurrent-to-voltage converter generates the first voltage at the output of the amplifier.

13. The event-driven pixel of claim 12, wherein the amplifier is configured to receive an enable signal to selectively enable the amplifier.

14. The event-driven pixel of claim 12, wherein: The photocurrent / voltage converter further includes a plurality of second transistors arranged in series between (a) the light sensor and the input of the amplifier and (b) the source of the first transistor; and Each of the second transistors has a gate coupled to a corresponding bias potential.

15. A method for operating an event-driven pixel, the method comprising: utilizing a light sensor to photogenerate a photocurrent in response to receiving incident light from an external scene; converting the photocurrent into a first voltage; Generating a differential signal, wherein generating the differential signal comprises: sampling a reference light level based at least in part on the first voltage at a first time using a capacitive voltage divider of a differential circuit of the event-driven pixel, and generating a second voltage at a gate of a source follower transistor of the differential circuit using the capacitive voltage divider, wherein the second voltage is based at least in part on (i) the first voltage at a second time and (ii) the reference light level, wherein the differential signal is based at least in part on the second voltage, and wherein a magnitude of the differential signal indicates whether the event-driven pixel has detected an event in the external scene; and The differential signal is output onto the column lines in response to assertion of a row select signal.

16. The method of claim 15, wherein sampling the reference light level comprises asserting a reset signal applied to the differential circuit such that the voltage at the gate of the source follower transistor is set to a reference voltage.

17. The method of claim 16, wherein asserting the reset signal comprises asserting the reset signal in response to assertion of a global reset signal applied to the event-driven pixel to initialize the event-driven pixel.

18. The method of claim 16, wherein asserting the reset signal comprises asserting the reset signal in response to a combination of the assertion of the row select signal and the assertion of a confirm signal applied to the event-driven pixel, and wherein the assertion of the confirm signal is dependent on the magnitude of the differential signal exceeding a threshold.

19. The method of claim 15, wherein: the capacitive voltage divider comprises a capacitor coupled between the gate of the source follower transistor and a varactor of the event-driven pixel; and Sampling the reference light level includes biasing a bottom plate of the capacitor to a low reference potential based at least in part on assertion of a sample and hold signal S&H applied to the varactor.

20. The method of claim 15, wherein: The capacitive voltage divider includes a capacitor coupled between a gate of the source follower transistor and a varactor of the event-driven pixel; and Generating the second voltage includes biasing a bottom plate of the capacitor to a low reference potential based at least in part on assertion of a sample and hold signal S&H applied to the varactor diode.

21. The method of claim 15, wherein: The capacitive voltage divider includes a capacitor coupled between a gate of the source follower transistor and a varactor of the event-driven pixel; and Outputting the differential signal includes amplifying the second voltage based at least in part on assertion of a boost signal applied to the varactor, wherein amplifying the second voltage includes reducing a capacitance of the capacitor.

22. The method of claim 15, further comprising: asserting a confirmation signal when the magnitude of the differential signal exceeds a threshold; and The differential circuit is reset in response to an overlap of (a) the assertion of the row select signal and (b) the assertion of the confirm signal.

23. The method of claim 22, wherein resetting the differential circuit comprises: asserting a reset signal applied to the differential circuit such that the voltage at the gate of the source follower transistor is set to a reference voltage; and A new reference light level is sampled based at least in part on the assertion of the reset signal.

24. The method of claim 18, further comprising: comparing the magnitude of the differential signal to a threshold value; and Resetting of the differential circuit is prevented when (a) the row select signal is asserted, (b) a global reset signal is not asserted, and (c) the magnitude of the differential signal does not exceed the threshold.

25. The method of claim 15, wherein converting the photocurrent to the first voltage comprises converting the photocurrent to the first voltage using a photocurrent-to-voltage converter of the event-driven pixel, and wherein the method further comprises selectively disabling an amplifier of the photocurrent-to-voltage converter when light generates the photocurrent.

26. An imaging system comprising: Event-driven pixels, which include: a photodetector configured to generate a photocurrent in response to incident light received from an external scene, a photocurrent / voltage converter coupled to the photodetector to convert the photocurrent into a voltage, and a differential circuit coupled to the photocurrent-to-voltage converter and configured to generate a differential signal based at least in part on the voltage, wherein the differential circuit comprises: a capacitive voltage divider having: (a) a first capacitor coupled to an output of the photocurrent / voltage converter, and (b) a second capacitor coupled to the first capacitor opposite the output of the photocurrent / voltage converter; a source follower transistor having a gate coupled to a node between the first capacitor and the second capacitor; a reset transistor coupled between a reference voltage and the node and having a gate configured to receive a reset signal; and a row select transistor coupled between the source follower transistor and a column line and configured to output the differential signal onto the column line in response to assertion of a row select signal; a threshold comparison circuit coupled to the differential circuit via the column lines, wherein the threshold comparison circuit is configured to compare the differential signal to one or more thresholds; and a control circuit coupled to the threshold comparison circuit and to the event-driven pixel, wherein the control circuit is configured to, when the differential signal exceeds a threshold value of the one or more threshold values, (i) register that the event-driven pixel has detected an event in the external scene, and (ii) initiate a reset of the differential circuit such that the node is set to the reference voltage.

27. The imaging system of claim 26, wherein the threshold comparison circuit comprises: a first comparator having an input coupled to the column line and configured to compare the differential signal to a first threshold of the one or more thresholds; and A second comparator has an input coupled to the column line and is configured to compare the differential signal to a second threshold of the one or more thresholds.

28. The imaging system of claim 26, wherein the event-driven pixel further comprises a varactor coupled to the second capacitor opposite to the first capacitor.

29. The imaging system of claim 28, wherein the varactor diode comprises: a first transistor coupled between the second capacitor and a second reference voltage and having a gate configured to receive a sample and hold signal; and A second transistor is coupled between the second capacitor and a third reference voltage and has a gate configured to receive a boost signal.

30. The imaging system of claim 26, wherein: The event-driven pixel further includes a reset control circuit having a first input configured to receive a global reset signal from the control circuit, a second input configured to receive the row select signal, a third input configured to receive a validation signal, and an output coupled to the gate of the reset transistor; The control circuit is configured to assert the confirmation signal when the differential signal exceeds the threshold so as to initiate the resetting of the differential circuit; and The reset control circuit is configured to assert the reset signal in response to: Assertions of the global reset signal, assertion of the confirm signal while the row select signal is asserted, or Its combination.

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