An event-driven pixel, a method for manipulating the event-driven pixel, and an imaging system.

Abstract

A low-power event-driven pixel with passive differential difference detection circuitry (and reset control circuitry thereof) is disclosed herein. In one embodiment, the event-driven pixel includes a photosensor, a photocurrent / voltage converter, and a difference circuit. The difference circuit includes: (a) a first circuit branch configured to sample a reference brightness level based on a voltage output by the photocurrent / voltage converter and output a first analog brightness level based on the reference brightness level to a first column line; and (b) a second circuit branch configured to sample a brightness level based on the voltage and output a second analog brightness level based on the brightness level to a second column line. The difference between the second analog brightness level and the first analog brightness level indicates whether the event-driven pixel has detected an event in an external scene.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors. For example, several embodiments of the present technology relate to event-driven pixels, including low-power event-driven pixels having passive differential difference detection circuitry and reset control circuitry thereof. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) both through device architecture design and image acquisition processing.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge after absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as an analog image signal from the column bit line and converted into a digital value to provide information representative of the external scene. Summary of the invention

[0004] One aspect of the present invention relates to an event-driven pixel, comprising: a photosensor configured to generate a photocurrent in response to incident light received from an external scene; a photocurrent / voltage converter coupled to the photosensor to convert the photocurrent into a voltage; and a difference circuit coupled to the photocurrent / voltage converter, wherein the difference circuit includes: a first circuit branch configured to (i) sample a reference brightness level based at least in part on the voltage and an assertion of a reset signal applied to the event-driven pixel and (ii) output a first analog brightness level to a first column line, wherein the first analog brightness level is based at least in part on the reference brightness level; and a second circuit branch configured to (i) sample a brightness level based at least in part on the voltage and an assertion of a switch signal applied to the event-driven pixel and (ii) output a second analog brightness level to a second column line, wherein the second analog brightness level is based at least in part on the brightness level, wherein a difference between the second analog brightness level and the first analog brightness level indicates whether the event-driven pixel has detected an event in the external scene.

[0005] Another aspect of the present invention relates to a method of operating an event-driven pixel, the method comprising: generating a photocurrent with a photosensor in response to receiving incident light from an external scene; converting the photocurrent into a first voltage; generating a differential difference signal based at least in part on the first voltage, wherein generating the differential difference signal comprises: (a) sampling a reference brightness level onto a first capacitor of a difference circuit of the event-driven pixel; (b) generating a first analog brightness level based at least in part on the reference brightness level using a first source follower transistor of the difference circuit; (c) sampling the brightness level onto a second capacitor of the difference circuit; and (d) generating a second analog brightness level using a second source follower transistor of the difference circuit, wherein a difference between the second analog brightness level and the first analog brightness level indicates whether the event-driven pixel has detected an event in the external scene; and outputting the differential difference signal in response to assertion of a row select signal, wherein outputting the differential difference signal comprises: (i) outputting the first analog brightness level onto a first column line; and (ii) outputting the second analog brightness level onto a second column line.

[0006] Another aspect of the present invention relates to an imaging system, comprising: an event-driven pixel, comprising: a photodetector configured to generate a photocurrent in response to incident light received from an external scene; a photocurrent / voltage converter coupled to the photodetector to convert the photocurrent into a voltage, and a difference circuit coupled to the photocurrent / voltage converter, wherein the difference circuit is configured to: (i) sample a reference brightness level onto a first capacitor, the reference brightness level being based at least in part on the voltage; (ii) output a first analog brightness level based at least in part on the reference brightness level onto a first column line; (iii) sample the brightness level onto a second capacitor, the brightness level being based at least in part on the voltage; and (iv) output a second analog brightness level based at least in part on the brightness level onto a second column line. on a column line, wherein a difference between the second analog brightness level and the first analog brightness level indicates whether the event-driven pixel has detected an event in the external scene; a threshold comparison circuit coupled to the first and second column lines and configured to compare the difference between the second analog brightness level and the first analog brightness level with one or more thresholds; and a control circuit coupled to the threshold comparison circuit and the event-driven pixel, wherein the control circuit is configured to, when the difference between the second analog brightness level and the first analog brightness level exceeds a threshold value among the one or more threshold values: (i) register that the event-driven pixel has detected the event; and (ii) initiate a reset of the difference circuit of the event-driven pixel so that a new reference brightness level is sampled onto the first capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present technology are described below with reference to the following figures, wherein like or similar reference symbols are used throughout to refer to like or similar components unless otherwise specified.

[0008] Figure 1 and 2 is a partial schematic block diagram of an imaging system including event-driven pixels, each configured in accordance with various embodiments of the present technology.

[0009] Figure 3 and 4 is a partial schematic diagram of a reset control circuit configured in accordance with various embodiments of the present technology.

[0010] Figure 5 is a timing diagram illustrating a method of operating an event-driven pixel according to various embodiments of the present technology.

[0011] Figure 6 is a partial schematic diagram of another event-driven pixel configured in accordance with various embodiments of the present technology.

[0012] Fig. 7A is a partial schematic diagram of a MOS varactor circuit configured in accordance with various embodiments of the present technology.

[0013] Figure 7B The present invention is to illustrate the operation of various embodiments according to the present technology. Fig. 7A Timing diagram of the MOS varactor circuit method.

[0014] Figure 8 It is available for Fig. 7A Partial schematic diagram of a three-terminal device in a MOS varactor circuit.

[0015] Figures 9 to 12 is a partial schematic diagram of a photocurrent / voltage converter coupled to a photosensor, each configured in accordance with various embodiments of the present technology.

[0016] Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in understanding the various aspects of the present technology. Additionally, common but well-understood elements or methods that are useful or necessary in commercially feasible embodiments are generally not depicted in the figures or described in detail below to avoid unnecessarily obscuring the description of the various aspects of the present technology. DETAILED DESCRIPTION

[0017] The present disclosure relates to event-driven sensors. For example, several embodiments of the present technology relate to event-driven pixels including low-power event-driven pixels with passive differential difference detection circuitry and / or to event-driven pixels with reset control circuitry. In the following description, specific details are set forth to provide a thorough understanding of aspects of the present technology. However, one skilled in the relevant art will recognize that the systems, devices, and techniques described herein may be practiced without one or more of the specific details set forth herein or with other methods, components, materials, etc.

[0018] Reference throughout this specification to an "example" or "embodiment" means that a particular feature, structure, or characteristic described in connection with the example or embodiment is included in at least one example or embodiment of the present technology. Thus, the use of the phrases "for example," "as an example," or "embodiment" herein are not necessarily all referring to the same example or embodiment and are not necessarily limited to the particular example or embodiment discussed. Furthermore, the features, structures, or characteristics of the present technology described herein may be combined in any suitable manner to provide additional examples or embodiments of the present technology.

[0019] For ease of description, spatially relative terms (e.g., "below," "below," "above," "below," "above," "up," "top," "bottom," "left," "right," "center," "middle," and the like) may be used herein to conveniently describe the relationship of one element or feature relative to one or more other elements or features, as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device or system in use or operation. For example, if the device or system illustrated in the figures is rotated, turned, or flipped around a horizontal axis, an element or feature described as being "below" or "below" or "below" one or more other elements or features may be oriented to be "above" one or more other elements or features. Therefore, the exemplary terms "below" or "below" are non-limiting and may cover both above and below orientations. The device or system may be oriented in other ways illustrated in the figures in addition or alternatively (e.g., rotated ninety degrees around a vertical axis or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when an element is referred to as being “between” two other elements, it can be the only element between the other two elements, or one or more intervening elements may also be present.

[0020] Throughout this specification, several terms of the art are used. These terms have their ordinary meaning in the art to which they belong, unless specifically defined herein or the context of their use clearly indicates otherwise. It should be noted that element names and symbols (e.g., Si vs. silicon) are used interchangeably throughout this document; however, both have the same meaning.

[0021] A. Overview

[0022] Active pixel sensors typically employ a pixel array with a globally defined integration time. Thus, pixels in an array of an active pixel sensor typically have the same integration time, and each pixel in the array is typically converted into a digital signal regardless of its content (e.g., whether there have been changes in the external scene captured by the pixel since the pixel was last read out).

[0023] In contrast, an event-driven sensor (e.g., an event vision sensor or a dynamic vision sensor) reads out pixels and / or converts corresponding pixel signals into digital signals only when the pixels capture a change (e.g., an event) in an external scene. In other words, pixels of an event-driven sensor that do not detect a change in an external scene are not read out, and / or pixel signals corresponding to such pixels are not converted into digital signals. Thus, each pixel of an event-driven sensor may be independent of other pixels of the event-driven sensor, and only pixels that detect a change in an external scene need to be read out and / or have their corresponding pixel signals converted into digital signals and / or recorded (thereby saving power).

[0024] Many event-driven pixels include local amplifiers and comparators for event threshold detection. The amplifier and comparator circuits of each event-driven pixel typically require a DC bias current on the order of nanoamperes, resulting in milliwatts of power consumption in megapixel event-driven sensors, regardless of whether any events occur in the external scene. In other words, the current power consumption of many event-driven pixels makes such event-driven pixels unsuitable for use with battery-operated always-on event-driven sensors, where sub-milliwatt power consumption of the event-driven sensor is desired (e.g., to extend battery life).

[0025] Some event-driven pixels (a) measure the voltage generated based on the photocurrent output from the photosensor without amplification in the output stage and (b) include a common-source gm stage to compensate for the lack of signal amplification in the output stage. The use of a common-source gm stage is expected to result in excessive non-uniformity, increased nonlinearity, challenges in correctly setting the operating point for all event-driven pixels of the event-driven sensor, and / or challenges in calibrating the event-driven pixels. In addition, because signal amplification occurs only after the output stage, the noise performance of event-driven pixels using a common-source gm stage is expected to be inferior to that of the event-driven sensors described above.

[0026] To address these issues, several event-driven pixels of the present technology each include: (a) a photosensor configured to generate a photocurrent in response to incident light received from an external scene; (b) a photocurrent / voltage converter coupled to the photosensor to convert the photocurrent into a voltage; and (c) a passive difference circuit coupled to the photocurrent / voltage converter and configured to generate a differential difference signal (e.g., complementary analog signal levels) based at least in part on the voltage. The use of a passive difference circuit can reduce power consumption of the event-driven pixel. In some embodiments, the passive difference circuit of the present technology may include a single and / or multiple sampling capacitors. In these and other embodiments, the difference circuit may include one or more source follower buffers or transistors. The inclusion of a source follower buffer in the difference circuit is expected to (a) produce improved uniformity and / or linearity and / or (b) improve the dynamic response of the event-driven pixel, especially compared to event-driven pixels that employ a common-source amplifier to reintroduce gain. In these and other embodiments, event-driven pixels of the present technology may include column-level event threshold detection to (a) reduce static power consumption of event-driven pixels and / or (b) implement frame-based readout of event-driven pixels.

[0027] In these and other embodiments, the photocurrent / voltage converter of the present technology may include an amplifier. The amplifier of the photocurrent / voltage converter can be used to increase the response speed to changes in the voltage output from the photocurrent / voltage converter. In other words, the amplifier can be used in low-latency applications to increase the speed at which the difference circuit of the event-driven pixel generates the differential analog signal level based on the voltage output from the photocurrent / voltage converter. In some embodiments, the amplifier of the photocurrent / voltage converter can be configured to receive an enable signal to selectively enable (or disable) the amplifier to save power. For example, the amplifier of the photocurrent / voltage converter can sometimes be powered down when the event-driven pixel is not outputting the differential analog signal level (e.g., when the frame is not being read out), thereby reducing the power consumption of the event-driven pixel.

[0028] In these and yet other embodiments, the event-driven pixel of the present technology includes a reset control circuit. The reset control circuit can be configured to: (a) initialize the event-driven pixel in response to assertion of a global reset signal; and / or (b) reset the event-driven pixel when a differential difference signal is read out from the event-driven pixel (e.g., in response to assertion of a row select signal) and the complementary analog signal levels of the differential difference signal indicate that an event has occurred within an external scene (e.g., resulting in assertion of a confirmation signal). Thus, the event-driven pixel of the present technology is expected to be suitable for use with battery-operated always-on event-driven sensors while avoiding several challenges discussed above and observed in many event-driven pixels.

[0029] B. Selected implementations of low power event driven pixels, reset control circuits, and associated systems, devices, and methods example

[0030] Figure 1 is a partial schematic block diagram of an imaging system 100 configured in accordance with various embodiments of the present technology. As shown, the imaging system 100 includes an event-driven pixel 120 and a threshold comparison circuit 108. In other embodiments of the present technology, the threshold comparison circuit 108 may be incorporated into the event-driven pixel 120.

[0031] Figure 1 The event-driven pixel 120 includes a photosensor 102, a photocurrent / voltage converter 104, a difference circuit 106, and a reset control circuit 110. The photosensor 102 is illustrated as Figure 1 A photodiode having an anode coupled to ground (eg, a negative power rail or another reference voltage) and a cathode coupled to the photocurrent / voltage converter 104. In operation, Figure 1 The photosensor 102 is configured to generate photoelectric charge or photocurrent in response to incident light 114 received from an external scene. In other embodiments of the present technology, the photosensor 102 may be another suitable type of photosensor or photodetector (e.g., a metal-semiconductor-metal (MSM) photodetector, a phototransistor, a photoconductive detector, or a phototube).

[0032] Figure 1 A photocurrent / voltage converter 104 is coupled to the photosensor 102 and is configured to convert a photocurrent generated by the photosensor 102 into a voltage. A difference circuit 106 is coupled to the photocurrent / voltage converter 104. Based on the voltage received from the photocurrent / voltage converter 104, the difference circuit 106 is configured to (a) sample a reference signal, brightness level, or voltage when the event-driven pixel 120 is reset and (b) generate a differential difference signal (e.g., by sampling the signal, brightness level, or voltage to read out together with the reference signal). When the row select signal rsel(m) is asserted, the difference circuit 106 may output the differential difference signal onto a bit line or column line 107. More specifically, the difference circuit 106 may output a complementary analog voltage signal of the differential difference signal to an input of a threshold comparison circuit 108 via the column line 107. The complementary analog voltage signal may correspond to the sampled reference signal and the sampled signal discussed above.

[0033] In some embodiments, the photocurrent / voltage converter 104 may be configured to receive an enable signal EN. Fig.11 and 12Discussed in more detail, enable signal EN may be used to selectively enable (e.g., power up, such as turning on, enabling current flow, or forcing into a higher power mode or state) or disable (e.g., power down, such as turning off, disabling current flow, or forcing into a lower power mode or state) one or more amplifiers of photocurrent / voltage converter 104. Disabling the amplifiers is expected to reduce power consumption of event-driven pixels 120, thereby reducing power consumption of imaging system 100 and / or an image sensor (not shown) incorporated into imaging system 100.

[0034] The reset control circuit 110 controls the reset of the event-driven pixel 120. More specifically, the reset control circuit 110 receives a global reset signal GRST, a row selection signal rsel(m), and an acknowledgement signal col_ack(n). Figures 2 to 6 Discussed in more detail, the reset control circuit is configured to (a) generate a reset signal RST based on assertion of a global reset signal GRST, a row select signal rsel(m), and / or an acknowledge signal col_ack(n) and (b) initiate sampling of a new reference signal in the difference circuit 106 in response to assertion of the reset signal RST.

[0035] Threshold comparison circuit 108 is coupled to the output of difference circuit 106. In the illustrated embodiment, threshold comparison circuit 108 is a circuit that is peripheral to event-driven pixel 120 and is coupled to event-driven pixel 120 via column line 107. Placing threshold comparison circuit 108 on column line 107 so that threshold comparison circuit 108 is shared among event-driven pixel 120 and other event-driven pixels (not shown) coupled to column line 107 is expected to reduce static power consumption compared to event-driven pixels that incorporate dedicated threshold comparison circuits.

[0036] In operation, the threshold comparison circuit 108 is configured to detect events occurring within the external scene. More specifically, when an event occurs in the external scene, the event is indicated as a rapid or sudden change in intensity or brightness in the incident light 114 received by the photosensor 102. In other words, if the external scene is static, such that no events occur, the brightness of the incident light 114 remains substantially unchanged. Thus, the photocurrent generated by the photosensor 102 remains substantially constant. However, if an event (e.g., movement) occurs within the external scene, the event is indicated by an asynchronous rapid or sudden change in the brightness of the incident light 114 received by the photosensor 102. The change in brightness may be from darker to brighter or from brighter to darker. Therefore, there may be an asynchronous change in the photocurrent generated by the photosensor 102, which in turn may result in a change in the differential difference signal generated by the difference circuit 106. Thus, the threshold comparison circuit 108 may be configured to receive a differential difference signal in the form of complementary analog voltage levels from the difference circuit 106, determine a difference between the complementary analog voltage levels, compare the difference to one or more thresholds, and detect an event occurring in the external scene based on the comparison. For example, the threshold comparison circuit 108 may detect that an event has occurred in the external scene when the magnitude of the difference between the complementary analog voltage levels output by the difference circuit 106 exceeds the magnitude of a threshold.

[0037] When the threshold comparison circuit 108 detects an event, the confirmation signal col_ack(n) may be asserted to prompt the reset control circuit 110 to: (a) assert the reset signal RST to reset the event-driven pixel 120; and (b) start sampling a new reference voltage in the difference circuit 106. Additionally or alternatively, the threshold comparison circuit 108 may output event information (e.g., the location where the event was detected, such as the xy coordinates of the photosensor 102 in the pixel array used to detect the event; the changed polarity of the photocurrent for the event (e.g., brighter or darker); and / or the time when the event occurred) for recording. On the other hand, when the threshold comparison circuit 108 does not detect an event, the confirmation signal col_ack(n) may remain unasserted, so that (without the assertion of the global reset signal GRST) the event-driven pixel 120 is not reset by the reset control circuit 110, and the difference circuit 106 continues to generate a differential difference signal based on the previously sampled reference voltage (e.g., the difference circuit 106 retains the previously sampled reference signal).

[0038] It should be noted that the Figure 1The image sensor of the imaging system 100 does not need to record a complete regular image, and therefore does not have the burden of having to capture all of the highly redundant information of a normal image frame by frame. Instead, the image sensor may record only event information. In other words, outside of the threshold comparison performed by the threshold comparison circuit 108, the image sensor may ignore portions of the frame of the image or video in which no event is detected, thereby achieving ultra-high frame rate and / or ultra-high speed capabilities at a low data rate. In some embodiments, events may be read out synchronously or asynchronously. In these and other embodiments, event data from the event-driven pixels 120 may be combined with normal image or video capture to reconstruct high frame rate, high quality images or videos with event detection via software, an artificial intelligence (AI) network, or other suitable techniques.

[0039] Figure 2 is a partial schematic diagram of an imaging system 200 configured in accordance with various embodiments of the present technology. The imaging system 200 may be Figure 1 As shown, the imaging system 200 includes a control circuit 215, an event-driven pixel 220, and a threshold comparison circuit 208.

[0040] The event-driven pixel 220 includes a photosensor 202, a photocurrent / voltage converter 204, a difference circuit 206, and a reset control circuit 210. The photosensor 202 includes an anode and a cathode coupled to ground (e.g., a negative power rail or another reference voltage). The photocurrent / voltage converter 204 of the event-driven pixel 220 is coupled to the cathode of the photosensor 202 and is configured to convert the photocurrent generated by the photosensor 202 into a voltage V A In some embodiments, the voltage V A has a logarithmic relationship with the intensity of incident light received by the photosensor 202 from the external scene. Several exemplary configurations of the photocurrent / voltage converter 204 are described below with reference to Figures 9 to 12 Discuss in more detail.

[0041] The difference circuit 206 of the event-driven pixel 220 includes two branches, each of which is coupled to the output of the photocurrent / voltage converter 204. The first branch of the difference circuit 206 includes a first transistor 221, a first capacitor 223 having a first capacitance C1, a first source follower buffer or transistor 225, and a first row select transistor 227. The second branch of the difference circuit 206 includes a second transistor 222, a second capacitor 224 having a second capacitance C2, a second source follower buffer or transistor 226, and a second row select transistor 228. In some embodiments, the first source follower transistor 225 and / or the second source follower transistor 226 are linear source follower transistors.

[0042] Referring to the first branch, the first transistor 221 includes: (a) a drain coupled to the output of the photocurrent / voltage converter 204 and the drain of the second transistor 222 of the second branch; (b) a source coupled to the first capacitor 223 and the gate of the first source follower transistor 225; and (c) a gate coupled to the output of the reset control circuit 210 to receive the reset signal RST. The first capacitor 223 is coupled between (a) the source of the first transistor 221 and the gate of the first source follower transistor 225 and (b) ground (e.g., a negative power rail or another reference voltage). The drain of the first source follower transistor 225 is coupled to a power supply voltage (e.g., a positive power rail or another reference voltage), and the source of the first source follower transistor 225 is coupled to the drain of the first row select transistor 227. The first row select transistor 227 includes (a) a source coupled to the first column line 207a and (b) a gate configured to receive the row select signal rsel(m). As discussed in more detail below, the first branch is configured to be based at least in part on the voltage V A The reference brightness level V on the first capacitor 223 C1 Sampling and converting the corresponding reference brightness level V C1 The analog voltage signal V O1 Output to the first column line 207a.

[0043] Referring to the second branch, the drain of the second transistor 222 is coupled to the output of the photocurrent / voltage converter 204 and the drain of the first transistor 221 of the first branch. The second transistor 222 further includes: (a) a source coupled to the second capacitor 224 and the gate of the second source follower transistor 226; and (b) a gate configured to receive the switching signal sw(m). The second capacitor 224 is coupled between (a) the source of the second transistor 222 and the gate of the second source follower transistor 226 and (b) ground (e.g., a negative power rail or another reference voltage). The drain of the second source follower transistor 226 is coupled to a power supply voltage (e.g., a positive power rail or another reference voltage), and the source of the second source follower transistor 226 is coupled to the drain of the second row select transistor 228. The second row select transistor 228 includes (a) a source coupled to the second column line 207b and (b) a gate configured to receive the row select signal rsel(m). As discussed in more detail below, the second branch is configured to be based at least in part on the voltage V A The brightness level V on the second capacitor 224 C2 Sampling and corresponding to the brightness level V C2 The analog voltage signal V O2 Output to the second column line 207b.

[0044] In some embodiments, the switch signal sw(m) may be distributed to all or a subset (e.g., multiple, unique) of the event-driven pixels in a row. For example, the switch signal sw(m) may be distributed to multiple event-driven pixels in a row to minimize the pixel transistor count. Alternatively, the switch signal sw(m) may be dedicated to a single event-driven pixel 220 of the imaging system 200.

[0045] In some embodiments, difference circuit 206 may be coupled to photocurrent / voltage converter 204 such that difference circuit 206 and / or photocurrent / voltage converter 204 function as a high-pass filter configured to filter out lower frequency components from the output of photosensor 202 and / or photocurrent / voltage converter 204. Thus, event-driven pixel 220 may ignore slow or gradual changes in the photocurrent generated by photosensor 202 in response to incident light from an external scene, and may instead detect rapid or sudden changes that occur in the photocurrent generated by photosensor 202 in response to incident light.

[0046] Based on the voltage V output from the photocurrent / voltage converter 204 A , the difference circuit 206 can generate a voltage V C1 and V C2 , which are respectively applied to the gate of the first source follower transistor 225 and the gate of the first source follower transistor 226. Then, the first source follower transistor 225 can C1 The first analog signal level is output to the first row selection transistor 227, and the second source follower transistor 226 can be based on the voltage V C2 The first row select transistor 227 can output the first analog signal level (shown as Figure 2 The voltage V O1 ) is output to the first column line 207a, and the second row select transistor 228 can output the second analog signal level (shown as Figure 2 The voltage V O2 ) is output onto the second column line 207b. As discussed in more detail below, the first analog signal level and the second analog signal level may be complementary signals of a differential signal indicating whether an event has occurred in the external scene. In this way, the voltage V outputted from the photocurrent / voltage converter 204 based at least in part on A, the difference circuit 206 can output the complement of the differential difference signal onto the first and second column lines 207a and 207b when the control circuit 215 asserts the row select signal rsel(m) applied to the gates of the first and second row select transistors 227 and 228. In addition, because the first and second capacitors 223 and 224 are passive components and because the first and second transistors 221 and 222 are configured to function as switches, the difference circuit 206 consumes a small amount of power compared to difference circuits that employ active circuit components, making the difference circuit 206 suitable for use in low-power battery-operated and / or always-on event-driven sensors. The difference circuit 206 can therefore be viewed as a low-power passive differential difference detection circuit.

[0047] The complementary analog voltage signal V of the differential difference signal output from the event-driven pixel 220 to the first and second column lines 207a and 207b O1 and V O2 is fed into the threshold comparison circuit 208. As shown, the threshold comparison circuit 208 includes an amplifier 231, a first comparator 232, and a second comparator 233. In some embodiments, the amplifier 231 may be an analog difference amplifier or a differential analog / digital converter (ADC), such as a ramp-type differential ADC. The amplifier 231 includes a positive input coupled to the first column line 207a, a negative input coupled to the second column line 207b, and an output coupled to (i) the input of the first comparator 232 and (ii) the input of the second comparator 233. The first comparator 232 is configured to compare the output of the amplifier 231 with a first threshold, and the second comparator 233 is configured to compare the output of the amplifier 231 with a second threshold. In some embodiments, the first comparator 232 may be triggered when the brightness or intensity of the light incident on the photosensor 202 of the event-driven pixel 220 changes in one direction (e.g., from darker to brighter). When triggered, the first comparator 232 may assert a signal UP, which may indicate that an event has occurred in the external scene. In these and other embodiments, the second comparator 233 may be triggered when the brightness or intensity of light incident on the photosensor 202 changes in the other direction (e.g., from brighter to darker). When triggered, the second comparator 233 may assert the signal DOWN, which may indicate that an event has occurred in the external scene. The signals UP and DOWN are passed to the control circuit 215, and the control circuit 215 may assert the confirmation signal col_ack(n) when the signal UP or the signal DOWN indicates that an event has occurred in the external scene (e.g., when the signal UP or the signal DOWN is asserted).

[0048] Reference again Figure 2The reset control circuit 210 includes a first input (input a) configured to receive a row select signal rsel(m), a second input (input b) configured to receive an acknowledgement signal col_ack(n), and a third input (input c) configured to receive a global reset signal GRST. The reset control circuit 210 further includes an output (output y) configured to apply the reset signal RST to the gate of the first transistor 221 of the difference circuit 206. The assertion of the reset signal RST may depend at least in part on the states of the row select signal rsel(m), the acknowledgement signal col_ack(n), and the global reset signal GRST received from the control circuit 215 and input into the reset control circuit 210. For example, as discussed in more detail below, the control circuit 215 may assert the row select signal rsel(m) to read out the complementary signal of the differential difference signal from the difference circuit 206, and may assert the acknowledgement signal col_ack(n) when the threshold comparison circuit 208 detects that an event has occurred in the external scene based on the differential difference signal. Continuing with this example, the reset control circuit 210 may assert the reset signal RST when the row selection signal rsel(m) and the confirmation signal col_ack(n) are simultaneously asserted. As another example, the control circuit 215 may assert the global reset signal GRST to reset or initialize the event-driven pixel 220, and the reset control circuit 210 may assert the reset signal RST in response to the assertion of the global reset signal GRST.

[0049] Figure 3 and 4 In various embodiments of the present technology, Figure 2 First, refer to the partial schematic diagram of the reset control circuit 210 of the reset control circuit 310 and the reset control circuit 410. Figure 3 , the reset control circuit 310 includes an AND logic gate 341, an OR logic gate 342, and a delay element 343. The AND logic gate 341 includes a first input configured to receive the row selection signal rsel(m) via a first input (input a) of the reset control circuit 310 and a second input configured to receive the confirmation signal col_ack(n) via a second input (input b) of the reset control circuit 310. The OR logic gate 342 includes a first input coupled to the output of the AND logic gate 341, a second input configured to receive the global reset signal GRST via a third input (input c) of the reset control circuit 310, and an output (output x) coupled to the input of the delay element 343. The delay element 343 includes an output coupled to the output (output y) of the reset control circuit 310.

[0050] In operation, the reset control circuit 310 is configured to assert the reset signal RST when (a) the global reset signal GRST is asserted or (b) the row select signal rsel(m) and the acknowledge signal col_ack(n) are asserted together. In other words, the reset control circuit 310 is configured to assert the reset signal RST whenever (a) the global reset signal GRST is asserted or (b) the difference signal is asserted from Figure 2 When an event drives the difference circuit 206 of the pixel 220 to read out and the difference signal indicates that an event has occurred in the external scene, RST is asserted. Otherwise, the reset control circuit 310 outputs the reset signal RST in its unasserted state. As discussed in more detail below, on the falling edge of the output (output x) of the OR logic gate 342, the delay element 343 is configured to keep the reset signal RST in the asserted state for a non-reactive period. In other embodiments, the reset control circuit 310 may lack or omit the delay element (e.g., such that the output (output x) of the OR logic gate 342 is connected (e.g., directly) to the output (output y) of the reset control circuit 310 and / or such that the reset signal RST is de-asserted on the falling edge of the output (output x) of the OR logic gate 342 without a non-reactive period).

[0051] Reference now Figure 4 , the reset control circuit 410 includes a plurality of transistors (in Figure 4 458) and capacitor 459. The first to fourth transistors 451 to 454 are arranged as NAND logic gates. More specifically, the source of the first transistor 451 is coupled to ground (e.g., a negative power rail or another reference voltage), the drain of the first transistor 451 is coupled to the source of the second transistor 452, and the gate of the first transistor 451 is configured to receive the acknowledgement signal col_ack(n) via the second input (input b) of the reset control circuit 410. The drain of the second transistor 452 is coupled to the drain of the third transistor 453 and the drain of the fourth transistor 454, and the gate of the second transistor 452 is configured to receive the row select signal rsel(m) via the first input (input a) of the reset control circuit 410. The source of the third transistor 453 is coupled to a power supply voltage (e.g., a positive power supply rail or another reference voltage), the drain of the third transistor 453 is coupled to the drain of the fourth transistor 454, and the gate of the third transistor 453 is configured to receive the row select signal rsel(m) via the first input (input a) of the reset control circuit 410. The source of the fourth transistor 454 is coupled to the power supply voltage, and the gate of the fourth transistor 454 is configured to receive the acknowledgement signal col_ack(n) via the second input (input b) of the reset control circuit 410.

[0052] The seventh transistor 457 of the reset control circuit 410 is arranged as a low active switch that charges the capacitor 459. In particular, the source of the seventh transistor 457 is coupled to the supply voltage, the gate of the seventh transistor 457 is coupled to the output of the NAND logic gate (e.g., to the drain of the second transistor 452, to the drain of the third transistor 453, and to the drain of the fourth transistor 454), and the drain of the seventh transistor 457 is coupled to the capacitor 459 and the output (output y) of the reset control circuit 410. The capacitor 459 is coupled between (a) ground and (b) the drain of the seventh transistor 457 and the output (output y) of the reset control circuit 410.

[0053] The fifth transistor 455 and the sixth transistor 456 of the reset control circuit 410 are arranged as pass transistors. More specifically, (a) the source of the fifth transistor 455 is coupled to the drain of the third transistor 453 and the drain of the fourth transistor 454; (b) the drain of the fifth transistor 455 is coupled to the drain of the second transistor 452 and the gate of the seventh transistor 457; (c) the source of the sixth transistor 456 is coupled to ground; and (d) the drain of the sixth transistor 456 is coupled to the drain of the second transistor 452, the drain of the fifth transistor 455, and the gate of the seventh transistor 457. The gate of the fifth transistor 455 and the gate of the sixth transistor 456 are each configured to receive a global reset signal via a third input (input c) of the reset control circuit 410.

[0054] The eighth transistor 458 is arranged as a resistive element configured to discharge the capacitor 459 when the low activity switch is released (e.g., when the seventh transistor 457 is turned off). More specifically, the source of the eighth transistor 458 is coupled to ground; the drain of the eighth transistor 458 is coupled to the drain of the seventh transistor 457, the capacitor 459, and the output (output y) of the reset control circuit 410; and the gate of the eighth transistor 458 is configured to receive a programmable or trimmable bias voltage. As discussed in more detail below, the eighth transistor 458 is configured to keep the reset signal RST in an asserted state for a non-reactive period when the seventh transistor 457 is turned from on to off.

[0055] In operation, the reset control circuit 410 functions similarly to the reset control circuit 310. Specifically, when both the row selection signal rsel(m) and the confirmation signal col_ack(n) are asserted, the seventh transistor 457 is turned on via the output of the NAND logic gate (formed by the first to fourth transistors 451 to 454), the capacitor 459 is charged, and the reset signal RST output from the reset control circuit 410 is asserted. In addition, when the global reset signal GRST is asserted, the seventh transistor 457 is turned on via the sixth transistor 456 used as a pass transistor, the capacitor 459 is charged, and the reset signal RST output from the reset control circuit 410 is asserted. At all other times, the seventh transistor 457 is turned off, the capacitor 459 is discharged or remains uncharged, and the reset signal RST output from the reset control circuit 410 is not asserted.

[0056] The capacitor 459 of the reset control circuit 410 is discharged through the eighth transistor 458 when (a) the global reset signal is de-asserted after being asserted or (b) the row select signal rsel(m) or the confirmation signal col_ack(n) is de-asserted after both the row select signal rsel(m) and the confirmation signal col_ack(n) are asserted together. The rate at which the capacitor 459 is discharged through the eighth transistor 458 (a) depends on the programmable bias voltage applied to the gate of the eighth transistor 458 and (b) is inversely related to the length of the unresponsive period during which the reset signal RST remains asserted after the eighth transistor 458 begins to discharge the capacitor 459. For example, a higher bias voltage can be used to discharge the capacitor 459 faster through the eighth transistor 458 and thus for a shorter unresponsive period. Continuing with this example, a lower bias voltage can be used to discharge the capacitor 459 slower through the eighth transistor 458 and thus for a longer unresponsive period.

[0057] It should be understood that in other embodiments of the present technology, Figure 2 The reset control circuit 210 may have Figure 2 , 3 4, and another schematic configuration other than the schematic configuration shown in FIG. 4, and another schematic item can selectively reset the event-driven pixel 220 based on the row selection signal rsel(m), the confirmation signal col_ack(n) and / or the global reset signal GRST. For example, as discussed above, in some embodiments of the present technology, the event-driven pixel 220 can be omitted. Figure 3 The delay element 343 of the reset control circuit 310 is configured so that there is no unresponsive period after the global reset signal GRST, the confirmation signal col_ack(n) and / or the row selection signal rsel(m) are de-asserted. As another example, in some embodiments, Figure 4The reset control circuit 410 may have no unresponsive period after the global reset signal GRST, the confirmation signal col_ack(n), and / or the row selection signal rsel(m) are de-asserted. As a specific example, the capacitor 459 and / or the eighth transistor 458 of the reset control circuit 410 may be omitted, and / or the bias voltage applied to the gate of the eighth transistor 458 may be set so that the capacitor 459 is quickly (e.g., immediately) discharged. It should be further understood that in other embodiments, the difference circuit 206, the event-driven pixel 220, the threshold comparison circuit 208, and / or the control circuit 215 may have a plurality of different configurations. Figure 2 In fact, it can be used as a schematic configuration other than the schematic configuration shown in FIG. Figure 2 Examples of alternative illustrative configurations of the present technology that may be used in addition to or in place of the difference circuit 206 and / or event-driven pixel 220 are described below with respect to Figure 6 Discuss in detail.

[0058] Figure 5 The present invention is to illustrate the operation of various embodiments according to the present technology. Figure 2 The timing diagram 560 of the imaging system 200 and the method of event-driven pixel 220 is shown. Figure 2 and 5 For the sake of clarity and understanding, it is assumed that the photocurrent generated by the photosensor 202 is linear (e.g. Figure 5 ). It is also assumed that the photocurrent / voltage converter 204 converts the photocurrent generated by the photosensor 202 into a logarithmically increasing voltage V A (As in Figure 5 In other embodiments, the voltage V generated by the photocurrent / voltage converter 204 is A may be another function (eg, linear, square root, etc.) of the photocurrent generated by photosensor 202 .

[0059] exist Figure 5 At time t0 shown in FIG. 1 , the control circuit 215 of the imaging system 200 performs a global reset by asserting the global reset signal GRST to initialize the event-driven pixel 220. When the global reset signal GRST is asserted, the reset control circuit 210 of the event-driven pixel 220 asserts the reset signal RST applied to the gate of the first transistor 221. Then, the first transistor 221 is turned on, and the voltage V output from the photocurrent / voltage converter 204 is A The sampled value is stored on the first capacitor 223 as the reference brightness level V C1 At the same time, the control circuit 215 asserts the switch signal sw(m), thereby activating the second transistor 222 and the voltage V output from the photocurrent / voltage converter 204. AThe sample is then transferred to the second capacitor 224 as the brightness level V C2 .

[0060] At time t1, the control circuit 215 de-asserts the global reset signal GRST. Subsequently, the reset control circuit 210 de-asserts the reset signal RST. Therefore, at time t1, the reference brightness level V C1 is frozen at a voltage V equal to that at time t1 A (For example, V A (t1)) and may remain at that voltage level until the difference circuit 206 of the event-driven pixel 220 is reset (e.g., at time t5). The control circuit 215 keeps the switch signal sw(m) asserted so that the brightness level V C2 Continue to track the voltage V output from the photocurrent / voltage converter 204 A .

[0061] At time t2, control circuit 215 deasserts switch signal sw(m) and asserts row select signal rsel(m) (e.g., as part of a readout scan to locate a pixel of imaging system 200 that has detected an event). When row select signal rsel(m) is asserted, first row select transistor 227 and second row select transistor 228 are activated. Thus, corresponding to reference brightness level V C1 The analog brightness level V O1 is read out onto the first column line 207a and corresponds to the instantaneous brightness level V at time t2 C2 The analog brightness level V O2 is read out to the second column line 207b. The instantaneous brightness level V at time t2 C2 Equivalent to the voltage V at time t2 A (For example, V A As discussed above, the simulated brightness level V O1 And simulated brightness level V O2 It is the complementary signal of the differential difference signal.

[0062] Analog brightness level V O1 And simulated brightness level V O2 is fed into a corresponding input of amplifier 231 of threshold comparison circuit 208. As discussed above, amplifier 231 may be an analog difference amplifier or a differential ADC. In the case where amplifier 231 is an analog difference amplifier, amplifier 231 may be auto-zeroed to reduce offset variability (e.g., upon receiving an analog brightness level V O1 And simulated brightness level V O2 Before). Amplifier 231 outputs a voltage at node O representing the analog brightness level V O1 With analog brightness level V O2In some embodiments, the output of the amplifier 231 at the node O may be equal to (a) the auto-zero voltage V of the amplifier 231. AZ and (b) simulated brightness level V O1 With analog brightness level V O2 The sum of the differences in voltage between , where gain or attenuation is provided by amplifier 231. For example, the signal at node O can be calculated using the following equation 1:

[0063]

[0064] The output of amplifier 231 appears at node O and is fed into first and second comparators 232 and 233 of threshold comparison circuit 208. First comparator 232 compares the output of amplifier 231 with a first threshold voltage V th-up , and the second comparator 233 compares the output of the amplifier 231 with the second threshold voltage V th-down .like Figure 5 As shown in FIG. 1 , the output of the amplifier 231 appearing at the node O between time t2 and time t3 does not exceed the first threshold voltage V th-up Or the second threshold voltage V th-down . Therefore, the output of the amplifier 231 will not trigger the first comparator 232 or the second comparator 233 between time t2 and time t3. Thus, both the signal UP and the signal DOWN remain unasserted during this time period. Therefore, the control circuit 215 does not register an event based on the differential difference signal read out from the event-driven pixel 220 at time t2, and the confirmation signal col_ack(n) remains unasserted. Because the confirmation signal col_ack(n) remains unasserted, the reset control circuit 210 of the event-driven pixel 220 does not reset the difference circuit 206 (e.g., there is no intervening assertion of the global reset signal GRST). Therefore, the reference brightness level V on the first capacitor 223 C1 remains frozen and is equal to the voltage V at time t1 A (For example, V A (t1)).

[0065] At time t3, the control circuit 215 deasserts the row selection signal rsel(m) and asserts the switch signal sw(m) to activate the second transistor 222. The switch signal sw(m) remains asserted from time t3 to time t4, which means that the second transistor 222 remains activated from time t3 to time t4. Therefore, the brightness level V C2 Track the voltage V output from the photocurrent / voltage converter 204 during this period A .

[0066] At time t4, control circuit 215 deasserts switch signal sw(m) and asserts row select signal rsel(m) (e.g., as part of a readout scan to locate a pixel of imaging system 200 that has detected an event). When row select signal rsel(m) is asserted, first row select transistor 227 and second row select transistor 228 are activated. Thus, corresponding to reference brightness level V C1 The analog brightness level V O1 is read out onto the first column line 207a and corresponds to the instantaneous brightness level V at time t4 C2 The analog brightness level V O2 is read out to the second column line 207b. The instantaneous brightness level V at time t4 C2 Equivalent to the voltage V at time t4 A (For example, V A (t4)). As discussed above, the simulated brightness level V O1 And simulated brightness level V O2 It is the complementary signal of the differential difference signal.

[0067] Analog brightness level V O1 And simulated brightness level V O2 is fed into a corresponding input of amplifier 231 of threshold comparison circuit 208. In the case where amplifier 231 is an analog difference amplifier, amplifier 231 may be automatically zeroed to reduce offset variability (e.g., upon receiving an analog brightness level V O1 And simulated brightness level V O2 Before). Amplifier 231 outputs a voltage at node O representing the analog brightness level V O1 With analog brightness level V O2 The output of the amplifier 231 at the node O is fed into the first and second comparators 232 and 233. The first comparator 232 compares the output of the amplifier 231 with the first threshold voltage V th-up , and the second comparator 233 compares the output of the amplifier 231 with the second threshold voltage V th-down .like Figure 5 As shown in FIG. 1 , the output of the amplifier 231 appearing at the node O between time t4 and time t5 exceeds the first threshold voltage V th-up and does not exceed the second threshold voltage V th-down Therefore, the output of the amplifier 231 triggers the first comparator 232 and does not trigger the second comparator 233. Thus, the first comparator 232 asserts the signal UP, while the signal DOWN output from the second comparator 233 remains unasserted.

[0068] At time t5, in response to the assertion of the signal UP, the control circuit 215 registers the event and asserts the acknowledgement signal col_ack(n). Because both the acknowledgement signal col_ack(n) and the row selection signal rsel(m) are asserted between time t5 and time t6, the reset control circuit 210 implements a local reset of the event-driven pixel 220 by asserting the reset signal RST between time t5 and time t6. Subsequently, the asserted reset signal RST is applied to the gate of the first transistor 221, and the difference circuit 206 of the event-driven pixel 220 is reset. More specifically, the voltage V corresponding to the output from the photocurrent / voltage converter 204 is A The new reference photovoltage V C1 The voltage is sampled onto the first capacitor 223 .

[0069] At time t6, the control circuit 215 de-asserts the row selection signal rsel(m) and the confirmation signal col_ack(n). Then, the reset control circuit 210 de-asserts the reset signal RST. Therefore, at time t6, the reference brightness level V on the first capacitor 223 is C1 is frozen at a voltage V equivalent to that at time t6 A (For example, V A (t6)) and may remain at that voltage level until the difference circuit 206 of the event-driven pixel 220 is reset again (e.g., at time t8). The control circuit 215 also asserts the switch signal sw(m) at time t6 to activate the second transistor 222 so that the voltage V output from the photocurrent / voltage converter 204 is tracked. A New brightness level V C2 is sampled on the second capacitor 224. The switch signal sw(m) remains asserted until time t7. Therefore, the brightness level V C2 Tracking the voltage V output from the photocurrent / voltage converter 204 between time t6 and time t7 A .like Figure 5 , the photocurrent output by the photoelectric sensor 202 and the voltage V output by the photocurrent / voltage converter 204 A decreases between time t6 and time t7. Because the brightness level V C2 Tracking the voltage V output from the photocurrent / voltage converter 204 A , so the brightness level V C2 It also decreases between time t6 and time t7.

[0070] At time t7, control circuit 215 deasserts switch signal sw(m) and asserts row select signal rsel(m) (e.g., as part of a readout scan to locate a pixel of imaging system 200 that has detected an event). When row select signal rsel(m) is asserted, first row select transistor 227 and second row select transistor 228 are activated. Thus, corresponding to reference brightness level V C1 The analog brightness level V O1 is read out onto the first column line 207a and corresponds to the instantaneous brightness level V at time t7 C2 The analog brightness level V O2 is read out to the second column line 207b. The instantaneous brightness level V at time t7 C2 Equivalent to the voltage V at time t7 A (For example, V A (t7)). As discussed above, the simulated brightness level V O1 And simulated brightness level V O2 It is the complementary signal of the differential difference signal.

[0071] Analog brightness level V O1 And simulated brightness level V O2 is fed into a corresponding input of amplifier 231 of threshold comparison circuit 208. In the case where amplifier 231 is an analog difference amplifier, amplifier 231 may be automatically zeroed to reduce offset variability (e.g., upon receiving an analog brightness level V O1 And simulated brightness level V O2 Before). Amplifier 231 outputs a voltage at node O representing the analog brightness level V O1 With analog brightness level V O2 The output of the amplifier 231 at the node O is fed into the first and second comparators 232 and 233. The first comparator 232 compares the output of the amplifier 231 with the first threshold voltage V th-up , and the second comparator 233 compares the output of the amplifier 231 with the second threshold voltage V th-down .like Figure 5 As shown in FIG. 1 , the output of the amplifier 231 appearing at the node O between time t7 and time t8 exceeds the second threshold voltage V th-down and does not exceed the first threshold voltage V th-up Therefore, the output of the amplifier 231 triggers the second comparator 233 and does not trigger the first comparator 232. Thus, the second comparator 233 asserts the signal DOWN, while the signal UP output from the first comparator 232 remains unasserted.

[0072] At time t8, in response to the assertion of the signal DOWN, the control circuit 215 registers the event and asserts the acknowledge signal col_ack(n). Because both the acknowledge signal col_ack(n) and the row select signal rsel(m) are asserted between time t8 and time t9, the reset control circuit 210 implements a local reset of the event-driven pixel 220 by asserting the reset signal RST between time t8 and time t9. Subsequently, the asserted reset signal RST is applied to the gate of the first transistor 221, and the difference circuit 206 of the event-driven pixel 220 is reset. More specifically, the voltage V corresponding to the output from the photocurrent / voltage converter 204 is A The new reference photovoltage V C1 The voltage is sampled onto the first capacitor 223 .

[0073] At time t9, the control circuit 215 de-asserts the row selection signal rsel(m) and the confirmation signal col_ack(n). Then, the reset control circuit 210 de-asserts the reset signal RST. Therefore, at time t9, the reference brightness level V on the first capacitor 223 is C1 is frozen at a voltage V equivalent to that at time t9 A (For example, V A (t9)) and may remain at that voltage level until difference circuit 206 of event-driven pixel 220 is reset again.

[0074] Continue to refer to the above discussion Figure 2 and 5 , asserting the switch signal sw(m) will increase the brightness level V C2 The sample is sampled onto the second capacitor 224; the deassertion of the switch signal sw(m) will increase the brightness level V C2 and asserting the row select signal rsel(m) results in (a) the complementary analog brightness level V of the differential difference signal O1 and V O2 is read into the amplifier 231 and (b) the output of the amplifier 231 is fed into the first and second comparators 232 and 233. As also discussed above, when the output of the amplifier 231 triggers the first comparator 232 or the second comparator 233 of the threshold comparison circuit 208, the control circuit 215 registers the event and asserts the acknowledge signal col_ack(n), which in turn causes the reset control circuit 210 to assert the reset signal RST because the acknowledge signal col_ack(n) is asserted while the row select signal rsel(m) is also asserted. When the reset signal RST is asserted, the reference brightness level V C1 is updated and tracks the voltage V output from the photocurrent / voltage converter 204 ABecause the row select signal rsel(m) remains asserted during this period, the complementary signal V O1 and V O2 is continuously read into the threshold comparison circuit 208, even (a) after the control circuit 215 registers an event and (b) at the reference brightness level V C1 is allowed to vary with voltage V A Therefore, depending on the voltage V A The change during the period when the reset signal RST is asserted, the reference brightness level V C1 The corresponding change in the threshold comparison circuit 208 may cause the triggering of the first comparator 232 and / or the second comparator 233 to exceed the initial triggering that causes the control circuit 215 to assert the confirmation signal col_ack(n). Thus, in some embodiments, the control circuit 215 may be configured to ignore the additional triggering of the first comparator 232 and / or the second comparator 233 while the reset signal RST remains asserted after the control circuit 215 asserts the confirmation signal col_ack(n).

[0075] In these and other embodiments, the imaging system 200 may include additional pixel logic to prevent additional triggering of the first comparator 232 and / or the second comparator 233 of the threshold comparison circuit 208 during a period of time when both the reset signal RST and the row select signal rsel(m) are asserted in response to detecting an event after the assertion of the acknowledge signal col_ack(n). For example, the imaging system 200 may include additional pixel logic to prevent additional triggering of the first comparator 232 and / or the second comparator 233 of the threshold comparison circuit 208 during a period of time when both the reset signal RST and the row select signal rsel(m) are asserted in response to detecting an event after the assertion of the acknowledge signal col_ack(n). Figure 5 , the additional pixel logic asserts the switch signal sw(m) whenever the reset signal RST is asserted, except for the times shown as being asserted in FIG. Figure 5 As an example, the additional pixel logic can ensure that the switch signal sw(m) is asserted: (a) between time t0 and time t2, (b) between time t3 and time t4, (c) between time t5 and time t7, and (d) between time t8 and time t9. Asserting the switch signal sw(m) when the reset signal RST is asserted permits the brightness level V on the second capacitor 224 to be sampled. C2 Tracking the voltage V output from the photocurrent / voltage converter 204 A , and at the same time sample the reference brightness level V on the first capacitor 223 C1 is allowed to track the voltage V A In other words, the brightness level V C2 is permitted with reference brightness level V C1 The complementary analog brightness level V of the differential difference signal read into the threshold comparison circuit 208 is thereby eliminated. O1 and VO2 Any difference between , while the row select signal rsel(m) remains asserted after the event is detected. Therefore, as long as the reset signal RST remains asserted, additional triggering of the first comparator 232 and the second comparator 233 after the event is detected is prevented.

[0076] Figure 6 FIG. 6 is a partial schematic diagram of another event-driven pixel 620 configured in accordance with various embodiments of the present technology. As shown, the event-driven pixel 620 is similar to Figure 2 event-driven pixel 220. For example, the event-driven pixel 620 includes: (a) a photosensor 602; (b) a photocurrent / voltage converter 604; and (c) a difference circuit 606, which has a first branch (including a first transistor 621, a first capacitor 623 with a first capacitance C1, a first source follower buffer or transistor 625, and a first row selection transistor 627) and a second branch (including a second transistor 622, a second capacitor 624 with a second capacitance C2, a second source follower buffer or transistor 626, and a second row selection transistor 628). Although Figure 6 Not shown, but the event-driven pixel 620 may further include a reset control circuit similar to Figure 2 The reset control circuit 210 of the event-driven pixel 620 has an output coupled to the gate of the first transistor 621. The photosensor 602, the photocurrent / voltage converter 604, the difference circuit 606 and the reset control circuit of the event-driven pixel 620 can be similar to Figure 2 The event-driven pixel 620 operates similarly to the photosensor 202, the photocurrent / voltage converter 204, the difference circuit 206, and the reset control circuit 210. Therefore, a detailed discussion of these components of the event-driven pixel 620 is omitted here for the sake of brevity.

[0077] and Figure 2 Compared with the event-driven pixel 220, Figure 6 The event-driven pixel 620 further includes a passive MOS varactor 670 (e.g., a varicap). The varactor 670 includes a first transistor 671 and a second transistor 672. The first capacitor 623 and the second capacitor 624 are coupled in parallel to each other between the output of the photocurrent / voltage converter 604 and the first and second transistors 671 and 672 of the varactor 670. The first transistor 671 is electrically coupled to a reference voltage V REF2 (eg, ground, a negative power rail, or another low reference potential) and the first and second capacitors 623 and 624, and the second transistor 672 is electrically coupled to the reference voltage V REF3 (For example, V DD, a positive power rail or another high reference voltage) and the first and second capacitors 623 and 624. The first transistor 671 includes a gate configured to receive the sample and hold signal S&H, and the second transistor 672 includes a gate configured to receive the signal Boost. As described in more detail below, the varactor diode 670 can be used in the event-driven pixel 620 to provide signal amplification and reduce noise.

[0078] Now refer to Fig. 7A and 7B The characteristics of the varactor diode 670 are explained. Fig. 7A is a partially simplified schematic diagram of a MOS varactor circuit 780 configured in accordance with various embodiments of the present technology, and Figure 7B It is to explain the operation Fig. 7A MOS varactor circuit 780 may generally correspond to Figure 6 620. For example, Fig. 7A The MOS varactor circuit 780 may generally correspond to the first transistor 621, the second transistor 622, the first capacitor 623, the second capacitor 624, the first transistor 671 and / or the second transistor 672 of the event-driven pixel 620. Therefore, for clarity and understanding, Fig. 7A and 7B Use with Figure 6 Reference numbers and signals used in the present invention are similar to reference numbers and signals used in the present invention.

[0079] As shown, the MOS varactor circuit 780 includes a switch 721 controlled by a reset signal RST, a switch 771 controlled by a sample and hold signal S&H, a switch 772 controlled by a signal Boost, and a MOS capacitor 723 having a drain terminal and a source terminal coupled to each other. The switch 721 selectively couples the gate of the MOS capacitor 723 to a reference voltage V REF1 Similarly, switch 771 selectively couples the source and drain terminals of MOS capacitor 723 to a reference voltage V REF2 , and switch 772 selectively couples the source and drain terminals of MOS capacitor 723 to a reference voltage V REF3 The switch 771 and the switch 772 may form at least a portion of the varactor diode 770 .

[0080] Reference together Fig. 7A and 7B, when (i) the reset signal RST and the sample and hold signal S&H are both asserted and (ii) the signal Boost remains unasserted, the MOS varactor circuit 780 operates in a first operation phase (e.g., tracking or inversion phase), and a signal is sampled onto the MOS capacitor 723. More specifically, the drain and source terminals of the MOS capacitor 723 are biased to the reference voltage V via the switch 771. REF2 Assume (a) the reference voltage V REF2 is a low reference potential (for example, ground, the negative supply rail, or a voltage lower than the reference voltage V REF1 and (b) a reference voltage V REF1 is large enough to cause channel inversion by pulling charge from the drain and source terminals of MOS capacitor 723 to form a channel. The capacitance of MOS capacitor 723 can be defined by the gate oxide capacitance because the junction capacitance is at the reference voltage V REF2 Down.

[0081] On the other hand, when (i) the signal Boost is asserted and (ii) the reset signal RST and the sample and hold signal S&H are not asserted, the MOS varactor circuit 780 operates in the second operation phase (e.g., amplification or accumulation phase) and the voltage at the node G increases. More specifically, the drain and source terminals of the MOS capacitor 723 are biased to the reference voltage V REF3 Assuming the reference voltage V REF3 is a high reference potential (e.g., V DD , positive supply rail or above the reference voltage V REF1 and / or V REF2 ), the channel inversion charge will be removed. In addition, although the charge at the gate (node ​​G) of MOS capacitor 723 will not change when MOS varactor circuit 780 transitions into the second operation stage, the capacitance seen by the gate (node ​​G) of MOS capacitor 723 is the series connection of the gate capacitance and the diffusion capacitance in the bulk of the semiconductor biased to ground or another low voltage. Because the series connection of these capacitances is less than the individual contribution of the gate oxide capacitance and because the charge at the gate (node ​​G) of MOS capacitor 723 remains unchanged, the voltage at node G increases to the potential given by the following equations 2 and 3:

[0082] Where Equation 2

[0083]

[0084] The above discussion of MOS varactor circuit 780 ignores the fringing capacitance at the junction of the source and drain terminals of MOS capacitor 723, which should be kept to a minimum. In some embodiments of the present technology, a three-terminal device (e.g. Figure 8 The three-terminal device 881 described in can be used to reduce, minimize or eliminate the fringing capacitance at the junction of the source and drain terminals.

[0085] Reference again Figure 6 , in view of the above Figures 7A to 8 When the reset signal RST is asserted, the first transistor 621 is activated and corresponds to the voltage V output from the photocurrent / voltage converter 204. A The reference brightness level V C1 is sampled onto the second capacitor 624. At the reference brightness level V C1 During the sampling period of , the sample and hold signal S&H applied to the gate of the first transistor 671 of the varactor diode 670 can be asserted so that the bottom plates of the first and second capacitors 623 and 624 are biased to the reference voltage V through the first transistor 671. REF2 (eg, ground, a negative power rail, or another low reference potential). As discussed above, when the switch signal sw(m) is asserted, the second transistor 622 is activated and corresponds to the voltage V output by the photocurrent / voltage converter 604. A Brightness level V C2 is continuously sampled onto the second capacitor 624 for as long as the switch signal sw(m) remains asserted. C2 During the sampling period of , the sample and hold signal S&H applied to the gate of the first transistor 671 may be asserted again so that the bottom plates of the first and second capacitors 623 and 624 are biased to the reference voltage V through the first transistor 671. REF2 . When the brightness level V C2 After sampling onto the second capacitor 624, the switch signal sw(m) and the sample and hold signal S&H may be deasserted. In a non-overlapping manner, the signal Boost applied to the gate of the second transistor 672 of the varactor 670 may then be asserted to pull out the inverting change from the channel formed on the first and second capacitors 623 and 624. Subsequently, the capacitance of the first and second capacitors 623 and 624 seen by the gates of the first and second source follower transistors 625 and 626 decreases, resulting in a reference brightness level V C1 and brightness level V C2 Then, corresponding to the amplified reference brightness level V C1 and the amplified brightness level V C2 The complementary analog brightness level of can be read out from the event-driven pixel 620 and compared to detect whether an event has occurred in the external scene, as described above. Figure 2 and 5In this manner, event-driven pixel 620 may employ varactor 670 to provide passive signal amplification and noise reduction by cycling varactor 670 through inversion and accumulation phases.

[0086] Figures 9 to 12 1 and 12 are partial schematic diagrams of photocurrent / voltage converters 904, 1004, 1104, and 1204 configured according to various embodiments of the present technology. Photocurrent / voltage converters 904, 1004, 1104, and 1204 may each be configured in Figure 2 The event-driven pixel 220 is used to convert the photocurrent into a voltage, and is therefore described as being coupled to Figure 2 Each of the photocurrent / voltage converters 904, 1004, 1104, and 1204 can be used in other event-driven pixels of the present technology, including Figure 6 The event of drives pixel 620. Thus, each of photocurrent / voltage converters 904, 1004, 1104, and 1204 may be coupled to photosensor 602 or another photosensor of the present technology.

[0087] First reference Fig. 9 , the photocurrent / voltage converter 904 includes a transistor 991 having (a) a source coupled to the cathode of the photosensor 202 and (b) a drain coupled to a supply voltage (e.g., a positive power rail or another reference voltage). The gate of the transistor 991 is coupled to a bias voltage. In operation, the photocurrent / voltage converter 904 is configured to convert the photocurrent output by the photosensor 202 into a voltage V A , the voltage V A can be fed to a difference circuit (e.g., Figure 2 The difference circuit 206, Figure 6 , and / or another difference circuit of the present technology), as discussed above. More specifically, the photocurrent / voltage converter 904 is configured to generate a voltage V A , the voltage V A has a logarithmic or other (eg, linear, square root, etc.) relationship to the intensity of incident light received by photosensor 202 from the external scene.

[0088] Reference now Fig.10 , the photocurrent / voltage converter 1004 includes a transistor 1091 having (a) a drain coupled to a power supply voltage (e.g., a positive power rail or another reference voltage) and (b) a gate coupled to a bias voltage. The photocurrent / voltage converter 1004 further includes a plurality of transistors 1092 stacked in series with each other (in Fig.10The first transistor 1092a of the plurality of transistors includes a source coupled to the cathode of the photosensor 202, and the nth transistor 1092n of the plurality of transistors includes a source coupled to the source of the transistor 1091 and the photocurrent / voltage converter 1004 generates a voltage V at the source. A The drain of the output of the photocurrent / voltage converter 1004.

[0089] As shown, each of the first to nth transistors 1092a to 1092n includes a gate configured to receive a corresponding bias voltage. The bias voltages applied to the gates of the first to nth transistors 1092a to 1092n may be the same, or at least some of the bias voltages may be different from each other. The bias voltages applied to the gates of the first to nth transistors 1092a to 1092n may operate the first to nth transistors 1092a to 1092n in weak inversion, so that the first to nth transistors 1092a to 1092n provide signal amplification. In other words, the first to nth transistors 1092a to 1092n may be used to amplify the voltage V generated at the output (node ​​A) of the photocurrent / voltage converter 1004. A .

[0090] Reference now Fig.11 , the photocurrent / voltage converter 1104 includes a transistor 1191 having (a) a source coupled to the cathode of the photosensor 202 and (b) a drain coupled to a power supply voltage (e.g., a positive power rail or another reference voltage). The photocurrent / voltage converter 1104 further includes an amplifier 1193 having: (a) an input (e.g., an inverting input) coupled to the cathode of the photosensor 202 and the source of the transistor 1191; and (b) an output coupled to (i) the photocurrent / voltage converter 1104 at which a voltage V is generated. A The output of the photocurrent-to-voltage converter 1104 and (ii) the gate of the transistor 1191. In some embodiments, the amplifier 1193 can be an operational amplifier (opamp) and / or can include another input (not shown), such as a non-inverting input, coupled to ground (e.g., a negative power rail or another reference voltage).

[0091] Amplifier 1193 can be used to increase the voltage V generated at the output of photocurrent / voltage converter 1104 between the source and gate of transistor 1191. A In other words, amplifier 1193 can be used in low-latency applications to increase the response speed of the difference circuit (e.g., Figure 2 The difference circuit 206, Figure 6 The difference circuit 606 or another difference circuit of the present technology) is based on the voltage VA At the speed at which it produces a differential difference signal.

[0092] like Fig.11 As shown in FIG. 1 , amplifier 1193 may be configured to receive an enable signal EN . Enable signal EN Can be used to selectively enable or disable amplifier 1193. For example, the enable signal EN Sometimes it can be used to selectively disable amplifier 1193 or place amplifier 1193 in a power-down mode when the corresponding event-driven pixel is not sampling the reference signal or outputting the differential difference signal (thereby reducing the power consumption of the corresponding event-driven pixel) and sometimes it can be used to selectively enable amplifier 1193 or place amplifier 1193 in a power-up mode when the corresponding event-driven pixel is sampling the reference signal or is expected to output the differential difference signal on the column line (for example, when the row select signal rsel(m) is asserted). In some embodiments, amplifier 1193 may need time to stabilize. In these embodiments, enable signal EN may be asserted a given time before the differential difference signal is read out from the corresponding event-driven pixel onto the column line.

[0093] Reference now Fig.12 , the photocurrent / voltage converter 1204 represents Fig.10 The photocurrent / voltage converter 1004 and Fig.11 More specifically, the photocurrent / voltage converter 1204 includes a transistor 1291, a plurality of transistors 1292 (in Fig.12 1292a to 1292n) and an amplifier 1293. Multiple transistors 1292 are stacked in series with each other. A first transistor 1292a of the multiple transistors includes a source coupled to a cathode of the photosensor 202 and an input (e.g., an inverting input) of the amplifier 1293. An nth transistor 1292n of the multiple transistors includes a drain coupled to the source of transistor 1291. Amplifier 1293 includes an output that is coupled to (i) a photocurrent / voltage converter 1204 at which a voltage V is generated. A The output of the photocurrent-to-voltage converter 1204 and (ii) the gate of the transistor 1291. In some embodiments, the amplifier 1293 can be an operational amplifier (opamp) and / or can include another input (not shown), such as a non-inverting input, coupled to ground (e.g., a negative power rail or another reference voltage). The transistor 1291 includes a drain coupled to a supply voltage (e.g., a positive power rail or another reference voltage).

[0094] Similar to Fig.10 The first to n-th transistors 1092a to 1092n of the photocurrent / voltage converter 1004, Fig.12 Each of the first to nth transistors 1292a to 1292n includes a gate configured to receive a corresponding bias voltage. The bias voltages applied to the gates of the first to nth transistors 1292a to 1292n may be the same, or at least some of the bias voltages may be different from each other. The bias voltages applied to the gates of the first to nth transistors 1292a to 1292n may operate the first to nth transistors 1292a to 1292n in weak inversion, so that the first to nth transistors 1292a to 1292n provide signal amplification, as discussed above.

[0095] Similar to Fig.11 The amplifier 1193 of the photocurrent / voltage converter 1104 can be used to increase the voltage V generated at the output of the photocurrent / voltage converter 1204 between the source and gate of the transistor 1191. A In other words, amplifier 1293 can be used in low-latency applications to improve the response speed of the difference circuit corresponding to the event-driven pixel (e.g., Figure 2 The difference circuit 206, Figure 6 The difference circuit 606 or another difference circuit of the present technology) is based on the voltage V A In addition or alternatively, amplifier 1293 may be configured to receive an enable signal EN , and the above Fig.11 Consistent with the discussion of amplifier 1193 of photocurrent / voltage converter 1104, amplifier 1293 may be selectively enabled or disabled (eg, to reduce power consumption of photocurrent / voltage converter 1204 and thus power consumption of a corresponding event-driven pixel).

[0096] C. in conclusion

[0097] The above detailed description of the embodiments of the present technology is not intended to be exhaustive or to limit the technology to the precise form disclosed above. Although specific embodiments and examples of the present technology are described above for illustrative purposes, those skilled in the relevant art will recognize that various equivalent modifications are possible within the scope of the present technology. For example, although the steps are presented in the order given above, alternative embodiments may perform the steps in a different order. In addition, the various embodiments described herein may also be combined to provide additional embodiments.

[0098] It should be understood from the foregoing that the specific embodiments of the present technology have been described herein for illustrative purposes, but the well-known structures and functions are not shown or described in detail to avoid unnecessary blurring of the description of the embodiments of the present technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is clearly limited to mean excluding only a single item of other items in a list of two or more than two items, the use of "or" in this list should be interpreted as including any single item in the list of (a), all items in the list of (b) or any combination of items in the list of (c). In addition, as used herein, the phrase "and / or" as in "A and / or B" refers to only A, only B and both A and B. In addition, the use of the terms "including", "including", "having" and "having" throughout the text means at least including the features, so that any larger number of identical features and / or other features of additional types are not excluded. In addition, as used herein, the phrases "based on", "depending on", "as a result of..." and "in response to" should not be interpreted as reference conditional closed sets. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on" or the phrase "based at least in part on." Moreover, the terms "connected" and "coupled" may be used interchangeably herein and refer to both direct and indirect connections or couplings. For example, element A being "connected" or "coupled" to element B may mean that (i) A is directly "connected" or "coupled" to B and / or (ii) A is indirectly "connected" or "coupled" to B, where the context permits.

[0099] It should also be understood from the foregoing that various modifications can be made without departing from the present disclosure or the present technology. For example, it should be understood by those of ordinary skill in the art that the various components of the present technology can be further divided into subcomponents, or the various components and functions of the present technology can be combined and integrated. In addition, certain aspects of the present technology described in the context of a particular embodiment may also be combined or eliminated in other embodiments. In addition, although the advantages associated with certain embodiments of the present technology have been described in the context of the embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments that are not explicitly shown or described herein.

Claims

1. An event-driven pixel, comprising: a photosensor configured to generate a photocurrent in response to incident light received from an external scene; a photocurrent / voltage converter coupled to the photosensor to convert the photocurrent into a voltage; and a difference circuit coupled to the photocurrent-to-voltage converter, wherein the difference circuit comprises: a first circuit branch configured to (i) sample the voltage to generate a reference brightness level based at least in part on an assertion of a reset signal applied to the event-driven pixel and (ii) output a first analog brightness level on a first column line, wherein the first analog brightness level is based at least in part on the reference brightness level, and a second circuit branch configured to (i) sample the voltage to produce a brightness level based at least in part on an assertion of a switch signal applied to the event-driven pixel and (ii) output a second analog brightness level on a second column line, wherein the second analog brightness level is based at least in part on the brightness level, Wherein a difference between the second analog brightness level and the first analog brightness level indicates whether the event-driven pixel has detected an event in the external scene.

2. The event-driven pixel according to claim 1, wherein: The first circuit branch comprises: a row select transistor coupled to the first column line and configured to receive a row select signal at a gate of the row select transistor, a source follower transistor coupled to the row select transistor, a capacitor coupled to the gate of the source follower transistor, and a transistor having a drain coupled to the photocurrent-to-voltage converter, a source coupled to the capacitor and the gate of the source follower transistor, and a gate configured to receive the reset signal; and The first circuit branch is configured to sample the voltage to generate the reference brightness level onto the capacitor.

3. The event-driven pixel of claim 2, wherein the capacitor is coupled between (a) the gate of the source follower transistor and the source of the transistor and (b) ground.

4. The event-driven pixel of claim 1 , wherein: The second circuit branch comprises: a row select transistor coupled to the second column line and configured to receive a row select signal at a gate of the row select transistor, a source follower transistor coupled to the row select transistor, a capacitor coupled to the gate of the source follower transistor, and a transistor having a drain coupled to the photocurrent-to-voltage converter, a source coupled to the capacitor and the gate of the source follower transistor, and a gate configured to receive the switching signal; and The second circuit branch is configured to sample the voltage to produce the brightness level onto the capacitor.

5. The event-driven pixel of claim 4, wherein the capacitor is coupled between (a) the gate of the source follower transistor and the source of the transistor and (b) ground. 6 . The event-driven pixel of claim 1 , wherein the switch signal is supplied to a plurality of event-driven pixels in an event-driven pixel row including the event-driven pixel.

7. The event-driven pixel of claim 1 , further comprising: A varactor is coupled to (a) a first capacitor of the first circuit branch and (b) a second capacitor of the second circuit branch.

8. The event-driven pixel of claim 7, wherein the varactor diode comprises: a first transistor having a gate configured to receive a sample and hold signal, wherein the first transistor is coupled between (i) a first reference voltage and (ii) the first capacitor or the second capacitor; and A second transistor has a gate configured to receive a boosted signal, wherein the second transistor is coupled between (i) a second reference voltage and (ii) the first capacitor or the second capacitor.

9. The event-driven pixel of claim 7, wherein the first and second capacitors are coupled in parallel with each other between (a) the photocurrent-to-voltage converter and (b) the varactor diode.

10. The event-driven pixel of claim 1, further comprising a reset control circuit coupled to the difference circuit, wherein the reset control circuit is configured to: initializing the difference circuit in response to assertion of a global reset signal applied to the reset control circuit; and The difference circuit is reset in response to a combination of: (a) assertion of a row select signal applied to the reset control circuit; and (b) assertion of a confirmation signal applied to the reset control circuit when the difference between the second analog brightness level and the first analog brightness level indicates that the event-driven pixel has detected the event in the external scene.

11. The event-driven pixel of claim 10, wherein: The reset control circuit comprises: an AND logic gate having a first input configured to receive the row select signal and a second input configured to receive the confirmation signal, and an OR logic gate having a first input coupled to the output of the AND logic gate, a second input configured to receive the global reset signal, and an output coupled to the output of the reset control circuit; and The output of the reset control circuit is coupled to the first branch of the difference circuit and is configured to apply the reset signal to the first branch of the difference circuit.

12. The event-driven pixel of claim 10, wherein: The reset control circuit comprises: a NAND logic gate having a first input configured to receive the row select signal and a second input configured to receive the confirm signal, at least one pass transistor coupled to the output of the NAND logic gate and configured to receive the global reset signal, and a low activity switch configured to couple a supply voltage to an output of the reset control circuit based at least in part on the output of the NAND logic gate, the output of the at least one pass transistor, or a combination thereof; and The output of the reset control circuit is coupled to the first branch of the difference circuit and is configured to apply the reset signal to the first branch of the difference circuit.

13. The event-driven pixel of claim 1 , wherein: The photocurrent / voltage converter includes a first transistor having a drain coupled to a supply voltage, a source coupled to the photosensor, and a gate coupled to a first bias potential; and The photocurrent / voltage converter generates the voltage between the source of the first transistor and the photosensor.

14. The event-driven pixel of claim 13, wherein: The photocurrent / voltage converter further includes a plurality of second transistors arranged in series between the photosensor and the source of the first transistor; Each of the second transistors has a gate coupled to a corresponding bias potential; and The photocurrent / voltage converter generates the voltage between the source of the first transistor and terminals of the plurality of second transistors arranged in series with respect to the photosensor.

15. The event-driven pixel of claim 1, wherein: The photocurrent / voltage converter comprises: a transistor having a source coupled to the photosensor and a drain coupled to a supply voltage, and an amplifier having an input coupled to the photosensor and the source of the transistor and an output coupled to a gate of the transistor; and The photocurrent-to-voltage converter generates the voltage at the output of the amplifier.

16. The event-driven pixel of claim 15, wherein the amplifier is configured to receive an enable signal to selectively enable the amplifier.

17. The event-driven pixel of claim 15, wherein: The photocurrent / voltage converter further includes a plurality of second transistors arranged in series between (a) the photosensor and the input of the amplifier and (b) the source of the transistor; and Each of the second transistors has a gate coupled to a corresponding bias potential.

18. A method for operating an event-driven pixel, the method comprising: photogenerating a photocurrent with a photosensor in response to receiving incident light from an external scene; converting the photocurrent into a first voltage; generating a differential difference signal based at least in part on the first voltage, wherein generating the differential difference signal comprises: (a) sampling the first voltage to generate a reference brightness level onto a first capacitor of a difference circuit of the event-driven pixel; (b) generating a first analog brightness level based at least in part on the reference brightness level using a first source follower transistor of the difference circuit; (c) sampling the first voltage to generate a brightness level onto a second capacitor of the difference circuit; and (d) generating a second analog brightness level using a second source follower transistor of the difference circuit, wherein a difference between the second analog brightness level and the first analog brightness level indicates whether the event-driven pixel has detected an event in the external scene; and The differential difference signal is output in response to assertion of a row select signal, wherein outputting the differential difference signal includes: (i) outputting the first analog brightness level onto a first column line; and (ii) outputting the second analog brightness level onto a second column line.

19. The method of claim 18, wherein sampling the first voltage to generate the reference brightness level onto the first capacitor comprises asserting a reset signal applied to the difference circuit such that the voltage on the first capacitor tracks the first voltage.

20. The method of claim 19, further comprising asserting a switch signal applied to the difference circuit whenever the reset signal is asserted such that a voltage on the second capacitor tracks the first voltage while the voltage on the first capacitor tracks the first voltage.

21. The method of claim 18, wherein sampling the first voltage to generate the reference brightness level comprises biasing a bottom plate of the first capacitor to a low reference potential based at least in part on assertion of a sample and hold signal S&H applied to a varactor of the event-driven pixel.

22. The method of claim 18, wherein sampling the first voltage to generate the brightness level onto the second capacitor comprises asserting a switch signal applied to the difference circuit such that the voltage on the second capacitor tracks the first voltage.

23. The method of claim 18, wherein sampling the first voltage to produce the brightness level includes biasing a bottom plate of the second capacitor to a low reference potential based at least in part on assertion of a sample and hold signal S&H applied to a varactor of the event-driven pixel.

24. The method of claim 18, wherein outputting the differential difference signal comprises amplifying the reference brightness level and the brightness level based at least in part on assertion of a boost signal applied to a varactor of the event-driven pixel, wherein amplifying the reference brightness level and the brightness level comprises reducing capacitance of the first and second capacitors.

25. The method of claim 18, further comprising: asserting a confirmation signal when the difference between the second analog brightness level and the first analog brightness level exceeds a threshold; and In response to an overlap of (a) the assertion of the row select signal and (b) the assertion of the verify signal, the difference circuit is reset.

26. The method of claim 25, wherein resetting the difference circuit comprises: asserting a reset signal applied to the difference circuit such that the voltage on the first capacitor tracks the first voltage; and The first voltage is sampled based at least in part on the assertion of the reset signal to produce a new reference brightness level on a first capacitor.

27. The method of claim 26, wherein resetting the difference circuit comprises: continuously outputting the differential difference signal in response to the assertion of the row select signal; and After asserting the confirmation signal and until after de-asserting the reset signal, a result of a comparison between (a) the difference between the second analog brightness level and the first analog brightness level and (b) the threshold is ignored.

28. The method of claim 18, further comprising: comparing the difference between the second analog brightness level and the first analog brightness level with a threshold; and Resetting of the difference circuit is prevented when (a) the row select signal is asserted, (b) a global reset signal is not asserted, and (c) the difference between the second analog brightness level and the first analog brightness level does not exceed the threshold.

29. The method of claim 28, further comprising generating the difference between the second analog brightness level and the first analog brightness level at an output of an amplifier, wherein generating the difference includes auto-zeroing the amplifier.

30. The method of claim 18, further comprising initializing the difference circuit, wherein initializing the difference circuit comprises asserting a global reset signal applied to the event-driven pixels.

31. The method of claim 18, wherein converting the photocurrent to the first voltage comprises converting the photocurrent to the first voltage using a photocurrent / voltage converter of the event-driven pixel, and wherein the method further comprises selectively disabling an amplifier of the photocurrent / voltage converter when light generates the photocurrent.

32. An imaging system comprising: Event-driven pixels, which include: a photodetector configured to generate a photocurrent in response to incident light received from an external scene; a photocurrent / voltage converter coupled to the photodetector to convert the photocurrent into a voltage, and a difference circuit coupled to the photocurrent-to-voltage converter, wherein the difference circuit is configured to: (i) sample the voltage to generate a reference brightness level onto a first capacitor; (ii) outputting a first analog brightness level based at least in part on the reference brightness level onto a first column line; (iii) sampling the voltage to generate a brightness level onto a second capacitor; and (iv) outputting a second analog brightness level based at least in part on the brightness level onto a second column line, wherein a difference between the second analog brightness level and the first analog brightness level indicates whether the event-driven pixel has detected an event in the external scene; a threshold comparison circuit coupled to the first and second column lines and configured to compare the difference between the second analog brightness level and the first analog brightness level to one or more thresholds; and a control circuit coupled to the threshold comparison circuit and the event-driven pixel, wherein the control circuit is configured to, when the difference between the second analog brightness level and the first analog brightness level exceeds a threshold value among the one or more threshold values: (i) register that the event-driven pixel has detected the event; and (ii) initiating a reset of the difference circuit of the event-driven pixel so that a new reference brightness level is sampled from the voltage onto the first capacitor.

33. The imaging system of claim 32, wherein: The threshold comparison circuit comprises: an amplifier having a first input coupled to the first column line and a second input coupled to the second column line, the amplifier being configured to produce the difference between the second analog brightness level and the first analog brightness level at an output of the amplifier, a first comparator having an input coupled to the output of the amplifier and an output coupled to the control circuit, the first comparator being configured to compare (a) the difference between the second analog brightness level and the first analog brightness level with (b) a first threshold value of the one or more threshold values, and a second comparator having an input coupled to the output of the amplifier and an output coupled to the control circuit, the second comparator configured to compare (a) the difference between the second analog brightness level and the first analog brightness level with (b) a second threshold of the one or more thresholds; and The amplifier comprises an analog difference amplifier or a differential analog-to-digital converter.

34. The imaging system of claim 32, wherein: The event-driven pixel further comprises a varactor diode; and The first capacitor and the second capacitor are coupled in parallel with each other between (a) an output of the photocurrent / voltage converter and (b) the varactor diode.

Images