Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a plurality of scanning lines, a plurality of data lines and a plurality of sub-pixels. The plurality of scanning lines are arranged along a first direction. The plurality of data lines are arranged along a second direction. The second direction intersects the first direction. Each scanning line is electrically connected with a row of sub-pixels arranged along the second direction. The plurality of sub-pixels comprise a first pixel column and a second pixel column. The first pixel column and the second pixel column are arranged adjacent to each other along the second direction. The first pixel column comprises a plurality of first pixel units arranged along the first direction. The second pixel column comprises a plurality of second pixel units arranged along the first direction. The first pixel unit and the second pixel unit each comprise three sub-pixels arranged along the first direction. The colors of the three sub-pixels are different from each other. At least two adjacent first pixel units and at least two adjacent second pixel units are electrically connected with the same data line, so as to improve the problem of display abnormality caused by pixel misalignment display.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Currently, display panels can meet users' daily viewing needs while also supporting high refresh rate display requirements in entertainment modes. However, existing ultra-high-definition display panels with a tri-gate 3-dot flip architecture are prone to pixel misalignment when switching from a low refresh rate (e.g., 60 Hz) to a high refresh rate (e.g., 120 Hz), leading to display abnormalities. Summary of the Invention

[0003] This application provides a display panel and a display device that can improve the display abnormality caused by pixel misalignment when the display panel switches from a first preset refresh rate to a second preset refresh rate.

[0004] On one hand, embodiments of this application provide a display panel, including: multiple scan lines, multiple data lines, and multiple sub-pixels; the multiple scan lines are arranged along a first direction; the multiple data lines are arranged along a second direction, which intersects the first direction; each scan line is electrically connected to a row of sub-pixels arranged along the second direction; the multiple sub-pixels include a first pixel column and a second pixel column, the first pixel column and the second pixel column are arranged adjacent to each other along the second direction; the first pixel column includes multiple first pixel units arranged along the first direction; the second pixel column includes multiple second pixel units arranged along the first direction; each first pixel unit and each second pixel unit includes three sub-pixels arranged along the first direction; the three sub-pixels have different colors; at least two adjacent first pixel units and at least two adjacent second pixel units are electrically connected to the same data line.

[0005] Optionally, in some embodiments of this application, the display panel includes at least a first display mode and a second display mode. In the first display mode, the refresh rate of the display panel is a first preset refresh rate. In the second display mode, the refresh rate of the display panel is a second preset refresh rate, where the second preset refresh rate is N times the first preset refresh rate, and N is a positive integer greater than 1. In the second display mode, at least two adjacent first pixel units electrically connected to the same data line have sub-pixels of the same color that are simultaneously turned on, or at least two adjacent second pixel units electrically connected to the same data line have sub-pixels of the same color that are simultaneously turned on.

[0006] Optionally, in some embodiments of this application, the time for the display panel to display one frame of the display image includes a scanning cycle, the scanning cycle including a first sub-scanning cycle and a second sub-scanning cycle that are consecutive in time, and the number of the first pixel units that are scanned in the first sub-scanning cycle is equal to the number of the second pixel units that are scanned in the second sub-scanning cycle.

[0007] Optionally, in some embodiments of this application, both the first pixel unit and the second pixel unit include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along the first direction; the display panel further includes a cascaded first gate driving unit, a second gate driving unit, and a third gate driving unit, wherein the first gate driving unit receives a first clock signal and is electrically connected to the corresponding first sub-pixel through the scan line, the second gate driving unit receives a second clock signal and is electrically connected to the corresponding second sub-pixel through the scan line, and the third gate driving unit receives a third clock signal and is electrically connected to the corresponding third sub-pixel through the scan line; the time difference between the time for the first clock signal to switch from a low potential to a high potential and the time for the second clock signal to switch from a low potential to a high potential is between 2 microseconds and 3 microseconds, and the time difference between the time for the second clock signal to switch from a low potential to a high potential and the time for the third clock signal to switch from a low potential to a high potential is between 2 microseconds and 3 microseconds.

[0008] Optionally, in some embodiments of this application, the second clock signal is turned on while the first clock signal is held at a high level, and the second clock signal is turned off while the third clock signal is held at a high level, wherein the third clock signal switches from a low level to a high level when the first clock signal switches from a high level to a low level.

[0009] Optionally, in some embodiments of this application, every two first pixel units are arranged adjacent to each other along the first direction, every two second pixel units are arranged adjacent to each other along the first direction, and at least some of the first pixel units and the second pixel units are arranged alternately along the first direction.

[0010] Optionally, in some embodiments of this application, the first clock signal switches from a low potential to a high potential while the third clock signal remains at a high potential.

[0011] Optionally, in some embodiments of this application, the number of the first pixel units electrically connected to the same data line and the number of the second pixel units are equal.

[0012] Optionally, in some embodiments of this application, the data signals transmitted by two adjacent data lines have opposite polarities, and at least some of the data lines input data signals to the corresponding sub-pixels at different times.

[0013] On the other hand, this application provides a display device, including a display panel and a driving circuit as described above, wherein the display panel is electrically connected to the driving circuit, and the driving circuit is used to drive the display panel.

[0014] Optionally, in some embodiments of this application, the driving circuit includes a system chip and a timing controller. The system chip is electrically connected to the timing controller, and the timing controller is electrically connected to the display panel. The system chip is used to send a command to the timing controller to switch the refresh rate. The timing controller is used to send a feedback signal to the system chip according to the command to switch the refresh rate. The system chip is also used to determine whether the current refresh rate is the same as the switched refresh rate based on the feedback signal. If the current refresh rate is not the same as the switched refresh rate, the system chip sends driving data corresponding to the switched refresh rate to the timing controller. The timing controller is also used to provide the display panel with a scan signal and a data signal corresponding to the switched refresh rate based on the driving data, so as to control the display panel to display the image.

[0015] The display panel provided in this application includes: multiple scan lines, multiple data lines, and multiple sub-pixels. The multiple scan lines are arranged along a first direction; the multiple data lines are arranged along a second direction, which intersects with the first direction; each scan line is electrically connected to a row of sub-pixels arranged along the second direction; the multiple sub-pixels include a first pixel column and a second pixel column, which are arranged adjacent to each other along the second direction; the first pixel column includes multiple first pixel units arranged along the first direction; the second pixel column includes multiple second pixel units arranged along the first direction; each first pixel unit and each second pixel unit includes three sub-pixels arranged along the first direction, and the three sub-pixels have different colors; at least two adjacent first pixel units and at least two adjacent second pixel units are electrically connected to the same data line. The display panel provided in this application, through the above-described configuration, allows at least two adjacent first pixel units and at least two adjacent second pixel units to be electrically connected on the same data line. This enables the display panel to simultaneously scan sub-pixels of the same color in at least two first pixel units located in the first pixel column, or simultaneously scan sub-pixels of the same color in at least two second pixel units located in the second pixel column, when switching from a first preset refresh rate to a second preset refresh rate. This controls the multiple sub-pixels simultaneously displayed by the display panel at the second preset refresh rate to be located in the same pixel column, thereby avoiding pixel misalignment and improving the display abnormality caused by pixel misalignment. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the display panel provided in the first embodiment of this application;

[0017] Figure 2 This is a first driving timing diagram of a display panel provided in an embodiment of this application;

[0018] Figure 3 This is a second driving timing diagram of the display panel provided in an embodiment of this application;

[0019] Figure 4 This is a schematic diagram of the display panel provided in the second embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the display panel provided in the third embodiment of this application;

[0021] Figure 6 This is a schematic diagram of a display device provided in an embodiment of this application;

[0022] Figure 7 This is a first driving principle diagram of a display device provided in an embodiment of this application;

[0023] Figure 8 This is a second driving principle diagram of the display device provided in the embodiments of this application. Detailed Implementation

[0024] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0025] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0026] In embodiments of this application, the display panel includes at least a first display mode and a second display mode. The first display mode corresponds to a first preset refresh rate. The second display mode corresponds to a second preset refresh rate. The first preset refresh rate is less than the second preset refresh rate, and the second preset refresh rate is N times the first preset refresh rate, where N is a positive integer greater than 1, for example, N is 1, 2, 3, 4... Specifically, the value range of the first preset refresh rate includes 0 Hz to 100 Hz, that is, the value of the first preset refresh rate includes 0 Hz, 10 Hz, 20 Hz, 30 Hz, 40 Hz, 50 Hz, 60 Hz, 70 Hz, 80 Hz, 90 Hz, and 100 Hz. Preferably, the value of the first preset refresh rate is 60 Hz.

[0027] In embodiments of this application, the second preset refresh frequency ranges from 110 Hz to 360 Hz, specifically 110 Hz, 120 Hz, 130 Hz, 140 Hz, 150 Hz, 160 Hz, 170 Hz, 180 Hz, 190 Hz, 200 Hz, 210 Hz, 220 Hz, 230 Hz, 240 Hz, 250 Hz, 260 Hz, 270 Hz, 280 Hz, 290 Hz, 300 Hz, 310 Hz, 320 Hz, 330 Hz, 340 Hz, 350 Hz, and 360 Hz. Preferably, the second preset refresh frequency is 120 Hz.

[0028] like Figure 1As shown, an embodiment of this application provides a display panel 100, including: multiple scan lines G, multiple data lines D, and multiple sub-pixels 10. The multiple scan lines G are arranged along a first direction Y. The multiple data lines D are arranged along a second direction X, which intersects with the first direction Y. Each scan line G is electrically connected to a row of sub-pixels 10 arranged along the second direction X. The multiple sub-pixels 10 are divided into a first pixel column 101 and a second pixel column 102. The first pixel column 101 and the second pixel column 102 are arranged adjacent to each other along the second direction X. The first pixel column 101 includes multiple first pixel units 20 arranged along the first direction Y, and the second pixel column 102 includes multiple second pixel units 30 arranged along the first direction Y. Each first pixel unit 20 and each second pixel unit 30 includes three sub-pixels 10 arranged along the first direction Y, and the three sub-pixels 10 have different colors. At least two adjacent first pixel units 20 and at least two adjacent second pixel units 30 are electrically connected to the same data line D.

[0029] The display panel 100 provided in the embodiments of this application electrically connects at least two adjacent first pixel units 20 and at least two adjacent second pixel units 30 to the same data line D, so that when the display panel 100 switches from a first preset refresh rate to a second preset refresh rate, it can simultaneously scan sub-pixels 10 of the same color in at least two first pixel units 20 located in the first pixel column 101, or simultaneously scan sub-pixels 10 of the same color in at least two second pixel units 30 located in the second pixel column 102. This controls the multiple sub-pixels 10 displayed simultaneously by the display panel 100 at the second preset refresh rate to be located in the same pixel column, so as to avoid the phenomenon of pixel misalignment display and improve the display abnormality caused by pixel misalignment display.

[0030] In the embodiments of this application, every two first pixel units 20 are arranged adjacently along the first direction Y, and every two second pixel units 30 are arranged adjacently along the first direction Y, and every two first pixel units 20 and every two second pixel units 30 are arranged alternately along the first direction Y. Specifically, every M first pixel units 20 are adjacent along the first direction Y, and every M second pixel units 30 are adjacent along the first direction Y, and every M first pixel units 20 and every M second pixel units 30 are arranged alternately along the first direction Y, where M is a positive integer greater than or equal to 2, for example, M is 2, 3, 4...

[0031] In the embodiments of this application, the number of adjacent first pixel units 20 along the first direction Y can be adjusted according to the second preset refresh rate value of the display panel 100 (the first preset refresh rate value is 60 Hz). For example, when the second preset refresh rate value of the display panel 100 is 120 Hz, the number of adjacent first pixel units 20 along the first direction Y is 2N. When the second preset refresh rate value of the display panel 100 is 180 Hz, the number of adjacent first pixel units 20 along the first direction Y is 3N. When the second preset refresh rate value of the display panel 100 is 240 Hz, the number of adjacent first pixel units 20 along the first direction Y is 4N. When the second preset refresh rate value of the display panel 100 is 360 Hz, the number of adjacent first pixel units 20 along the first direction Y is 6N. N is a positive integer greater than or equal to 1, for example, N is 1, 2, 3, 4...

[0032] The number of adjacent second pixel units 30 along the first direction Y corresponds to the number of adjacent first pixel units 20 along the first direction Y. For example, if the number of adjacent first pixel units 20 along the first direction Y is 2N, then the number of adjacent second pixel units 30 along the first direction Y is also 2N. If the number of adjacent first pixel units 20 along the first direction Y is 3N, then the number of adjacent first pixel units 20 along the first direction Y is also 3N. This avoids display abnormalities caused by pixel misalignment at the second preset refresh rate. Furthermore, the staggered arrangement of the first pixel units 20 and second pixel units 30 along the first direction Y reduces the loss of display resolution and ensures the display quality of the display panel 100.

[0033] In embodiments of this application, the display panel includes at least a first display mode and a second display mode. In the first display mode, the refresh rate of the display panel is a first preset refresh rate, and in the second display mode, the refresh rate of the display panel is a second preset refresh rate, which is N times the first preset refresh rate, where N is a positive integer greater than 1. For example, the first preset refresh rate is 60 Hz, and the second preset refresh rate is 120 Hz. In the second display mode, sub-pixels 10 of the same color in at least two adjacent first pixel units 20 electrically connected to the same data line D are simultaneously turned on. For example, red sub-pixels 10 in two adjacent first pixel units 20 electrically connected to the same data line D are simultaneously turned on. Alternatively, sub-pixels 10 of the same color in at least two adjacent second pixel units 30 electrically connected to the same data line D are simultaneously turned on. For example, green sub-pixels 10 in two adjacent second pixel units 30 electrically connected to the same data line D are simultaneously turned on.

[0034] In the embodiments of this application, the first sub-pixel row, the second sub-pixel row, and the third sub-pixel row are each electrically connected to a scan line G.

[0035] In embodiments of this application, the display panel 100 further includes a first gate driving unit (GOA1, GOA4, GOA7, GOA10...), a second gate driving unit (GOA2, GOA5, GOA8, GOA11...), and a third gate driving unit (GOA3, GOA6, GOA9, GOA12...) connected in cascade. Multiple first gate driving units GOA1, second gate driving units GOA2, and third gate driving units GOA3, arranged along the first direction Y, are electrically connected to clock signal lines (CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK9, CK10, CK11, CK12...). The clock signal lines (CK1, CK4, CK7, CK10...) input first clock signals (ck1, ck4, ck7, ck10...) to the first gate driving unit GOA1, the clock signal lines (CK2, CK5, CK8, CK11...) input second clock signals (ck2, ck5, ck8, ck11...) to the second gate driving unit GOA2, and the clock signal lines (CK3, CK6, CK9, CK12...) input third clock signals (ck3, ck6, ck9, ck12...) to the third gate driving unit GOA3.

[0036] In the embodiments of this application, both the first pixel unit 20 and the second pixel unit 30 include a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13 arranged along the first direction Y. A first gate driving unit (GOA1, GOA4, GOA7, GOA10...) receives a first clock signal (ck1, ck4, ck7, ck10...) and is electrically connected to the corresponding first sub-pixel 11 via a scan line G. A second gate driving unit (GOA2, GOA5, GOA8, GOA11...) receives a second clock signal (ck2, ck5, ck8, ck11...) and is electrically connected to the corresponding second sub-pixel 12 via a scan line G. A third gate driving unit (GOA3, GOA6, GOA9, GOA12...) receives a third clock signal (ck3, ck6, ck9, ck12...) and is electrically connected to the corresponding third sub-pixel 13 via a scan line G. In the first clock signal, second clock signal, and third clock signal connected to the adjacent first gate driving unit, second gate driving unit, and third gate driving unit, the time difference between the first clock signal (ck1, ck4, ck7, ck10...) switching from low potential to high potential and the time difference between the second clock signal (ck2, ck5, ck8, ck11...) switching from low potential to high potential is between 2 microseconds and 3 microseconds, and the time difference between the second clock signal (ck2, ck5, ck8, ck11...) switching from low potential to high potential and the time difference between the third clock signal (ck3, ck6, ck9, ck12...) switching from low potential to high potential is between 2 microseconds and 3 microseconds.

[0037] Specifically, this application does not specifically limit the number of clock signal lines. Those skilled in the art can adjust the number of clock signal lines according to actual needs. For example, the number of clock signal lines can be 6, 8, or 10, etc.

[0038] Specifically, the colors of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are all different; for example, the colors of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are red, green, and blue, respectively. Multiple sub-pixels 10 are divided into multiple repeating sub-pixel rows, each including a first sub-pixel row, a second sub-pixel row, and a third sub-pixel row. The first sub-pixel row includes multiple first sub-pixels 11, the second sub-pixel row includes multiple second sub-pixels 12, and the third sub-pixel row includes multiple third sub-pixels 13. Data line D is electrically connected to a corresponding column of sub-pixels 10.

[0039] In the embodiments of this application, the number of first pixel units 20 and the number of second pixel units 30 electrically connected to the same data line D are equal. Specifically, the number of first pixel units 20 electrically connected to each data line D is equal to the number of second pixel units 30.

[0040] In the embodiments of this application, the data signals transmitted by two adjacent data lines D have opposite polarities, and at least some of the data lines D input data signals to the sub-pixel 10 at different times. By setting the polarities of the data signals transmitted by two adjacent data lines D to be opposite, the coupling capacitance between the sub-pixel 10 and the two adjacent data lines D can be canceled, thereby improving display quality. The different times at which at least some of the data lines D input data signals to the sub-pixel 10 result in different charging times for the sub-pixel 10, and consequently, different display times. This facilitates displaying a specified sub-pixel 10 within a preset time to display a preset display image.

[0041] like Figure 1 and Figure 2 As shown, at the first preset refresh rate, the first clock signal (ck1, ck4, ck7, ck10...), the second clock signal (ck2, ck5, ck8, ck11...), and the third clock signal (ck3, ck6, ck9, ck12...) of the display panel 100 sequentially switch from low to high potential in the order of (ck1, ck2, ck3, ck4, ck5, ck6, ck7, ck8, ck9, ck10, ck11, ck12...). Correspondingly, multiple scan lines G in the display panel are opened row by row, charging multiple sub-pixels 10 row by row.

[0042] like Figure 1 and Figure 3 As shown, the time for the display panel 100 to display a frame includes at least one scanning period T. The scanning period T includes a first sub-scanning period t01 and a second sub-scanning period t02 that are consecutive in time. The number of first pixel units 20 that are scanned in the first sub-scanning period t01 is equal to the number of second pixel units 30 that are scanned in the second sub-scanning period t02.

[0043] In embodiments of this application, the second clock signal (ck2, ck5, ck8, ck11...) is turned on while the corresponding first clock signal (ck1, ck4, ck7, ck10...) remains at a high level, and the second clock signal (ck2, ck5, ck8, ck11...) is turned off while the corresponding third clock signal (ck3, ck6, ck9, ck12...) remains at a high level. The third clock signal (ck3, ck6, ck9, ck12...) switches from a low level to a high level when the corresponding first clock signal (ck1, ck4, ck7, ck10...) switches from a high level to a low level. For example, the second clock signal ck2 is turned on while the corresponding first clock signal ck1 remains at a high level, and the second clock signal ck2 is turned off while the third clock signal ck3 remains at a high level. The third clock signal ck3 switches from a low level to a high level when the first clock signal ck1 switches from a high level to a low level.

[0044] In the embodiments of this application, during the first sub-scan cycle t01, the first clock signal lines (CK1 and CK4) simultaneously input high-level first clock signals (ck1 and ck4) to the corresponding first gate driving units (GOA1 and GOA4), thereby simultaneously turning on the sub-pixel 10 controlled by the first scan line G1 and the fourth scan line G4. Sequentially, the second clock signal lines (CK2 and CK5) simultaneously input high-level second clock signals (ck2 and ck5) to the corresponding second gate driving units (GOA2 and GOA5), thereby simultaneously turning on the sub-pixel 10 controlled by the second scan line G2 and the fifth scan line G5. The third clock signal lines (CK3 and CK6) simultaneously input high-level third clock signals (ck3 and ck6) to the corresponding third gate driving units (GOA3 and GOA6), thereby simultaneously turning on the sub-pixel 10 controlled by the third scan line G3 and the sixth scan line G6. During the second sub-scan cycle t02, the first clock signal lines (CK7 and CK10) simultaneously input high-level first clock signals (ck7 and ck10) to the corresponding first gate driving units (GOA7 and GOA10), thereby simultaneously turning on the sub-pixel 10 controlled by the seventh scan line G7 and the tenth scan line G10. Sequentially, the second clock signal lines (CK8 and CK11) simultaneously input high-level second clock signals (ck8 and ck11) to the corresponding second gate driving units (GOA8 and GOA11), thereby simultaneously turning on the sub-pixel 10 controlled by the eighth scan line G8 and the eleventh scan line G11. The third clock signal lines (CK9 and CK12) simultaneously input high-level third clock signals (ck9 and ck12) to the corresponding third gate driving units (GOA9 and GOA12), thereby simultaneously turning on the sub-pixel 10 controlled by the ninth scan line G9 and the twelfth scan line G12.

[0045] like Figure 4 As shown, an embodiment of this application provides a display panel 200. The display panel 200 differs from the display panel 100 in that: the display panel 200 includes a first display area AA1, a second display area AA2, and a third display area AA3 arranged along a first direction Y, with the second display area AA2 located between the first display area AA1 and the second display area AA2. The first display area AA1 and the third display area AA3 each have at least two first pixel units 20, and the second display area AA2 has at least two second pixel units 30.

[0046] In the embodiments of this application, the number of first pixel units 20 in the first display area AA1 and the third display area AA3 can be adjusted according to the second preset refresh rate value of the display panel (the first preset refresh rate value is 60 Hz). For example, when the second preset refresh rate value of the display panel 200 is 120 Hz, the number of first pixel units 20 in the first display area AA1 and the third display area AA3 is 2N. When the second preset refresh rate value of the display panel 200 is 180 Hz, the number of first pixel units 20 in the first display area AA1 and the third display area AA3 is 3N. When the second preset refresh rate value of the display panel 200 is 240 Hz, the number of first pixel units 20 in the first display area AA1 and the third display area AA3 is 4N. When the second preset refresh rate value of the display panel 200 is 360 Hz, the number of first pixel units 20 in the first display area AA1 and the third display area AA3 is 6N. The number of second pixel units 30 in the second display area AA2 corresponds to the number of first pixel units 20 in the first display area AA1. For example, if the number of first pixel units 20 in the first display area AA1 is 2N, then the number of second pixel units 30 in the second display area AA2 is also 2N. If the number of first pixel units 20 in the first display area AA1 is 3N, then the number of second pixel units 30 in the second display area AA2 is also 3N.

[0047] In the embodiments of this application, the area of ​​the second display area AA2 is larger than the area of ​​the first display area AA1, and the area of ​​the second display area AA2 is also larger than the area of ​​the third display area AA3. The areas of the first display area AA1 and the third display area AA3 are equal. Further, the areas of the first display area AA1 and the third display area AA3 may not be equal. Specifically, the number of first pixel units 20 in the first display area AA1 is less than the number of second pixel units 30 in the second display area AA2, and the number of first pixel units 20 in the third display area AA3 is less than the number of second pixel units 30 in the second display area AA2. Figure 2 As shown, the number of first pixel units 20 electrically connected to the same data line D is less than the number of second pixel units 30.

[0048] Specifically, the display panel 200 includes: multiple scan lines G, multiple data lines D, and multiple sub-pixels 10. The multiple scan lines G are arranged along a first direction Y. The multiple data lines D are arranged along a second direction X, which intersects with the first direction Y. The scan lines G are electrically connected to the multiple sub-pixels 10 arranged along the second direction X. The multiple sub-pixels 10 are divided into a first pixel column 101 and a second pixel column 102. The first pixel column 101 and the second pixel column 102 are arranged adjacent to each other along the second direction X. The first pixel column 101 includes multiple first pixel units 20 arranged along the first direction Y, and the second pixel column 102 includes multiple second pixel units 30 arranged along the first direction Y. At least two adjacent first pixel units 20 and at least two adjacent second pixel units 30 are electrically connected to the same data line D.

[0049] In embodiments of this application, both the first pixel unit 20 and the second pixel unit 30 include three sub-pixels 10 arranged along the first direction Y, and the three sub-pixels 10 have different colors. Specifically, the colors of the three sub-pixels 10 are red, green, and blue, respectively. The colors of the sub-pixels 10 can also be other colors.

[0050] In embodiments of this application, sub-pixels 10 of the same color in at least two adjacent first pixel units 20 electrically connected to the same data line D are simultaneously activated. For example, red sub-pixels 10 in two adjacent first pixel units 20 electrically connected to the same data line D are simultaneously activated. Alternatively, sub-pixels 10 of the same color in at least two adjacent second pixel units 30 electrically connected to the same data line D are simultaneously activated. For example, green sub-pixels 10 in two adjacent second pixel units 30 electrically connected to the same data line D are simultaneously activated.

[0051] Specifically, multiple sub-pixels 10 within each row of 10 sub-pixels have the same color. These rows of 10 sub-pixels are divided into multiple repeating sub-pixel rows. Each repeating sub-pixel row includes three adjacent rows of 10 sub-pixels with different colors; for example, a repeating sub-pixel row includes 10 rows of red sub-pixels, 10 rows of green sub-pixels, and 10 rows of blue sub-pixels. Each row of 10 sub-pixels is electrically connected to a scan line G. A data line D is electrically connected to the corresponding column of sub-pixels 10.

[0052] In the embodiments of this application, the number of first pixel units 20 and the number of second pixel units 30 electrically connected to the same data line D are equal. Specifically, the number of first pixel units 20 electrically connected to each data line D is equal to the number of second pixel units 30.

[0053] In the embodiments of this application, the data signals transmitted by two adjacent data lines D have opposite polarities, and at least some of the data lines D input data signals to the sub-pixel 10 at different times. By setting the polarities of the data signals transmitted by two adjacent data lines D to be opposite, the coupling capacitance between the sub-pixel 10 and the two adjacent data lines D can be canceled, thereby improving display quality. The different times at which at least some of the data lines D input data signals to the sub-pixel 10 result in different charging times for the sub-pixel 10, and consequently, different display times. This facilitates displaying a specified sub-pixel 10 within a preset time to display a preset display image.

[0054] The other structures of display panel 200 are the same as those of display panel 100, so they will not be described in detail here.

[0055] The display panel 200 provided in the embodiments of this application divides the display panel 200 into a first display area AA1, a second display area AA2, and a third display area AA3. The first display area AA1 and the third display area AA3 are provided with only a first pixel unit 20, and the second display area AA2 is provided with only a second pixel unit 30. The second display area AA2 is the central area of ​​the display panel 200, and the area of ​​the second display area AA2 is larger than that of the first display area AA1 and the third display area AA3. Meanwhile, at least two adjacent first pixel units 20 and at least two adjacent second pixel units 30 are electrically connected to the same data line D, so that when the display panel 200 switches from the first preset refresh rate to the second preset refresh rate, it can simultaneously scan the sub-pixels 10 of the same color in at least two first pixel units 20 located in the first pixel column 101, or simultaneously scan the sub-pixels 10 of the same color in at least two second pixel units 30 located in the second pixel column 102. This controls the multiple sub-pixels 10 displayed simultaneously by the display panel 200 at the second preset refresh rate to be located in the same pixel column, so as to avoid the phenomenon of pixel misalignment and improve the resolution of the display panel 200.

[0056] like Figure 5 As shown, an embodiment of this application provides a display panel 300. The display panel 300 differs from the display panel 100 in that the display panel 300 includes a first display area AA1 and a second display area AA2 adjacent along a first direction Y. The first display area AA1 is provided with at least two first pixel units 20, and the second display area AA2 is provided with at least two second pixel units 30.

[0057] In the embodiments of this application, the number of first pixel units 20 in the first display area AA1 can be adjusted according to the second preset refresh rate value of the display panel (the first preset refresh rate value is 60 Hz). For example, when the second preset refresh rate value of the display panel 300 is 120 Hz, the number of first pixel units 20 in the first display area AA1 is 2N. When the second preset refresh rate value of the display panel 300 is 180 Hz, the number of first pixel units 20 in the first display area AA1 is 3N. When the second preset refresh rate value of the display panel 300 is 240 Hz, the number of first pixel units 20 in the first display area AA1 is 4N. When the second preset refresh rate value of the display panel 300 is 360 Hz, the number of first pixel units 20 in the first display area AA1 is 6N. The number of second pixel units 30 in the second display area AA2 corresponds to the number of first pixel units 20 in the first display area AA1. For example, if the number of first pixel units 20 in the first display area AA1 is 2N, then the number of second pixel units 30 in the second display area AA2 is also 2N. If the number of first pixel units 20 in the first display area AA1 is 3N, then the number of second pixel units 30 in the second display area AA2 is also 3N.

[0058] In the embodiments of this application, the area of ​​the second display area AA2 is equal to the area of ​​the first display area AA1. Specifically, the area of ​​the first display area AA1 and the area of ​​the third display area AA3 may not be equal.

[0059] In embodiments of this application, the number of first pixel units 20 in the first display area AA1 is equal to the number of second pixel units 30 in the second display area AA2. The number of first pixel units 20 in the first display area AA1 may also be less than the number of second pixel units 30 in the second display area AA2. For example... Figure 3 As shown, the number of first pixel units 20 electrically connected to the same data line D is equal to the number of second pixel units 30.

[0060] Specifically, the display panel 300 includes: multiple scan lines G, multiple data lines D, and multiple sub-pixels 10. The multiple scan lines G are arranged along a first direction Y. The multiple data lines D are arranged along a second direction X, which intersects with the first direction Y. The scan lines G are electrically connected to the multiple sub-pixels 10 arranged along the second direction X. The multiple sub-pixels 10 are divided into a first pixel column 101 and a second pixel column 102. The first pixel column 101 and the second pixel column 102 are arranged adjacent to each other along the second direction X. The first pixel column 101 includes multiple first pixel units 20 arranged along the first direction Y, and the second pixel column 102 includes multiple second pixel units 30 arranged along the first direction Y. At least two adjacent first pixel units 20 and at least two adjacent second pixel units 30 are electrically connected to the same data line D.

[0061] In embodiments of this application, both the first pixel unit 20 and the second pixel unit 30 include three sub-pixels 10 arranged along the first direction Y, and the three sub-pixels 10 have different colors. Specifically, the colors of the three sub-pixels 10 are red, green, and blue, respectively. The colors of the sub-pixels 10 can also be other colors.

[0062] In embodiments of this application, sub-pixels 10 of the same color in at least two adjacent first pixel units 20 electrically connected to the same data line D are simultaneously activated. For example, red sub-pixels 10 in two adjacent first pixel units 20 electrically connected to the same data line D are simultaneously activated. Alternatively, sub-pixels 10 of the same color in at least two adjacent second pixel units 30 electrically connected to the same data line D are simultaneously activated. For example, green sub-pixels 10 in two adjacent second pixel units 30 electrically connected to the same data line D are simultaneously activated.

[0063] Specifically, multiple sub-pixels 10 within each row of 10 sub-pixels have the same color. These rows of 10 sub-pixels are divided into multiple repeating sub-pixel rows. Each repeating sub-pixel row includes three adjacent rows of 10 sub-pixels with different colors; for example, a repeating sub-pixel row includes 10 rows of red sub-pixels, 10 rows of green sub-pixels, and 10 rows of blue sub-pixels. Each row of 10 sub-pixels is electrically connected to a scan line G. A data line D is electrically connected to the corresponding column of sub-pixels 10.

[0064] In the embodiments of this application, the number of first pixel units 20 and the number of second pixel units 30 electrically connected to the same data line D are equal. Specifically, the number of first pixel units 20 electrically connected to each data line D is equal to the number of second pixel units 30.

[0065] In the embodiments of this application, the data signals transmitted by two adjacent data lines D have opposite polarities, and at least some of the data lines D input data signals to the sub-pixel 10 at different times. By setting the polarities of the data signals transmitted by two adjacent data lines D to be opposite, the coupling capacitance between the sub-pixel 10 and the two adjacent data lines D can be canceled, thereby improving display quality. The different times at which at least some of the data lines D input data signals to the sub-pixel 10 result in different charging times for the sub-pixel 10, and consequently, different display times. This facilitates displaying a specified sub-pixel 10 within a preset time to display a preset display image.

[0066] The other structures of display panel 300 are the same as those of display panel 100, so they will not be described in detail here.

[0067] The display panel 300 provided in the embodiments of this application divides the display panel 300 into a first display area AA1 and a second display area AA2. The first display area AA1 is provided with only first pixel units 20, and the second display area AA2 is provided with only second pixel units 30. At the same time, at least two adjacent first pixel units 20 and at least two adjacent second pixel units 30 are electrically connected to the same data line D. This allows the display panel 300 to simultaneously scan sub-pixels 10 of the same color in at least two first pixel units 20 located in the first pixel column 101, or simultaneously scan sub-pixels 10 of the same color in at least two second pixel units 30 located in the second pixel column 102, when switching from a first preset refresh frequency to a second preset refresh frequency. This controls the multiple sub-pixels 10 simultaneously displayed by the display panel 300 at the second preset refresh frequency to be located in the same pixel column, thereby avoiding pixel misalignment and improving the resolution of the display panel 300.

[0068] like Figure 6 As shown, an embodiment of this application provides a display device 400, including the aforementioned display panel 100 / 200 / 300 and a driving circuit 410. The display panel 100 / 200 / 300 is electrically connected to the driving circuit 410, and the driving circuit 410 is used to drive the display panel 100 / 200 / 300.

[0069] Specifically, the driving circuit 410 includes a system chip 411 and a timing controller 412. The system chip 411 is electrically connected to the timing controller 412, and the timing controller 412 is electrically connected to the display panel. Figure 7 As shown, the system chip 411 is used to receive image data from the display panel to provide corresponding driving data to the timing controller 412. The timing controller 412 provides a scanning signal and a data signal corresponding to the refresh rate to the display panel according to the driving data to control the display panel to display the screen. Figure 7Taking a refresh rate of 60 Hz as an example.

[0070] like Figure 8 As shown, when a user performs a refresh rate switching operation, such as switching from 60 Hz to 120 Hz, the system chip 411 sends a command to the timing controller 412 to switch the refresh rate via a signal line in a preset interface. Upon receiving this command, the timing controller 412 sends a feedback signal to the system chip 411 via a signal line. The system chip 411, upon receiving the feedback signal, determines whether the current refresh rate is the same as the refresh rate after the switch. If the current refresh rate is different from the refresh rate after the switch, the system chip 411 sends the drive data corresponding to the refresh rate after the switch to the timing controller 412. The timing controller 412 then provides the display panel with a scan signal and a data signal corresponding to the refresh rate based on this drive data to control the display panel's display screen.

[0071] The above provides a detailed description of a display panel and display device provided by the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of this application, and the above description should not be construed as a limitation on the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: Multiple scan lines, wherein the multiple scan lines are arranged along a first direction; Multiple data lines are arranged along a second direction, which intersects with the first direction. Multiple sub-pixels, each scan line is electrically connected to a row of sub-pixels arranged along the second direction, the multiple sub-pixels include a first pixel column and a second pixel column, the first pixel column and the second pixel column are arranged adjacent to each other along the second direction, the first pixel column includes multiple first pixel units arranged along the first direction, the second pixel column includes multiple second pixel units arranged along the first direction, and each first pixel unit and second pixel unit includes three sub-pixels arranged along the first direction, the three sub-pixels have different colors; At least two adjacent first pixel units and at least two adjacent second pixel units are electrically connected to the same data line; The display panel includes at least a first display mode and a second display mode. In the first display mode, the refresh rate of the display panel is a first preset refresh rate. In the second display mode, the refresh rate of the display panel is a second preset refresh rate. The second preset refresh rate is N times the first preset refresh rate, where N is a positive integer greater than 1. In the second display mode, the sub-pixels of the same color in at least two adjacent first pixel units electrically connected to the same data line are turned on simultaneously, or the sub-pixels of the same color in at least two adjacent second pixel units electrically connected to the same data line are turned on simultaneously.

2. The display panel according to claim 1, characterized in that, The time it takes for the display panel to display one frame of the image includes a scanning cycle. The scanning cycle includes a first sub-scanning cycle and a second sub-scanning cycle that are consecutive in time. The number of first pixel units that are scanned in the first sub-scanning cycle is equal to the number of second pixel units that are scanned in the second sub-scanning cycle.

3. The display panel according to claim 1 or 2, characterized in that, Both the first pixel unit and the second pixel unit include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along the first direction; The display panel further includes a first gate driving unit, a second gate driving unit, and a third gate driving unit connected in cascade. The first gate driving unit receives a first clock signal and is electrically connected to the corresponding first sub-pixel through the scan line. The second gate driving unit receives a second clock signal and is electrically connected to the corresponding second sub-pixel through the scan line. The third gate driving unit receives a third clock signal and is electrically connected to the corresponding third sub-pixel through the scan line. The time difference between the first clock signal switching from low potential to high potential and the second clock signal switching from low potential to high potential is between 2 microseconds and 3 microseconds, and the time difference between the second clock signal switching from low potential to high potential and the third clock signal switching from low potential to high potential is between 2 microseconds and 3 microseconds.

4. The display panel according to claim 3, characterized in that, The second clock signal is turned on while the first clock signal is held at a high level, and the second clock signal is turned off while the third clock signal is held at a high level, wherein the third clock signal is switched from a low level to a high level when the first clock signal switches from a high level to a low level.

5. The display panel according to claim 3, characterized in that, Every two first pixel units are arranged adjacent to each other along the first direction, every two second pixel units are arranged adjacent to each other along the first direction, and at least some of the first pixel units and second pixel units are arranged alternately along the first direction.

6. The display panel according to claim 3, characterized in that, The first clock signal switches from a low level to a high level while the third clock signal remains at a high level.

7. The display panel according to claim 1, characterized in that, The number of the first pixel units electrically connected to the same data line and the number of the second pixel units are equal.

8. The display panel according to claim 1, characterized in that, The data signals transmitted by two adjacent data lines have opposite polarities, and at least some of the data lines input data signals to the corresponding sub-pixels at different times.

9. A display device, characterized in that, The device includes a display panel as described in any one of claims 1-8 and a driving circuit, wherein the display panel is electrically connected to the driving circuit, and the driving circuit is used to drive the display panel.

10. The display device according to claim 9, characterized in that, The driving circuit includes a system chip and a timing controller. The system chip is electrically connected to the timing controller, and the timing controller is electrically connected to the display panel. The system chip is used to send a command to the timing controller to switch the refresh rate. The timing controller is used to send a feedback signal to the system chip according to the command to switch the refresh rate. The system chip is also used to determine whether the current refresh rate is the same as the refresh rate after switching according to the feedback signal. If the current refresh rate is not the same as the refresh rate after switching, the system chip sends the driving data corresponding to the refresh rate after switching to the timing controller. The timing controller is also used to provide the display panel with a scan signal and a data signal corresponding to the refresh rate after switching according to the driving data, so as to control the display panel to display the screen.

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