Video data transmission method, device, system, vehicle and storage medium

Abstract

The application relates to a video data transmission method, device, system, vehicle and storage medium. The method comprises the following steps: a receiving end shares a memory cache address of the receiving end, wherein the receiving end is connected with a sending end through a PCIe bus; the receiving end updates a BAR space address corresponding to video data shared by the sending end according to the memory cache address, so that the sending end adopts a DMA transmission mode to transmit the video data to the memory cache address shared by the receiving end according to the updated BAR space address through the PCIe bus. The scheme provided by the application can reduce the hardware cost of video data transmission, improve the bandwidth of video data transmission, improve the speed of video data transmission and ensure the reliability of video data transmission.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a video data transmission method, apparatus, system, vehicle, and storage medium. Background Technology

[0002] In related technologies, video transmission in a System-on-Chip (SoC) utilizes a GSML (Gigabit Multimedia Serial Link) video encryption / deserialization chip or Ethernet. However, video transmission schemes using video encryption / deserialization chips have high hardware costs and limitations on transmitted video formats and bandwidth. Video transmission schemes using Ethernet also require high-end network cards, resulting in high hardware costs, and cannot guarantee video transmission stability, bandwidth cannot be flexibly expanded, and transmission bandwidth is limited.

[0003] In summary, video transmission between SOCs using related technologies has high hardware costs and limited bandwidth. Summary of the Invention

[0004] To address or partially address the problems existing in related technologies, this application provides a video data transmission method, apparatus, system, vehicle, and storage medium, which can reduce the hardware cost of video data transmission, increase the bandwidth of video data transmission, improve the speed of video data transmission, and ensure the reliability of video data transmission.

[0005] A first aspect of this application provides a video data transmission method, the method comprising:

[0006] The receiving end shares the memory cache address of the receiving end, wherein the receiving end and the sending end are connected via a PCIe bus;

[0007] The receiving end updates the BAR space address shared by the sending end and corresponding to the video data according to the memory cache address, so that the sending end uses DMA transmission mode to transmit the video data to the memory cache address shared by the receiving end through the PCIe bus according to the updated BAR space address.

[0008] In one embodiment, the receiving end shares the memory cache address of the receiving end, including:

[0009] The receiving end constructs a V4L2 video framework and shares the memory cache address of the receiving end through the V4L2 video framework.

[0010] In one embodiment, sharing the memory cache address of the receiving end through the V4L2 video framework includes:

[0011] The receiving end establishes a circular buffer queue at the receiving end through the V4L2 video frame;

[0012] The receiving end's memory cache address is shared through the circular buffer queue.

[0013] In one embodiment, sharing the memory cache address of the receiving end through the circular buffer queue includes: sharing the memory cache address of the receiving end to the BAR space through the circular buffer queue;

[0014] The receiving end updates the shared BAR space address corresponding to the video data at the sending end according to the memory cache address, so that the sending end uses DMA transmission mode to transmit the video data to the shared memory cache address at the receiving end via the PCIe bus, including:

[0015] The receiving end obtains the BAR space address configured by the sending end for the video data and shared with the BAR space, wherein the BAR space address includes DMA destination address, DMA status address, and DMA trigger control configuration;

[0016] The receiving end updates the DMA destination address according to the memory cache address, and triggers the DMA transmission of the sending end according to the DMA trigger control configuration, so that the sending end adopts the DMA transmission mode according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus.

[0017] In one embodiment, the receiving end updates the DMA destination address according to the memory cache address, and triggers the DMA transfer of the sending end according to the DMA trigger control configuration, so that the sending end uses DMA transfer mode according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus, including:

[0018] The receiving end updates the DMA destination address according to the memory cache address;

[0019] The receiving end triggers the DMA transmission of the sending end according to the DMA trigger control configuration;

[0020] The receiving end controls the DMA channel corresponding to the DMA status address to be enabled through a software token control method based on the DMA status address, so that the sending end uses the DMA transmission method according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus.

[0021] In one embodiment, the receiving end controls the DMA channel corresponding to the DMA state address to be enabled via a software token control method based on the DMA state address, including:

[0022] The receiving end configures the channel priority for the DMA channel corresponding to the DMA status address based on the real-time requirements of the video data transmission and the DMA status address.

[0023] When the channel priority of the DMA channel meets the set level, the receiving end controls the DMA channel corresponding to the DMA status address to be enabled.

[0024] A second aspect of this application provides a video data transmission apparatus, the apparatus comprising:

[0025] A sharing module is used for the receiving end to share the memory cache address of the receiving end, wherein the receiving end and the sending end are connected via a PCIe bus;

[0026] The update module is used by the receiving end to update the BAR space address shared by the sending end and corresponding to the video data according to the memory cache address, so that the sending end can use DMA transmission mode to transmit the video data to the memory cache address shared by the receiving end through the PCIe bus according to the updated BAR space address.

[0027] A third aspect of this application provides a video data transmission system, the system comprising:

[0028] The receiving end is used to share the memory cache address and update the BAR space address corresponding to the video data shared by the sending end according to the memory cache address, wherein the receiving end and the sending end are connected through a PCIe bus;

[0029] The transmitting end is used to share the BAR space address corresponding to the video data, and uses DMA transmission mode according to the updated BAR space address to transmit the video data corresponding to the BAR space address of the transmitting end to the memory cache address shared by the receiving end through the PCIe bus.

[0030] A fourth aspect of this application provides a vehicle, comprising:

[0031] Processor; and

[0032] A memory that stores executable code, which, when executed by the processor, causes the processor to perform the method described above.

[0033] The fifth aspect of this application provides a computer-readable storage medium having executable code stored thereon, which, when executed by a processor of a vehicle, causes the processor to perform the method described above.

[0034] The technical solution provided in this application may include the following beneficial effects:

[0035] The technical solution of this application uses a PCIe bus to connect the receiving end and the transmitting end. It utilizes the DMA capability of the transmitting end's SOC to enable the transmitting end to use the DMA transmission method of the transmitting end's SOC. Video data is moved to the shared memory cache address of the receiving end via the PCIe bus, achieving zero-copy transmission of video data. This meets the requirements for large-volume video data transmission, has low CPU usage, good compatibility, a complete plug-and-play management mechanism, and can simultaneously support multiple peripheral devices. It reduces the hardware cost of video data transmission between SOCs, increases the bandwidth of video data transmission, reduces the latency of video data transmission, improves the speed of video data transmission, and ensures the reliability of video data transmission.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0037] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0038] Figure 1 This is a schematic flowchart illustrating a video data transmission method according to an embodiment of this application;

[0039] Figure 2 This is a flowchart illustrating a video data transmission method according to another embodiment of this application;

[0040] Figure 3 This is a schematic diagram illustrating the application of the video data transmission method shown in the embodiments of this application;

[0041] Figure 4 This is a schematic diagram of the structure of a video data transmission device shown in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the structure of a video data transmission system shown in an embodiment of this application;

[0043] Figure 6 This is a schematic diagram of the vehicle structure shown in the embodiments of this application. Detailed Implementation

[0044] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make this application more thorough and complete, and to fully convey the scope of this application to those skilled in the art.

[0045] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0046] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0047] This application provides a video data transmission method that can reduce the hardware cost of video data transmission, increase the bandwidth of video data transmission, improve the speed of video data transmission, and ensure the reliability of video data transmission.

[0048] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0049] Figure 1 This is a flowchart illustrating a video data transmission method according to an embodiment of this application.

[0050] See Figure 1 A video data transmission method, comprising:

[0051] Step 101: The receiving end shares the memory cache address of the receiving end, wherein the receiving end and the sending end are connected through the PCIe bus.

[0052] In one embodiment, the receiving end can be a first SOC, and the transmitting end can be a second SOC. The first SOC and the second SOC are two SOCs supporting PCIe interfaces, and they can be connected via a PCIe bus through their PCIe interfaces. When the first SOC acquires video data from the second SOC, the first SOC can enable the PCIe path, complete the relevant PCIe path configuration, and set the first SOC as the receiving end (RC end) and the second SOC as the transmitting end (EP end). The RC end is responsible for receiving video data, and the EP end is responsible for transmitting video data.

[0053] In one embodiment, the receiving end can share the memory cache address where the receiving end stores video data with the PCIe BAR space.

[0054] Step 102: The receiving end updates the shared BAR space address corresponding to the video data on the sending end according to the memory cache address, so that the sending end can use DMA to transmit the video data to the shared memory cache address on the receiving end through the PCIe bus according to the updated BAR space address.

[0055] In one embodiment, the transmitting end may use DMA (Direct Memory Access) transmission mode to transfer video data from one address space of the transmitting end to one address space of the receiving end via the PCIe bus according to the updated BAR space address.

[0056] In one embodiment, the transmitting end can configure a corresponding BAR space address for the video data. The BAR space address includes a DMA destination address, a DMA status address, and a DMA trigger control configuration. The BAR space address is shared with the PCIe BAR space. The receiving end updates the shared BAR space address corresponding to the video data based on the shared memory cache address, so that the transmitting end uses DMA transmission mode to transfer the video data corresponding to the BAR space address to the shared memory cache address of the receiving end via the PCIe bus.

[0057] In one embodiment, for video data transmitted using DMA, the sending end can map the BAR space address corresponding to the video data to a corresponding DMA linked list, and share the DMA linked list corresponding to the video data to the PCIe BAR space. When the video data is in a ready state, the sending end notifies the receiving end via an interrupt. Based on the received interrupt, the receiving end updates the DMA linked list corresponding to the video data shared by the sending end in the BAR space according to the shared memory cache address. Based on the DMA linked list, the receiving end triggers the sending end to use DMA transmission, so that the sending end, according to the updated DMA linked list, uses DMA transmission to transfer the video data corresponding to the DMA linked list to the receiving end's shared memory cache address via the PCIe bus.

[0058] The video data transmission method of this application embodiment involves a receiving end sharing a memory cache address. The receiving end and the transmitting end are connected via a PCIe bus. The receiving end updates the shared BAR space address corresponding to the video data based on the memory cache address. This allows the transmitting end to use DMA transmission mode based on the updated BAR space address to transmit the video data to the shared memory cache address via the PCIe bus. By utilizing the DMA capability of the transmitting end's SOC, the receiving end and the transmitting end are connected via the PCIe bus, enabling the transmitting end to move the video data to the shared memory cache address via the PCIe bus. This achieves zero-copy transmission of video data. PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that supports bidirectional transmission mode and data channel-specific transmission mode. The data transmission mode, which uses multiple channels of the PCIe bus (x1, x2, x4, x8, x12, x16, and x32), offers a unidirectional bandwidth of up to 250MB / s and a bidirectional bandwidth of up to 500MB / s. This meets the requirements for transmitting large amounts of video data, has low system resource consumption, good compatibility, a complete plug-and-play management mechanism, and can support multiple peripheral devices simultaneously. It reduces the hardware cost of video data transmission, increases the bandwidth of video data transmission, reduces the latency of video data transmission, improves the speed of video data transmission, and ensures the reliability of video data transmission.

[0059] Figure 2 This is a flowchart illustrating a video data transmission method according to another embodiment of this application.

[0060] See Figure 2 A video data transmission method, comprising:

[0061] Step 201: Share the memory cache address of the receiving end to the BAR space through a circular buffer queue.

[0062] In one embodiment, the receiving end can be a first SOC, and the transmitting end can be a second SOC. The first SOC and the second SOC are two SOCs supporting PCIe interfaces, and they can be connected via a PCIe bus through their PCIe interfaces. When the first SOC acquires video data from the second SOC, the first SOC can enable the PCIe path, complete the relevant PCIe path configuration, and set the first SOC as the receiving end (RC end) and the second SOC as the transmitting end (EP end). The RC end is responsible for receiving video data, and the EP end is responsible for transmitting video data.

[0063] In one embodiment, the receiving end constructs a V4L2 video framework and shares the receiving end's memory cache address through the V4L2 video framework.

[0064] In one embodiment, V4L2 is short for Video for linux2, which is the kernel driver for video devices in Linux. The receiving end can obtain a buffer from the receiving end and establish a circular buffer (vring) of the V4L2 video framework. A circular buffer queue is established in the circular buffer (vring) of the receiving end through the V4L2 video framework. The memory cache address of the receiving end is shared to the BAR space of PCIe through the circular buffer queue in the manner of buffer dequeue and enqueue.

[0065] In one embodiment, the RC end can establish a V4L2 video framework based on the number of video channels. The number of video channels can be determined by detecting or based on configuration, with one video device corresponding to one video channel. The corresponding video device is registered using a for loop calling `video_register_device`. The corresponding `struct v4l2_ioctl_ops` operation interface is implemented. The open read / write interface corresponding to `struct v4l2_file_operations` is also implemented, and the read / write interface and operation interface are used to control and transmit / receive PCIe data. The V4L2 video framework is bound to the video device. This allows the RC end to receive video data from the PCIe bus by operating on the video device node, completing the buffering of video data from the PCIe bus to the RC end. The RC end can share the receiver's memory cache address to the PCIe BAR space through the V4L2 video frame's circular buffer queue, using a circular buffer queue to enqueue / dequeue the buffers. When receiving video data, the circular buffer queue is used to enqueue / dequeue the video data from the PCIe bus.

[0066] In one embodiment, the RC end can share the memory cache address of the receiving end storing video data to the PCIe BAR space through the circular buffer queue of the V4L2 video framework, using the circular buffer queue in a buffer enqueue / buffer dequeue manner.

[0067] Step 202: The receiving end obtains the BAR space address configured by the sending end for video data and shared to the BAR space, wherein the BAR space address includes the DMA destination address, DMA status address, and DMA trigger control configuration.

[0068] In one embodiment, the EP end can invoke its DMA engine to configure corresponding BAR space addresses for the EP end's video data based on the multiple DMA channels of the EP end's DMA. The BAR space address includes a DMA destination address, a DMA status address, and a DMA trigger control configuration. The DMA destination address is used by the RC end to specify the destination memory address for receiving video data. The DMA status address indicates the DMA transmission status, such as data transmission in progress or data transmission being possible. The DMA trigger control configuration controls the EP end's DMA engine to move the video data to the destination memory address on the RC end. The sending end can share the BAR space address corresponding to the video data in a queue to the BAR space; the receiving end obtains the BAR space address configured by the sending end for the video data and shared in a queue to the BAR space.

[0069] In one embodiment, the EP end transmits video data using DMA (Direct Memory Access) transmission. The EP end can map the BAR (Browser Area Code) address corresponding to the video data to a corresponding DMA linked list. The DMA linked list may include a DMA source address, DMA data transfer size, DMA destination address, DMA status address, DMA trigger control configuration, and a next linked list descriptor. The DMA source address indicates the source address of the video data being transferred by DMA in the EP end's physical memory or the first address of the subsequent linked list. The data transfer size defines the length of the video data block transferred by the linked list. One video data item can correspond to one or more DMA linked lists. Multiple DMA linked lists can be combined into a circular DMA linked list entry, which is shared with the PCIe BAR space. The receiving end can obtain the DMA linked list of the circular DMA linked list entry shared by the sending end in the BAR space.

[0070] In one embodiment, the transmitting end shares the DMA list corresponding to the video data to the PCIe BAR space, and the video data is in a ready state. When the video data is in the ready state, the transmitting end can notify the receiving end via an interrupt. The receiving end retrieves the DMA list in the BAR space based on the received interrupt.

[0071] Step 203: The receiving end updates the DMA destination address according to the memory cache address, and triggers the DMA transmission of the sending end according to the DMA trigger control configuration, so that the sending end adopts the DMA transmission mode according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus.

[0072] In one embodiment, the receiving end updates the DMA destination address according to the memory cache address; the receiving end triggers the DMA transmission of the sending end according to the DMA trigger control configuration; the receiving end controls the DMA channel corresponding to the DMA status address to be enabled through the software token control method according to the DMA status address, so that the sending end adopts the DMA transmission method according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus.

[0073] In one embodiment, when the DMA state of the EP is ready, the RC end updates the memory cache address of the circular buffer queue to the DMA destination address of the BAR space address. According to the DMA trigger control configuration, the DMA transfer of the EP end is triggered. According to the DMA state address of the BAR space address, the DMA channel corresponding to the DMA state address of the BAR space address is controlled to be opened through the software token control method, so that the EP end calls the DMA engine to use the DMA transfer method to transfer the video data corresponding to the BAR space address. According to the BAR space address after updating the DMA destination address, the video data corresponding to the BAR space address is transferred to the memory cache address in the DMA destination address through the PCIe bus via the opened DMA channel.

[0074] In one embodiment, when the DMA state is ready at the EP end, the RC end updates the memory cache address shared with the BAR space to the DMA destination address of the DMA list in the DMA state ready; the DMA transmission at the EP end is triggered according to the DMA trigger control configuration of the DMA list; according to the DMA state address of the DMA list, the DMA channel corresponding to the DMA state address is controlled to be opened through the software token control method, so that the sending end adopts the DMA transmission mode; according to the DMA list after updating the DMA destination address, the video data corresponding to the DMA list is transmitted to the memory cache address in the DMA destination address through the PCIe bus using the opened DMA channel.

[0075] In one embodiment, the receiving end configures the channel priority for the DMA channel corresponding to the DMA status address based on the real-time requirements of the video data transmission and the DMA status address. When the channel priority of the DMA channel meets the set level, the receiving end controls the DMA channel corresponding to the DMA status address to be enabled, so that the sending end adopts the DMA transmission mode according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus.

[0076] In one embodiment, the RC end can update the DMA destination address of the DMA list to the memory cache address of the RC end in the circular buffer queue, trigger DMA transmission according to the DMA trigger control configuration, and configure the corresponding channel priority for the DMA channel corresponding to the DMA list according to the real-time requirements of the video data cached in the DMA channel corresponding to the DMA list and the DMA status address of the DMA channel corresponding to the DMA list. According to the principle of high priority first processing, when the channel priority of the DMA channel is the highest priority, the RC end controls the DMA channel corresponding to the DMA list to be opened, so that the sending end can use the DMA transmission mode through the DMA channel to transmit the video data corresponding to the DMA list to the shared memory cache address of the receiving end through the PCIe bus according to the updated DMA destination address of the DMA list.

[0077] In one embodiment, the DMA at the EP end has multiple DMA channels, and the RC end can control the traffic of each DMA channel based on the token status of the software token. The RC end configures a channel priority for each DMA channel, and the channel priority coefficient score of the DMA channel decreases with each delayed processing cycle, thus lowering the priority of the DMA channel. By following the principle of prioritizing high-priority processing, the traffic of each DMA channel is comprehensively scheduled, ensuring that high-priority DMA channels have more time to process data. By setting different channel priorities, the number of times video data is continuously transmitted by the DMA channel is controlled, thereby controlling the data traffic of the DMA channel and preventing a single DMA channel from continuously occupying traffic.

[0078] In one embodiment, an interrupt (e.g., a PCIe MSI-X interrupt) can be registered at the RC end. When the video data at the EP end is in a ready state, the transmitting end can notify the RC end via an interrupt. The EP end can determine that the video data at the EP end is ready when sharing the DMA list corresponding to the video data to the circular DMA list entry in the BAR space, and notify the RC end via an MSI-X interrupt.

[0079] In one embodiment, if an error occurs during the transmission of video data using the DMA transmission method at the sending end, the sending end can notify the receiving end by interrupting the transmission.

[0080] In one embodiment, when the video data transmission is completed at the sending end using DMA transmission mode, the sending end can notify the receiving end by interruption.

[0081] Figure 3 This is a schematic diagram illustrating the application of the video data transmission method shown in the embodiments of this application.

[0082] like Figure 3As shown, RC terminal 301 can be a domain controller of the vehicle, such as CDCU (Center Domain Control Unit), and EP terminal 302 can be another domain controller of the vehicle, such as RDCU (Right Domain Control Unit). RC terminal 301 and EP terminal 302 are connected via PCIe bus 303. EP terminal 302 obtains YUV format video data through VPU (Video Processing Unit) 304. Obtaining video data through VPU reduces the CPU load on the EP terminal. The YUV format video data is stored in a memory cache, with the memory cache address on the EP terminal being SRCBuffer. The EP terminal can configure a DMA list for this video data, which includes the DMA source address (SRCBuffer), DMA data transfer size, DMA destination address, DMA status address, DMA trigger control configuration, and next list descriptor. The DMA list is shared with the PCIe BAR space. An interrupt is used to notify the RC terminal and EP terminal that the video data is ready. The RC end shares the memory buffer address (DST Buffer) for receiving video data to the PCIe BAR space via a circular buffer queue using buffer enqueue / dequeue. It then updates the memory buffer address (DST Buffer) to the DMA destination address, which is the DST Buffer. Based on the DMA list of the video data, it selects a DMA channel and configures its priority. When the DMA channel's priority is the highest, it enables the DMA channel. Finally, it triggers the DMA transfer according to the DMA trigger control configuration. On the EP end, after the RC triggers the DMA transfer according to the DMA trigger control configuration, the EP end's DMA engine, based on the updated DMA destination address and the DMA list, uses the corresponding enabled DMA channel to transfer the video data from the SRC Buffer to the RC end's DST Buffer via the PCIe bus using DMA. The RC end receives video data from the PCIe bus through the circular buffer queue of the V4L2 video framework, and stores the video data in the memory buffer at the address DST Buffer.

[0083] The video data transmission method of this application embodiment uses a PCIe bus to connect the receiving end and the transmitting end. It utilizes the DMA capability of the transmitting end's SOC to enable the transmitting end to use the DMA transmission mode of the transmitting end's SOC. The video data from the transmitting end is transferred to the receiving end via the PCIe bus, achieving zero-copy transmission of video data. This method can meet the requirements for large-volume video data transmission, has low CPU usage, good compatibility, a complete plug-and-play management mechanism, and can simultaneously support multiple peripheral devices. It can reduce the hardware cost of video data transmission between SOCs, increase the bandwidth of video data transmission, reduce the latency of video data transmission, improve the speed of video data transmission, and ensure the reliability of video data transmission.

[0084] Furthermore, in the video data transmission method of this application embodiment, the receiving end constructs a V4L2 video framework to share the receiving end's memory cache address and receive video data from the PCIe bus through the V4L2 video framework, providing the transmission capability of multiple video data streams, saving hardware costs, avoiding the limitation on the number of videos caused by insufficient SOC video interfaces, and increasing the bandwidth of video data transmission.

[0085] Furthermore, in the video data transmission method of this application embodiment, when the channel priority of the DMA channel meets the set level, the video data of the sending end corresponding to the BAR space address is transmitted to the receiving end through the PCIe bus. The receiving end uses a software token mechanism to control the traffic of each DMA channel interaction and the switching on and off of the DMA channel, thereby realizing QOS (Quality of Service) data traffic control to ensure the performance of the PCIe bus connection and the stability of video data transmission.

[0086] Corresponding to the aforementioned application function implementation method embodiments, this application also provides a video data transmission device, a vehicle, and corresponding embodiments.

[0087] Figure 4 This is a schematic diagram of the structure of a video data transmission device shown in an embodiment of this application.

[0088] See Figure 4 A video data transmission device includes a sharing module 401 and an update module 402.

[0089] The shared module 401 is used for the receiver to share the memory cache address of the receiver, wherein the receiver and the transmitter are connected via a PCIe bus.

[0090] The update module 402 is used by the receiving end to update the BAR space address shared by the sending end and corresponding to the video data according to the memory cache address, so that the sending end can use DMA to transmit the video data to the memory cache address shared by the receiving end through the PCIe bus according to the updated BAR space address.

[0091] In one embodiment, the receiving end can be a first SOC, and the transmitting end can be a second SOC. The first SOC and the second SOC are two SOCs supporting PCIe interfaces, and they can be connected via a PCIe bus through their PCIe interfaces. When the first SOC acquires video data from the second SOC, the first SOC can enable the PCIe path, complete the relevant PCIe path configuration, and set the first SOC as the receiving end (RC end) and the second SOC as the transmitting end (EP end). The RC end is responsible for receiving video data, and the EP end is responsible for transmitting video data.

[0092] In one embodiment, the sharing module 401 can share the memory cache address of the receiving end storing video data with the PCIe BAR space.

[0093] In one embodiment, the transmitting end can use DMA transmission mode to transmit the video data corresponding to the BAR space address from one address space of the transmitting end to one address space of the receiving end through the PCIe bus, according to the BAR space address updated by the update module 402.

[0094] In one embodiment, the transmitting end can configure a corresponding BAR space address for the video data. The BAR space address includes a DMA destination address, a DMA status address, and a DMA trigger control configuration. The BAR space address is shared with the PCIe BAR space. The update module 402 updates the shared BAR space address corresponding to the video data at the transmitting end according to the shared memory cache address, so that the transmitting end uses DMA transmission mode to transmit the video data corresponding to the BAR space address to the shared memory cache address at the receiving end via the PCIe bus.

[0095] In one embodiment, for video data transmitted using DMA, the sending end can map the BAR space address corresponding to the video data to a corresponding DMA linked list, and share the DMA linked list corresponding to the video data to the PCIe BAR space. When the video data is in a ready state, the sending end notifies the receiving end via an interrupt. The update module 402, based on the received interrupt, updates the DMA linked list corresponding to the video data shared by the sending end in the BAR space according to the shared memory cache address. Based on the DMA linked list, the sending end is triggered to use DMA transmission, so that the sending end, according to the updated DMA linked list, uses DMA transmission to transfer the video data corresponding to the DMA linked list to the shared memory cache address of the receiving end via the PCIe bus.

[0096] The technical solution of this application embodiment uses a PCIe bus to connect the receiving end and the transmitting end. Utilizing the DMA capability of the transmitting end's SOC, the transmitting end uses the DMA transmission method of the transmitting end's SOC to transfer video data from the transmitting end to the receiving end via the PCIe bus, achieving zero-copy transmission of video data. This meets the requirements for large-volume video data transmission, has low CPU usage, good compatibility, a complete plug-and-play management mechanism, and can simultaneously support multiple peripheral devices. It can reduce the hardware cost of video data transmission between SOCs, increase the bandwidth of video data transmission, reduce the latency of video data transmission, improve the speed of video data transmission, and ensure the reliability of video data transmission.

[0097] Figure 5 This is a schematic diagram of the structure of a video data transmission system shown in an embodiment of this application.

[0098] See Figure 5 A video data transmission system includes a receiver 501 and a transmitter 502.

[0099] The receiver 501 is used to share the memory cache address and update the BAR space address corresponding to the video data shared by the transmitter 502 according to the memory cache address. The receiver 501 and the transmitter 502 are connected through the PCIe bus.

[0100] The transmitter 502 is used to share the BAR space address corresponding to the video data. Based on the updated BAR space address, it uses DMA to transmit the video data corresponding to the BAR space address from the transmitter 502 to the shared memory cache address of the receiver 501 via the PCIe bus.

[0101] In one embodiment, the receiving end 501 shares the memory buffer address (DST Buffer) of the received video data to the PCIe BAR space via a circular buffer queue using a buffer enqueue / dequeue method. The sending end 502 configures a DMA list for the video data whose memory buffer address is SRCBuffer. This DMA list includes the DMA source address (SRCBuffer), DMA data transfer size, DMA destination address, DMA status address, DMA trigger control configuration, and the next list descriptor. It shares the DMA list to the PCIe BAR space and notifies the RC and EP ends that the video data is ready via an interrupt. The receiving end 501 updates the memory buffer address (DST Buffer) of the circular buffer queue to the DMA destination address, which is the DST Buffer. Based on the DMA list of the video data, it selects a DMA channel and configures a channel priority for that DMA channel. When the channel priority of the DMA channel is the highest priority, it controls the DMA channel to start. Finally, it triggers DMA transfer according to the DMA trigger control configuration. After receiving end 501 triggers DMA transfer according to the DMA trigger control configuration, the DMA engine of sending end 502, based on the DMA list after updating the DMA destination address of the video data, uses the corresponding enabled DMA channel in the DMA list to transfer the video data at memory buffer address SRCBuffer to memory buffer address DST Buffer of receiving end 501 via the PCIe bus using DMA transfer. Receiving end 501 receives the video data from the PCIe bus through the circular buffer queue of the V4L2 video framework, using a buffer enqueue / buffer dequeue method, and stores the video data in memory buffer address DST Buffer.

[0102] In one embodiment, an interrupt (e.g., a PCIe MSI-X interrupt) can be registered at the receiving end 501. When the video data at the sending end 502 is ready, the sending end 502 can notify the receiving end 501 via an interrupt. After receiving the interrupt notification, the receiving end 501 updates the buffer address of the circular buffer queue to the DMA destination address corresponding to the BAR space, and triggers the sending end 502 to transfer the video data corresponding to the updated DMA destination address using DMA transfer mode through the BAR space. After the receiving end 501 triggers the sending end 502 to transfer the video data, the sending end 502 transfers the video data corresponding to the updated DMA destination address using DMA transfer mode according to the updated DMA destination address. After the sending end 502 completes the video data transfer, it notifies the receiving end 501 again via an interrupt to receive the next frame of video data in a loop when the next frame of video data is ready.

[0103] Regarding the apparatus and system in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated further here.

[0104] Figure 6 This is a schematic diagram of the vehicle structure shown in the embodiments of this application.

[0105] See Figure 6 The vehicle 1000 includes a memory 1010 and a processor 1020.

[0106] The processor 1020 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0107] Memory 1010 may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices. ROM may store static data or instructions required by processor 1020 or other modules of the computer. Permanent storage devices may be read-write storage devices. Permanent storage devices may be non-volatile storage devices that retain stored instructions and data even when the computer is powered off. In some embodiments, permanent storage devices use mass storage devices (e.g., magnetic or optical disks, flash memory) as permanent storage devices. In other embodiments, permanent storage devices may be removable storage devices (e.g., floppy disks, optical drives). System memory may be a read-write storage device or a volatile read-write storage device, such as dynamic random access memory. System memory may store some or all of the instructions and data required by the processor during operation. Furthermore, memory 1010 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (e.g., DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical disks may also be used. In some embodiments, the memory 1010 may include a removable storage device that is readable and / or writable, such as a laser disc (CD), a read-only digital multifunction optical disc (e.g., DVD-ROM, dual-layer DVD-ROM), a read-only Blu-ray disc, a high-density optical disc, a flash memory card (e.g., SD card, mini SD card, Micro-SD card, etc.), a magnetic floppy disk, etc. Computer-readable storage media do not contain carrier waves or transient electronic signals transmitted wirelessly or via wired connections.

[0108] The memory 1010 stores executable code, which, when processed by the processor 1020, can cause the processor 1020 to execute part or all of the methods described above.

[0109] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.

[0110] Alternatively, this application may be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium) storing executable code (or computer program or computer instruction code) thereon, which, when executed by a processor of a vehicle (or server, or electronic device, etc.), causes the processor to perform part or all of the steps of the above-described method according to this application.

[0111] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A video data transmission method, characterized in that, include: The receiving end shares the memory cache address of the receiving end, including: the receiving end constructs a V4L2 video framework on the receiving end, and the receiving end establishes a circular cache queue on the receiving end through the V4L2 video framework; The receiver shares the memory cache address through the circular buffer queue; wherein the receiver and the transmitter are connected via a PCIe bus. The receiving end updates the BAR space address shared by the sending end and corresponding to the video data according to the memory cache address, so that the sending end uses DMA transmission mode to transmit the video data to the memory cache address shared by the receiving end through the PCIe bus according to the updated BAR space address.

2. The method according to claim 1, characterized in that, The step of sharing the memory cache address of the receiving end through the circular cache queue includes: sharing the memory cache address of the receiving end to the BAR space through the circular cache queue; The receiving end updates the shared BAR space address corresponding to the video data at the sending end according to the memory cache address, so that the sending end uses DMA transmission mode to transmit the video data to the shared memory cache address at the receiving end via the PCIe bus, including: The receiving end obtains the BAR space address configured by the sending end for the video data and shared with the BAR space, wherein the BAR space address includes DMA destination address, DMA status address, and DMA trigger control configuration; The receiving end updates the DMA destination address according to the memory cache address, and triggers the DMA transmission of the sending end according to the DMA trigger control configuration, so that the sending end adopts the DMA transmission mode according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus.

3. The method according to claim 2, characterized in that, The receiving end updates the DMA destination address according to the memory cache address, and triggers the DMA transfer of the sending end according to the DMA trigger control configuration, so that the sending end adopts the DMA transfer mode according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus, including: The receiving end updates the DMA destination address according to the memory cache address; The receiving end triggers the DMA transmission of the sending end according to the DMA trigger control configuration; The receiving end controls the DMA channel corresponding to the DMA status address to be enabled through a software token control method based on the DMA status address, so that the sending end uses the DMA transmission method according to the BAR space address after updating the DMA destination address, and transmits the video data to the memory cache address shared by the receiving end through the PCIe bus.

4. The method according to claim 3, characterized in that, The receiving end controls the DMA channel corresponding to the DMA status address to be enabled via a software token control method based on the DMA status address, including: The receiving end configures the channel priority for the DMA channel corresponding to the DMA status address based on the real-time requirements of the video data transmission and the DMA status address. When the channel priority of the DMA channel meets the set level, the receiving end controls the DMA channel corresponding to the DMA status address to be enabled.

5. A video data transmission device, characterized in that, include: A sharing module is used for the receiving end to share the memory cache address of the receiving end, including: the receiving end constructs a V4L2 video framework on the receiving end, the receiving end establishes a circular buffer queue on the receiving end through the V4L2 video framework; and shares the memory cache address of the receiving end through the circular buffer queue; wherein the receiving end and the transmitting end are connected through a PCIe bus; The update module is used by the receiving end to update the BAR space address shared by the sending end and corresponding to the video data according to the memory cache address, so that the sending end can use DMA transmission mode to transmit the video data to the memory cache address shared by the receiving end through the PCIe bus according to the updated BAR space address.

6. A video data transmission system, characterized in that, include: A receiving end is used to share a memory cache address, including: constructing a V4L2 video framework at the receiving end; establishing a circular cache queue at the receiving end through the V4L2 video framework; sharing the memory cache address of the receiving end through the circular cache queue; and updating the BAR space address shared by the sending end and corresponding to the video data according to the memory cache address, wherein the receiving end and the sending end are connected through a PCIe bus. The transmitting end is used to share the BAR space address corresponding to the video data, and uses DMA transmission mode according to the updated BAR space address to transmit the video data corresponding to the BAR space address of the transmitting end to the memory cache address shared by the receiving end through the PCIe bus.

7. A vehicle, characterized in that, include: processor; as well as A memory having executable code stored thereon, which, when executed by the processor, causes the processor to perform the method as described in any one of claims 1-4.

8. A computer-readable storage medium, characterized in that: It stores executable code that, when executed by the vehicle's processor, causes the processor to perform the method as described in any one of claims 1-4.

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