SPI BOOT method compatible with multiple SPI Flash types

Abstract

This application relates to an SPI BOOT method compatible with multiple SPI Flash devices. The method, through RBL design and table-based Boot Image design, can detect and acquire the offset of the user program during transmission, adaptively correcting the offset. This solves compatibility issues caused by different default values ​​of the dummy clock cycles parameter and different methods of reading and writing to the parameter register in different SPI device models, as well as data offset issues caused by delays due to board-level routing delays and non-compliant chip layout and routing. By incorporating boot mode information into the Boot Image, chip pin resources are saved, avoiding the risks of multi-channel signal interference and insufficient pin drive force during port multiplexing, and enhancing the scalability of boot mode types. Furthermore, a wider variety of boot modes facilitates SPI BOOT compatibility with various SPI Flash device models.

Description

Technical Field

[0001] This application relates to the field of embedded and IC technology, and in particular to an SPIBOOT method compatible with multiple SPI Flash chips. Background Technology

[0002] SPI is a high-speed, multi-wire, synchronous communication bus widely used as a peripheral interface for chips due to its simplicity and pin-saving nature. The SPI interface bus includes six logic lines: SS (Slave Select), SCLK (Serial Clock), and DQ (Serial Data I / O). When an external SPI Flash device is used for booting, the user program is stored in this Flash. After receiving a fast read command and address from the chip, the SPI Flash device first returns a dummy bit set of bits (length determined by the dummy clock cycles parameter) before returning the actual user data. SPI booting is designed according to the SPI standard protocol, including full-duplex, two-wire, and four-wire data transmission modes. In existing SPI booting technology, in full-duplex mode booting, commands, addresses, and data are all in full-duplex mode; in two-wire mode booting, commands, addresses, and data are all in two-wire mode; and in four-wire mode booting, commands, addresses, and data are all in four-wire mode. The booting logic is mainly implemented by the RBL (Real-Time Block) embedded in the chip, and booting is completed by executing the RBL. The steps are as follows: the chip exits reset, configuration information (bootstrap mode) enters the chip through external pins and is latched into a specific register (such as SPI_BOOT). RBL reads this configuration information to complete the SPI component initialization, and then controls SPI to initialize the SPI Flash device, including accessing the dummy clockcycles parameter (to make the parameter known for later deletion of dummy bits), and configuring the transmission mode of the SPI Flash device according to the selected transmission mode (full-duplex, two-wire, four-wire). After initialization, a read command and address are sent to the SPI Flash device to read user data, and the dummy bits in the read user data are deleted to obtain the real user data. Finally, the user data is moved to the destination address, and the user program is jumped to start execution, thus implementing the booting of the user program.

[0003] The usage standards for different SPI Flash devices are not fully unified, and the bootstrap logic is implemented in unmodifiable hardware, leading to incompatibility issues between SPI BOOTs and different SPI Flash devices. Existing SPI BOOTs in DSPs / CPUs are typically customized based on the usage standards of specific manufacturers or models of SPI Flash devices, and there is currently no SPI BOOT design that is compatible with various models from multiple manufacturers. Adding bootstrap mode options is one way to improve compatibility. Traditional SPI BOOTs input the bootstrap mode through chip pins, but an excessive number of BOOT pins will over-consume limited pin resources. If port multiplexing is used to improve pin resource utilization, it will increase the risk of multi-channel signal interference and reduce pin driving capability.

[0004] Therefore, in the context of the localization of high-tech products, and in response to the current situation where SPI BOOT is incompatible with various models of SPI Flash devices, as well as the user's demand for using domestically produced SPI Flash devices, a new SPI BOOT technology is needed. Summary of the Invention

[0005] Therefore, it is necessary to provide an SPI BOOT method that is compatible with multiple SPI Flash chips to address the aforementioned technical issues.

[0006] A method for SPI BOOT compatible with multiple SPI Flash devices, wherein the SPI Flash devices are interconnected with the chip via an SPI interface, the method comprising:

[0007] The boot mode information of SPI BOOT mode is collected into the Boot Image, which is stored in the SPIFlash device. The Boot Image includes a header, SPI_BOOT segment, header, number of bytes of the original user program, destination address of the original user program, original user data, and end marker.

[0008] After the chip exits power-on reset, it begins executing RBL, which is used to decode the Boot Image.

[0009] The chip receives data from the SPI Flash device and adaptively detects and acquires the offset of the user program during transmission.

[0010] Correct data misalignment based on offset, retain user program segments and end markers, and delete other segments.

[0011] Move the original user program segment of a preset byte length to the program's destination address, and repeat this process to move n user program segments to their respective destination addresses.

[0012] When the end marker is detected, the PC jumps to the specified address to begin executing the user program.

[0013] In one embodiment, after the chip exits power-on reset, it begins executing RBL, using RBL to decode the Boot Image, including:

[0014] After the chip exits power-on reset, it begins executing RBL, which initializes and configures the SPI components.

[0015] The chip controls the SPI to read the SPI_BOOT segment from the SPI Flash device to determine the bootstrap mode of the SPI Flash device; then, it initializes and configures the SPI Flash device according to the bootstrap mode of the SPI Flash device.

[0016] The SPI controller sends read commands to the SPI Flash device based on the SPIProtoType corresponding to the bootstrap mode of the SPI Flash device.

[0017] Configure the SPI ProtoType register according to the bootstrap mode of the SPI Flash device, clear the SPI receive queue, and then generate SPICLK for a specific period.

[0018] In one embodiment, the SPI is controlled to send a read command to the SPI Flash device according to the SPIProtoType corresponding to the bootstrap mode of the SPI Flash device. The read command includes: 03h command, 0Bh command, 3Bh command and 6Bh command.

[0019] Before sending the 6Bh instruction, it is necessary to determine whether the SPI_BOOT segment control enables writing 1 to the QE bit of the SPI Flash device and whether the enable bit is 1. If it is not 1, the QE bit of the SPI Flash device is set to 1 and then the 6Bh instruction is sent. If it is 1, the 6Bh instruction is sent.

[0020] When the enable bit controlling whether to write 1 to the QE bit of the SPI Flash device is not 0, then the QE bit is written to 1; a four-wire fast read data command is sent.

[0021] In one embodiment, after the chip exits power-on reset, it begins to execute RBL. RBL initializes and configures the SPI components, including configuring full-duplex mode and configuring CPOL and CPHA as 2'b 00 or 2'b11.

[0022] In one embodiment, the chip controls the SPI to read the SPI_BOOT segment from the SPI Flash device, including:

[0023] The chip sends a 03h command or a 0Bh command to the SPI Flash device to read the SPI_BOOT segment from the Boot Image.

[0024] In one embodiment, the chip receives data from the SPI Flash device and adaptively detects and acquires the offset of the user program during transmission, including:

[0025] The chip receives data from the SPI Flash device; the data includes dummy bits and a Boot Image excluding the SPI_BOOT segment and the header preceding that segment.

[0026] RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment.

[0027] In one embodiment, when the header after the SPI_BOOT segment is header one: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including:

[0028] Set N=0, dummy bits length=0x20, K=0.

[0029] RBL analyzes the data read from SPI word by word. If the first word is equal to the preset value, then dummy bitslength = 0x20 and K = 1; if the first word is not equal to the preset value, then dummy bits length = 0 and K = 0.

[0030] Calculate N to find the number of zeros in the (2+K)th word; then calculate the offset, and delete dummy bits and the table header; the offset is:

[0031] Offset = dummy bits length + N.

[0032] In one embodiment, when the header after the SPI_BOOT segment is header two: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including:

[0033] Set N=0, dummy bits length=0x0, K=0.

[0034] If DQ is connected to a pull-up or pull-down column, when the first word equals the preset value, then the dummy bits length = 0x20, K = 1; check if D(1+K) equals the header; if not, shift left starting from the 1+Kth word, incrementing N = N+1 for each left shift, until D(N+K) equals the header; if equal, calculate the offset, delete the dummy bits and the header; the offset is:

[0035] Offset = dummy bits length + N.

[0036] If DQ is not connected to a pull-up or pull-down, check if D(1+K) equals the header. If not, shift left starting from the 1+Kth word, incrementing N = N+1 for each left shift, until D(N+K) equals the header. If they are equal, calculate the offset and delete the dummy bits and the header. The offset is:

[0037] Offset = dummy bits length + N.

[0038] In one embodiment, when the header after the SPI_BOOT segment is header three: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including:

[0039] Set N=0, dummy bits length=0x20, K=0.

[0040] RBL analyzes the data read from SPI word by word and determines whether D(3) equals 0x0. If it does, then dummy bits length = 0x20 and K = 1; otherwise, dummy bits length = 0 and K = 0.

[0041] Calculate the number of zeros in the (4+K)th word as N, then calculate the offset, delete dummy bits and the table header; the offset is:

[0042] dummy bits length=dummy bits length+N.

[0043] In one embodiment, the bootstrap mode includes, but is not limited to, signal sampling mode control, SPICLK rate control, SPI Flash device QE, and ProtoType.

[0044] The aforementioned SPI BOOT method, compatible with multiple SPI Flash models, utilizes RBL design and table-format Boot Image design to detect and acquire the offset of the user program during transmission, adaptively correcting this offset. This solves compatibility issues caused by different default values ​​for the dummy clock cycles parameter and different methods of reading and writing to the parameter register in different SPI flash devices, as well as data offset issues caused by delays due to board-level routing delays and non-compliant chip layout and routing. By incorporating the bootstrap mode information of the SPI BOOT method into the Boot Image, chip pin resources are saved, avoiding the risks of multi-channel signal interference and insufficient pin drive force during port multiplexing, and enhancing the scalability of bootstrap mode types. Furthermore, a wider variety of bootstrap modes facilitates SPI BOOT compatibility with various SPI flash device models. Attached Figure Description

[0045] Figure 1 This is a hardware structure diagram of an SPI Flash device interconnecting with a chip via SPI in one embodiment;

[0046] Figure 2 This is a flowchart illustrating an SPI BOOT method compatible with multiple SPI Flash types in one embodiment.

[0047] Figure 3 In another embodiment, the Boot Image is in Table format;

[0048] Figure 4 This is a flowchart illustrating a method for calculating the dummy bits length in another embodiment;

[0049] Figure 5 This is a flowchart illustrating a method for calculating the dummy bits length in another embodiment;

[0050] Figure 6 This is a flowchart illustrating a method for calculating the dummy bits length in another embodiment;

[0051] Figure 7 This is a schematic diagram of the RBL process in another embodiment. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0053] The SPI BOOT method proposed in this application, which is compatible with multiple SPI Flash devices, is a BOOT method where the SPI (Serial Peripheral Interface) acts as the slave and the chip acts as the master. The BOOT logic is mainly implemented by the ROM BootLoader (RBL) embedded in the chip. Due to the differences in the functions and usage of different SPI flash devices, and the late start of domestic production, domestic SPI BOOTs generally refer to the usage standards of classic foreign SPI flash devices for personalized design, and cannot be compatible with multiple domestic and foreign SPI flash devices at the same time. This low compatibility is not conducive to the localization of products. This invention proposes a bootstrapping technology that is compatible with multiple SPI flash devices through research on multiple domestic and foreign SPI flash devices. This method mainly uses RBL design and table format Boot Image design to detect and obtain the offset of the user program during transmission. The offset mainly comes from the output delay of the SPI flash device, and secondarily from the board-level routing delay and the delay caused by non-compliant internal layout and routing of the chip. The BOOT can adaptively correct this offset; it can flexibly switch SPI bootstrapping modes without occupying external pins; and it uses a bootstrapping process that is common to various SPI flash device models. This ultimately resolves the incompatibility issue of SPI BOOT with different types of SPI flash devices. This technology belongs to the field of embedded systems and ICs.

[0054] Compared to traditional SPI bootstrapping, this application adds a function that can adaptively correct user data transmission misalignment. This is mainly achieved by implementing a dummy bits length detection function with a detection length range of 0 to 64 bits, which meets the requirement of correcting SPI read data misalignment caused within the dummy clock cycles parameter range. Furthermore, it adopts a set of highly compatible SPI bootstrapping procedures and SPI Flash device instruction sets. These technologies facilitate users in flexibly selecting SPI Flash device models for bootstrapping and promote the localization of SPI Flash devices.

[0055] The SPI BOOT function is mainly implemented by the RBL in the BOOT component. The SPI Flash device is interconnected with the chip via SPI, and the Boot Image is stored in the SPI Flash device. The hardware structure of the SPI Flash device interconnecting with the chip via SPI is as follows: Figure 1 As shown.

[0056] In one embodiment, such as Figure 2As shown, an SPI BOOT method compatible with multiple SPI Flash devices is provided. The SPI Flash devices are interconnected with the chip via an SPI interface. The method includes the following steps:

[0057] Step 100: Collect the bootstrap mode information of SPI BOOT into a Boot Image, which is stored in the SPI Flash device. The Boot Image includes a header, an SPI_BOOT segment, a table header, the number of bytes of the original user program, the destination address of the original user program, the original user data, and an end marker. A Table-formatted Boot Image is shown below. Figure 3 As shown.

[0058] Specifically, traditional SPI BOOT inputs boot modes via chip pins. However, an excessive number of BOOT pins can over-consume limited pin resources. While port multiplexing can improve pin resource utilization, it increases the risk of multi-channel signal interference and reduces pin driving capability. This invention integrates boot modes into the Boot Image and uses RBL for decoding, avoiding the aforementioned problems and enhancing the scalability of boot mode types. The SPI_BOOT configuration is shown in Table 1.

[0059] Table 1 SPI_BOOT Configuration

[0060]

[0061]

[0062] Step 102: After the chip exits power-on reset, it begins to execute RBL, using RBL to decode the Boot Image.

[0063] Specifically, after the chip exits power-on reset, it begins executing RBL. RBL initializes and configures the SPI Flash component, including at least configuring full-duplex mode and configuring CPOL and CPHA to 2'b 00 or 2'b11 (all SPI Flash devices support this configuration). Then, it sends a 03h command (read) or 0Bh (full-duplex fast read) to the SPI Flash device to read the SPI_BOOT segment (bootstrap mode) from the Boot Image. The bootstrap mode, as shown in Table 1, includes signal sampling mode control, SPICLK rate control, SPI Flash device QE, and ProtoType. If the SPI Flash device requires a 1 after the QE bit is enabled (i.e., written to), it can use the four-wire read mode; therefore, the user needs to set the SPI_BOOT segment QE bit to 1.

[0064] The order of the SPI_BOOT functional fields is not limited to those mentioned above, and the functions included in the SPI_BOOT segment are not limited to those mentioned above. The header before the SPI_BOOT segment and the header after the segment have completely identical content and functions, so the functions of the header before the SPI_BOOT segment will not be repeated here.

[0065] Step 104: The chip receives data from the SPI Flash device and adaptively detects and obtains the offset of the user program during transmission.

[0066] Specifically, the default value for the dummy clock cycles parameter varies among different SPI flash device models, and the methods for reading and writing to this register also differ. Since BOOT is hardware logic, the dummy clock cycles parameter for different models cannot be obtained by adjusting the way the SPI flash device register is accessed. When a different SPI flash device with different dummy clock cycles parameters and different register access methods is used, and the dummy clock cycles parameter is also unknown, the chip cannot correctly delete dummy bits from the received data and extract the actual valid data. Examples of differences in the dummy clock cycles parameter among different SPI flash device models are as follows: In fast read mode, the default value for the dummy clock cycles of the Numonyx-N25Q128 SPI flash device is 15, determined by the high four bits of the VCR (Volatile Configuration Register). The default value for the Fudan Microelectronics-JFM25F128 SPI flash device is 8, determined by the status register protection bits (LC1, LC0).

[0067] Traditional SPI boot controls the dummy bits length by reading and writing to the dummy clock cycles parameter register to correctly delete dummy bits and correct boot image misalignment. However, the way the host accesses the dummy clock cycles parameter register differs across SPI Flash devices, and the default values ​​of the dummy clock cycles parameter also vary, affecting the compatibility of SPI boot with different SPI Flash devices. This method, through RBL and boot image design, can detect and acquire the offset of the user program during transmission, adaptively correcting this offset. It solves the compatibility problems caused by different default values ​​of the dummy clock cycles parameter and different ways of reading and writing to the parameter register across different SPI Flash devices, as well as data offset problems caused by delays due to board-level routing delays and non-compliant chip layout and routing.

[0068] Step 106: Correct data misalignment based on offset, retain user program segment and end marker, and delete other segments.

[0069] Step 108: Move the original user program segment of the preset byte length to the destination address of the program, and move n user program segments to their respective destination addresses in this way;

[0070] Step 110: When the end marker is detected, the PC jumps to the specified address to start executing the user program.

[0071] In the aforementioned SPI BOOT method compatible with multiple SPI Flash models, the method uses RBL design and table-format Boot Image design to detect and acquire the offset of the user program during transmission, achieving adaptive correction of this offset. This solves the compatibility problems caused by different default values ​​of the dummy clock cycles parameter and different methods of reading and writing to the parameter register in different SPI flash devices, as well as the data offset problems caused by delays due to board-level routing delays and non-compliant chip layout and routing. By aggregating the bootstrap mode information of the SPI BOOT method into the Boot Image, chip pin resources are saved, the risks of multi-channel signal interference and insufficient pin drive force during port multiplexing are avoided, and the scalability of bootstrap mode types is enhanced. At the same time, a wider variety of bootstrap modes facilitates SPI BOOT compatibility with various SPI flash devices.

[0072] As the design capabilities of domestically produced memory chips continue to improve, and products become increasingly mature and diverse, domestic consumers are increasingly favoring domestic brands. However, previous bootloader designs generally referenced the usage standards of classic foreign memory chips, resulting in customized designs that limited the domestic substitution of memory chips. Therefore, by optimizing the bootloader process and boot image design to achieve SPI bootloader compatibility with various SPI flash devices, this approach not only unlocks the consumption potential of domestically produced memory chips but also provides a new solution to the memory chip compatibility issues encountered when booting other components.

[0073] In one embodiment, step 102 includes the following steps:

[0074] Step 200: After the chip exits power-on reset, it begins executing RBL, which initializes and configures the SPI components.

[0075] Step 204: The chip controls the SPI to read the SPI_BOOT segment from the SPI Flash device to determine the bootstrap mode of the SPI Flash device; then, it initializes and configures the SPI Flash device according to the bootstrap mode of the SPI Flash device.

[0076] Step 206: Control the SPI to send a read command to the SPI Flash device according to the SPIProtoType corresponding to the bootstrap mode of the SPI Flash device.

[0077] Step 208: Configure the SPI ProtoType register according to the bootstrap mode of the SPI Flash device, clear the SPI receive queue, and then generate SPICLK for a specific period.

[0078] Traditional SPI bootloaders are typically customized based on the usage standards of specific manufacturers or models of SPI Flash devices. However, the usage standards for different SPI Flash device models are not entirely unified, mainly in terms of the presence and functionality of instructions. This affects the compatibility of SPI bootloaders with different SPI Flash device models. This invention employs an instruction set compatible with various SPI Flash device models and handles their special features, such as QE, to produce a bootloader process for accessing SPI Flash devices.

[0079] In one embodiment, the read instructions in step 206 include: 03h instruction, 0Bh instruction, 3Bh instruction and 6Bh instruction; before sending the 6Bh instruction, it is necessary to determine whether the enable bit for writing 1 to the QE bit of the SPI Flash device is 1. If it is not 1, the QE bit of the SPI Flash device is set to 1 and then the 6Bh instruction is sent. If it is 1, the 6Bh instruction is sent.

[0080] Specifically, different models of SPI Flash devices have both commonalities and unique characteristics. To ensure SPI BOOT compatibility across various models, it is necessary to extract the commonalities and handle the unique characteristics accordingly. This study examines eight commonly used SPI Flash device models and selects a universal SPI Flash device instruction set (consistent instructions and functions). The read instructions include 03h (full-duplex send command and address, full-duplex read data, no dummy clock cycles), 0Bh (full-duplex send command and address, full-duplex fast read data), 3Bh (full-duplex send command and address, two-wire fast read data), and 6Bh (full-duplex send command and address, four-wire fast read data). Since SPI Flash devices default to full-duplex mode, switching the SPI Flash device mode before using the above instructions is unnecessary. Some SPI Flash devices can only use four-wire read after QE (four-wire mode enable) is configured. The QE bit characteristics of different SPI Flash devices are shown in Table 2. Whether to write 1 to the QE bit of the SPI Flash device is controlled by SPI_BOOT

[10] . If SPI_BOOT

[10] is 0, there is no operation; if it is 1, 1 is written to the QE bit of the SPI Flash device. The way to write the QE bit of all SPI Flash devices is the same, that is, first send the write enable command (06h) to the SPI Flash device, and then write S9 (the first bit of the status register, i.e., the QE bit) through the write status register command (31h).

[0081] Table 2. Characteristics of the QE bit in different SPI Flash devices.

[0082]

[0083] In one embodiment, after the chip exits power-on reset, it begins to execute RBL. RBL initializes and configures the SPI components, including configuring full-duplex mode and configuring CPOL and CPHA as 2'b 00 or 2'b11.

[0084] In one embodiment, step 204, in which the chip controls the SPI to read the SPI_BOOT segment from the SPI Flash device, includes: the chip sending a 03h command or an 0Bh chip to the SPI Flash device to read the SPI_BOOT segment from the Boot Image.

[0085] In one embodiment, step 104 includes: the chip receiving data from the SPI Flash device; the data includes dummy bits and a Boot Image excluding the SPI_BOOT segment and the header before that segment; the RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment.

[0086] In one embodiment, when the header after the SPI_BOOT segment is header one: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including: setting N=0, dummy bits length=0x20, K=0; RBL analyzes the data read from SPI by word, if the first word is equal to the preset value, then dummy bits length=0x20, K=1; if the first word is not equal to the preset value, then dummy bits length=0, K=0; calculates the number of zero bits in the 2+Kth word as N; then calculates the offset, deletes the dummy bits and the header; the offset is: offset = dummy bits length + N.

[0087] In one embodiment, when the header after the SPI_BOOT segment is header two: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including: setting N=0, dummy bits length=0x0, K=0; if DQ is connected to pull-up or pull-down, when the first word equals the preset value, then dummy bits length=0x20, K=1; determining whether D(1+K) is equal to the header, if not, then shifting left from the 1+Kth word, N=N+1 for each left shift, until D(N+K) equals the header; if equal, then calculating the offset, deleting the dummy bits and the header; the offset is: offset = dummy bits length+N; If DQ is not connected to a pull-up or pull-down, check if D(1+K) is equal to the header. If not, start left shifting from the 1+Kth word, incrementing N=N+1 for each left shift, until D(N+K) equals the header. If they are equal, calculate the offset and delete the dummy bits and the header. The offset is: offset = dummy bits length+N.

[0088] In one embodiment, when the header after the SPI_BOOT segment is header three: RBL calculates the offset of the user program in the transmission by processing the header after the SPI_BOOT segment, including: setting N=0, dummy bits length=0x20, K=0; RBL analyzes the data read by SPI by word, and judges whether D(3) equals 0x0. If it is true, then dummy bits length=0x20, K=1; if it is not true, then dummy bits length=0, K=0; calculates the number of 0s in the 4+Kth word as N, then calculates the offset, and deletes the dummy bits and the header; the offset is: dummy bits length=dummy bits length+N.

[0089] Specifically, three similar methods are proposed for calculating the dummy bits length. These three methods are represented by three header values: header 1 for method 1, header 2 for method 2, and header 3 for method 3. D(x) represents the x-th word retrieved by RBL from the SPI receive queue (receive FIFO). Method 1 is as follows... Figure 4 As shown, SPI reads dummy bits and the Boot Image (excluding the SPI_BOOT segment and the header before it). RBL analyzes the data read by SPI, checking if the first word is equal to 0xffffffff (when DQ is connected to a pull-up resistor) or 0x0 (when DQ is connected to a pull-down resistor). If they are equal, then dummy bit length = 0x20 and K = 1. If they are not equal, then dummy bit length = 0 and K = 0. Then, it is calculated that N bits in the 2+Kth word are 0, so dummy bit length = dummy bit length + N. Method 2 is as follows. Figure 5 As shown, if DQ is not connected to a pull-up or pull-down switch, ignore the dotted part. If DQ is connected to a pull-up or pull-down switch, use the dotted part (consistent with the first half of Method 1). Then check if D(1+K) equals the header. If not, start shifting left from the 1+Kth word, incrementing N by N+1 for each left shift, until D(N+K) equals the header. At this point, the dummy bits length = dummy bits length + N. Method 3 is as follows. Figure 6As shown, we do not consider the pull-up / pull-down resistors connected to DQ because we directly judge D(3), so any number of dummy bits will not affect the judgment. We judge whether D(3) is equal to 0x0. If they are equal, then dummy bits length = 0x20 and K = 1. If they are not equal, then dummy bits length = 0 and K = 0. We then calculate that there are N bits that are 0 in the 4+Kth word, so dummy bits length = dummy bits length + N. The table header corresponding to the above method is not limited to the one listed in this embodiment, and can also be other values, as long as it satisfies the function of the above method.

[0090] In one embodiment, the bootstrap mode includes, but is not limited to, signal sampling mode control, SPICLK rate control, SPI Flash device QE, and ProtoType.

[0091] In one specific embodiment, the entire BOOT process is summarized in conjunction with the RBL flowchart, such as... Figure 7 As shown:

[0092] Step 1: After the chip exits power-on reset, it starts executing RBL. RBL initializes and configures the SPI components to full-duplex mode, and sets CPOL and CPHA to 2'b 00 or 2'b 11.

[0093] Step 2: Control the SPI to read (03h instruction or 0Bh instruction) from the SPI Flash device into the SPI_BOOT segment, and then initialize and configure the SPI component according to the bootstrap mode.

[0094] Step 3: Control the SPI to send a read command (03h / 0Bh / 3Bh / 6Bh) to the SPI Flash device according to the SPIProtoType corresponding to the bootstrap mode, followed by sending the read address. Additionally, before sending the four-wire fast read command (6Bh), the QE bit value of the SPI_BOOT segment needs to be checked to determine whether the QE bit of the SPI Flash device should be set to 1 before sending the read command.

[0095] Step 4: Configure the SPI ProtoType register according to the bootstrap mode, clear the SPI receive queue, and then generate SPICLK for a specific period.

[0096] Step 5: Receive data from the SPI Flash device, including dummy bits and Boot Image (excluding the SPI_BOOT segment and the header before it). RBL calculates the offset of the user data by processing the header.

[0097] Step 6: Correct the data misalignment based on the offset, retain the user program segment and the end marker, and delete other segments.

[0098] Step 7: Move the original user program segment of length i bytes to the destination address of the program, and move the n user program segments to their respective destination addresses in this way.

[0099] Step 8: When the end flag segment is detected, the PC jumps to the specified address to start executing the user program.

[0100] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An SPI BOOT method compatible with multiple SPI Flash, characterized in that, The SPI Flash device is interconnected with the chip via an SPI interface, and the method includes: The boot mode information of SPI BOOT mode is collected into the Boot Image, which is stored in the SPI Flash device. The Boot Image includes a header, SPI_BOOT segment, header, number of bytes of the original user program, destination address of the original user program, original user data, and end flag. After the chip exits power-on reset, it begins executing RBL, using RBL to decode the Boot Image; The chip receives data from the SPI Flash device and adaptively detects and acquires the offset of the user program during transmission; Correct data misalignment based on the offset, retain the user program segment and end marker, and delete other segments; Move the original user program segment of a preset byte length to the destination address of the program, and move n user program segments to their respective destination addresses in this way; When the end marker is detected, the PC jumps to the specified address to begin executing the user program.

2. The method of claim 1, wherein, After the chip exits power-on reset, it begins executing RBL, which decodes the Boot Image using RBL, including: After the chip exits power-on reset, it begins executing RBL, which initializes and configures the SPI components. The chip controls the SPI to read the SPI_BOOT segment from the SPI Flash device to determine the bootstrap mode of the SPI Flash device; then, it initializes and configures the SPI Flash device according to the bootstrap mode of the SPI Flash device. The SPI controller sends read commands to the SPI Flash device based on the SPI ProtoType corresponding to the bootstrap mode of the SPI Flash device. Configure the SPI ProtoType register according to the bootstrap mode of the SPI Flash device, clear the SPI receive queue, and then generate SPICLK for a specific period.

3. The method of claim 2, wherein, According to the SPIProtoType corresponding to the bootstrap mode of the SPI Flash device, the SPI controls the SPI to send read commands to the SPI Flash device. The read commands in the steps include: 03h command, 0Bh command, 3Bh command and 6Bh command. Before sending the 6Bh instruction, it is necessary to determine whether the enable bit for writing 1 to the QE bit of the SPI Flash device is 1 in the SPI_BOOT segment. If it is not 1, the QE bit of the SPI Flash device is set to 1 and then the 6Bh instruction is sent. If it is 1, the 6Bh instruction is sent. When the enable bit controlling whether to write 1 to the QE bit of the SPI Flash device is not 0, then the QE bit is written to 1; a four-wire fast read data command is sent.

4. The method of claim 2, wherein, After the chip exits power-on reset, it begins executing RBL. RBL initializes and configures the SPI components, including configuring full-duplex mode and configuring CPOL and CPHA to 2'b 00 or 2'b 11.

5. The method of claim 2, wherein, The chip controls the SPI to read the SPI_BOOT segment from the SPI Flash device, including: The chip sends a 03h command or a 0Bh command to the SPI Flash device to read the SPI_BOOT segment from the Boot Image.

6. The method of claim 1, wherein, The chip receives data from the SPI Flash device and adaptively detects and acquires the offset of the user program during transmission, including: The chip receives data from the SPI Flash device; the data includes dummy bits and a BootImage excluding the SPI_BOOT segment and the header preceding that segment. RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment.

7. The method according to claim 6, characterized in that, When the header after the SPI_BOOT segment is header one: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including: Set N=0, dummy bits length=0x20, K=0; RBL analyzes the data read from SPI word by word. If the first word equals the preset value, then the dummy bits length = 0x20 and K = 1; if the first word does not equal the preset value, then the dummy bits length = 0 and K = 0. Calculate N as the number of zeros in the (2+K)th word; then calculate the offset, and delete dummy bits and the table header; the offset is: Offset = dummy bits length + N.

8. The method according to claim 6, characterized in that, When the header after the SPI_BOOT segment is header two: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including: Set N=0, dummy bits length=0x0, K=0; If DQ is connected to a pull-up or pull-down column, when the first word equals a preset value, then the dummy bits length = 0x20 and K = 1; determine if D(1+K) equals the header; if not, shift left starting from the 1+Kth word, incrementing N = N+1 for each left shift, until D(N+K) equals the header; if equal, calculate the offset and delete the dummy bits and the header; the offset is: Offset = dummy bits length + N; If DQ is not connected to a pull-up or pull-down, check if D(1+K) equals the header. If not, shift left starting from the 1+Kth word, incrementing N = N+1 for each left shift, until D(N+K) equals the header. If they are equal, calculate the offset and delete the dummy bits and the header. The offset is: Offset = dummy bits length + N.

9. The method of claim 6, wherein, When the header after the SPI_BOOT segment is header three: RBL calculates the offset of the user program during transmission by processing the header after the SPI_BOOT segment, including: Set N=0, dummy bits length=0x20, K=0; RBL analyzes the data read from SPI word by word and determines whether D(3) equals 0x0. If it does, then dummy bits length = 0x20 and K = 1; otherwise, dummy bits length = 0 and K = 0. Calculate N, the number of zeros in the (4+K)th word, then calculate the offset, and delete dummy bits and the table header; the offset is: dummy bits length=dummy bits length+N.

10. The method of claim 1, wherein, The bootstrap mode includes, but is not limited to, signal sampling mode control, SPICLK rate control, SPI Flash device QE, and ProtoType.

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