Memory device and operating method of a memory device

Abstract

Embodiments of the present disclosure relate to a memory device and an operating method of a memory device, the memory device including a first memory block and a second memory block, each of the first memory block and the second memory block including a plurality of memory cells. The memory device further includes a voltage generator for applying an operating voltage to a first global line, selectively applying a positive voltage to a global selection line included in a second global line while the operating voltage is applied, and applying a ground voltage to other global lines among the second global line except for the global selection line. The memory device further includes a row decoder for turning on a first pass switch between the first global line and a first local line connected to the first memory block, and turning off a second pass switch between the second global line and a second local line connected to the second memory block.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0095615, filed on August 1, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to memory devices and methods of operating memory devices, and more specifically, to memory devices configured to perform programming operations and methods of operating such memory devices. Background Technology

[0004] A memory device may include: an array of memory cells in which data is stored; peripheral circuitry configured to perform programming, reading, or erasing operations; and control logic configured to control the peripheral circuitry.

[0005] A memory cell array may include multiple memory blocks, and each memory block may include multiple memory cells. The memory device may be implemented as a two-dimensional or three-dimensional structure.

[0006] In a memory device implemented as a two-dimensional structure, memory cells can be arranged in a direction parallel to the substrate. Because the memory cells are arranged parallel to the substrate, the channels of the memory cells can be formed from single-crystal silicon.

[0007] In memory devices implemented as three-dimensional structures, memory cells can be stacked in a direction perpendicular to the substrate. Because the memory cells are stacked on top of the substrate, the channels of the memory cells can be formed from polysilicon. Polysilicon is configured with multiple grains, and therefore the boundaries of the grains can become trap points. When these trap points are filled with holes, the channel may become in a donor-like state. The channel potential can be increased to a positive level. This phenomenon can occur in unselected memory blocks when programming operations are performed in selected memory blocks. When channel boost occurs in unselected memory blocks, it can affect subsequent operations that can be performed in those unselected memory blocks, and therefore, the reliability of the memory device may be reduced. Summary of the Invention

[0008] Some embodiments provide memory devices and methods of operating memory devices, wherein channel boost can be suppressed in unselected memory blocks during programming operations of selected memory blocks.

[0009] According to embodiments of the present disclosure, a memory device includes: a first memory block and a second memory block, each including a plurality of memory cells; a voltage generator configured to apply an operating voltage to a first global line, selectively apply a positive voltage to a global select line included in a second global line while the operating voltage is applied, and apply a ground voltage to other global lines in the second global line besides the global select line; and a line decoder configured to turn on a first pass switch between the first global line and a first local line connected to the first memory block, and configured to turn off a second pass switch between the second global line and a second local line connected to the second memory block.

[0010] According to another embodiment of this disclosure, the memory device includes: a first memory block and a second memory block, each including a plurality of memory cells; a voltage generator configured to apply an operating voltage to a first global line, selectively apply a positive voltage to a global select line included in the second global line while the operating voltage is applied, and apply a ground voltage to other global lines in the second global line besides the global select line; and a row decoder configured to apply a first block select signal having a high voltage to a first pass switch between the first global line and a first local line connected to the first memory block, and selectively apply a negative voltage to a second pass switch between the second global line and a second local line connected to the second memory block.

[0011] According to another embodiment of the present disclosure, a method of operating a memory device includes: turning on a first pass switch between a first global line and a first local line connected to a first memory block; turning off a second pass switch between a second global line and a second local line connected to a second memory block; applying a programming voltage to a selected global word line in the first global line; applying a positive voltage to a global select line in the second global line when the programming voltage is applied to the selected global word line; and applying a negative voltage to the gate of the second pass switch when the programming voltage is applied to the selected global word line. Attached Figure Description

[0012] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be readily apparent to those skilled in the art.

[0013] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals refer to similar elements throughout.

[0014] Figure 1 This is a schematic diagram of a memory device.

[0015] Figure 2 It is a diagram illustrating a memory block.

[0016] Figure 3 This is a diagram illustrating a voltage generator and a line decoder.

[0017] Figure 4A and Figure 4B This is a diagram illustrating the selection transistors for selected and unselected memory blocks during programming operations.

[0018] Figure 5A and Figure 5B This is a diagram illustrating gate-induced drain leakage (GIDL) that may occur in an unselected memory block.

[0019] Figure 6 The diagram illustrates the voltage used for programming operations according to this disclosure.

[0020] Figure 7 It is a diagram illustrating programming operations according to this disclosure.

[0021] Figure 8A and Figure 8B This is a diagram illustrating the operation of a selection transistor according to the present disclosure.

[0022] Figure 9 It is a diagram illustrating the voltage of the selected line during a voltage change period according to this disclosure. Detailed Implementation

[0023] For the purpose of describing embodiments according to the concepts of this disclosure, the specific structural and functional descriptions disclosed herein are merely illustrative. Embodiments according to the concepts of this disclosure may be implemented in various forms. Therefore, this disclosure should not be construed as limiting itself to the embodiments set forth herein.

[0024] In the following text, it will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another, and not to imply the number or order of elements.

[0025] Figure 1 This is a schematic diagram of a memory device.

[0026] See Figure 1 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control circuitry 130.

[0027] The memory cell array 110 may include multiple memory blocks BLK1 to BLKj. The multiple memory blocks BLK1 to BLKj may be implemented in a three-dimensional structure. For example, each of the multiple memory blocks BLK1 to BLKj may include multiple memory cells, and the multiple memory cells may be stacked in the vertical direction above the substrate.

[0028] The peripheral circuitry 120 can be configured to perform programming, reading, or erasing operations on the memory cell array 110 under the control of the control circuitry 130. For example, the peripheral circuitry 120 may include a voltage generator 21, a row decoder 22, a source voltage generator 23, a page buffer group 24, a column decoder 25, and input / output circuitry 26.

[0029] Voltage generator 21 can be configured to generate various operating voltages using the internal power supply voltage supplied to memory device 100. For example, voltage generator 21 can generate programming voltage, pass voltage, verification voltage, read voltage, erase voltage, turn-on voltage, turn-off voltage, ground voltage, etc. Furthermore, voltage generator 21 can generate positive or negative voltages with different levels. Voltage generator 21 can adjust the level and output timing of the operating voltage in response to opcode OPCD. Voltage generator 21 can output the operating voltage via a first global line 1GL and a second global line 2GL. For example, voltage generator 21 may include a first operating voltage generator 1OVG and a second operating voltage generator 2OVG, where the first operating voltage generator 1OVG is configured to output the operating voltage via the first global line 1GL, and the second operating voltage generator 2OVG is configured to output the operating voltage via the second global line 2GL. The first operating voltage generator 1OVG and the second operating voltage generator 2OVG can be configured to output different voltages according to the opcode. For example, when the first operating voltage generator 1OVG outputs a voltage to be transmitted to the selected memory block, the second operating voltage generator 2OVG can be configured to output a ground voltage or a positive voltage via the second global line 2GL. Alternatively, when the second operating voltage generator 2OVG outputs a voltage to be transmitted to the selected memory block, the first operating voltage generator 1OVG can be configured to output a ground voltage or a positive voltage via the first global line 1GL.

[0030] The row decoder 22 can be configured to receive voltages output from the voltage generator 21 via a first global line 1GL and a second global line 2GL, and transmit the received voltages to local lines LL. Local lines LL can be connected to each of a plurality of memory blocks BLK1 to BLKj. The row decoder 22 can transmit operating voltages to local lines LL connected to selected memory blocks in response to a row address RADD. For example, the row decoder 22 can transmit operating voltages to local lines LL connected to selected memory blocks and transmit ground voltage or positive voltages to local lines LL connected to unselected memory blocks. The row decoder 22 can be configured to increase the voltage of some lines in local lines LL connected to unselected memory blocks by using gate-induced drain leakage (GIDL).

[0031] The source voltage generator 23 can be configured to generate a source voltage in response to the source voltage control signal SVCS and output the source voltage through the source line SL. The source line SL can be connected to multiple memory blocks BLK1 to BLKj, and therefore, the source voltage applied to the source line SL can be transmitted to multiple memory blocks BLK1 to BLKj.

[0032] Page buffer group 24 can be connected to multiple memory blocks BLK1 to BLKj via bit lines BL and to column decoder 25 via column lines CL. Page buffer group 24 may include page buffers (not shown) configured to operate in response to page buffer control signal PBSIG. Page buffers (not shown) can be configured to temporarily store data during programming, reading, or erasing operations. For example, during a programming operation, page buffer group 24 can temporarily store data received via column line CL and output a programming enable voltage or programming disable voltage to bit line BL based on the temporarily stored data. Furthermore, page buffer group 24 can determine data by sensing the voltage or current of bit line BL during a programming verification operation performed during a programming operation or an erasure verification operation performed during an erasure operation. During a reading operation, page buffer group 24 can read data by sensing the voltage or current of bit line BL and output the read data via column line CL.

[0033] The column decoder 25 can be connected to the page buffer group 24 via the column line CL and to the input / output circuit 26 via the data line DL. The column decoder 25 can transmit data in response to the column address CADD by connecting the data line DL and the column line CL to each other.

[0034] The input / output circuit 26 can be connected to the column decoder 25 via the data line DL and to an external device via the input / output line I / O. The external device may be a controller (not shown) that transmits commands (CMD), addresses (ADD), or data to the memory device 100. The input / output circuit 26 can transmit commands (CMD) and addresses (ADD) received via the input / output line I / O to the control circuit 130, and transmit data received via the input / output line I / O to the column decoder 25 via the data line DL. Alternatively, the input / output circuit 26 can output data received via the data line DL via the input / output line I / O.

[0035] Control circuitry 130 may include software and circuitry configured to output opcode OPCD, row address RADD, source voltage control signal SVCS, page buffer control signal PBSIG, and column address CADD according to command CMD and address ADD. For example, control circuitry 130 may include software that executes programming, reading, or erasing algorithms in response to command CMD, and circuitry configured to output various signals according to the selected algorithm in response to command CMD. Programming operations will be described as an example. Control circuitry 130 may execute a programming algorithm in response to a command for programming operations. Control circuitry 130 may output opcode OPCD, source voltage control signal SVCS, and page buffer control signal PBSIG according to the programming algorithm, and output row address RADD and column address CADD according to address ADD.

[0036] Figure 2 It is a diagram illustrating a memory block.

[0037] See Figure 2 , Figure 1 The diagram illustrates any one of the multiple memory blocks BLK1 to BLKj. Memory block BLK may include strings ST connected between the first to nth bit lines BL1 to BLn and the source line SL. Each string ST may include a source select transistor SST, memory cells MC1 to MCi, and a drain select transistor DST connected in series with each other. Although one source select transistor SST and one drain select transistor DST are included... Figure 2 Each of the strings ST shown may contain multiple source selection transistors SST and multiple drain selection transistors DST, but multiple source selection transistors DST may be included in a single string ST.

[0038] The gates of source-select transistors (SSTs) included in different strings (STs) can be connected to the first or second source-select line SSL1 or SSL2. For example, source-select transistors (SSTs) arranged in the X direction can be connected to the same source-select line, while some source-select transistors (SSTs) arranged in the Y direction can be connected to different source-select lines. For example, the first and second source-select transistors (SSTs) arranged in the Y direction can be connected to the first source-select line SSL1, and the third and fourth source-select transistors (SSTs) arranged in the Y direction can be connected to the second source-select line SSL2.

[0039] The gates of memory cells MC1 to MCi, which are included in different strings ST, can be connected to word lines WL1 to WLi. For example, memory cells arranged along the XY plane can be connected to the same word line, while memory cells arranged along the Z direction can be connected to different word lines. For example, the first memory cell MC1 arranged along the XY plane can be connected to the first word line WL1, and the i-th memory cell MCi arranged along the XY plane can be connected to the i-th word line WLi.

[0040] The gates of drain select transistors (DSTs) included in different strings (STs) can be connected to any of the first to fourth drain select lines (DSL1 to DSL4). The gates of drain select transistors (DSTs) arranged in the X direction are all connected to the same drain select line, but drain select transistors (DSTs) arranged in the Y direction can be connected to different drain select lines. For example, when drain select transistors (SSTs) are arranged sequentially along the Y direction, the first drain select transistor can be connected to the first drain select line (DSL1), the second drain select transistor can be connected to the second drain select line (DSL2), the third drain select transistor can be connected to the third drain select line (DSL3), and the fourth drain select transistor can be connected to the fourth drain select line (DSL4).

[0041] The number of source select lines and drain select lines connected to the memory block BLK is not limited to Figure 2 The number shown.

[0042] During programming or reading operations, the string ST connected to the selected drain line in the selected memory block can become the selected string, and the string ST connected to the unselected drain select line in the selected memory block can become the unselected string. For example, when a positive turn-on voltage is applied to the first drain select line DSL1 and a 0V turn-off voltage is applied to the second to fourth drain select lines DSL2 to DSL4, the first drain select line DSL1 can become the selected drain select line, and the second to fourth drain select lines DSL2 to DSL4 can become the unselected drain select lines. Therefore, the string ST connected to the first drain select line DSL1 can become the selected string, while the string ST connected to the second drain select lines DSL2 to the fourth drain select lines DSL4 can become the unselected string.

[0043] In programming or reading operations, the first source selection line SSL1, selected from the first and second source selection lines SSL1 and SSL2 and connected to the selected string, can become the selected source selection line, and the second source selection line SSL2, selected from the first and second source selection lines SSL1 and SSL2 and connected to the unselected string, can become the unselected source selection line. Therefore, the selected string and some unselected strings can be connected to the selected source line, and only the unselected string can be connected to the unselected source selection line.

[0044] Memory cells connected to the same word line can form a page PG. A page refers to a physical page. For example, memory cells arranged along the X direction in the first memory cell MC1 connected to the first word line WL1 can form a page PG. Therefore, multiple pages can be connected to each of the first to the i-th word lines WL1 to WLi.

[0045] Programming or reading operations can be performed on the selected page. The selected page can be determined by the selected word line and the selected drain select line. For example, in a programming operation, when the first word line WL1 is the selected word line and the first drain select line DSL1 is the selected drain select line, the memory cells included in the string connected to the first drain select line DSL1 among the memory cells connected to the first word line WL1 can constitute the selected page.

[0046] Memory cells can be programmed in various ways. For example, programming operations can be divided into single-level cell or multi-level cell methods based on the number of bits of data stored in a memory cell. A single-level cell method can store 1 bit of data in a memory cell, while a multi-level cell method can store 2 bits of data in a memory cell. Furthermore, programming operations can be divided into three-level cell methods storing 3 bits of data in a memory cell and four-level cell methods storing 4 bits of data in a memory cell. Additionally, programming operations can be performed in various ways to store 5 or more bits of data in a memory cell.

[0047] Figure 3 This is a diagram illustrating a voltage generator and a line decoder.

[0048] See Figure 3 The voltage generator 21 may include a first operating voltage generator 1OVG and a second operating voltage generator 2OVG. The first operating voltage generator 1OVG or the second operating voltage generator 2OVG can generate operating voltages used for programming, reading, or erasing operations, and the operating voltages can be output via a first global line 1GL or a second global line 2GL. When the first operating voltage generator 1OVG outputs an operating voltage to be applied to a selected memory block, the second operating voltage generator 2OVG can output a ground voltage or a positive voltage. When the second operating voltage generator 2OVG outputs an operating voltage to be applied to a selected memory block, the first operating voltage generator 1OVG can output a ground voltage or a positive voltage.

[0049] The first global line 1GL may include the global drain selection line GDSL, the first to the i-th global word lines GWL1 to GWLi, and the global source selection line GSSL. The second global line 2GL may also include the global drain selection line GDSL, the first to the i-th global word lines GWL1 to GWLi, and the global source selection line GSSL.

[0050] The line decoder 22 may include a first decoder 1DEC, a second decoder 2DEC, and first to fourth pass switch groups 1PSG to 4PSG. Each of the first to fourth pass switch groups 1PSG to 4PSG may include pass switches PS connected in parallel with each other. Because the pass switches PS need to transmit high voltages such as programming voltages, the pass switches PS can be implemented using high-voltage transistors. For example, the pass switches PS can be implemented using high-voltage NMOS transistors. The first and second decoders 1DEC and 2DEC can determine the levels of the first and second block select signals 1BLKST and 2BLKST in response to the line address RADD.

[0051] The first decoder 1DEC can be configured such that its output is jointly applied to the first block selection signal 1BLKST via the second and fourth switch groups 2PSG and 4PSG. The second decoder 2DEC can be configured such that its output is jointly applied to the second block selection signal 2BLKST via the first and third switch groups 1PSG and 3PSG.

[0052] The first switch group 1PSG can be configured to, in response to the second block selection signal 2BLKST output from the second decoder 2DEC, connect the first global line 1GL to the local line LL connected to the first memory block BLK1, or block the first global line 1GL from the local line LL connected to the first memory block BLK1. The second switch group 2PSG can be configured to, in response to the first block selection signal 1BLKST output from the first decoder 1DEC, connect the second global line 2GL to the local line LL connected to the second memory block BLK2, or block the second global line 2GL from the local line LL connected to the second memory block BLK2. The third switch group 3PSG is configured to, in response to the second block selection signal output from the second decoder 2DEC, connect the second global line 2GL to the local line LL connected to the third memory block BLK3, or block the second global line 2GL from the local line LL connected to the third memory block BLK3. The fourth switch group 4PSG can be configured to connect the first global line 1GL to the local line LL connected to the fourth memory block BLK4 in response to the first block selection signal 1BLKST output from the first decoder 1DEC, or to block the first global line 1GL from the local line LL connected to the fourth memory block BLK4.

[0053] The first to fourth pass switch groups 1PSG to 4PSG are configured similarly to each other, and therefore the first pass switch group 1PSG will be described in detail below.

[0054] The first pass switch group 1PSG can be turned on when the second select signal 2BLKST is high, and turned off when the second select signal 2BLKST is ground. High voltage is a positive voltage above 0V and can be a level higher than the programming voltage. For example, high voltage can be set to a level obtained by adding the threshold voltage turned on by switch PS to the programming voltage.

[0055] When the second block select signal 2BLKST is high, the pass switch PS, included in the first pass switch group 1PSG, is turned on. Therefore, the global drain select line GDSL, the first to the i-th global word lines GWL1 to GWLi, and the global source select line GSSL, included in the first global line 1GL, can be connected to the drain select line DSL, the first to the i-th word lines WL1 to WLi, and the source select line SSL, which are connected to the first memory block BLK1. Thus, the operating voltage applied to the first global line 1GL can be transmitted to the first memory block BLK1 via the first pass switch group 1PSG.

[0056] When the second block selection signal 2BLKST is ground voltage, the pass switch PS, which is included in the first pass switch group 1PSG, is turned off, and therefore, the local line LL connected to the first memory block BLK1 can be floated.

[0057] When the second selection signal 2BLKST is a negative voltage below ground, it can be turned off via switch PS. Although GIDL appears in some areas via switch PS as the level of the negative voltage increases, the voltage applied to the global drain select line GDSL and the global source select line GSSL is not transmitted to the drain select line DSL and the source select line SSL.

[0058] Figure 4A and Figure 4B This is a diagram illustrating the selection transistors for selected and unselected memory blocks during programming operations. Figure 4A The diagram illustrates the selected memory block, while Figure 4B The diagram shows the memory blocks that were not selected.

[0059] See Figure 4A and Figure 4BThe enable voltage Von can be applied to the drain select line DSL and source select line SSL connected to the selected memory block Sel_BLK. The programming voltage Vpgm can be applied to the selected word line connected to the selected memory block Sel_BLK, and the voltage Vpass can be applied to the unselected word line Unsele_WL connected to the selected memory block Sel_BLK. A source voltage Vsl with a positive voltage can be applied to the source line SL connected to the selected memory block Sel_BLK, and the programming enable voltage Val or programming disable voltage Vinh can be applied to the first to nth bit lines BL1 to BLn connected to the selected memory block Sel_BLK. The programming enable voltage Val can be set to ground or 0V, while the programming disable voltage Vinh can be set to a positive voltage. Because the first to nth bit lines BL1 to BLn will be electrically connected to the string in the selected memory block Sel_BLK, a positive turn-on voltage Von can be applied to the drain select line DSL, and the drain select transistor DST can be turned on (ON) by the turn-on voltage Von. A positive source voltage Vsl can be applied to the source line SL, but ground voltage can be applied to the source line SL according to the programming operation. Because the turn-on voltage Von is applied to the source select line SSL, the source select transistor SST can also be turned on (ON). When it is assumed that the first word line WL1 is the selected word line, the other second to i-th word lines WL2 to WLi become unselected word lines. The programming voltage Vpgm can be applied to the first word line WL1 as the selected word line, and the voltage Vpass can be applied to the second to i-th word lines WL2 to WLi as unselected word lines.

[0060] The first to nth bit lines BL1 to BLn are commonly connected to the selected memory block Sel_BLK and the unselected memory block Unsel_BLK. Therefore, to prevent channel boost in the unselected memory block Unsel_BLK, the drain select transistor DST and source select transistor SST, included in the unselected memory block Unsel_BLK, will be turned off. To turn off the drain select transistor DST and source select transistor SST, a ground voltage can be applied to the drain select line DSL, source select line SSL, and the first to i-th word lines WL1 to WLi connected to the unselected memory block Unsel_BLK, or the drain select line DSL, source select line SSL, and the first to i-th word lines WL1 to WLi can be floated.

[0061] However, when ground voltage VSS is applied to the drain select line DSL or the source select line SSL, leakage current may be generated at the drain select transistor DST or the source select transistor SST due to the voltage difference between the drain and gate or the source and gate. When leakage current is generated at the drain select transistor DST or the source select transistor SST, the positive voltage applied to the bit line or source line SL is introduced into the string, and channel boost may therefore occur.

[0062] The following will describe in detail the reasons for leakage current generated at the drain-select transistor (DST) or source-select transistor (SST).

[0063] Figure 5A and Figure 5B This is a diagram illustrating gate-induced drain leakage (GIDL) that may occur in an unselected memory block. Figure 5A It is a diagram illustrating the GIDL that may occur at the drain-select transistor (DST), and Figure 5B This is a diagram illustrating the GIDL that may occur at the source selection transistor SST.

[0064] See Figure 5A A drain-select transistor (DST) may include a channel layer CH, a tunnel insulating layer Tx, a charge trapping layer Ct, a barrier layer Bx, and a drain-select line DSL. When the memory device is implemented in a three-dimensional structure, the channel layer CH may be formed of polysilicon. The tunnel insulating layer Tx and the barrier layer Bx may be formed of insulating materials. For example, the tunnel insulating layer Tx and the barrier layer Bx may be formed of oxide layers or silicon oxide layers. The charge trapping layer Ct may be formed of nitride layers. The drain-select line DSL may be formed of conductive materials. For example, the drain-select line DSL may be formed of conductive materials such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni).

[0065] The drain DR of the drain-select transistor DST can be connected to the bit line BL. When a programming inhibit voltage Vinh, as a positive voltage, is applied to the bit line BL and a ground voltage VSS is applied to the drain-select line DSL, the drain DR region can extend into the region adjacent to the drain-select line DSL due to the voltage difference between the drain DR and the drain-select line DSL. Therefore, GIDL may occur when holes H escape from the channel layer CH between the drain DR and the tunnel insulating layer Tx, and then electrons e move to the region from which holes H escape. When GIDL occurs, leakage current is generated at the drain-select transistor DST, which is to be kept in the off state, and thus the programming inhibit voltage Vinh applied to the bit line BL can be gradually introduced into the channel layer CH. Therefore, channel boost may occur in the channel layer CH.

[0066] See Figure 5BThe source selection transistor SST is implemented with the same structure as the drain selection transistor DST, and therefore the description of the structure of the source selection transistor SST will be omitted.

[0067] The source SC of the source-select transistor SST can be connected to the source line SL. When a positive source voltage Vsl is applied to the source line SL and a ground voltage VSS is applied to the source-select line SSL, the source SC region can extend into the region adjacent to the source-select line SSL due to the voltage difference between the source SC and the source-select line SSL. Therefore, GIDL may occur when holes H escape from the channel layer CH between the source SC and the tunnel insulating layer Tx, and then electrons e move to the region from which holes H escape. When GIDL occurs, leakage current is generated at the source-select transistor SST, which is to be kept in the off state, and thus the source voltage Vsl applied to the source line SL can be gradually introduced into the channel layer CH. Therefore, channel boost may occur in the channel layer CH.

[0068] In the following embodiments, an operational method for preventing GIDL from occurring in a drain-select transistor (DST) or source-select transistor (SST) included in an unselected memory block is disclosed.

[0069] Figure 6 The diagram illustrates the voltage used for programming operations according to this disclosure.

[0070] See Figure 3 and Figure 6 During the programming operation of the selected memory block Sel_BLK, the voltage of the global line and the voltage of the block selection signal corresponding to the unselected memory block Unsel_BLK can be adjusted.

[0071] Assume that among the first to fourth memory blocks BLK1 to BLK4, the fourth memory block BLK4 is the selected memory block Sel_BLK, and the first to third memory blocks BLK1 to BLK3 are the unselected memory blocks Unsel_BLK.

[0072] Because the operating voltage Vop applied to the selected memory block Sel_BLK is applied to the selected memory block Sel_BLK through the first global line 1GL and the fourth through switch group 4PSG, the first operating voltage generator 1OVG can generate the operating voltage Vop, and the first decoder 1DEC can output the first block selection signal 1BLKST with a high voltage.

[0073] In the unselected memory block Unsel_BLK, the first memory block BLK1 corresponds to the first pass switch group 1PSG and the first global line 1GL, the second memory block BLK2 corresponds to the second pass switch group 2PSG and the second global line 2GL, and the third memory block BLK3 corresponds to the third pass switch group 3PSG and the second global line 2GL.

[0074] During the programming operation of the selected memory block Sel_BLK, a ground voltage VSS is applied to the second global line 2GL, but a positive voltage Vp can be applied to some global lines during certain periods of the programming operation. For example, the second operating voltage generator 2OVG can apply a positive voltage Vp to the global drain select line GDSL and the global source select line GSSL during certain periods of the programming operation. The reason for applying a positive voltage Vp to the global drain select line GDSL and the global source select line GSSL is that the positive voltage is transmitted to the drain select line DSL and the source select line SSL connected to the unselected memory block Unsel_BLK, so as to prevent GIDL from occurring in the drain select transistor and the source select transistor. In order to transmit the positive voltage Vp applied to the second global line 2GL to the unselected memory block Unsel_BLK, the second decoder 2DEC can output a second block select signal 2BLKST with a negative voltage Vn during certain periods of the programming operation.

[0075] In the unselected memory blocks Unsel_BLK, the first memory block BLK1 may be affected by the voltage applied to the first global line 1GL and the voltage of the second block selection signal 2BLKST, the second memory block BLK2 may be affected by the voltage applied to the second global line 2GL and the voltage of the first block selection signal 1BLKST, and the third memory block BLK3 may be affected by the voltage applied to the second global line 2GL and the voltage of the second block selection signal 2BLKST.

[0076] The time it takes for the voltage applied to the second global line 2GL to change from ground voltage VSS to a positive voltage Vp and the time it takes for the second block select signal 2BLKST to change from ground voltage VSS to a negative voltage Vn can be equal to each other. For example, when a pass voltage or programming voltage is applied to the word line, the pass voltage or programming voltage can change from ground voltage VSS to a positive voltage Vp or a negative voltage Vn.

[0077] The following describes in detail how to change the voltage applied to each line and the voltage of the block select signal during programming operations.

[0078] Figure 7 It is a diagram illustrating programming operations according to this disclosure. Figure 8A and Figure 8BThis is a diagram illustrating the operation of a selection transistor according to the present disclosure.

[0079] See Figure 6 and Figure 7 During the voltage application periods T1 to T2, a positive turn-on voltage Von can be applied to the global drain select line GDSL and the global source select line GSSL, which are included in the first global line 1GL, and a voltage Vpass can be applied to the selected global word line Sel_GWL and the unselected global word line Unsel_GWL. To transfer the operating voltage Vop applied to the first global line 1GL to the selected memory block Sel_BLK, the first block select signal 1BLKST can have a high voltage HV. The high voltage HV can be set to a voltage obtained by adding the programming voltage Vpgm to at least the threshold voltage of the switch. A ground voltage VSS can be applied to the global word line GWL, which is included in the second global line 2GL, and either the ground voltage VSS or the positive voltage Vp can be applied to the global drain select line GDSL and the global source select line GSSL. The second block select signal 2BLKST can have a ground voltage VSS.

[0080] During the programming voltage application periods T2 to T3, the programming voltage Vpgm can be applied to the selected global word line Sel_GWL, which is included in the first global line 1GL. Because the first block select signal 1BLKST has a high voltage HV, the programming voltage Vpgm applied to the selected global word line Sel_GWL can be transmitted to the selected word line connected to the selected memory block Sel_BLK.

[0081] See Figure 8A When the voltage on the drain select line DSL is increased from the ground voltage VSS to a low positive voltage L_Vp, the voltage difference between the gate and drain DR of the drain select transistor DST can be reduced. For example, if the voltage on the drain select line DSL is increased to a low positive voltage L_Vp when the programming disable voltage Vinh is applied to the bit line BL, the voltage difference between the drain DR and the gate can be reduced. Therefore, the drain DR region of the drain select transistor DST will not expand, and no channel will be formed in the channel layer CH. Therefore, the drain select transistor DST can be turned off.

[0082] See Figure 8BWhen the voltage on the source select line SSL is increased from ground voltage VSS to a low positive voltage L_Vp, the voltage difference between the gate and source SC of the source select transistor SST can be reduced. For example, if the voltage on the source select line SSL is increased to a low positive voltage L_Vp when the source voltage Vsl is applied to the source line SL, the voltage difference between the source SC and the gate can be reduced. Therefore, the source SC region of the source select transistor SST does not expand, and no channel is formed in the channel layer CH. Therefore, the source select transistor SST can be turned off.

[0083] As described above, the drain select transistor (DST) and source select transistor (DST) of the unselected memory block remain off, thereby preventing channel boosting in the string of the unselected memory block.

[0084] See Figure 6 and Figure 7 After applying a positive voltage Vp to the global drain select line GDSL and the global source select line GSSL for a first time tk1, a ground voltage VSS can be applied to the global drain select line GDSL and the global source select line GSSL again. After the second select signal 2BLKST maintains a negative voltage Vn for a second time tk2, the second select signal 2BLKST can be increased to the ground voltage VSS again.

[0085] Figure 9 It is a diagram illustrating the voltage of the selected line during a voltage change period according to this disclosure.

[0086] Figure 9 It is a simplified diagram. Figure 3 The diagram shown is a schematic diagram. Therefore, many lines and detailed circuits through the switch group are omitted, and the connection relationships between components are shown.

[0087] See Figure 9 ,for Figure 7 The first time tk1 or the second time tk2 shown can apply different voltages to the drain select line DSL and the source select line SSL connected to the selected memory block Sel_BLK or the unselected memory block Unsel_BLK.

[0088] The drain select line DSL and source select line SSL connected to the fourth memory block BLK4, which is the selected memory block Sel_BLK, may be affected by the voltage applied to the first global line 1GL and the voltage of the first block select signal 1BLKST. For example, an on-state voltage Von is applied to the global drain line and global source line included in the first global line 1GL, and the first block select signal 1BLKST has a high voltage HV. Therefore, the on-state voltage Von applied to the global drain line and global source line can be transmitted to the drain select line DSL and source select line SSL of the selected memory block Sel_BLK.

[0089] The drain select line DSL and source select line SSL of the third memory block BLK3, which is an unselected memory block Unsel_BLK, may be affected by the voltage applied to the second global line 2GL and the voltage of the second block select signal 2BLKST. For example, a positive voltage Vp is applied to the global drain line and global source line included in the second global line 2GL, and the second block select signal 2BLKST has a negative voltage Vn. Therefore, the drain select line DSL and source select line SSL of the third memory block BLK3 can be floated.

[0090] The drain select line DSL and source select line SSL of the second memory block BLK2, which is an unselected memory block Unsel_BLK, may be affected by the voltage applied to the second global line 2GL and the voltage of the first block select signal 1BLKST. For example, a positive voltage Vp is applied to the global drain line and global source line included in the second global line 2GL, and the first block select signal 1BLKST has a high voltage HV. Therefore, the positive voltage Vp applied to the global drain line and global source line can be transmitted to the drain line DSL and source line SSL of the second memory block BLK2.

[0091] The drain select line DSL and source select line SSL of the first memory block BLK1, which is an unselected memory block Unsel_BLK, may be affected by the voltage applied to the first global line 1GL and the voltage of the second block select signal 2BLKST. For example, an on-state voltage Von is applied to the global drain line and global source line included in the first global line 1GL, and the second block select signal 2BLKST has a negative voltage Vn. Therefore, the drain select line DSL and source select line SSL of the first memory block BLK1 can be floated.

[0092] As described above, during the programming operation of the selected memory block, the drain and source selection transistors in the unselected memory block remain off, preventing channel voltage boosting in the unselected memory block's string. Therefore, when performing subsequent operations in the unselected memory block after the programming operation of the selected memory block is complete, the time spent initializing the channel of the unselected memory block can be shortened. Furthermore, since there is no residual channel voltage, the reliability of performing subsequent operations in the unselected memory block is improved.

[0093] According to some embodiments of this disclosure, during programming operations on a selected memory block, channel boost in an unselected memory block can be suppressed, thereby improving the reliability of subsequent operations that can be performed in the unselected memory block.

[0094] While this disclosure has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0095] In the above embodiments, all steps may be selectively performed, and / or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0096] Furthermore, embodiments of the present disclosure have been illustrated and described in the accompanying drawings and specification. Although specific terminology has been used, it is only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many variations can be made within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

Claims

1. A memory device, comprising: A first memory block and a second memory block, each of the first memory block and the second memory block comprising a plurality of memory cells; A voltage generator configured to apply an operating voltage to a first global line, selectively apply a positive voltage to a global select line included in a second global line while the operating voltage is being applied, and apply a ground voltage to a second global line included in the second global line other than the global select line; as well as A row decoder is configured to turn on a first pass switch between a first global line and a first local line connected to the first memory block, and to turn off a second pass switch between a second global line and a second local line connected to the second memory block.

2. The memory device of claim 1, wherein the voltage generator comprises: A first operating voltage generator is configured to apply the operating voltage, the ground voltage, or the positive voltage to the first global line; as well as A second operating voltage generator is configured to apply the operating voltage, the ground voltage, or the positive voltage to the second global line.

3. The memory device of claim 2, wherein the second operating voltage generator is configured to: apply the ground voltage to the second global line when the first operating voltage generator applies the operating voltage to the first global line, and The second operating voltage generator is configured to apply the positive voltage to the global selection line included in the second global line during the period when the first operating voltage generator applies the programming voltage to the selected global word line in the first global line.

4. The memory device of claim 3, wherein the second operating voltage generator is configured to: apply the positive voltage to the global select line for a certain period of time while the programming voltage is applied to the selected global word line in the first global line, and then apply the ground voltage to the global select line.

5. The memory device of claim 1, wherein the operating voltage includes a programming voltage, a pass voltage, and a turn-on voltage.

6. The memory device of claim 1, wherein the row decoder further comprises: A first decoder, configured to output a first block selection signal for simultaneously controlling the first pass switch in response to a row address; as well as A second decoder is configured to output a second block selection signal in response to the row address for simultaneously controlling the second pass switch.

7. The memory device of claim 6, wherein the first line is connected between the first global line and the first local line via switches. The first global line consists of a global selection line and a global word line, and The first local line consists of a local selection line and a local word line.

8. The memory device of claim 7, wherein the local select line is connected to the gate of the select transistor of the first memory block, and The local word line is connected to the gate of the memory cell between the select transistors.

9. The memory device of claim 6, wherein the second line is connected between the second global line and the second local line via switches. The second global line consists of a global selection line and a global word line, and The second local line consists of a local selection line and a local word line.

10. The memory device of claim 9, wherein the local select line is connected to the gate of the select transistor of the second memory block, and The local word line is connected to the gate of the memory cell between the select transistors.

11. The memory device of claim 6, wherein the first decoder is configured to output a first block select signal as a high voltage to turn on the first pass switch.

12. The memory device of claim 11, wherein the high voltage is configured as a first voltage obtained by adding the threshold voltage of the first through switch to the programming voltage, or is configured as a second voltage higher than the first voltage obtained by adding the threshold voltage of the first through switch to the programming voltage.

13. The memory device of claim 6, wherein the second decoder is configured to output a second block selection signal as a negative voltage to turn off the second pass switch.

14. A memory device, comprising: A first memory block and a second memory block, each of the first memory block and the second memory block comprising a plurality of memory cells; A voltage generator configured to apply an operating voltage to a first global line, selectively apply a positive voltage to a global select line included in a second global line while the operating voltage is being applied, and apply a ground voltage to a second global line included in the second global line other than the global select line; as well as A row decoder is configured to apply a first block select signal with a high voltage to a first pass switch between a first global line and a first local line connected to the first memory block, and selectively apply a negative voltage to a second pass switch between a second global line and a second local line connected to the second memory block.

15. The memory device of claim 14, wherein the voltage generator is configured to: apply a ground voltage to the second global line while the operating voltage is applied to the first global line, and The voltage generator is configured to apply the positive voltage to the global selection line included in the second global line when the programming voltage is included in the operating voltage.

16. The memory device of claim 14, wherein the row decoder is configured to apply the negative voltage to the second pass switch while the voltage generator applies the positive voltage to the global select line included in the second global line.

17. A method of operating a memory device, the method comprising: A first pass switch is connected between the first global line and the first local line connected to the first memory block; Turn off the second pass switch between the second global line and the second local line connected to the second memory block; Apply a programming voltage to the selected global word line in the first global line; When the programming voltage is applied to the selected global word line, a positive voltage is applied to the global selection line included in the second global line; as well as When the programming voltage is applied to the selected global word line, a negative voltage is applied to the gate of the second pass switch.

18. The method of claim 17, wherein when the first pass switch is turned on, a first block selection signal having a high voltage is applied to the gate of the first pass switch.

19. The method of claim 18, wherein the high voltage is configured as a first voltage obtained by adding the threshold voltage of the first through switch to the programming voltage, or is configured as a second voltage higher than the first voltage obtained by adding the threshold voltage of the first through switch to the programming voltage.

20. The method of claim 17, wherein when the second pass switch is turned off, a second block selection signal having a ground voltage is applied to the gate of the second pass switch.

21. The method of claim 17, wherein while applying the programming voltage to the selected global word line in the first global line, the negative voltage is applied to the gate of the second through switch.

22. The method of claim 21, wherein while applying the negative voltage to the gate of the second pass switch, the application of the positive voltage to the global select line included in the second global line is performed.

23. The method of claim 17, further comprising: Before applying the positive voltage to the global selection line in the second global line, a ground voltage is applied to the second global line.

24. The method of claim 17, wherein the second pass switch is turned off between the global select line and the local select line connected to the select transistor of the second memory block, and The local selection line is included in the second local line.

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