FPGA-based high-performance LDPC optical communication error correction system

Abstract

The application discloses an FPGA-based high-performance LDPC optical communication error correction system, comprising a transmitting end, a space channel and a receiving end connected in sequence; a signal laser emits an optical signal to a Mach-Zehnder modulator; a coding control module encodes to-be-sent data by using a check matrix subjected to Gaussian elimination, and modulates code elements obtained through the Mach-Zehnder modulator to the optical signal; the optical signal is transmitted to the receiving end through the space channel; an optoelectronic detector converts the received optical signal into an electrical signal and sends the electrical signal to a decoding control module for decoding and error correction; and a host computer displays a system bit error rate in real time according to a decoding and error correction result of the decoding control module. The application solves the problem of transmission data errors caused by channel noise in optical communication, realizes high-throughput data transmission, and meets the requirements of most high-speed communication LDPC error correction systems.

Description

Technical Field

[0001] This invention belongs to the field of optical communication technology, specifically relating to a high-performance error correction system for LDPC optical communication based on FPGA. Background Technology

[0002] Optical communication, a communication technology that uses light to transmit signals, has become an indispensable part of modern communication systems. By utilizing optical transmission media such as optical fibers, optical communication achieves high-bandwidth, long-distance, and low-latency data transmission, and is widely used in fields such as the Internet, data center interconnection, long-distance communication, satellite communication, and mobile communication. The rapid development of optical communication has led to increasingly higher requirements for its reliability and performance. In optical communication, signal transmission is easily affected by nonlinear effects in optical fibers, optical attenuation, and noise, which can lead to an increase in the bit error rate during data transmission. To overcome these challenges, optical communication systems typically employ error correction coding techniques, among which LDPC codes are widely recognized as a highly efficient error correction code.

[0003] LDPC codes are linear error-correcting codes with a low bit error rate approaching the Shannon limit. They are widely used in communication systems due to their excellent error correction performance, especially in low signal-to-noise ratio environments. Key characteristics of LDPC codes include sparsity and a distributed parity-check structure. Sparse matrices offer significant advantages in data storage and processing. Compared to dense matrices, sparse matrices contain a large number of zero elements, thus saving storage space. The distribution of binary fields allows addition circuits to be replaced with NAND gates, effectively improving system performance. This makes them suitable for efficient hardware implementation.

[0004] An FPGA is a programmable hardware platform with high flexibility and parallel computing capabilities. It can be customized to meet the requirements of communication systems, enabling high-performance hardware acceleration of LDPC codecs. The parallelism and low latency of FPGAs make them an ideal implementation platform for LDPC codes in coherent communication systems.

[0005] Although LDPC is a powerful error-correcting code, its implementation still has some drawbacks. First, LDPC code decoding is relatively complex, requiring significant computational resources, which can lead to high power consumption and latency. Furthermore, achieving high speeds on FPGAs places high demands on the timing design of the encoder and decoder. Second, hardware implementation typically requires large amounts of memory, increasing cost. Additionally, the performance of LDPC codes is highly dependent on parameter configuration and the choice of decoding algorithm, requiring careful optimization. Finally, LDPC codes are very sensitive to the conditions of the communication channel and may not be suitable for certain noise models. Overcoming these drawbacks requires further research and engineering optimization to improve the practicality and performance of LDPC codes.

[0006] Patent publication number CN110071727B discloses an encoding method, decoding method, error correction method, and apparatus that can improve encoding efficiency. However, the matrix elimination method of this invention mainly processes RS codes, aiming to generate data within one cycle and reduce multiple iterative shifts, thereby improving decoding efficiency and system throughput. It does not reduce the FPGA area occupied by the matrix or optimize system resource usage. Patent publication number CN111917517A discloses a long-range maritime communication method that effectively addresses channel fading and improves encoding gain. It does not require additional infrastructure or specialized user transceiver equipment, thus reducing the cost of maritime communication. However, this invention uses most likelihood estimation, employing probabilistic statistical methods. This method requires an ADC during hardware implementation, increasing system cost.

[0007] Current FPGA-based LDPC error correction systems rarely consider the direct relationship between communication rate, error correction performance, and hardware implementation complexity. In practical applications, they still suffer from high complexity, low communication rate, and poor performance. There is a lack of a high-speed, high-performance, and easily configurable LPDC encoding and decoding error correction system. Summary of the Invention

[0008] Technical problem solved: This invention provides a high-performance error correction system for LDPC optical communication based on FPGA, which solves the problem of data transmission errors caused by channel noise in optical communication. It can achieve high throughput data transmission at high speeds of 2Gbps and above. At the same time, the parameterized design is more flexible and the system bit error rate performance can be observed in real time, which can meet the requirements of most high-speed communication LDPC error correction systems.

[0009] Technical solution:

[0010] A high-performance error correction system for LDPC optical communication based on FPGA, the high-performance error correction system for LDPC optical communication includes a transmitter, a spatial channel and a receiver connected in sequence;

[0011] The transmitting end includes a signal laser, an encoding control module, and a Mach-Zehnder modulator. The signal laser transmits an optical signal to the Mach-Zehnder modulator. The encoding control module uses a parity-check matrix that has undergone Gaussian elimination to encode the data to be transmitted. The encoded code is then modulated onto the optical signal by the Mach-Zehnder modulator. The optical signal is transmitted to the receiving end via a spatial channel.

[0012] The receiving end includes a photodetector, a decoding control module, and a host computer for real-time display of the bit error rate. The photodetector converts the received optical signal into an electrical signal and sends it to the decoding control module for decoding and error correction. The host computer displays the system bit error rate in real time based on the decoding and error correction results of the decoding control module.

[0013] Furthermore, the encoding control module includes a ROM memory, a first GTX module, a FIFO memory, an enable control module, a logic encoding module, a ROM array module, a MUX module, and a second GTX module;

[0014] The ROM memory is used to store data to be transmitted, and the ROM array module is used to store the parity check matrix after Gaussian elimination. The first GTX module reads data from the ROM memory, changes the clock domain of the read data through the FIFO memory, and sends it to the logic encoding module. The logic encoding module encodes the received data using the parity check matrix after Gaussian elimination while outputting the received data, and synchronously outputs the encoded code. The received data and the encoded code are sent to the second GTX module through the MUX module at the same time.

[0015] The enable control module is used to control the working cycle of the logic encoding module.

[0016] Furthermore, the logic encoding module encodes one frame of data in 16 cycles;

[0017] In the i-th cycle, the logic encoding module performs an XOR operation on the data output by the FIFO module and the parity matrix data read from the ROM array module, and simultaneously increments the address pointer in the ROM array module. In the (i+1)-th cycle, the XOR operation is performed again on the data output by the FIFO module and the parity matrix data read from the ROM array module, and the XOR result is XORed with the calculation result of the i-th cycle. After repeating this process for 16 cycles, the parity subscript p is calculated; i = 1, 2, ..., 15.

[0018] Furthermore, the processing of the data to be transmitted by the transmitting end includes the following steps:

[0019] Step A1: Store the (512, 256) parity check matrix after Gaussian elimination in a ROM array module consisting of 4 first ROM units in the form of (16*64);

[0020] Step A2: The input data is in frame format, using a 100MHz clock. Each frame contains 17 data points, each 16 bits. The first data point, 02bc, serves as the frame header, used to synchronize the input data. The input data is processed across clock domains via a FIFO module. The FIFO module's read clock is 200MHz. The FIFO module's processing logic is as follows: the write enable signal is continuously pulled high, and the read enable signal is pulled high for 16 clock cycles starting from the second clock cycle, then pulled low for the next 18 clock cycles. The first 16 data points output by the FIFO module are the original information, and the last 18 data points are 0.

[0021] Step A3: Input the data read from the FIFO module into the encoding control module. The encoding control module performs the operation logic through the state machine. In the first 16 clock cycles, it outputs the received data and calculates the checksum in real time. In each clock cycle, 16 bits are XORed with the data stored in the first ROM unit in parallel. At the same time, the address pointer of the first ROM unit is incremented by one. In the second clock cycle, the XOR operation is continued with the number stored in the first ROM unit and the data calculated in the first cycle. A total of 16 clock cycles are calculated.

[0022] Step A4: Output the original information in the first 16 cycles and the calculated checksum in the last 16 cycles through the multiplexer to complete the encoding. Connect the encoded data to the optoelectronic modulator through the GTX port to modulate the encoded information into the optical signal.

[0023] Furthermore, the decoding control module includes an input buffer module, N check sequence calculation modules, N error node calculation modules, N comparison modules, N flip modules, an iteration module, and an output buffer module; each set of check sequence calculation modules, error node calculation modules, comparison modules, and flip modules constitutes a channel, for a total of N channels, and the N channels perform decoding and error correction in parallel;

[0024] The input buffer module receives the encoded information and selects different channels for data input based on the count. Under the control of the iteration module, the encoded information is repeatedly processed M times through the verification sequence calculation module, the error node calculation module, the comparison module, and the flipping module to complete the decoding and error correction. The corrected encoded information is then processed through the output buffer model. M and N are both positive integers greater than or equal to 1.

[0025] Furthermore, the decoding control module's process for decoding and correcting encoded information includes the following steps:

[0026] Step B1: Store the parity check matrix after Gaussian elimination in 8 second ROM units in the form of (64*64), and transpose it to store it in another 8 third ROM units in the form of (64*64);

[0027] Step B2: Input the encoded information obtained by the photodetector through GTX, and store it every four cycles through the input buffer module. Convert the 16-bit data into 64-bit data and store all the encoded information for 32 cycles.

[0028] Step B3: Perform an XOR operation between the 64-bit data in the input buffer and the stored parity matrix in the parity sequence calculation module. Update the address of the second ROM unit in each cycle. Obtain the parity sequence through 8 cycles of operation.

[0029] Step B4: Perform an XOR operation and an addition operation on the calculated check sequence and the transpose of the check matrix in the error node calculation module. Update the address of the third ROM unit in each cycle. Obtain the error node information through 8 cycles of operation.

[0030] Step B5: Compare the 512-bit node information pairwise, and retain the node information with the highest error probability in each clock cycle. Obtain the index of the node with the highest error probability after 9 cycles.

[0031] Step B6: Flip the bits at the corresponding index in the stored 512-bit information using the index to complete one decoding and error correction operation;

[0032] Step B7: Re-input the encoded information after completing one error correction into the verification sequence calculation module, repeat steps B1 to B6, iterate M times, and complete all error corrections.

[0033] Furthermore, the host computer is equipped with a bit error rate observation module;

[0034] The bit error rate observation module uses a specific value point sent in a loop as the starting position. When the data reaches the starting position, the original information and the error-corrected code information are compared in real time, and the probability of transmission error is calculated and displayed in real time.

[0035] Beneficial effects:

[0036] First, the FPGA-based LDPC optical communication high-performance error correction system of the present invention can realize the rapid replacement of any parity check matrix through parameterized design, which facilitates testing the effect of different parity check matrices on LDPC encoding.

[0037] Secondly, the FPGA-based LDPC optical communication high-performance error correction system of the present invention can increase the system throughput and effectively improve the system's communication rate through pipeline and multi-channel design.

[0038] Third, the FPGA-based LDPC optical communication high-performance error correction system of the present invention obtains the verification matrix through Gaussian elimination, which can effectively reduce the number of calculations required for the verification matrix and save related FPGA internal resources. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the encoding control module structure according to an embodiment of the present invention;

[0040] Figure 2 This is a diagram illustrating the encoding control logic of an embodiment of the present invention.

[0041] Figure 3 This is a schematic diagram of the FPGA encoding result according to an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the decoding control module structure according to an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of the structure of each module of the LDPC decoder according to an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of the FPGA decoding result according to an embodiment of the present invention;

[0045] Figure 7 This is a schematic diagram of the structure of a high-performance error correction system for LDPC optical communication based on FPGA, according to an embodiment of the present invention. Detailed Implementation

[0046] The following embodiments are provided to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0047] Figure 7 This is a schematic diagram of the FPGA-based LDPC optical communication high-performance error correction system according to an embodiment of the present invention. See also... Figure 1 The LDPC optical communication high-performance error correction system includes a transmitter, a space channel, and a receiver connected in sequence.

[0048] The transmitter includes a signal laser, an encoding control module (encoding FPGA), and a Mach-Zehnder modulator. The signal laser transmits an optical signal to the Mach-Zehnder modulator. The encoding control module uses a parity-check matrix that has undergone Gaussian elimination to encode the data to be transmitted. The encoded code is then modulated onto the optical signal by the Mach-Zehnder modulator. The optical signal is then transmitted to the receiver via a spatial channel.

[0049] The receiving end includes a photodetector, a decoding control module, and a host computer for real-time display of the bit error rate. The photodetector converts the received optical signal into an electrical signal and sends it to the decoding control module for decoding and error correction. The host computer displays the system bit error rate in real time based on the decoding and error correction results of the decoding control module.

[0050] The data processing process at the transmitting end is as follows Figure 1 As shown, the parity check matrix after Gaussian elimination is first stored in four first ROM units in the form of (16*64). Data input from the outside is received through GTX. Data is received cyclically. Each frame of data contains 17 data, each data is 16 bits in size, the frame header is 02bc, and the following 16 data are fixed data that are repeatedly sent, totaling 256 bits, denoted as symbol information s.

[0051] Since the length of the encoded checksum is 256 bits, which is equivalent to doubling the amount of information, if the encoded symbols are to be generated in the same amount of time, the clock rate needs to be doubled. A FIFO module is used for data processing. First, three frames of data are buffered. In order to prevent the FIFO module from being exhausted, the write enable is kept high, and the read enable changes its 0 and 1 states every 17 cycles. In this way, the speed of reading data is the same as the speed of writing data, which will not cause the FIFO module to overflow. The data output by the FIFO module is the symbol information s in the first 16 cycles and 0 in the last 18 cycles. The data in the first 16 cycles is directly output to GTX through a multiplexer, and at the same time, the data is input to the logic encoding module for LDPC encoding.

[0052] According to the formula The checksum p is a modulo-2 operation between the symbol information and the check matrix. The encoding module encodes one frame of data in 16 cycles. In the first cycle, the data output from the FIFO module is XORed with the data read from the first ROM unit, and the address pointer in the first ROM unit is incremented by one. The above steps are repeated in the second cycle, and the result is XORed with the result of the first cycle. Figure 2 As shown, repeating the above steps for 16 cycles will calculate the checksum p. Outputting the calculated checksum to GTX completes the LDPC encoding. The encoded result is shown in the diagram. Figure 3 As shown.

[0053] The encoded data is connected to a Mach-Zehnder modulator via the SMA port of the encoding FPGA, and the Mach-Zehnder modulator modulates the encoded data into an optical signal.

[0054] The receiving end includes a photodetector, a decoding control module (decoding FPGA), and an observation module that displays the bit error rate in real time;

[0055] The photodetector converts the optical signal passing through the channel into an electrical signal, which is then input to the decoding FPGA through the SMA port. Due to the presence of noise in the channel and the threshold voltage for judgment by the decoding FPGA, errors may occur in the information read. The decoding FPGA is used to correct these errors.

[0056] The structural design of the decoding FPGA is as follows Figure 4 As shown, it includes an input buffer module, a check sequence calculation module, an error node calculation module, a comparison module, a reversal module, an iteration module, and an output buffer module. The interface diagrams of each module are shown below. Figure 5 As shown.

[0057] First, preprocessing is performed. The (256, 512) parity-check matrix after Gaussian elimination is stored in eight second ROM units in (64*64) format. This matrix is ​​then transposed and stored in another eight third ROM units in (64*64) format. The encoded information obtained from the photodetector is input via GTX and converted from single-bit data to 16-bit data using serial-to-parallel conversion. Then, a buffer module stores the 16-bit data every four cycles, converting it back to 64-bit data and storing all the encoded information for 32 cycles. A multi-channel decoding method is used with a multiplexer. A counter is used, and the input buffer is output to different channels each time it is ready. In this embodiment, there are a total of five channels, and each channel performs decoding operations independently, with the decoding operations for a single channel being serial.

[0058] The logic for a specific decoding channel is as follows;

[0059] The sequence s′=Hc is verified according to the formula. T Therefore, the 64-bit data output from the input buffer module is XORed with the stored parity matrix in the parity sequence calculation module. The ROM address is updated every cycle, and the parity sequence is obtained after 8 cycles. According to the formula node information f(n) = s′*H, in order to obtain node information, the calculated parity sequence is XORed with the transpose of the above parity matrix and added in the error node calculation module. Similarly, the ROM address is updated every cycle, and the error node information is obtained after 8 cycles. After obtaining the node information, it is input to the comparison module. The 512-bit node information is compared pairwise, and the node information with the highest error probability is retained every clock cycle. The index of the information node with the highest error probability is obtained after 9 cycles. After obtaining the position of the information code with the highest error probability, the corresponding bit in the stored 512-bit information is flipped according to the index, completing one decoding and error correction. The encoded information after one error correction is re-inputted into the parity sequence calculation module, and steps one to six are repeated. This process is repeated 10 times to complete all error correction. The decoding result is as follows. Figure 6 As shown.

[0060] To improve the system throughput, a multi-channel pipeline design with frequency multiplication is adopted. The 100MHz clock of the buffer input module is used for data synchronization processing through a frequency-doubled FIFO. Subsequent node processing uses a 200MHz clock. Data is simultaneously input into different channels through a multiplexer, and iterative decoding operations are performed simultaneously on multiple channels. Finally, the data is output in sequence through a multiplexer and output buffer.

[0061] To improve the system's configurability and flexibility, the interfaces of the relevant modules are designed in a modular fashion, which allows for quick adjustment of the relevant interfaces according to the size of the parity check matrix, enabling the encoding and decoding of different parity check matrices.

[0062] Building upon this foundation, to facilitate real-time bit error rate (BER) monitoring of the system, this embodiment also includes a BER monitoring module. This module instructs the encoding FPGA to cyclically send the same data and continuously monitor the BER-corrected data. By observing the BER-corrected data and the original data, the total number of errors per bit and the total number of data sent are calculated to determine the system's BER. The main principle of the BER monitoring module is as follows: the BER-corrected information sequence is input into the module, and the cyclically sent data is written into the detection ROM. The starting position of the relevant data is located using the frame header 02bc of the received data. When the data reaches the starting position, the data in the detection ROM is read. The BER-corrected data is compared with the data read from the ROM for each frame to calculate the probability of errors, thereby allowing real-time monitoring of the BER performance.

[0063] In summary, the FPGA-based high-performance error correction system for LDPC optical communication of this invention can achieve high-speed real-time LDPC encoding. By multiplying the frequency and using a multi-channel design, the throughput of LDPC encoding is greatly increased. By using Gaussian elimination preprocessing, the resource consumption in the FPGA is greatly reduced. The real-time encoding and decoding efficiency is as high as 2Gbps or more. Furthermore, the structure adopts a parameterized design, which has the advantage of flexible configuration. By storing the parity check matrix in ROM, different parity check matrices can be implemented by changing the data in the ROM.

[0064] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. An FPGA-based LDPC optical communication error correction system, characterized in that, The LDPC optical communication error correction system includes a transmitter, a spatial channel, and a receiver connected in sequence. The transmitting end includes a signal laser, an encoding control module, and a Mach-Zehnder modulator. The signal laser transmits an optical signal to the Mach-Zehnder modulator. The encoding control module uses a parity-check matrix that has undergone Gaussian elimination to encode the data to be transmitted. The encoded code is then modulated onto the optical signal by the Mach-Zehnder modulator. The optical signal is transmitted to the receiving end via a spatial channel. The encoding control module includes a ROM memory, a first GTX module, a FIFO memory, an enable control module, a logic encoding module, a ROM array module, a MUX module, and a second GTX module. The ROM memory is used to store data to be sent, and the ROM array module is used to store the parity check matrix after Gaussian elimination; the first GTX module reads data from the ROM memory, and after changing the clock domain of the read data through the FIFO memory, it sends the data to the logic encoding module. The logic encoding module encodes the received data using a check matrix that has undergone Gaussian elimination while outputting the received data, and synchronously outputs the encoded code. The received data and the encoded code are then sent to the second GTX module via the MUX module. The enable control module is used to control the working cycle of the logic encoding module; The receiving end includes a photodetector, a decoding control module, and a host computer for real-time display of the bit error rate; the photodetector converts the received optical signal into an electrical signal and sends it to the decoding control module for decoding and error correction; the host computer displays the system bit error rate in real time based on the decoding and error correction results of the decoding control module. The decoding control module includes: two ROM array modules, an input buffer module, N check sequence calculation modules, N error node calculation modules, N comparison modules, N flip modules, an iteration module, and an output buffer module; each set of check sequence calculation modules, error node calculation modules, comparison modules, and flip modules forms a channel, for a total of N channels, and the N channels perform decoding and error correction in parallel; The ROM array module stores the parity check matrix after Gaussian elimination and the transpose of the parity check matrix; The input buffer module receives the encoded information and selects different channels for data input based on the count. Under the control of the iteration module, the encoded information is repeatedly processed M times through the verification sequence calculation module, the error node calculation module, the comparison module, and the flipping module to complete the decoding and error correction. The corrected encoded information is then processed through the output buffer model. M and N are both positive integers greater than or equal to 1.

2. The FPGA-based LDPC optical communication error correction system according to claim 1, characterized in that, The logic encoding module encodes one frame of data in 16 cycles. In the i-th cycle, the logic encoding module performs an XOR operation on the data output by the FIFO module and the parity matrix data read from the ROM array module, while simultaneously incrementing the address pointer in the ROM array module. In the (i+1)-th cycle, the XOR operation is performed again on the data output by the FIFO module and the parity matrix data read from the ROM array module, and the XOR result is XORed with the calculation result of the i-th cycle. After repeating this process for 16 cycles, the parity is calculated. i = 1, 2, ..., 15.

3. The FPGA-based LDPC optical communication error correction system according to claim 1, characterized in that, The data processing process at the transmitting end includes the following steps: Step A1: Store the (512,256) parity check matrix after Gaussian elimination in a ROM array module consisting of 4 first ROM units in a 16*64 format; Step A2: The input data is in frame format, using a 100MHz clock. Each frame contains 17 data points, each 16 bits. The first data point, 02bc, serves as the frame header, used to synchronize the input data. The input data is processed across clock domains via a FIFO module. The FIFO module's read clock is 200MHz. The FIFO module's processing logic is as follows: the write enable signal is continuously pulled high, and the read enable signal is pulled high for 16 clock cycles starting from the second clock cycle, then pulled low for the next 18 clock cycles. The first 16 data points output by the FIFO module are the original information, and the last 18 data points are 0. Step A3: Input the data read from the FIFO module into the encoding control module. The encoding control module performs the operation logic through the state machine. In the first 16 clock cycles, it outputs the received data and calculates the checksum in real time. In each clock cycle, 16 bits are XORed with the data stored in the first ROM unit in parallel. At the same time, the address pointer of the first ROM unit is incremented by one. In the second clock cycle, the XOR operation is continued with the number stored in the first ROM unit and the data calculated in the first cycle. A total of 16 clock cycles are calculated. Step A4: Output the original information in the first 16 cycles and the calculated checksum in the last 16 cycles through the multiplexer to complete the encoding. Connect the encoded data to the optoelectronic modulator through the GTX port to modulate the encoded information into the optical signal.

4. The FPGA-based LDPC optical communication error correction system according to claim 1, characterized in that, The decoding control module performs decoding and error correction on the encoded information, including the following steps: Step B1: Store the parity check matrix after Gaussian elimination in 8 second ROM units in 64*64 format, and transpose it to store it in another 8 third ROM units in 64*64 format. Step B2: Input the encoded information obtained by the photodetector through GTX, and store it every four cycles through the input buffer module. Convert the 16-bit data into 64-bit data and store all the encoded information for 32 cycles. Step B3: Perform an XOR operation between the 64-bit data in the input buffer and the stored parity matrix in the parity sequence calculation module. Update the address of the second ROM unit in each cycle. Obtain the parity sequence through 8 cycles of operation. Step B4: Perform an XOR operation and an addition operation on the calculated check sequence and the transpose of the check matrix in the error node calculation module. Update the address of the third ROM unit in each cycle. Obtain the error node information through 8 cycles of operation. Step B5: Compare the 512-bit node information pairwise, and retain the node information with the highest error probability in each clock cycle. Obtain the index of the node with the highest error probability after 9 cycles. Step B6: Flip the bits at the corresponding index in the stored 512-bit information using the index to complete one decoding and error correction operation; Step B7: Re-input the encoded information after completing one error correction into the verification sequence calculation module, repeat steps B1 to B6, iterate M times, and complete all error corrections.

5. The FPGA-based LDPC optical communication error correction system according to claim 1, characterized in that, The host computer is equipped with a bit error rate monitoring module; The bit error rate observation module uses a specific value point sent in a loop as the starting position. When the data reaches the starting position, the original information and the error-corrected code information are compared in real time, and the probability of transmission error is calculated and displayed in real time.

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