Pixel circuit, display panel, driving method and display device

Abstract

The present disclosure provides a pixel circuit, a display panel, a driving method and a display device. The pixel circuit comprises a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a write control circuit and a first control circuit; a first end of the first energy storage circuit is electrically connected with a control end of the driving circuit, and a second end of the first energy storage circuit is electrically connected with a first end of the driving circuit; a first end of the second energy storage circuit is electrically connected with the control end of the driving circuit; the write control circuit controls the communication or disconnection between a write end and a second end of the second energy storage circuit under the control of a first write control signal; the first control circuit controls the communication or disconnection between a power supply voltage end and the first end of the driving circuit under the control of a first control signal; and the driving circuit generates a driving current for driving the light emitting element under the control of the potential of the control end thereof. The present disclosure can provide a current type pixel circuit applied to an organic light emitting diode display and capable of threshold voltage self-compensation.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to PCT International Application No. PCT / CN2022 / 098080, filed on June 10, 2022, and PCT International Application No. PCT / CN2022 / 096196, filed on May 31, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a pixel circuit, display panel, driving method, and display device. Background Technology

[0004] OLED (Organic Light Emitting Diode) displays are currently a hot topic in flat panel display research, and pixel circuit design is a core technology of OLED displays. However, existing technologies do not provide a current-driven pixel circuit capable of threshold voltage self-compensation for OLED displays. Summary of the Invention

[0005] In one aspect, embodiments of this disclosure provide a pixel circuit, including a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a write control circuit, and a first control circuit;

[0006] The first terminal of the first energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the first energy storage circuit is electrically connected to the first terminal of the drive circuit; the first energy storage circuit is used to store electrical energy.

[0007] The first terminal of the second energy storage circuit is electrically connected to the control terminal of the drive circuit; the second energy storage circuit is used to store electrical energy.

[0008] The write control circuit is electrically connected to the first write control terminal, the write terminal and the second terminal of the second energy storage circuit, respectively, and is used to control the connection or disconnection between the write terminal and the second terminal of the second energy storage circuit under the control of the first write control signal provided by the first write control terminal.

[0009] The first control circuit is electrically connected to the first control terminal, the power supply voltage terminal, and the first terminal of the drive circuit, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first terminal of the drive circuit under the control of the first control signal provided by the first control terminal.

[0010] The second terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential at its control terminal.

[0011] Optionally, the first control circuit is used to control the connection between the power supply voltage terminal and the first terminal of the drive circuit under the control of the first control signal during two discontinuous phases within a display cycle.

[0012] Optionally, the display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially.

[0013] The first control circuit is used to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first control signal during the initialization phase, the data preparation phase, the data writing phase, and the light emission phase; and to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first control signal during the self-discharge phase.

[0014] Optionally, the write control circuit is used to disconnect the write terminal from the second terminal of the second energy storage circuit under the control of the first write control signal during the data preparation stage and the light emission stage, and to connect the write terminal to the second terminal of the second energy storage circuit under the control of the first write control signal during the initialization stage, the self-discharge stage and the data writing stage.

[0015] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a reference voltage writing circuit;

[0016] The reference voltage writing circuit is electrically connected to the second writing control terminal, the reference voltage terminal, and the control terminal of the driving circuit, respectively, and is used to write the reference voltage provided by the reference voltage terminal to the control terminal of the driving circuit under the control of the second writing control signal provided by the second writing control terminal.

[0017] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a second control circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0018] The second control circuit is electrically connected to the second control terminal, the reset voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to control the reset voltage provided by the reset voltage terminal to be written into the first electrode of the light-emitting element under the control of the second control signal provided by the second control terminal.

[0019] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a resistor circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element through the resistor circuit, and the second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0020] Optionally, the first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor; and the write control circuit includes a first transistor.

[0021] The first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit.

[0022] The first terminal of the second capacitor is electrically connected to the control terminal of the driving circuit;

[0023] The control electrode of the first transistor is electrically connected to the first write control terminal, the first electrode of the first transistor is electrically connected to the write terminal, the second electrode of the first transistor is electrically connected to the second terminal of the second capacitor, and the back gate of the first transistor is electrically connected to the second voltage terminal.

[0024] Optionally, the first control circuit includes a second transistor; the driving circuit includes a driving transistor.

[0025] The control electrode of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first terminal of the driving circuit; the back gate of the second transistor is electrically connected to the second voltage terminal.

[0026] The control terminal of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, and the second terminal of the driving transistor is the second terminal of the driving circuit; the back gate of the driving transistor is electrically connected to the second voltage terminal.

[0027] Optionally, the reference voltage writing circuit includes a third transistor;

[0028] The control electrode of the third transistor is electrically connected to the second write control terminal, the first electrode of the third transistor is electrically connected to the reference voltage terminal, the second electrode of the third transistor is electrically connected to the control terminal of the driving circuit, and the back gate of the third transistor is electrically connected to the second voltage terminal.

[0029] Optionally, the second control circuit includes a fourth transistor;

[0030] The control electrode of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is electrically connected to the reset voltage terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element, and the back gate of the fourth transistor is electrically connected to the third voltage terminal.

[0031] Optionally, the fourth transistor is an n-type transistor, and the third voltage terminal is the reset voltage terminal; or,

[0032] The fourth transistor is a p-type transistor, and the third voltage terminal is the second voltage terminal.

[0033] Optionally, the fourth transistor is an n-type transistor; a deep n-type junction is disposed between the back gate of the fourth transistor and the P-type substrate to isolate the back gate of the fourth transistor from the P-type substrate; both the back gate of the fourth transistor and the first terminal of the fourth transistor are electrically connected to the reset voltage terminal.

[0034] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes n-hydrazine and p-hydrazine;

[0035] The doping concentration of the n-hydrazine is greater than that of the deep n-hydrazine;

[0036] The ratio of the thickness of the n-hydrazine to the thickness of the deep n-hydrazine is greater than or equal to 0.4 and less than or equal to 0.6;

[0037] The ratio of the thickness of the p-hydrazine to the thickness of the deep n-hydrazine is greater than or equal to 0.4 and less than or equal to 0.6.

[0038] In a second aspect, embodiments of this disclosure provide a display panel including multiple rows and columns of the aforementioned pixel circuitry.

[0039] In a third aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, the driving method comprising:

[0040] Under the control of the first write control signal, the write control circuit controls the connection or disconnection between the write terminal and the second terminal of the second energy storage circuit.

[0041] Under the control of the first control signal, the first control circuit controls the connection or disconnection between the power supply voltage terminal and the first terminal of the drive circuit.

[0042] The driving circuit generates a driving current to drive the light-emitting element under the control of the potential at its control terminal.

[0043] Optionally, the driving method includes:

[0044] Within a display cycle, in two discontinuous phases, the first control circuit, under the control of the first control signal, controls the connection between the power supply voltage terminal and the first terminal of the drive circuit.

[0045] Optionally, the display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially; the driving method includes:

[0046] During the initialization phase, the data preparation phase, the data writing phase, and the light emission phase, the first control circuit, under the control of the first control signal, controls the connection between the power supply voltage terminal and the first terminal of the driving circuit.

[0047] During the self-discharge phase, the first control circuit, under the control of the first control signal, controls the disconnection between the power supply voltage terminal and the first terminal of the drive circuit.

[0048] Optionally, the display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially; the driving method includes:

[0049] During the initialization phase, the data preparation phase, and the light emission phase, the write control circuit, under the control of the first write control signal, controls the write terminal to disconnect from the second terminal of the second energy storage circuit.

[0050] During the self-discharge phase and the data writing phase, the write control circuit, under the control of the first write control signal, controls the connection between the write terminal and the second terminal of the second energy storage circuit.

[0051] In a fourth aspect, embodiments of this disclosure provide a display device including the display panel described above.

[0052] Optionally, the display panel includes a first silicon substrate, and pixel circuits and gate driving circuits disposed on the first silicon substrate;

[0053] The display device further includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

[0054] Optionally, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate;

[0055] The minimum width of the signal lines included in the display panel is greater than the width of the signal lines included in the display driver chip. Attached Figure Description

[0056] Figure 1 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0057] Figure 2 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0058] Figure 3 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] Figure 4This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] Figure 5 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] Figure 6 This is a public announcement Figure 5 The timing diagram of at least one embodiment of the pixel circuit shown;

[0062] Figure 7 This is a schematic diagram of the structure of an NMOS transistor (N-type metal-oxide-semiconductor transistor) and a PMOS transistor (P-type metal-oxide-semiconductor transistor) in at least one embodiment of this disclosure;

[0063] Figure 8 These are schematic diagrams of the structures of NMOS transistors and PMOS transistors in related technologies.

[0064] Figure 9 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] Figure 10 This is a structural diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0066] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0067] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first electrode and the other terminal as the second electrode.

[0068] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0069] The pixel circuit described in this embodiment includes a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a write control circuit, and a first control circuit;

[0070] The first terminal of the first energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the first energy storage circuit is electrically connected to the first terminal of the drive circuit; the first energy storage circuit is used to store electrical energy.

[0071] The first terminal of the second energy storage circuit is electrically connected to the control terminal of the drive circuit; the second energy storage circuit is used to store electrical energy.

[0072] The write control circuit is electrically connected to the first write control terminal, the write terminal and the second terminal of the second energy storage circuit, respectively, and is used to control the connection or disconnection between the write terminal and the second terminal of the second energy storage circuit under the control of the first write control signal provided by the first write control terminal.

[0073] The first control circuit is electrically connected to the first control terminal, the power supply voltage terminal, and the first terminal of the drive circuit, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first terminal of the drive circuit under the control of the first control signal provided by the first control terminal.

[0074] The second terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential at its control terminal.

[0075] When the pixel circuit described in the embodiments of this disclosure is in operation...

[0076] The write control circuit, under the control of the first write control signal, controls the voltage signal provided by the write terminal to be written to the second terminal of the second energy storage circuit; the first control circuit, under the control of the first control signal, controls the connection or disconnection between the power supply voltage terminal and the first terminal of the drive circuit, so as to control the self-discharge threshold compensation process of the drive transistor included in the drive circuit; the first energy storage circuit and the second energy storage circuit can control the potential of the control terminal of the drive circuit by voltage division; the drive circuit generates a drive current for driving the light-emitting element under the control of the potential of its control terminal.

[0077] When the pixel circuit described in this embodiment is in operation, it can control the driving current of the driving circuit to drive the light-emitting element to emit light to be independent of the threshold voltage of the driving transistor included in the driving circuit by controlling and adjusting the capacitance value of the first capacitor included in the first energy storage circuit and the capacitance value of the second capacitor included in the second energy storage circuit.

[0078] This disclosure provides a simple current-type pixel circuit capable of threshold voltage self-compensation for use in OLED (organic light-emitting diode) displays.

[0079] In at least one embodiment of this disclosure, the first control circuit can be used to control the connection between the power supply voltage terminal and the first terminal of the drive circuit under the control of the first control signal during two discontinuous phases in a display cycle.

[0080] When the pixel circuit described in this embodiment is working, the display cycle of the pixel circuit may include an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially.

[0081] The first control circuit is used to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first control signal during the initialization phase, the data preparation phase, the data writing phase, and the light emission phase; and to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first control signal during the self-discharge phase.

[0082] In at least one embodiment of this disclosure, the two discontinuous stages may be the initialization stage and the self-discharge stage, but are not limited thereto.

[0083] When the pixel circuit described in this embodiment is working, the display cycle of the pixel circuit may include an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially.

[0084] The write control circuit is used to disconnect the write terminal from the second terminal of the second energy storage circuit under the control of the first write control signal during the data preparation stage and the light emission stage, and to connect the write terminal to the second terminal of the second energy storage circuit under the control of the first write control signal during the initialization stage, the self-discharge stage and the data writing stage.

[0085] like Figure 1 As shown, the pixel circuit described in at least one embodiment of this disclosure includes a light-emitting element E0, a first control circuit 10, a driving circuit 11, a first energy storage circuit 12, a second energy storage circuit 13, and a write control circuit 14.

[0086] The first control circuit 10 is electrically connected to the first control terminal DS, the power supply voltage terminal Vd, and the first terminal of the drive circuit 11, respectively, and is used to control the connection or disconnection between the power supply voltage terminal Vd and the first terminal of the drive circuit 11 under the control of the first control signal provided by the first control terminal DS; the power supply voltage terminal Vd is used to provide power supply voltage;

[0087] The first terminal of the first energy storage circuit 12 is electrically connected to the control terminal of the drive circuit 11, and the second terminal of the first energy storage circuit 12 is electrically connected to the first terminal of the drive circuit 11; the first energy storage circuit 12 is used to store electrical energy.

[0088] The first terminal of the second energy storage circuit 13 is electrically connected to the control terminal of the drive circuit 11;

[0089] The write control circuit 14 is electrically connected to the first write control terminal WS1, the write terminal DW, and the second terminal of the second energy storage circuit 13, respectively, and is used to control the connection or disconnection between the write terminal DW and the second terminal of the second energy storage circuit 13 under the control of the first write control signal provided by the first write control terminal WS1.

[0090] The second terminal of the driving circuit 11 is electrically connected to the light-emitting element E0. The driving circuit 11 is used to generate a driving current to drive the light-emitting element E0 under the control of the potential at its control terminal.

[0091] This disclosure is as follows Figure 1 In at least one embodiment of the pixel circuit shown, during operation, the write control circuit 14 transmits the voltage signal provided by the write terminal DW under the control of the first write control signal; the first energy storage circuit 12 is used to store the data voltage and control the gate-source voltage of the driving transistor included in the drive circuit 11; the first control circuit 10 is capable of controlling the self-discharge threshold compensation process of the driving transistor included in the drive circuit 11.

[0092] This disclosure is as follows Figure 1 In at least one embodiment of the pixel circuit shown, when in operation, the data voltage is written by voltage division through the first energy storage circuit 12 and the second energy storage circuit 13, which expands the dynamic range of the data voltage and is beneficial to the design of the DAC (digital-to-analog converter) in the source driver and the uniformity of the data line output.

[0093] This disclosure is as follows Figure 1 In at least one embodiment of the pixel circuit shown, the display cycle includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially.

[0094] During the initialization phase, the data preparation phase, the data writing phase, and the light emission phase, the first control circuit 10, under the control of the first control signal, controls the connection between the power supply voltage terminal Vd and the first terminal of the driving circuit 11.

[0095] During the self-discharge phase, the first control circuit 10, under the control of the first control signal, controls the power supply voltage terminal Vd to disconnect from the first terminal of the drive circuit 11.

[0096] During the initialization phase, the data preparation phase, and the light emission phase, the write control circuit 14, under the control of the first write control signal, controls the write terminal DW to disconnect from the second terminal of the second energy storage circuit 13.

[0097] During the self-discharge phase and the data writing phase, the write control circuit 10, under the control of the first write control signal, controls the connection between the write terminal DW and the second terminal of the second energy storage circuit 13.

[0098] The pixel circuit described in at least one embodiment of this disclosure may further include a reference voltage writing circuit;

[0099] The reference voltage writing circuit is electrically connected to the second writing control terminal, the reference voltage terminal, and the control terminal of the driving circuit, respectively, and is used to write the reference voltage provided by the reference voltage terminal to the control terminal of the driving circuit under the control of the second writing control signal provided by the second writing control terminal.

[0100] In a specific implementation, the pixel circuit may further include a reference voltage writing circuit, which, under the control of a second writing control signal, writes the reference voltage to the control terminal of the driving circuit to control the on / off state of the driving transistors included in the driving circuit.

[0101] In at least one embodiment of this disclosure, the pixel circuit further includes a second control circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the first voltage terminal;

[0102] The second control circuit is electrically connected to the second control terminal, the reset voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to control the reset voltage provided by the reset voltage terminal to be written into the first electrode of the light-emitting element under the control of the second control signal provided by the second control terminal.

[0103] In a specific implementation, the second control circuit is used to write the reset voltage into the first electrode of the light-emitting element during the non-light-emitting stage under the control of the second control signal, so that the difference between the potential of the first electrode of the light-emitting element and the potential of the second electrode of the light-emitting element is less than the turn-on voltage of the light-emitting element, so as to control the light-emitting element not to emit light.

[0104] Optionally, the light-emitting element may be an organic light-emitting diode (OLED), with the first electrode of the light-emitting element being the anode of the OLED and the second electrode being the cathode of the OLED, but this is not a limitation.

[0105] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of this disclosure may further include a reference voltage writing circuit 16;

[0106] The reference voltage writing circuit 16 is electrically connected to the second writing control terminal WS2, the reference voltage terminal R2, and the control terminal of the driving circuit 11, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal R2 to the control terminal of the driving circuit 11 under the control of the second writing control signal provided by the second writing control terminal WS2.

[0107] This disclosure is as follows Figure 2 In at least one embodiment of the pixel circuit, the display cycle includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially.

[0108] During the initialization phase and the self-discharge phase, the reference voltage writing circuit 16, under the control of the second writing control signal, writes the reference voltage Vref provided by the reference voltage terminal R2 into the control terminal of the driving circuit 11.

[0109] During the data preparation stage, the data writing stage, and the light emission stage, the reference voltage writing circuit 16, under the control of the second writing control signal, controls the reference voltage terminal R2 to disconnect from the control terminal of the driving circuit 11.

[0110] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of this disclosure may further include a second control circuit 20;

[0111] The second terminal of the driving circuit 11 is electrically connected to the first electrode of the light-emitting element E0, and the second electrode of the light-emitting element E0 is electrically connected to the first voltage terminal V1.

[0112] The second control circuit 20 is electrically connected to the second control terminal AZ, the reset voltage terminal Vf, and the first electrode of the light-emitting element E0, respectively, and is used to control the reset voltage provided by the reset voltage terminal Vf to be written into the first electrode of the light-emitting element E0 under the control of the second control signal provided by the second control terminal AZ.

[0113] This disclosure is as follows Figure 3In at least one embodiment of the pixel circuit shown, when in operation, the second control circuit 20 is used to write the reset voltage provided by the reset voltage terminal Vf into the first electrode of the light-emitting element E0 under the control of the second control signal during the non-light-emitting stage, so that the difference between the potential of the first electrode of the light-emitting element E0 and the potential of the second electrode of the light-emitting element E0 is less than the turn-on voltage of the light-emitting element E0, so as to control the light-emitting element E0 not to emit light.

[0114] In this disclosure Figure 3 In at least one embodiment of the pixel circuit shown, the first voltage terminal V1 may be connected to the common electrode voltage Vcom, but is not limited thereto.

[0115] In at least one embodiment of this disclosure, Vcom can be greater than or equal to -12V and less than or equal to -9V, but is not limited thereto.

[0116] Optionally, the pixel circuit described in at least one embodiment of this disclosure may further include a resistor circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element through the resistor circuit to prevent a short circuit between the first electrode and the second electrode of the light-emitting element.

[0117] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0118] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure may further include a resistor circuit 40; the second terminal of the driving circuit 11 is electrically connected to the first electrode of the light-emitting element E0 through the resistor circuit 40.

[0119] In at least one embodiment of this disclosure, the resistor circuit may be made of the same body material as the gate of the driving transistor included in the driving circuit. For example, the body material may be polycrystalline silicon, and the conductivity of the resistor circuit may be able to withstand the conductivity of the gate of the driving transistor; however, this is not a limitation.

[0120] In at least one embodiment of this disclosure, the resistor circuit 40 may include a first resistor, the first end of which is electrically connected to the second end of the driving circuit 11, and the second end of which may be electrically connected to the first electrode of the light-emitting element E0, but is not limited thereto.

[0121] Optionally, the first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor; and the write control circuit includes a first transistor.

[0122] The first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit.

[0123] The first terminal of the second capacitor is electrically connected to the control terminal of the driving circuit;

[0124] The control electrode of the first transistor is electrically connected to the first write control terminal, the first electrode of the first transistor is electrically connected to the write terminal, the second electrode of the first transistor is electrically connected to the second terminal of the second capacitor, and the back gate of the first transistor is electrically connected to the second voltage terminal.

[0125] In at least one embodiment of this disclosure, the capacitance value of the second capacitor may be smaller than the capacitance value of the first capacitor, but is not limited thereto. Optionally, the first control circuit includes a second transistor; the driving circuit includes a driving transistor.

[0126] The control electrode of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first terminal of the driving circuit; the back gate of the second transistor is electrically connected to the second voltage terminal.

[0127] The control terminal of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, and the second terminal of the driving transistor is the second terminal of the driving circuit; the back gate of the driving transistor is electrically connected to the second voltage terminal.

[0128] Optionally, the reference voltage writing circuit includes a third transistor;

[0129] The control electrode of the third transistor is electrically connected to the second write control terminal, the first electrode of the third transistor is electrically connected to the reference voltage terminal, the second electrode of the third transistor is electrically connected to the control terminal of the driving circuit, and the back gate of the third transistor is electrically connected to the second voltage terminal.

[0130] Optionally, the second control circuit includes a fourth transistor;

[0131] The control electrode of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is electrically connected to the reset voltage terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element, and the back gate of the fourth transistor is electrically connected to the third voltage terminal.

[0132] In at least one embodiment of this disclosure, the fourth transistor may be an n-type transistor, and the third voltage terminal may be the reset voltage terminal; or,

[0133] The fourth transistor can be a p-type transistor, and the third voltage terminal is the second voltage terminal.

[0134] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown,

[0135] The first energy storage circuit 12 includes a first capacitor C1; the second energy storage circuit 13 includes a second capacitor C2; the write control circuit 14 includes a first transistor P1; the drive circuit 11 includes a drive transistor P0; the first control circuit 10 includes a second transistor P2; the second control circuit 20 includes a fourth transistor P4; the reference voltage write circuit 16 includes a third transistor P3; the light-emitting element is an organic light-emitting diode O1.

[0136] The first terminal of the first capacitor C1 is electrically connected to the gate of the driving transistor P0, and the second terminal of the first capacitor C1 is electrically connected to the source of the driving transistor P0.

[0137] The first terminal of the second capacitor C2 is electrically connected to the gate of the driving transistor P0;

[0138] The gate of the first transistor P1 is electrically connected to the first write control terminal WS1, the source of the first transistor P1 is electrically connected to the write terminal DW, and the drain of the first transistor P1 is electrically connected to the second terminal of the second capacitor C2; the back gate of the first transistor P1 is electrically connected to the high voltage terminal; the high voltage terminal is used to provide a high voltage VDD.

[0139] The gate of the third transistor P3 is electrically connected to the second write control terminal WS2, the source of the third transistor P3 is electrically connected to the reference voltage terminal R2, and the drain of the third transistor P3 is electrically connected to the gate of the driving transistor P0; the back gate of the third transistor is electrically connected to the high voltage terminal; the reference voltage terminal R2 is used to provide a reference voltage Vref;

[0140] The gate of the second transistor P2 is electrically connected to the first control terminal DS, the source of the second transistor P2 is electrically connected to the power supply voltage terminal Vd, and the drain of the second transistor P2 is electrically connected to the source of the driving transistor P0; the back gate of the second transistor P2 is electrically connected to the high voltage terminal; the power supply voltage terminal Vd is used to provide the power supply voltage ELVDD;

[0141] The gate of the fourth transistor P4 is electrically connected to the second control terminal AZ, the source of the fourth transistor P4 is electrically connected to the ground terminal G1, the drain of the fourth transistor P4 is electrically connected to the anode of the organic light-emitting diode O1, and the back gate of the fourth transistor P4 is electrically connected to the high voltage terminal.

[0142] The cathode of the organic light-emitting diode O1 is connected to a common electrode voltage Vcom.

[0143] In at least one embodiment of this disclosure, the first transistor P1, the second capacitor C2, and the fourth transistor P4 may be disposed outside the display area, and the driving transistor P0, the second transistor P2, the third transistor P3, and the first capacitor C1 may be disposed inside the display area, but are not limited thereto.

[0144] exist Figure 5 In at least one embodiment of the pixel circuit shown, the third voltage terminal is the high voltage terminal, the first voltage terminal is connected to the common electrode voltage Vcom, and the reset voltage terminal is the ground terminal G1.

[0145] In at least one embodiment of this disclosure, ELVDD-Vref is greater than or equal to 1.5V, and the value range of ELVDD can be greater than or equal to 2V and less than or equal to 8V, but is not limited thereto.

[0146] exist Figure 5 In at least one embodiment of the pixel circuit shown, all transistors are PMOS transistors, but this is not a limitation.

[0147] In this disclosure Figure 5 In at least one embodiment of the pixel circuit shown, the driving transistor P0 is equivalent to a current source controlled by the gate voltage, thereby realizing direct control of the driving current flowing through O1 by the data voltage Vdata. Therefore, this disclosure is as follows: Figure 5 At least one embodiment of the pixel circuit shown is a current-type pixel circuit.

[0148] In this public disclosure Figure 5 In at least one embodiment of the pixel circuit shown, the data voltage Vdata is written to the gate of the driving transistor P0 by voltage division through C1 and C2, so as to widen the dynamic range of the data voltage Vdata, which is beneficial to the design of the DAC (digital-to-analog converter) in the source driver and the uniformity of the data line output.

[0149] like Figure 6 As shown, this disclosure is as follows Figure 5 When at least one embodiment of the pixel circuit shown is in operation, the display cycle includes an initialization phase S1, a self-discharge phase S2, a data preparation phase S3, a data writing phase S5, and a light emission phase S6, which are set sequentially.

[0150] During the initialization phase S1, WS1, WS2, DS, and AZ provide low voltage signals, R1 and DW provide reference voltage Vref, P1 and P4 are turned on, P2 and P3 are turned on, the source of P0 is connected to the power supply voltage ELVDD, the gate of P0 is connected to the reference voltage Vref, and the drain of P0 is connected to ground G1. ELVDD-Vref is greater than |Vth| so that P0 can be turned on at the start of the self-discharge phase S2; where Vth is the threshold voltage of P0 without back gate effect.

[0151] During the self-discharge phase S2, AZ provides a low voltage signal, WS1 provides a low voltage signal, WS2 provides a low voltage signal, DS provides a high voltage signal, R1 provides a reference voltage Vref, DW provides a reference voltage Vref, P4 is turned on to connect the drain of P0 to ground G1; P3 is turned on to connect the gate of P0 to the reference voltage Vref; P1 is turned on and P2 is turned off.

[0152] At the start of the self-discharge phase S2, P0 is turned on, discharging through P0 and P4, causing the source potential Vs of P0 to decrease. As Vs decreases, a back-gate effect occurs, and |Vth_ef| equals a×(VDD-Vs)+|Vth|, where Vth_ef is the threshold voltage of P0 with the back-gate effect, and a is the coefficient of the back-gate effect. As Vs decreases, Vgs decreases synchronously. When |Vth_ef| increases to equal |Vgs|, P0 is turned off, and the discharge stops. At this time, a×(VDD-Vs)+|Vth|=Vg-Vs; Vs= Vg = Vref; where Vg is the gate voltage of P0 and Vs is the source voltage of P0; |Vgs| = ;

[0153] During the data preparation phase S3, WS1 provides a high voltage signal, WS2 provides a high voltage signal, DS provides a low voltage signal, AZ provides a low voltage signal, P1 and P3 are turned off, P2 is turned on, P4 is turned on, and the source potential Vs of P0 is pulled high to ELVDD.

[0154] During the data preparation phase S3, Vg changes from Vref to ELVDD- ;

[0155] During the data writing phase S5, WS1 provides a low voltage signal, WS2 provides a high voltage signal, EM provides a low voltage signal, DW provides the data voltage Vdata, AZ provides a low voltage signal, P3 is turned off, P2 is turned on, P4 is turned on, and P1 is turned on, so as to write the data voltage Vdata into the gate of P0, b=C2z / (C1z+C2z), where C1z is the capacitance value of C1, C2z is the capacitance value of C2; ΔVg is the change in the gate voltage of P0;

[0156] ΔVg = (Vdata - ELVDD + ... )×b;

[0157] Vg= ELVDD- +(Vdata- ELVDD+ )×b;

[0158] |Vgs|=-b×Vdata+b×ELVDD- + + ×|Vth|;

[0159] During the light-emitting stage S6, WS2 and WS1 provide high voltage signals, DS provides low voltage signals, AZ provides high voltage signals, P3, P1 and P4 are turned off, P2 is turned on, and P0 drives O1 to emit light.

[0160] In the light-emitting stage S6,

[0161] Io1 = K(|Vgs| - |Vth) 2

[0162] =K(-b×Vdata+b×ELVDD- + + ×|Vth|-|Vth) 2 ;

[0163] As can be seen from the above formula, when (b-1) / (1-a) equals 1, Io1 is independent of Vth.

[0164] As can be seen from the above work process, this disclosure... Figure 5 In at least one embodiment of the pixel circuit shown, during the light-emitting phase, the gate-source voltage of the driving transistor P0 can compensate for the threshold voltage of the driving transistor P0, so that the light-emitting current of the organic light-emitting diode O1 is independent of the threshold voltage Vth, thereby improving display uniformity.

[0165] This disclosure Figure 5At least one embodiment of the pixel circuit shown is a current-mode pixel circuit that uses all PMOS transistors. Compared with a current-mode pixel circuit built with NMOS transistors on the same process platform, it has a wider anode dynamic range for the following reasons:

[0166] For a current-mode pixel circuit built with NMOS transistors, when the voltage of the anode of the organic light-emitting diode O1 is set to a negative voltage, this negative voltage will be connected to the source or drain of the transistor in the pixel circuit. When the transistor is an n-type transistor, there is a forward-biased diode between the back gate and the source of the transistor, which causes a latch-up effect, making the pixel circuit work abnormally. Therefore, the current-mode pixel circuit using PMOS transistors has a wider anode dynamic range. When all the transistors in the current-mode pixel circuit are PMOS transistors, the potential of the anode of the organic light-emitting diode O1 can be a negative voltage.

[0167] This disclosure is as follows Figure 5 At least one embodiment of the pixel circuit shown employs a current-driven pixel driving method, and, as disclosed herein... Figure 5 In at least one embodiment of the pixel circuit shown, the driving circuit includes a PMOS transistor. When a short circuit occurs between the anode and cathode of O1, the dot line will not be defective because the anode voltage of O1 is negative.

[0168] This disclosure is as follows Figure 5 At least one embodiment of the pixel circuit shown can prevent the N-type substrate of the first transistor P1, which is used to transmit data voltage, from leaking current from the drain of the first transistor P1 to the first capacitor C1, thus preventing the occurrence of low grayscale bright spots, for the following reasons:

[0169] This disclosure is as follows Figure 5 At least one embodiment of the pixel circuit shown uses a PMOS transistor. Therefore, in the non-light-emitting stage, even if the N-type substrate of the first transistor P1 leaks to the drain of the first transistor P1 to the first capacitor C1 to raise the potential of the gate of P0, since the driving transistor P0 is also a PMOS transistor, the light emission brightness of the organic light-emitting diode will not increase and no bright spot will appear.

[0170] In related technologies, P0 is an NMOS transistor. The higher the gate potential of P0, the brighter the organic light-emitting diode. Therefore, during the non-light-emitting stage, the drain of P1 leaks current to the first capacitor C1, which raises the gate potential of P0, thereby increasing the light-emitting brightness of the organic light-emitting diode and creating bright spots. Based on this, at least one embodiment of this disclosure sets the transistor as a PMOS transistor to solve the above problem.

[0171] This disclosure Figure 5At least one embodiment of the pixel circuit shown is a current-type pixel circuit, which can compensate for the lifespan degradation caused by the increase in the internal resistance of the organic light-emitting diode O1, and, in this disclosure Figure 5 In at least one embodiment of the pixel circuit shown, the back gate of each transistor is connected to a high voltage VDD, but not to ELVDD, so that the substrate nwell potential of each transistor is separated from ELVDD, allowing ELVDD to be flexibly configured within a range smaller than VDD.

[0172] This disclosure is as follows Figure 5 At least one embodiment of the pixel circuit shown can be a current-type pixel circuit applied to silicon-based OLED (organic light-emitting diode) microdisplay chips, but is not limited thereto. At least one embodiment of this disclosure is based on a specific semiconductor process platform and uses only PMOS transistors for pixel circuit design, overcoming the space limitations of MOS transistors due to design rules in pixel circuits where PMOS and NMOS transistors coexist. This effectively shortens the pixel area and increases PPI (Pixels Per Inch).

[0173] In at least one embodiment of this disclosure, the fourth transistor may also be an N-type transistor, in which case the third voltage terminal may be a reset voltage terminal.

[0174] In a specific implementation, when the fourth transistor is an NMOS transistor, both the back gate and the source of the fourth transistor can be electrically connected to the reset voltage terminal.

[0175] A deep n-type hydrazine is disposed between the back gate of the fourth transistor and the P-type substrate to isolate the back gate of the fourth transistor from the P-type substrate; both the back gate and the source of the fourth transistor are electrically connected to the reset voltage terminal.

[0176] In related technologies, in a display panel, the back gate of the N-type transistor in the pixel circuit and the back gate of the N-type transistor in the driving circuit (the driving circuit is used to provide a driving signal for the pixel circuit) are both electrically connected to the P-type substrate. However, in at least one embodiment of this disclosure, the back gate of the fourth transistor in the pixel circuit needs to be electrically connected to the reset voltage terminal, while the P-type substrate is connected to a 0V voltage signal. Therefore, a deep n-type transistor needs to be provided between the P-type substrate and the back gate of the fourth transistor to isolate the P-type substrate from the back gate of the fourth transistor.

[0177] In at least one embodiment of this disclosure, the anode dynamic range of the organic light-emitting diode O1 needs to be extended to negative voltage. The withstand voltage of each transistor is 8V, while ELVDD is 3V. Therefore, the minimum anode reset voltage can be -5V. Thus, the back gate of the fourth transistor needs to be connected to a -5V voltage signal (generally, the source of the NMOS transistor and the back gate of the NMOS transistor are electrically connected to the same voltage terminal). Therefore, the P-type substrate needs to be isolated from the back gate of the fourth transistor.

[0178] Figure 7 This is a structural diagram of an NMOS transistor and a PMOS transistor in at least one embodiment of this disclosure.

[0179] exist Figure 7 In the diagram, 60 represents a P-type substrate, 61 represents a deep n-type hydrazine, 621 represents the gate of an NMOS transistor, 622 represents the gate of a PMOS transistor, 631 represents the back gate of an NMOS transistor, 632 represents the source of an NMOS transistor, 633 represents the drain of an NMOS transistor, 641 represents the back gate of a PMOS transistor, 642 represents the source of a PMOS transistor, and 643 represents the drain of a PMOS transistor. 65 represents an insulating structure. 661 and 663 represent N-type hydrazine, and 662 represents P-type hydrazine.

[0180] exist Figure 7 In this context, the NMOS transistor can be the fourth transistor.

[0181] like Figure 7 As shown, a deep n-type hydrazine 61 is provided between the back gate 631 of the NMOS transistor and the P-type substrate 60, so that the back gate of the NMOS transistor can be connected to a -5V voltage signal, while the P-type substrate 60 can be connected to a 0V voltage signal.

[0182] Optionally, the pixel circuit described in at least one embodiment of this disclosure may further include n-hydrazine; the doping concentration of the n-hydrazine is greater than the doping concentration of the deep n-hydrazine;

[0183] The ratio of the thickness of the n-hydrazine to the thickness of the deep n-hydrazine is greater than or equal to 0.4 and less than or equal to 0.6; however, it is not limited to this.

[0184] For example, the thickness of the n-hydrazine can be 0.5 μm, and the thickness of the deep n-hydrazine can be 1 μm.

[0185] In specific implementation, the pixel circuit described in at least one embodiment of this disclosure may further include p-hydrazine; the ratio of the thickness of the p-hydrazine to the thickness of the deep n-hydrazine is greater than or equal to 0.4 and less than or equal to 0.6; but is not limited thereto.

[0186] For example, the thickness of the p-hydrazine can be 0.5 μm, and the thickness of the deep n-hydrazine can be 1 μm.

[0187] In related technologies, if a deep n-type hydrazine is not provided between the back gate 631 and the P-type substrate 60 of the NMOS transistor, then the back gate 631 and the P-type substrate 60 of the NMOS transistor cannot be connected to different voltage signals.

[0188] Figure 8 This is a schematic diagram of the structure of NMOS transistors and PMOS transistors in related technologies.

[0189] Figure 8 and Figure 7 The difference is that it does not have a deep n-hydrazine 61.

[0190] like Figure 9 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of this disclosure further includes a first resistor R01;

[0191] The first resistor R01 is connected between the drain of the driving transistor P0 and the anode of the organic light-emitting diode O1;

[0192] The first end of the first resistor R01 is electrically connected to the drain of the driving transistor P0, and the second end of the first resistor R01 is electrically connected to the anode of the organic light-emitting diode O1.

[0193] The first resistor R01 can prevent a short circuit between the anode and cathode of the organic light-emitting diode O1.

[0194] The display panel described in this embodiment includes multiple rows and columns of the aforementioned pixel circuits.

[0195] The driving method described in this embodiment is applied to the pixel circuit described above, and the driving method includes:

[0196] Under the control of the first write control signal, the write control circuit controls the connection or disconnection between the write terminal and the second terminal of the second energy storage circuit.

[0197] Under the control of the first control signal, the first control circuit controls the connection or disconnection between the power supply voltage terminal and the first terminal of the drive circuit.

[0198] The driving circuit generates a driving current to drive the light-emitting element under the control of the potential at its control terminal.

[0199] Optionally, the display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially; the driving method described in at least one embodiment of this disclosure may include:

[0200] During the initialization phase, the data preparation phase, the data writing phase, and the light emission phase, the first control circuit, under the control of the first control signal, controls the connection between the power supply voltage terminal and the first terminal of the driving circuit.

[0201] During the self-discharge phase, the first control circuit, under the control of the first control signal, controls the disconnection between the power supply voltage terminal and the first terminal of the drive circuit.

[0202] Optionally, the display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially; the driving method described in at least one embodiment of this disclosure may include:

[0203] During the data preparation stage and the light emission stage, the write control circuit, under the control of the first write control signal, controls the write terminal to disconnect from the second terminal of the second energy storage circuit.

[0204] During the initialization phase, the self-discharge phase, and the data writing phase, the write control circuit, under the control of the first write control signal, controls the connection between the write terminal and the second terminal of the second energy storage circuit.

[0205] The display device described in at least one embodiment of this disclosure includes the display panel described above.

[0206] In at least one embodiment of this disclosure, the display panel includes a first silicon substrate, and pixel circuits and gate driving circuits disposed on the first silicon substrate;

[0207] The display device further includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

[0208] In a specific implementation, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate;

[0209] The minimum width of the signal lines included in the display panel is greater than the width of the signal lines included in the display driver chip. For example... Figure 10 As shown, the display panel includes a first silicon substrate 201, and pixel circuits and gate driving circuits 202 disposed on the first silicon substrate 201; Figure 10 In the diagram, the area labeled A0 is the effective display area, and the pixel circuit is disposed in the effective display area;

[0210] The display device further includes a second silicon substrate 203 and a display driver chip disposed on the second silicon substrate 203.

[0211] In at least one embodiment of this disclosure, the first transistor, the fourth transistor, and the second capacitor included in the pixel circuit may be disposed outside the effective display area, while the driving transistor, the second transistor, the third transistor, and the second capacitor included in the pixel circuit may be disposed inside the effective display area, but are not limited thereto.

[0212] Optionally, the capacitance value of the first capacitor may be greater than the capacitance value of the second capacitor, but this is not a limitation.

[0213] like Figure 10 As shown, the display driver chip may include a display driver integrated circuit 301, a source driver 302, a timing controller 303, a data processor 304, an input / output interface 305, a signal receiver 306, and a bias and reference voltage supply circuit 307; but is not limited thereto.

[0214] In at least one embodiment of this disclosure, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate;

[0215] The minimum width of the signal lines included in the display panel is greater than the width of the signal lines included in the display driver chip.

[0216] In at least one embodiment of this disclosure, different process technologies are used to fabricate the display panel and the display driver chip. For example, the display panel can be fabricated using a 100nm process and the display driver chip can be fabricated using a 28nm process, so that the linewidth of the signal lines included in the display driver chip is smaller than the linewidth of the signal lines included in the display panel, and the spacing between the signal lines included in the display driver chip is smaller than the spacing between the signal lines included in the display panel.

[0217] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0218] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, characterized in that, It includes a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a write control circuit, and a first control circuit; The first terminal of the first energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the first energy storage circuit is electrically connected to the first terminal of the drive circuit; the first energy storage circuit is used to store electrical energy. The first terminal of the second energy storage circuit is electrically connected to the control terminal of the drive circuit; the second energy storage circuit is used to store electrical energy. The write control circuit is electrically connected to the first write control terminal, the write terminal and the second terminal of the second energy storage circuit, respectively, and is used to control the connection or disconnection between the write terminal and the second terminal of the second energy storage circuit under the control of the first write control signal provided by the first write control terminal. The first control circuit is electrically connected to the first control terminal, the power supply voltage terminal, and the first terminal of the drive circuit, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first terminal of the drive circuit under the control of the first control signal provided by the first control terminal. The second terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of its control terminal. The display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially. The first control circuit is used to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first control signal during the initialization phase, the data preparation phase, the data writing phase, and the light emission phase; and to control the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first control signal during the self-discharge phase.

2. The pixel circuit as described in claim 1, characterized in that, The first control circuit is used to control the connection between the power supply voltage terminal and the first terminal of the drive circuit under the control of the first control signal during two discontinuous phases in a display cycle.

3. The pixel circuit as described in claim 1, characterized in that, The write control circuit is used to disconnect the write terminal from the second terminal of the second energy storage circuit under the control of the first write control signal during the data preparation stage and the light emission stage, and to connect the write terminal to the second terminal of the second energy storage circuit under the control of the first write control signal during the initialization stage, the self-discharge stage and the data writing stage.

4. The pixel circuit according to any one of claims 1 to 3, characterized in that, It also includes a reference voltage writing circuit; The reference voltage writing circuit is electrically connected to the second writing control terminal, the reference voltage terminal, and the control terminal of the driving circuit, respectively, and is used to write the reference voltage provided by the reference voltage terminal to the control terminal of the driving circuit under the control of the second writing control signal provided by the second writing control terminal.

5. The pixel circuit according to any one of claims 1 to 3, characterized in that, It also includes a second control circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the first voltage terminal; The second control circuit is electrically connected to the second control terminal, the reset voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to control the reset voltage provided by the reset voltage terminal to be written into the first electrode of the light-emitting element under the control of the second control signal provided by the second control terminal.

6. The pixel circuit according to any one of claims 1 to 3, characterized in that, It also includes a resistor circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light-emitting element through the resistor circuit, and the second electrode of the light-emitting element is electrically connected to the first voltage terminal.

7. The pixel circuit according to any one of claims 1 to 3, characterized in that, The first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor; the write control circuit includes a first transistor; The first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit. The first terminal of the second capacitor is electrically connected to the control terminal of the driving circuit; The control electrode of the first transistor is electrically connected to the first write control terminal, the first electrode of the first transistor is electrically connected to the write terminal, the second electrode of the first transistor is electrically connected to the second terminal of the second capacitor, and the back gate of the first transistor is electrically connected to the second voltage terminal.

8. The pixel circuit according to any one of claims 1 to 3, characterized in that, The first control circuit includes a second transistor; the driving circuit includes a driving transistor. The control electrode of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the power supply voltage terminal, and the second electrode of the second transistor is electrically connected to the first terminal of the driving circuit; the back gate of the second transistor is electrically connected to the second voltage terminal. The control terminal of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, and the second terminal of the driving transistor is the second terminal of the driving circuit; the back gate of the driving transistor is electrically connected to the second voltage terminal.

9. The pixel circuit as described in claim 4, characterized in that, The reference voltage writing circuit includes a third transistor; The control electrode of the third transistor is electrically connected to the second write control terminal, the first electrode of the third transistor is electrically connected to the reference voltage terminal, the second electrode of the third transistor is electrically connected to the control terminal of the driving circuit, and the back gate of the third transistor is electrically connected to the second voltage terminal.

10. The pixel circuit as described in claim 5, characterized in that, The second control circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is electrically connected to the reset voltage terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element, and the back gate of the fourth transistor is electrically connected to the third voltage terminal.

11. The pixel circuit as described in claim 10, characterized in that, The fourth transistor is an n-type transistor, and the third voltage terminal is the reset voltage terminal; or... The fourth transistor is a p-type transistor, and the third voltage terminal is the second voltage terminal.

12. The pixel circuit as described in claim 11, characterized in that, The fourth transistor is an n-type transistor; a deep n-type hydrazine is disposed between the back gate of the fourth transistor and the P-type substrate to isolate the back gate of the fourth transistor from the P-type substrate; the back gate of the fourth transistor and the first terminal of the fourth transistor are both electrically connected to the reset voltage terminal.

13. The pixel circuit as described in claim 12, characterized in that, It also includes n-hydrazine and p-hydrazine; The doping concentration of the n-hydrazine is greater than that of the deep n-hydrazine; The ratio of the thickness of the n-hydrazine to the thickness of the deep n-hydrazine is greater than or equal to 0.4 and less than or equal to 0.6; The ratio of the thickness of the p-hydrazine to the thickness of the deep n-hydrazine is greater than or equal to 0.4 and less than or equal to 0.

6.

14. A display panel, characterized in that, Includes a multi-row, multi-column pixel circuit as described in any one of claims 1 to 13.

15. A driving method applied to a pixel circuit as described in any one of claims 1 to 13, characterized in that, The driving method includes: Under the control of the first write control signal, the write control circuit controls the connection or disconnection between the write terminal and the second terminal of the second energy storage circuit. Under the control of the first control signal, the first control circuit controls the connection or disconnection between the power supply voltage terminal and the first terminal of the drive circuit. The driving circuit generates a driving current to drive the light-emitting element under the control of the potential at its control terminal; The display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially; the driving method includes: During the initialization phase, the data preparation phase, the data writing phase, and the light emission phase, the first control circuit, under the control of the first control signal, controls the connection between the power supply voltage terminal and the first terminal of the driving circuit. During the self-discharge phase, the first control circuit, under the control of the first control signal, controls the disconnection between the power supply voltage terminal and the first terminal of the drive circuit.

16. The driving method as described in claim 15, characterized in that, The driving method includes: Within a display cycle, in two discontinuous phases, the first control circuit, under the control of the first control signal, controls the connection between the power supply voltage terminal and the first terminal of the drive circuit.

17. The driving method as described in claim 15, characterized in that, The display cycle of the pixel circuit includes an initialization phase, a self-discharge phase, a data preparation phase, a data writing phase, and a light emission phase, which are set sequentially; the driving method includes: During the initialization phase, the data preparation phase, and the light emission phase, the write control circuit, under the control of the first write control signal, controls the write terminal to disconnect from the second terminal of the second energy storage circuit. During the self-discharge phase and the data writing phase, the write control circuit, under the control of the first write control signal, controls the connection between the write terminal and the second terminal of the second energy storage circuit.

18. A display device, characterized in that, Includes the display panel as described in claim 14.

19. The display device as claimed in claim 18, characterized in that, The display panel includes a first silicon substrate, and pixel circuits and gate driving circuits disposed on the first silicon substrate. The display device further includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

20. The display device as claimed in claim 19, characterized in that, The area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; The minimum width of the signal lines included in the display panel is greater than the width of the signal lines included in the display driver chip.

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