An etching process for deep silicon oxide waveguide and trench

Abstract

The application discloses an etching process for deep silicon oxide waveguide and groove. The wafer is etched and the wafer to be etched comprises photoresist, shallow silicon oxide, metal chromium, deep silicon oxide, quartz substrate and back metal chromium from top to bottom. The etching process comprises the following steps: S1, using photoresist with a preset thickness as a mask for the shallow silicon oxide and using a first process parameter to perform a first etching process. The first etching process is as follows: introducing fluorine-based gas into the cavity to perform plasma etching on the shallow silicon oxide on the upper layer of the metal chromium, so as to transfer the pattern on the photoresist to the shallow silicon oxide. The etching process for deep silicon oxide waveguide and groove disclosed by the application can realize the etching of an etching structure with a high aspect ratio, high absolute depth, perpendicular sidewall angle and smooth sidewall.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor etching technology, specifically relating to an etching process for deep silicon oxide waveguides and trenches. Background Technology

[0002] With the development of Micro-Electro-Mechanical Systems (MEMS) technology, silicon has begun to emerge as a low-cost, easily processed structural material in the microelectronics field. However, as a functional material, silicon still has many shortcomings. In the field of novel MEMS devices—photoelectric transmission—its transmission loss is relatively high, and many different materials have shown better performance (quality factor Q) than silicon. Specifically, in the fields of optical waveguides, microwave technology, sensors, and biochips, devices based on silicon oxide, quartz, and glass have emerged.

[0003] The high-depth and wide silicon oxide microstructures obtained by current silicon oxide etching technology are far from meeting the needs of the MEMS field. In addition, there are also defects such as non-perpendicular sidewall angles and large sidewall roughness when performing plasma etching on silicon oxide.

[0004] Therefore, further improvements will be made to address the aforementioned issues. Summary of the Invention

[0005] The main objective of this invention is to provide an etching process for deep silicon oxide waveguides and trenches, enabling the etching of structures with high aspect ratio, high absolute depth, perpendicular sidewall angles, and smooth sidewalls.

[0006] To achieve the above objectives, this invention provides an etching process for deep silicon oxide waveguides and trenches. The process involves etching a wafer, which, from top to bottom, comprises photoresist, shallow silicon oxide, metallic chromium, deep silicon oxide, a quartz substrate, and a back-side metallic chromium layer. The process includes the following steps:

[0007] Step S1: Use a photoresist of a preset thickness (preferably 1 μm) as a mask for shallow silicon oxide and perform a first etching process using the first process parameters. The first etching process is: introduce fluorine-based gas into the cavity to perform plasma etching on the shallow silicon oxide located on the metal chromium layer, thereby transferring the pattern on the photoresist to the shallow silicon oxide.

[0008] Step S2: Use the etched shallow silicon oxide as a mask for the metal chromium and perform a second etching process using the second process parameters. The second etching process is: introduce chlorine gas into the cavity to perform plasma etching on the metal chromium located on the upper layer of deep silicon oxide, thereby transferring the pattern on the shallow silicon oxide to the metal chromium.

[0009] Step S3: Use the etched chromium metal as a mask for the deep silicon oxide and perform a third etching process using the third process parameters. The third etching process is as follows: introduce fluorine-based gas (and other gas plasmas) into the cavity to perform plasma etching on the deep silicon oxide located on the quartz substrate, thereby transferring the pattern on the chromium metal to the deep silicon oxide.

[0010] As a further preferred technical solution to the above technical solution, the first process parameter is:

[0011] Upper electrode power: 1000~2000W;

[0012] Lower electrode power: 100-300W;

[0013] Cavity pressure: 5–10 mT;

[0014] CF4 flow rate: 20-40 sccm;

[0015] The flow rate of C4F8 is 40-80 sccm;

[0016] Ar flow rate: 10-40 sccm;

[0017] The N2 flow rate is 10–40 sccm.

[0018] As a further preferred technical solution to the above technical solution, the second process parameter is:

[0019] Upper electrode power: 100-600W;

[0020] Lower electrode power: 100-200W;

[0021] Cavity pressure: 5–10 mT;

[0022] Cl2 flow rate: 20-40 sccm;

[0023] O2 flow rate: 10-40 sccm.

[0024] As a further preferred technical solution to the above technical solution, the third process parameter is:

[0025] Upper electrode power: 1000~2000W;

[0026] Lower electrode power: 100-400W;

[0027] Cavity pressure: 5–10 mT;

[0028] CF4 flow rate: 10-80 sccm;

[0029] CHF3 flow rate: 40-200 sccm;

[0030] O2 flow rate: 10-40 sccm.

[0031] As a further preferred technical solution to the above technical solution, the fluorine-based gas in step S1 is CF4 or C4F8.

[0032] As a further preferred technical solution to the above technical solution, the chlorine-based gas in step S2 is Cl2 or BCl3.

[0033] As a further preferred technical solution to the above technical solution, the fluorine-based gas in step S3 is CF4, C4F8 or CHF3.

[0034] As a further preferred technical solution to the above technical solution, in step S3, other gases are also introduced into the cavity, and the other gases are Ar, O2 or a mixture of two gases.

[0035] The beneficial effects of this invention are as follows:

[0036] The etching process employs a three-step etching procedure to transfer patterns. First, in step S1, a first etching gas, composed of a fluorine-based gas and other gases, is introduced to etch the shallow silicon oxide layer. Then, the cavity is replaced, and a second etching gas, composed of a chlorine-based gas and other gases, is introduced to etch the chromium layer. After cleaning, the material is placed back into the cavity, and a third etching gas, composed of a second fluorine-based gas and other gases, is introduced for plasma etching, resulting in deep silicon oxide waveguides and trenches. This method maintains consistent depth for waveguides and trenches of different sizes during plasma etching of deep silicon oxide. The resulting deep silicon oxide etching structure exhibits high aspect ratio, high absolute depth, perpendicular sidewall angles, and smooth sidewalls, thereby improving the performance of MEMS devices. Attached Figure Description

[0037] Figure 1 This is a SEM characterization image of silicon oxide before etching in the prior art.

[0038] Figure 2 This is a SEM characterization image of silicon oxide after etching in the prior art.

[0039] Figure 3 This is a schematic diagram of the etching wafer required for the etching process of a deep silicon oxide waveguide and trench according to the present invention.

[0040] Figure 4 This is a schematic diagram of the pattern after photolithography in the etching process of a deep silicon oxide waveguide and trench according to the present invention.

[0041] Figure 5This is a schematic diagram of the etching process of a deep silicon oxide waveguide and trench according to the present invention, after etching a shallow silicon oxide layer.

[0042] Figure 6 This is a schematic diagram of the etching process of a deep silicon oxide waveguide and trench according to the present invention, after etching the chromium layer.

[0043] Figure 7 This is a schematic diagram of the etching process for deep silicon oxide waveguides and trenches according to the present invention, after etching deep silicon oxide.

[0044] Figure 8 This is a SEM image of a waveguide etched using parameters of a deep silicon oxide waveguide and trench etching process according to the present invention.

[0045] Figure 9 This is a SEM image of the trench etched using the etching process of a deep silicon oxide waveguide and trench according to the present invention.

[0046] The reference numerals in the attached figures include: 1. Photoresist; 2. Shallow silicon oxide; 3. Metallic chromium; 4. Deep silicon oxide; 5. Quartz substrate; 6. Backside metallic chromium. Detailed Implementation

[0047] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0048] In the preferred embodiments of the present invention, those skilled in the art should note that the etching and other techniques involved in the present invention can be considered as prior art.

[0049] Preferred embodiment.

[0050] In existing technologies, etching deep silicon oxide often involves using thick photoresist. However, thick photoresist is prone to collapse in small apertures, leading to aperture blockage. Simultaneously, the photoresist mask angle above large apertures cannot achieve a vertical morphology, preventing subsequent etching from ensuring the sidewalls of the deep silicon oxide are perpendicular. For example... Figure 1 As shown, the photoresist mask in the figure is curved, making it difficult to etch straight sidewall angles of silicon oxide. Figure 2 As shown, the sidewalls of the etched morphology are inclined. The process formulation used is as follows:

[0051] Cavity air pressure: 5mT;

[0052] Upper electrode power: 2200W;

[0053] Lower electrode power: 300W;

[0054] Ar flow rate: 25 sccm;

[0055] C4F8 flow rate: 50 sccm.

[0056] A highly vertical silicon oxide layer is the foundation for fabricating excellent devices; however, a good initial vertical angle is essential for ensuring the subsequent etching angle.

[0057] Under the above conditions, a hard mask is undoubtedly a better choice. In this invention, metallic chromium is chosen as the final mask for etching deep silicon oxide.

[0058] This invention discloses an etching process for deep silicon oxide waveguides and trenches, characterized in that the wafer to be etched comprises, from top to bottom, photoresist 1, shallow silicon oxide 2, metallic chromium 3, deep silicon oxide 4, quartz substrate 5, and back metallic chromium 6, and includes the following steps:

[0059] Will Figure 3 After undergoing processes such as coating, developing, and exposure, a patterned wafer is obtained, such as... Figure 4 As shown. It is worth noting that since only a shallow silicon oxide layer needs to be etched, the required photoresist thickness does not need to be too thick, which can ensure good pre-treatment. This is a prerequisite for the subsequent high vertical angle of the deep silicon oxide layer.

[0060] Step S1: Use photoresist 1 with a preset thickness (preferably 1µm) as a mask for shallow silicon oxide 2 and perform the first etching process using the first process parameters. The first etching process is as follows: introduce fluorine-based gas into the cavity (etching cavity) to perform plasma etching on the shallow silicon oxide 2 located on the metal chromium 3, thereby transferring the pattern on the photoresist 1 to the shallow silicon oxide 2. The etching time is determined by the thickness of the shallow silicon oxide 2, and about 10% over-etching can be used to ensure clean etching.

[0061] Step S2: The etched shallow silicon oxide 2 is used as a mask for the metallic chromium 3, and a second etching process is performed using the second process parameters. The second etching process is as follows: a chlorine-based gas is introduced into the cavity to perform plasma etching on the metallic chromium 3 located on the upper layer 4 of the deep silicon oxide, thereby transferring the pattern on the shallow silicon oxide 2 onto the metallic chromium 3. Figure 6 To transfer the pattern on the shallow silicon oxide layer to the metallic chromium layer, due to the metal mask, chlorine-based gas is required for etching (and the etching chamber needs to be replaced).

[0062] Step S3: The etched chromium metal 3 is used as a mask for the deep silicon oxide 4, and a third etching process is performed using the third process parameters. The third etching process is as follows: Fluorine-based gas (and other gas plasmas) is introduced into the cavity to perform plasma etching on the deep silicon oxide 4 located on the quartz substrate 5, thereby transferring the pattern on the chromium metal 3 to the deep silicon oxide 4. Figure 7 This is a schematic diagram of deep silicon oxide etching. This step performs the final transfer of the pattern on the metallic chromium, while the etching scheme for the deep silicon oxide changes.

[0063] Specifically, the first process parameter is:

[0064] Upper electrode power: 1000~2000W;

[0065] Lower electrode power: 100-300W;

[0066] Cavity pressure: 5–10 mT;

[0067] CF4 flow rate: 20-40 sccm;

[0068] The flow rate of C4F8 is 40-80 sccm;

[0069] Ar flow rate: 10-40 sccm;

[0070] The N2 flow rate is 10–40 sccm.

[0071] More specifically, the second process parameter is:

[0072] Upper electrode power: 100-600W;

[0073] Lower electrode power: 100-200W;

[0074] Cavity pressure: 5–10 mT;

[0075] Cl2 flow rate: 20-40 sccm;

[0076] O2 flow rate: 10-40 sccm.

[0077] Furthermore, the third process parameter is:

[0078] Upper electrode power: 1000~2000W;

[0079] Lower electrode power: 100-400W;

[0080] Cavity pressure: 5–10 mT;

[0081] CF4 flow rate: 10-80 sccm;

[0082] CHF3 flow rate: 40-200 sccm;

[0083] O2 flow rate: 10-40 sccm.

[0084] Furthermore, the fluorine-based gas in step S1 is CF4 or C4F8, and step S1 is etched using a first etching gas, which is a mixture of fluorine-based gas, Ar, and N2.

[0085] Preferably, the chlorine-based gas in step S2 is Cl2 or BCl3, and step S2 is performed by etching with a second etching gas, which is a mixture of chlorine-based gas and O2 and N2.

[0086] Preferably, the fluorine-based gas in step S3 is CF4, C4F8, or CHF3.

[0087] Preferably, in step S3, other gases are also introduced into the cavity (to increase physical etching), and the other gases are Ar, N2, O2 or a mixture of two gases.

[0088] Optionally, the ratio of C atoms to F atoms in the first and third etching gases needs to be maintained at a certain ratio, approximately between 1:2 and 1:4.

[0089] Optionally, the O2 content in the second etching gas should not be too high.

[0090] Optionally, the fluorine-based gas in steps S1 and S3 is a mixture of CF4, C4F8, CHF3, or SF6.

[0091] Optionally, the etching chamber should be replaced after step S1 to prevent machine contamination. Fluorine-based etching chambers should be distinguished from chlorine-based etching chambers.

[0092] Optionally, the wafer needs to be cleaned after step S2 to prevent metal ions from being introduced into the clean fluorine-based etching chamber.

[0093] Specific process effects are as follows: Figure 8 , 9 As shown, the etching angle is close to 90°, and the depth is about 6μm. Each etching step requires a cleaning and annealing process, depending on the specific circumstances.

[0094] It is worth mentioning that the etching and other technical features involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.

[0095] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. An etching process for deep silicon oxide waveguides and trenches, characterized in that, Etching a wafer, wherein the wafer to be etched, from top to bottom, comprises photoresist, shallow silicon oxide, metallic chromium, deep silicon oxide, quartz substrate, and back metallic chromium, includes the following steps: Step S1: Use a photoresist of a preset thickness as a mask for shallow silicon oxide and perform the first etching process using the first process parameters. The first etching process is: introduce fluorine-based gas into the cavity to perform plasma etching on the shallow silicon oxide located on the metal chromium layer, thereby transferring the pattern on the photoresist to the shallow silicon oxide. The first process parameter is: Upper electrode power: 1000~2000W; Lower electrode power: 100~300W; Cavity pressure: 5~10mT; CF4 flow rate: 20~40 sccm; The flow rate of C4F8 is 40~80 sccm; Ar flow rate: 10~40 sccm; N2 flow rate: 10~40 sccm; Step S2: Use the etched shallow silicon oxide as a mask for the metal chromium and perform a second etching process using the second process parameters. The second etching process is: introduce chlorine gas into the cavity to perform plasma etching on the metal chromium located on the upper layer of deep silicon oxide, thereby transferring the pattern on the shallow silicon oxide to the metal chromium. The second process parameter is: Upper electrode power: 100~600W; Lower electrode power: 100~200W; Cavity pressure: 5~10mT; Cl2 flow rate: 20~40 sccm; O2 flow rate: 10~40 sccm; Step S3: Use the etched chromium metal as a mask for deep silicon oxide and perform a third etching process using the third process parameters. The third etching process is: introduce fluorine-based gas into the cavity to perform plasma etching on the deep silicon oxide located on the quartz substrate, thereby transferring the pattern on the chromium metal to the deep silicon oxide. The third process parameter is: Upper electrode power: 1000~2000W; Lower electrode power: 100~400W; Cavity pressure: 5~10mT; CF4 flow rate: 10~80 sccm; CHF3 flow rate: 40~200 sccm; O2 flow rate: 10~40 sccm.

2. The etching process for deep silicon oxide waveguides and trenches according to claim 1, characterized in that, The fluorine-based gas in step S1 is either CF4 or C4F8.

3. The etching process for deep silicon oxide waveguides and trenches according to claim 1, characterized in that, The chlorine-based gas in step S2 is either Cl2 or BCl3.

4. The etching process for deep silicon oxide waveguides and trenches according to claim 1, characterized in that, The fluorine-based gas in step S3 is CF4, C4F8, or CHF3.

5. The etching process for deep silicon oxide waveguides and trenches according to claim 4, characterized in that, In step S3, other gases are introduced into the cavity, which may be Ar, O2, or a mixture of the two gases.

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