A digital LDO structure

Abstract

The application discloses a digital LDO structure, comprising: a 3-bit continuous-time flash ADC, which is used for comparing an output power voltage Vreg with 7 reference voltages to generate a 7-bit digital signal COMP<6:0>, wherein 7 is a positive integer; a digital control logic, an N-bit decimal index array, which is connected with a load circuit and the digital control logic respectively; and the load circuit is grounded. The digital control logic is used for controlling the switch quantity of a PMOS tube of the N-bit decimal index array by detecting the change of the 7-bit digital signal COMP<6:0>, and then adjusting the size of the output power voltage Vreg. The application has the advantages of accelerating the response speed, having no output capacitor, improving the dynamic range and reducing the steady-state power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a digital LDO structure. Background Technology

[0002] In modern microcontroller unit (MCU) / system-on-chip (SoC) chip design, low-dropout linear regulators (LDOs) are often required to operate at low voltages. Traditional analog LDOs cannot function properly at low voltages, and digital circuits have a higher tolerance for power supply noise than analog circuits, leading to the increasing prevalence of digital LDOs. Furthermore, digital LDOs do not require large output capacitors to suppress power supply voltage fluctuations during rapid load changes.

[0003] Classical Digital LDOs employ a synchronously clock-controlled Flash ADC and digital control logic (such as a PI controller) combined with a single PMOS array (i.e., all PMOS arrays are the same size). Classical Digital LDOs suffer from drawbacks including the need for an output capacitor and less-than-ideal response speed, dynamic range, and steady-state power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide a digital LDO structure, specifically a digital LDO structure that can accelerate response speed, eliminate output capacitors, improve dynamic range, and reduce steady-state power consumption.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0006] A digital LDO structure includes: a 3-bit continuous-time Flash ADC100 for comparing the output power supply voltage Vreg with 7 reference voltages to generate a 7-bit digital signal COMP<6:0>.

[0007] Digital control logic 101 and an N-bit fractional exponent array 102 are connected to the load circuit 103 and the digital control logic 101, respectively; the load circuit 103 is grounded. The digital control logic 101 is used to control the number of PMOS transistors in the N-bit fractional exponent array 102 by detecting changes in the 7-bit digital signal COMP<6:0>, thereby adjusting the magnitude of the output power supply voltage Vreg.

[0008] Optionally, the 3-bit continuous-time Flash ADC100 includes seven continuous-time comparators and seven voltage regulators. Each voltage regulator is connected to one input terminal of the corresponding continuous-time comparator. The seven voltage regulators generate reference voltages Vref<6:0> for the corresponding continuous-time comparators, and each reference voltage Vref is input to a corresponding continuous-time comparator. The input voltage Vreg of the comparator is input to each of the continuous-time comparators. The seven continuous-time comparators compare the input voltage Vreg of the corresponding comparator with the reference voltages Vref<6:0> respectively and output the 7-bit digital signal COMP<6:0>.

[0009] Optionally, each of the continuous-time comparators includes: the drain of MOSFET MP1 connected to the comparator's reference voltage Vref; the gate of MOSFET MP1 connected to the gate of MOSFET MN1; the source of MOSFET MP1 connected to the drain of MOSFET MN1; the drain of MOSFET MP2 connected to the comparator's input voltage Vreg; the gate of MOSFET MP2 connected to the gate of MOSFET MN2; the source of MOSFET MP2 connected to the drain of MOSFET MN2; and the drain of MOSFET MP3 connected to the comparator's input voltage Vreg.

[0010] The gate of MOSFET MP3 is connected to the gate of MOSFET MN3. The source of MOSFET MP3 is connected to the drain of MOSFET MN3. The sources of MOSFETs MN1 to MN3 are interconnected and grounded. The midpoint of the gate connection between MOSFET MP1 and MOSFET MN1 is connected to the midpoint of the source connection between MOSFET MP1 and MOSFET MN1; the voltage at the midpoint of the gate connection between MOSFET MP1 and MOSFET MN1 is Vx1. The midpoint of the source connection between MOSFET MP1 and MOSFET MN1 is connected to the midpoint of the gate connection between MOSFET MP2 and MOSFET MN2. The midpoint of the source connection between MOSFET MP2 and MOSFET MN2 is connected to the midpoint of the gate connection between MOSFET MP3 and MOSFET MN3.

[0011] The voltage Vx2 is the midpoint of the gate connection between MOSFETs MP3 and MN3. This midpoint is also connected to the input terminal of buffer 10. The input terminal of inverter 20 is connected to the input voltage Vreg of the comparator. The input terminal of NOR gate 30 is connected to both the output terminal of buffer 10 and the output terminal of inverter 20. The output terminal of NOR gate 30 outputs the comparator's output voltage COMP.

[0012] Optionally, the dimensions of the individual MOS transistors in each of the continuous-time comparators are as follows:

[0013]

[0014]

[0015] In the formula, m and n are integers, W represents the width of the MOSFET, L represents the length of the MOSFET, subscripts N1 to N3 represent MOSFETs MN1 to MN3 respectively, and subscripts P1 to P3 represent MOSFETs MP1 to MP3.

[0016] Optionally, each of the continuous-time comparators functions as follows: when the load circuit 103 is started, the input voltage Vreg of the comparator gradually increases from 0, and the MOS transistors MN2~MN3 and MP2~MP3 cannot work normally. At this time, the output voltage COMP is fixed at logic "0" by the inverter 20 and the NOR gate 30.

[0017] After the load circuit 103 is started, the voltage Vx1 stabilizes under the action of the MOS transistors MN1 and MP1.

[0018] When the input voltage Vreg of the comparator is greater than the reference voltage Vref of the comparator, the driving capability of the MOS transistor MP2 is greater than that of the MOS transistor MN2, and the level of the voltage Vx2 is close to the input voltage Vreg of the comparator. After being amplified by the MOS transistors MP3 and MN3, the buffer 10 and the NOR gate 30, the output voltage COMP becomes logic "1".

[0019] When the input voltage Vreg of the comparator is less than the reference voltage Vref of the comparator, the driving capability of the MOS transistor MP2 is less than that of the MOS transistor MN2.

[0020] The voltage Vx1 is brought close to ground, and then amplified by the MOS transistor MP3 and the MOS transistor MN3, the buffer 10 and the NOR gate 30, so that the output voltage COMP becomes logic "0".

[0021] Optionally, the digital control logic 101 includes: an N-bit bidirectional shift register (BSR), three double-edge detection structures, referred to as the first double-edge detection structure 1, the second double-edge detection structure 2, and the third double-edge detection structure 3, respectively; two D flip-flops, referred to as the first D flip-flop 4 and the second D flip-flop 5, respectively; an OR gate 6; and a selector 7. The data input terminal D of the first D flip-flop 4 and its supplementary output terminal... Connection; the supplementary output terminal of the first D flip-flop 4 The first double-edge detection structure 1 is connected to one end, and the other end of the first double-edge detection structure 1 is connected to the input of the selector 7; the output of the selector 7 is connected to one input of the OR gate 6. The output of the third double-edge detection structure 3 is connected to the other input of the OR gate 6; the input of the third double-edge detection structure 3 is connected to a Reset signal.

[0022] The clock input terminal CLK of the first D flip-flop 4 is connected to the output terminal of the OR gate 6 and the N-bit bidirectional shift register BSR, respectively.

[0023] The data input terminal D of the second D flip-flop 5 and its supplementary output terminal Connection; supplementary output terminal of the second D flip-flop 5 One end of the second double-edge detection structure 2 is connected to the second double-edge detection structure 2, and the output of the second double-edge detection structure 2 is connected to the input of the selector 7. The clock input CLK of the second D flip-flop 5 is connected to the output of the OR gate 6 and the N-bit bidirectional shift register BSR.

[0024] Optionally, the gate signal EN_PMOS of the N-bit fractional exponent array <n-1:0>Controlled by the bidirectional shift register BSR, the right side of the bidirectional shift register BSR is padded with 0s when shifting left, and the left side is padded with 1s when shifting right. When the 7-bit digital signal COMP<6:0> is 7'h00 or 7'hef, the bidirectional shift register BSR shifts left by 20 bits or right by 20 bits; when the 7-bit digital signal COMP<6:0> is 7'h01 or 7'h3f, the bidirectional shift register BSR shifts left by 10 bits or right by 10 bits; when the 7-bit digital signal COMP<6:0> is 7'h03 or 7'h1f, the bidirectional shift register BSR shifts left by 5 bits or right by 5 bits; when COMP<6:0> is 7'h0e or 7'h0f, the bidirectional shift register BSR shifts left by 1 bit or right by 1 bit.

[0025] Optionally, each of the said dual-edge detection structures includes: a delay unit and an XOR gate; and a supplementary output terminal of the first D flip-flop 4. The output signal is divided into two paths. One path is connected to one input of the XOR gate in the first double-edge detection structure 1. The other path passes through a delay unit and is connected to the other input of the XOR gate. The output of the XOR gate is connected to the selector 7. The supplementary output of the second D flip-flop 5... The output signal is divided into two paths: one path is connected to one input of the XOR gate in the second double-edge detection structure 2; the other path is connected to the other input of the XOR gate via a delay unit. The output of the XOR gate is connected to the selector 7. The Reset signal is divided into two paths: one path is connected to one input of the XOR gate in the third double-edge detection structure 3; the other path is connected to the other input of the XOR gate via a delay unit; the output of the XOR gate is connected to the OR gate 6.

[0026] Optionally, when the circuit starts up, the third dual-edge detection structure 3 triggers the generation of an asynchronous clock by detecting the edge of the Reset signal.

[0027] After the circuit is started, at each clock edge, a delay signal τ1 is generated by the first D flip-flop 4, or a delay signal τ2 is generated by the second D flip-flop 5. The edge of the delay signal τ1 or τ2 is detected as the next clock signal.

[0028] When the load circuit 103 enters a steady state, a delay signal τ1 is selected to generate a low-frequency clock signal. When the load circuit 103 has not entered a steady state, a delay signal τ2 is selected to generate a high-frequency clock signal.

[0029] Optionally, it is determined whether the time for the 7-bit digital signal COMP<6:0> to be 7'h0e or 7'h0f exceeds M clock cycles. If yes, the load circuit 103 enters a steady state; if no, the load circuit 103 has not entered a steady state. When the 7-bit digital signal COMP<6:0> is no longer 7'h0e or 7'h0f, the load circuit 103 leaves the steady state.

[0030] This invention has at least one of the following technical effects:

[0031] The asynchronous structure used in this invention can better accelerate the response speed compared to the existing synchronous structure.

[0032] This invention employs a fractional-index PMOS array, which, compared to the existing single-index PMOS array structure, can simultaneously ensure faster response speed and lower ripple while having a larger load dynamic range. This is because it can switch small-sized PMOS when the load changes are small and switch large-sized PMOS when the load changes are large. Furthermore, the fractional common ratio of the PMOS array ensures that the size changes are not abrupt (since it can simultaneously possess the above characteristics, no additional load capacitor is needed to improve the characteristics of the LDO).

[0033] The present invention has an asynchronous clock frequency switching structure, which dynamically monitors the load change. When the load change is large, it switches to a fast clock to quickly respond to the load change. When the load change is small (i.e., steady state), it switches to a slow clock to reduce steady state power consumption. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the overall structure of a Digital LDO structure according to an embodiment of the present invention;

[0035] Figure 2 A circuit diagram of a continuous-time comparator provided in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of a 3-bit continuous-time Flash ADC structure provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of a digital control logic structure provided in an embodiment of the present invention. Detailed Implementation

[0038] The following detailed description of a Digital LDO structure proposed in this invention, in conjunction with the accompanying drawings and specific embodiments, will further illustrate its advantages and features. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings for a clearer understanding of the objectives, features, and advantages of this invention. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to aid those skilled in the art, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0039] like Figure 1 As shown, this embodiment provides a digital LDO structure, including: a 3-bit continuous-time Flash ADC100, used to compare the output power supply voltage Vreg with 7 reference voltages to generate a 7-bit digital signal COMP<6:0>; (the 7-bit digital signal COMP<6:0> represents the 7-bit result of comparing Vreg with the 7 reference voltages Vref<6:0>).

[0040] Digital control logic 101 and an N-bit fractional exponent array 102 are connected to the load circuit 103 and the digital control logic 101, respectively; the load circuit 103 is grounded. The digital control logic 101 is used to control the number of PMOS transistors in the N-bit fractional exponent array 102 by detecting changes in the 7-bit digital signal COMP<6:0>, thereby adjusting the magnitude of the output power supply voltage Vreg.

[0041] This embodiment uses a continuous-time Flash ADC and asynchronous digital control logic, allowing information transmission between the two to be independent of external clock limitations. Therefore, the response time is determined only by the inherent delay of the ADC and the digital logic itself. This inherent delay is very small, thus eliminating the need for output capacitors.

[0042] like Figure 3 As shown, the 3-bit continuous-time Flash ADC100 includes seven continuous-time comparators and seven voltage regulators. Each voltage regulator is connected to one input terminal of the corresponding continuous-time comparator. The seven voltage regulators generate reference voltages Vref<6:0> for the corresponding continuous-time comparators, and each reference voltage Vref is input to a corresponding continuous-time comparator. The input voltage Vreg of the comparator is input to each of the continuous-time comparators. The seven continuous-time comparators compare the input voltage Vreg of the corresponding comparator with the reference voltages Vref<6:0> respectively and output the 7-bit digital signal COMP<6:0>.

[0043] like Figure 2 As shown, each of the continuous-time comparators includes: the drain of MOSFET MP1 connected to the comparator's reference voltage Vref; the gate of MOSFET MP1 connected to the gate of MOSFET MN1; the source of MOSFET MP1 connected to the drain of MOSFET MN1; the drain of MOSFET MP2 connected to the comparator's input voltage Vreg; the gate of MOSFET MP2 connected to the gate of MOSFET MN2; the source of MOSFET MP2 connected to the drain of MOSFET MN2; and the drain of MOSFET MP3 connected to the comparator's input voltage Vreg.

[0044] The gate of MOSFET MP3 is connected to the gate of MOSFET MN3. The source of MOSFET MP3 is connected to the drain of MOSFET MN3. The sources of MOSFETs MN1 to MN3 are interconnected and grounded. The midpoint of the gate connection between MOSFET MP1 and MOSFET MN1 is connected to the midpoint of the source connection between MOSFET MP1 and MOSFET MN1; the voltage at the midpoint of the gate connection between MOSFET MP1 and MOSFET MN1 is Vx1. The midpoint of the source connection between MOSFET MP1 and MOSFET MN1 is connected to the midpoint of the gate connection between MOSFET MP2 and MOSFET MN2. The midpoint of the source connection between MOSFET MP2 and MOSFET MN2 is connected to the midpoint of the gate connection between MOSFET MP3 and MOSFET MN3.

[0045] The voltage Vx2 is the midpoint of the gate connection between MOSFETs MP3 and MN3. This midpoint is also connected to the input terminal of buffer 10. The input terminal of inverter 20 is connected to the input voltage Vreg of the comparator. The input terminal of NOR gate 30 is connected to both the output terminal of buffer 10 and the output terminal of inverter 20. The output terminal of NOR gate 30 outputs the comparator's output voltage COMP.

[0046] In this embodiment, the size relationship of each MOS transistor in each continuous-time comparator is as follows:

[0047]

[0048]

[0049] In the formula, m and n are integers, W represents the width of the MOSFET, L represents the length of the MOSFET, subscripts N1 to N3 represent MOSFETs MN1 to MN3 respectively, and subscripts P1 to P3 represent MOSFETs MP1 to MP3.

[0050] The relationship between m and n is set according to the specific driving requirements. This comparator mainly demonstrates the comparison logic of the circuit.

[0051] In this embodiment, the size of the unit PMOS array increases in a geometric progression, with the common ratio q being a decimal.

[0052] In this fractional-exponential array N102, the sources of the PMOS transistors are all connected to the input power supply voltage Vin, the drains are all connected to the output power supply voltage Vreg, and the gates are connected to the signal EN_PMOS. <n-1:0>control.

[0053] Because a single PMOS array needs to handle the large ripple under light loads and the settling time under heavy loads, its load dynamic range is limited. A fractional-exponential PMOS array (where the PMOS array size varies by a fractional exponent) is characterized by small-sized PMOS transistors responding to load changes under light loads and large-sized PMOS transistors responding to load changes under heavy loads. Therefore, fractional-exponential PMOS arrays can ensure consistent ripple under different loads and achieve rapid stabilization under various load conditions.

[0054] Optionally, each of the continuous-time comparators functions as follows: in the circuit (referring to...) Figure 1 When the digital LDO structure circuit in the circuit is started, the input voltage Vreg of the comparator gradually increases from 0. When Vreg is small, MOS transistors MN2-MN3 and MP2-MP3 cannot work properly. At this time, the output voltage COMP is fixed at logic "0" by inverter 20 and NOR gate 30.

[0055] The circuit (referring to) Figure 1 After the digital LDO structure circuit in the circuit is started, the voltage Vx1 is stabilized under the action of the MOS transistors MN1 and MP1.

[0056] When the input voltage Vreg of the comparator is greater than the reference voltage Vref of the comparator, the driving capability of the MOS transistor MP2 is greater than that of the MOS transistor MN2, and the level of the voltage Vx2 is close to the input voltage Vreg of the comparator. After being amplified by the MOS transistors MP3 and MN3, the buffer 10 and the NOR gate 30, the output voltage COMP becomes logic "1".

[0057] When the input voltage Vreg of the comparator is less than the reference voltage Vref of the comparator, the driving capability of the MOS transistor MP2 is less than that of the MOS transistor MN2.

[0058] The voltage Vx1 is brought close to ground, and then amplified by the MOS transistor MP3 and the MOS transistor MN3, the buffer 10 and the NOR gate 30, so that the output voltage COMP becomes logic "0".

[0059] like Figure 4 As shown, the digital control logic 101 includes: an N-bit bidirectional shift register (BSR), three double-edge detection structures, referred to as the first double-edge detection structure 1, the second double-edge detection structure 2, and the third double-edge detection structure 3, two D flip-flops, referred to as the first D flip-flop 4 and the second D flip-flop 5, an OR gate 6, and a selector 7. The data input terminal D of the first D flip-flop 4 and its supplementary output terminal... Connection; the supplementary output terminal of the first D flip-flop 4 The first double-edge detection structure 1 is connected to one end, and the other end of the first double-edge detection structure 1 is connected to the input of the selector 7; the output of the selector 7 is connected to one input of the OR gate 6. The output of the third double-edge detection structure 3 is connected to the other input of the OR gate 6; the input of the third double-edge detection structure 3 is connected to a Reset signal.

[0060] The clock input terminal CLK of the first D flip-flop 4 is connected to the output terminal of the OR gate 6 and the N-bit bidirectional shift register BSR, respectively.

[0061] The data input terminal D of the second D flip-flop 5 and its supplementary output terminal Connection; supplementary output terminal of the second D flip-flop 5 One end of the second double-edge detection structure 2 is connected to the second double-edge detection structure 2, and the output of the second double-edge detection structure 2 is connected to the input of the selector 7. The clock input CLK of the second D flip-flop 5 is connected to the output of the OR gate 6 and the N-bit bidirectional shift register BSR.

[0062] In this embodiment, the gate signal EN_PMOS of the N-bit fractional exponent array <n-1:0>Controlled by the bidirectional shift register BSR, the right side of the bidirectional shift register BSR is padded with 0s when shifting left, and the left side is padded with 1s when shifting right. When the 7-bit digital signal COMP<6:0> is 7'h00 or 7'hef, the bidirectional shift register BSR shifts left by 20 bits or right by 20 bits; when the 7-bit digital signal COMP<6:0> is 7'h01 or 7'h3f, the bidirectional shift register BSR shifts left by 10 bits or right by 10 bits; when the 7-bit digital signal COMP<6:0> is 7'h03 or 7'h1f, the bidirectional shift register BSR shifts left by 5 bits or right by 5 bits; when COMP<6:0> is 7'h0e or 7'h0f, the bidirectional shift register BSR shifts left by 1 bit or right by 1 bit.

[0063] Please continue to refer to this. Figure 4 As shown, each of the aforementioned double-edge detection structures includes: a delay unit and an XOR gate; the supplementary output terminal of the first D flip-flop 4. The output signal is divided into two paths. One path is connected to one input of the XOR gate in the first double-edge detection structure 1. The other path passes through a delay unit and is connected to the other input of the XOR gate. The output of the XOR gate is connected to the selector 7. The supplementary output of the second D flip-flop 5... The output signal is divided into two paths: one path is connected to one input of the XOR gate in the second double-edge detection structure 2; the other path is connected to the other input of the XOR gate via a delay unit. The output of the XOR gate is connected to the selector 7. The Reset signal is divided into two paths: one path is connected to one input of the XOR gate in the third double-edge detection structure 3; the other path is connected to the other input of the XOR gate via a delay unit; the output of the XOR gate is connected to the OR gate 6.

[0064] In this embodiment, when the circuit is started, the third dual-edge detection structure 3 triggers the generation of an asynchronous clock by detecting the edge of the Reset signal.

[0065] After the circuit is started, at each clock edge, a delay signal τ1 is generated by the first D flip-flop 4, or a delay signal τ2 is generated by the second D flip-flop 5. The edge of the delay signal τ1 or τ2 is detected as the next clock signal.

[0066] When the load circuit 103 enters a steady state, a delay signal τ1 is selected to generate a low-frequency clock signal. When the load circuit 103 has not entered a steady state, a delay signal τ2 is selected to generate a high-frequency clock signal. That is, the delay signals τ1 and τ2 correspond to the low-frequency clock signal and the high-frequency clock signal, respectively, and the selection of the high / low frequency clock signal is determined by whether the load circuit 103 is in a steady state.

[0067] In this embodiment, the method for determining whether the load circuit has entered a steady state is as follows: determine whether the time for the 7-bit digital signal COMP<6:0> to be 7'h0e or 7'h0f exceeds M clock cycles (ensuring that the load circuit has been stable for a period of time). If yes, the load circuit 103 has entered a steady state; if no, the load circuit 103 has not entered a steady state. When the 7-bit digital signal COMP<6:0> is no longer 7'h0e or 7'h0f, the load circuit 103 has left the steady state.

[0068] In this embodiment, the digital control logic is controlled by an internally generated asynchronous clock, which can be made much faster than an external clock, thereby reducing the power supply voltage settling time. Furthermore, to reduce dynamic power consumption caused by steady-state clock fluctuations (referring to the power consumption of the digital LDO structure when the load circuit is stable), this embodiment uses a high-frequency asynchronous clock when responding to load changes, and a low-frequency asynchronous clock during steady-state operation.

[0069] In summary, this embodiment discloses a novel Digital LDO structure that improves the overall characteristics of a Digital LDO, simultaneously accelerating response speed, eliminating the need for output capacitors, increasing dynamic range, and reducing steady-state power consumption. The Digital LDO structure of this invention is well-suited for digital power supply applications in MCUs, SOCs, and the like.

[0070] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0072] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0073] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A digital LDO structure, characterized in that, include: A 3-bit continuous-time Flash ADC (100) is used to compare the output power supply voltage Vreg with 7 reference voltages to generate a 7-bit digital signal COMP<6:0>; Digital control logic (101). An N-bit decimal exponent array (102) is connected to the load circuit (103) and the digital control logic (101) respectively; the load circuit (103) is grounded; The digital control logic (101) is used to control the number of PMOS transistors in the N-bit fractional exponent array (102) by detecting the change of the 7-bit digital signal COMP<6:0>, thereby adjusting the magnitude of the output power supply voltage Vreg. The digital control logic (101) includes: an N-bit bidirectional shift register (BSR); The gate signal EN_PMOS of the N-bit decimal exponent array <n-1:0> Controlled by the bidirectional shift register BSR, when the bidirectional shift register BSR shifts to the left, the right side is filled with 0, and when the bidirectional shift register BSR shifts to the right, the left side is filled with 1; When the 7-bit digital signal COMP<6:0> is 7'h00 or 7'hef, the bidirectional shift register BSR shifts left by 20 bits or right by 20 bits; when the 7-bit digital signal COMP<6:0> is 7'h01 or 7'h3f, the bidirectional shift register BSR shifts left by 10 bits or right by 10 bits; when the 7-bit digital signal COMP<6:0> is 7'h03 or 7'h1f, the bidirectional shift register BSR shifts left by 5 bits or right by 5 bits; when COMP<6:0> is 7'h0e or 7'h0f, the bidirectional shift register BSR shifts left by 1 bit or right by 1 bit.

2. The digital LDO structure as described in claim 1, characterized in that, The 3-bit continuous-time Flash ADC (100) includes 7 continuous-time comparators and 7 voltage regulators; Each of the voltage regulators is connected to one input of the corresponding continuous-time comparator; Seven voltage regulators generate reference voltages Vref<6:0> corresponding to the continuous-time comparator, and each reference voltage Vref is input to the continuous-time comparator. The input voltage Vreg of the comparator is input to each of the continuous-time comparators; The seven continuous-time comparators compare the input voltage Vreg of the corresponding comparator with the reference voltage Vref<6:0> respectively, and then output the 7-bit digital signal COMP<6:0>.

3. The digital LDO structure as described in claim 2, characterized in that, Each of the continuous-time comparators includes: The drain of MOSFET MP1 is connected to the comparator's reference voltage Vref; The gate of the MOS transistor MP1 is connected to the gate of the MOS transistor MN1; The source of the MOS transistor MP1 is connected to the drain of the MOS transistor MN1; The drain of MOSFET MP2 is connected to the input voltage Vreg of the comparator; The gate of MOS transistor MP2 is connected to the gate of MOS transistor MN2; The source of the MOS transistor MP2 is connected to the drain of the MOS transistor MN2; The drain of MOSFET MP3 is connected to the input voltage Vreg of the comparator; The gate of the MOS transistor MP3 is connected to the gate of the MOS transistor MN3; The source of the MOS transistor MP3 is connected to the drain of the MOS transistor MN3; The sources of the MOS transistors MN1 to MN3 are interconnected and grounded; The midpoint of the gate connection between MOS transistor MP1 and MOS transistor MN1 is connected to the midpoint of the source connection between MOS transistor MP1 and MOS transistor MN1; the voltage Vx1 at the midpoint of the gate connection between MOS transistor MP1 and MOS transistor MN1; The midpoint of the connection between the source of MOS transistor MP1 and the drain of MOS transistor MN1 is connected to the midpoint of the connection between the gate of MOS transistor MP2 and MOS transistor MN2. The midpoint of the connection between the source of MOS transistor MP2 and the drain of MOS transistor MN2 is connected to the midpoint of the connection between the gate of MOS transistor MP3 and MOS transistor MN3. The voltage Vx2 at the midpoint of the gate connection between MOS transistor MP3 and MOS transistor MN3; The midpoint of the gate connection between the MOS transistor MP3 and the MOS transistor MN3 is also connected to the input terminal of the buffer (10); The input terminal of the inverter (20) is connected to the input voltage Vreg of the comparator; The input terminals of the NOR gate (30) are connected to the output terminals of the buffer (10) and the inverter (20), respectively; The output terminal of the NOR gate (30) outputs the comparator's output voltage COMP.

4. The digital LDO structure as described in claim 3, characterized in that, The dimensional relationships of the MOS transistors in each of the continuous-time comparators are as follows: In the formula, m and n are integers, W represents the width of the MOSFET, L represents the length of the MOSFET, subscripts N1 to N3 represent MOSFETs MN1 to MN3 respectively, and subscripts P1 to P3 represent MOSFETs MP1 to MP3 respectively.

5. The digital LDO structure as described in claim 4, characterized in that, The function of each continuous-time comparator is as follows: When the circuit is started, the input voltage Vreg of the comparator gradually increases from 0. The MOS transistors MN2~MN3 and MP2~MP3 cannot work normally. At this time, the output voltage COMP is fixed at logic "0" by the inverter (20) and the NOR gate (30). After the circuit is started, the voltage Vx1 stabilizes under the action of MOSFET MN1 and MOSFET MP1; When the input voltage Vreg of the comparator is greater than the reference voltage Vref of the comparator, the driving capability of the MOS transistor MP2 is greater than that of the MOS transistor MN2, and the voltage Vx2 is close to the input voltage Vreg of the comparator. After being amplified by the MOS transistors MP3 and MN3, the buffer (10) and the NOR gate (30), the output voltage COMP becomes logic "1". When the input voltage Vreg of the comparator is less than the reference voltage Vref of the comparator, the driving capability of the MOSFET MP2 is less than that of the MOSFET MN2. The voltage Vx1 is brought close to ground, and then amplified by the MOS transistor MP3, the MOS transistor MN3, the buffer (10), and the NOR gate (30), so that the output voltage COMP becomes logic "0".

6. The digital LDO structure as described in claim 5, characterized in that, The digital control logic (101) includes: The three double-edge detection structures are referred to as the first double-edge detection structure (1), the second double-edge detection structure (2), and the third double-edge detection structure (3), respectively. The two D flip-flops are referred to as the first D flip-flop (4) and the second D flip-flop (5). OR gate (6) and selector (7); The data input terminal D of the first D flip-flop (4) is connected to its supplementary output terminal; the supplementary output terminal of the first D flip-flop (4) is connected to one end of the first double-edge detection structure (1), and the other end of the first double-edge detection structure (1) is connected to the input terminal of the selector (7); the output terminal of the selector (7) is connected to one input terminal of the OR gate (6); The output of the third double-edge detection structure (3) is connected to the other input of the OR gate (6); the input of the third double-edge detection structure (3) is connected to the Reset signal; The clock input terminal CLK of the first D flip-flop (4) is connected to the output terminal of the OR gate (6) and the N-bit bidirectional shift register BSR, respectively. The data input terminal D of the second D flip-flop (5) is connected to its supplementary output terminal; the supplementary output terminal of the second D flip-flop (5) is connected to one end of the second double-edge detection structure (2), and the output terminal of the second double-edge detection structure (2) is connected to the input terminal of the selector (7); The clock input terminal CLK of the second D flip-flop (5) is connected to the output terminal of the OR gate (6) and the N-bit bidirectional shift register BSR, respectively.

7. The digital LDO structure as described in claim 6, characterized in that, Each of the aforementioned dual-edge detection structures includes: a delay unit and an XOR gate; The output signal of the supplementary output terminal of the first D flip-flop (4) is divided into two paths, one of which is connected to one input terminal of the XOR gate in the first double-edge detection structure (1); The other path passes through the delay unit and is connected to the other input of the XOR gate; The output of the XOR gate is connected to the selector (7); The output signal of the supplementary output terminal of the second D flip-flop (5) is divided into two paths; one path is connected to one input terminal of the XOR gate in the second double-edge detection structure (2); The other path passes through the delay unit and is connected to the other input of the XOR gate; The output of the XOR gate is connected to the selector (7); The Reset signal is divided into two paths. One path is connected to one input of the XOR gate in the third double-edge detection structure (3); the other path is connected to the other input of the XOR gate through the delay unit; and the output of the XOR gate is connected to the OR gate (6).

8. The digital LDO structure as described in claim 7, characterized in that, When the circuit starts, the third dual-edge detection structure (3) triggers the generation of an asynchronous clock by detecting the edge of the Reset signal; After the circuit is started, at each clock edge, a delay signal τ1 is generated by the first D flip-flop (4), or a delay signal τ2 is generated by the second D flip-flop (5), and the edge of the delay signal τ1 or τ2 is detected as the next clock signal; When the load circuit (103) enters a steady state, it selects a delay signal τ1 to generate a low-frequency clock signal. When the load circuit (103) has not entered a steady state, a delay signal τ2 is selected to generate a high-frequency clock signal.

9. The digital LDO structure as described in claim 8, characterized in that, If the time for the 7-bit digital signal COMP<6:0> to be 7'h0e or 7'h0f exceeds M clock cycles, the load circuit (103) enters a steady state; otherwise, the load circuit (103) does not enter a steady state. When the 7-bit digital signal COMP<6:0> is no longer 7'h0e or 7'h0f, the load circuit (103) leaves the steady state.

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