Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel includes a gate drive module, including a first gate drive unit and a second gate drive unit. The first gate drive unit is configured to receive an initial trigger signal and output a scan signal according to the initial trigger signal; a signal selection circuit is electrically connected to the first gate drive unit and the second gate drive unit, respectively. The signal selection circuit is configured to receive an inversion signal, a scan signal output by the first gate drive unit, and a low-level signal, and output a control signal to the second gate drive unit. The control signal is the scan signal or the low-level signal output by the first gate drive unit. The present application can realize different refresh frequency control for different partitions, achieving higher resolution and higher frequency display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of the display industry, users have increasingly demanded higher display quality. This is especially true for specific display scenarios such as virtual reality (VR), augmented reality (AR), immersive gaming, and racing sports, which place extremely high demands on display device refresh rates. Currently, problems such as motion blur and display smearing are quite serious at conventional display frequencies. High-resolution, high-frequency drivers can effectively reduce these issues, but increasing the display refresh rate directly doubles the amount of display data transmitted and leads to insufficient pixel charging. This, in turn, increases the number of data transmission interfaces, data transmission bandwidth, and display device power consumption, severely impacting the user's immersive experience with the display device. Summary of the Invention

[0003] The embodiments of the present application provide a display panel and a display device, which can realize different refresh frequency control for different partitions, thereby achieving higher resolution and higher frequency display.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0005] a gate driving module, comprising a first gate driving unit and a second gate driving unit, wherein the first gate driving unit is configured to receive an initial trigger signal and output a scanning signal according to the initial trigger signal;

[0006] a signal selection circuit, electrically connected to the first gate driving unit and the second gate driving unit, respectively, the signal selection circuit being configured to receive an inversion signal, a scanning signal output by the first gate driving unit, and a low-level signal, and output a control signal to the second gate driving unit, the control signal being the scanning signal output by the first gate driving unit or the low-level signal;

[0007] When the initial trigger signal is a trigger signal for the first frame, the control signal is a scanning signal output by the first gate drive unit based on the inversion signal; when the initial trigger signal is a trigger signal for the next frame of the first frame, the control signal is the low-level signal based on the inversion signal.

[0008] In some embodiments, the display panel further includes a first selection circuit electrically connected to the first gate driving unit, the first selection circuit being configured to receive the inversion signal, the initial trigger signal, and the low-level signal, and output a first control signal to the first gate driving unit, the first gate driving unit being configured to output a first scanning signal according to the first control signal, the first control signal being the initial trigger signal or the low-level signal;

[0009] The signal selection circuit is configured to receive the inversion signal, the first scanning signal output by the first gate driving unit, and the initial trigger signal, and output a second control signal to the second gate driving unit, wherein the second gate driving unit is configured to output a second scanning signal according to the second control signal, wherein the second control signal is the scanning signal output by the first gate driving unit or the initial trigger signal;

[0010] When the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate driving unit; when the first control signal is the low-level signal, the second control signal is the initial trigger signal.

[0011] In some embodiments, the display panel further includes a second selection circuit, the gate driving module further includes a third gate driving unit, and the second selection circuit is electrically connected to the second gate driving unit and the third gate driving unit respectively;

[0012] The second selection circuit is configured to receive the inversion signal, the low-level signal, and the second scanning signal output by the second gate driving unit, and output a third control signal to the third gate driving unit, where the third control signal is the low-level signal or the second scanning signal output by the second gate driving unit.

[0013] In some embodiments, when the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate driving unit, and the third control signal is the low-level signal; when the first control signal is the low-level signal, the second control signal is the initial trigger signal, and the third control signal is the second scanning signal output by the second gate driving unit; or,

[0014] When the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate driving unit, and the third control signal is the second scanning signal output by the second gate driving unit; when the first control signal is the low-level signal, the second control signal is the initial trigger signal, and the third control signal is the low-level signal.

[0015] In some embodiments, the display panel further includes a third selection circuit, the gate driving module further includes a fourth gate driving unit, and the third selection circuit is electrically connected to the first gate driving unit, the second gate driving unit, and the fourth gate driving unit respectively;

[0016] The third selection circuit is configured to receive the inversion signal, the scanning signal output by the second gate driving unit, and the scanning signal output by the first gate driving unit, and output a fourth control signal to the fourth gate driving unit, where the fourth control signal is the scanning signal output by the second gate driving unit or the scanning signal output by the first gate driving unit;

[0017] When the initial trigger signal is a trigger signal for the first frame, the control signal is a scanning signal output by the first gate drive unit, and the fourth control signal is a scanning signal output by the second gate drive unit; when the initial trigger signal is a trigger signal for the next frame of the first frame, the control signal is the low-level signal, and the fourth control signal is a scanning signal output by the first gate drive unit.

[0018] In some embodiments, the signal selection circuit includes a first control module, a second control module, and an inverting module, the second control module is connected to the inverting module, the first control module receives the scanning signal output by the first gate driving unit, the second control module receives the low-level signal, and the first control module and the inverting module are connected to the inversion signal;

[0019] When the inversion signal is at a high level, the signal selection circuit outputs the scanning signal output by the first gate driving unit; when the inversion signal is at a low level, the signal selection circuit outputs the low level signal.

[0020] In some embodiments, the first control module includes a first switching transistor, a gate of the first switching transistor is connected to the inversion signal, one of a source and a drain of the first switching transistor is connected to a scan signal output by the first gate driving unit, and the other of the source and the drain of the first switching transistor is connected to the second gate driving unit;

[0021] One end of the inverting module is connected to the inversion signal, and the other end of the inverting module is connected to the second control module;

[0022] The second control module includes a second switching transistor, the gate of the second switching transistor is connected to the other end of the inverting module, one of the source and drain of the second switching transistor is connected to the low-level signal, and the other of the source and drain of the second switching transistor is connected to the second gate driving unit.

[0023] In some embodiments, the display panel includes a first display area and a second display area, the first gate driving unit controls the pixel rows in the first display area to refresh, and the second gate driving unit controls the pixel rows in the second display area to refresh; the first gate driving unit and the second gate driving unit each include at least one gate driving circuit, and the driving mode of the at least one gate driving circuit is any one of unilateral driving, bilateral driving, and cross-bilateral driving.

[0024] In some embodiments, when the driving mode of the at least one gate drive circuit is bilateral drive or cross-bilateral drive, the signal selection circuit includes a first side selection circuit and a second side selection circuit, the first side selection circuit is respectively connected to the gate drive circuit on the first side of the first gate drive unit and the gate drive circuit on the first side of the second gate drive unit, and the second side selection circuit is respectively connected to the gate drive circuit on the second side of the first gate drive unit and the gate drive circuit on the second side of the second gate drive unit.

[0025] In a second aspect, the present application provides a display device, comprising a display panel as described in any one of the above.

[0026] The display panel and display device provided in the embodiments of the present application divide the display panel into areas where the first gate driving unit and the second gate driving unit respectively control refresh by setting a signal selection circuit. By controlling the display order of the partitions, different refresh frequency control can be achieved for the areas respectively controlled by the first gate driving unit and the second gate driving unit, thereby achieving higher resolution and higher frequency display. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0028] Figure 1 This is a schematic structural diagram of a display panel in one embodiment of the present application;

[0029] Figure 2 is a structural diagram of a display panel in another embodiment of the present application;

[0030] Figure 3 is a structural diagram of a display panel in another embodiment of the present application;

[0031] Figure 4 is a structural diagram of a display panel in another embodiment of the present application;

[0032] Figure 5 is a structural diagram of a display panel in another embodiment of the present application;

[0033] Figure 6 This is a schematic structural diagram of a signal selection circuit in another embodiment of the present application;

[0034] Figure 7 This is a structural diagram of a display panel driven by Interlace in the prior art;

[0035] Figure 8 1 is a schematic structural diagram of an Interlace-driven display panel in one embodiment of the present application;

[0036] Figure 9 This is a schematic structural diagram of a control circuit 1 in one embodiment of the present application;

[0037] Figure 10 This is a schematic diagram of the structure of the control circuit 2 in one embodiment of the present application;

[0038] Figure 11 This is a schematic diagram of the structure of the control circuit 3 in one embodiment of the present application;

[0039] Figure 12 This is a signal diagram of control circuits 1, 2, and 3 in one embodiment of the present application;

[0040] Figure 13 This is a signal diagram of control circuits 1, 2, and 3 in one embodiment of the present application;

[0041] Figure 14 This is a schematic diagram of display area refresh in one embodiment of the present application;

[0042] Figure 15 This is a schematic diagram of display area refresh in one embodiment of the present application;

[0043] Figure 16 This is a timing diagram of two adjacent frames in one embodiment of the present application.

[0044] Figure Number:

[0045] 100, gate drive module; 110, first gate drive unit; 120, second gate drive unit; 130, third gate drive unit; 140, fourth gate drive unit; 210, signal selection circuit; 211, first control module; 212, second control module; 213, inverting module; 220, first selection circuit; 230, second selection circuit; 240, third selection circuit. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0047] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0048] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0049] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0050] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0051] See also Figure 1 An embodiment of the present application provides a display panel, which includes a gate driving module 100 and a signal selection circuit 210. The scanning signal output by the gate driving module 100 is used to control the pixels of the display panel to refresh. The gate driving module 100 includes a first gate driving unit 110 and a second gate driving unit 120. The first gate driving unit 110 and the second gate driving unit 120 control some pixel rows of the display panel to refresh. Different pixel rows controlled by the same gate driving unit can be adjacent and continuous pixel rows or pixel rows arranged at intervals, and the number of pixel rows controlled by different gate driving units can be the same or different, which is not specifically limited in this embodiment.

[0052] The signal selection circuit 210 is electrically connected to the first gate driving unit 110 and the second gate driving unit 120 respectively, that is, the scanning signal output by the first gate driving unit 110 is input to the signal selection circuit 210, and the control signal output by the signal selection circuit 210 is output to the second gate driving unit 120.

[0053] The signal selection circuit 210 receives the inversion signal, the scanning signal output by the first gate driving unit 110, and the low-level signal, and outputs the scanning signal or the low-level signal output by the first gate driving unit 110 as a control signal to the second gate driving unit 120 according to the inversion signal. If the control signal is the scanning signal output by the first gate driving unit 110, the pixel row controlled by the second gate driving unit 120 will be refreshed. If the control signal is a low-level signal, the pixel row controlled by the second gate driving unit 120 will not be refreshed.

[0054] Since the inversion signal includes a high level and a low level, and the inversion signal alternates between adjacent frames, that is, when the inversion signal of the first frame is a high level, the inversion signal of the next frame of the first frame is switched to a low level, and the inversion signal of the next frame is switched to a high level again, and the cycle is repeated alternately.

[0055] The first gate driving unit 110 receives an initial trigger signal to start refreshing the screen. When the initial trigger signal is a trigger signal for the first frame of the screen, the control signal is a scanning signal output by the first gate driving unit 110. The pixel rows controlled by the first gate driving unit 110 and the second driving unit are refreshed and the data voltage corresponding to the first frame of the screen is written to realize the display of the first frame of the screen.

[0056] Based on the alternating changes of the above-mentioned inversion signal, when the initial trigger signal is the trigger signal of the next frame of the first frame, the control signal is a low-level signal, then the pixel row controlled by the first gate driving unit 110 will be refreshed, and the pixel row controlled by the second gate driving unit 120 will not be refreshed. Therefore, the pixel row controlled by the first gate driving unit 110 will be written with the data voltage corresponding to the second frame, and the pixel row controlled by the second gate driving unit 120 will still display the content displayed in the first frame.

[0057] In every two adjacent frames, the image of the pixel row controlled by the first gate driving unit 110 will be refreshed twice, and the image of the pixel row controlled by the second gate driving unit 120 will only be refreshed once. The refresh rate of the pixel row controlled by the first gate driving unit 110 is twice the refresh rate of the pixel row controlled by the second gate driving unit 120.

[0058] In this embodiment, the display panel is partitioned and controlled by adding a signal selection circuit 210. By controlling the partition display order, different refresh frequency controls can be achieved for different partitions, thereby achieving higher resolution and higher frequency display. Compared with the same resolution, the power consumption and transmission bandwidth requirements are reduced.

[0059] In one embodiment, different pixel rows controlled by the same gate driving unit are adjacent and continuous pixel rows, such as Figure 2 As shown, the display panel includes a first display area A and a second display area B. The sizes of the first display area A and the second display area B can be the same or different, which is not specifically limited in this embodiment. The first gate driving unit 110 controls the pixel rows in the first display area A to refresh, and the second gate driving unit 120 controls the pixel rows in the second display area B to refresh.

[0060] Through the control of the inversion signal in the signal selection circuit 210, when the initial trigger signal is the trigger signal of the first frame image, the control signal is the scanning signal output by the first gate driving unit 110, and the first display area A and the second display area B refresh and display the first frame image.

[0061] When the initial trigger signal is the trigger signal of the next frame of the first frame, the control signal is a low-level signal, then the first display area A is refreshed to the corresponding image of the next frame of the first frame, and the second display area B still maintains the corresponding image of the first frame, that is, the refresh rate of the first display area A is twice the refresh rate of the second display area B.

[0062] The first gate driving unit 110 and the second gate driving unit 120 each include at least one gate driving circuit. The driving mode of the at least one gate driving circuit is any one of unilateral driving, bilateral driving, and cross-bilateral driving.

[0063] In one embodiment, if unilateral driving is used, a signal selection circuit 210 is provided between the first gate driving unit 110 and the second gate driving unit 120. If bilateral driving or cross-bilateral driving is used, the gate driving circuits of the first gate driving unit 110 and the second gate driving unit 120 are distributed on the left and right sides of the display panel. The signal selection circuit 210 includes a first side selection circuit and a second side selection circuit. The first side selection circuit is respectively connected to the gate driving circuit on the first side of the first gate driving unit 110 and the gate driving circuit on the first side of the second gate driving unit 120, and the second side selection circuit is respectively connected to the gate driving circuit on the second side of the first gate driving unit 110 and the gate driving circuit on the second side of the second gate driving unit 120.

[0064] The first-side selection circuit and the second-side selection circuit have the same structure and signal connections. They synchronously control the left and right gate drive circuits to achieve the same refresh mode for pixel rows controlled by the same gate drive unit. Furthermore, if a selection circuit with the same function as signal selection circuit 210 is added, then the same two circuits would need to be provided to synchronously control the left and right gate drive circuits for bilateral or cross-bilateral driving.

[0065] In one embodiment, Figure 3 As shown, the display panel further includes a first selection circuit 220 electrically connected to the first gate driving unit 110. The first selection circuit 220 receives an inversion signal, an initial trigger signal, and a low-level signal, and outputs the initial trigger signal or the low-level signal as a first control signal to the first gate driving unit 110 according to the inversion signal. If the first control signal is the initial trigger signal, the pixel row controlled by the first gate driving unit 110 will be refreshed. If the first control signal is a low-level signal, the pixel row controlled by the first gate driving unit 110 will not be refreshed.

[0066] In addition, after the first selection circuit 220 is added, the signal connected to the signal selection circuit 210 needs to be adjusted. The signal selection circuit 210 receives the inversion signal, the first scanning signal output by the first gate driving unit 110, and the initial trigger signal, and outputs the first scanning signal or the initial trigger signal output by the first gate driving unit 110 as the second control signal to the second gate driving unit 120 based on the inversion signal. Regardless of whether the second control signal is the first scanning signal output by the first gate driving unit 110 or a low-level signal, the pixel rows controlled by the second gate driving unit 120 will be refreshed. The difference is that when the pixel rows controlled by the first gate driving unit 110 are not refreshed, the second gate driving unit 120 needs to be triggered by the initial trigger signal.

[0067] Therefore, the first control signal of the first frame is the initial trigger signal, the second control signal is the first scanning signal output by the first gate driving unit 110 , and the first display area A and the second display area B cooperate to display the first frame.

[0068] Due to the switching of the inversion signal, the first control signal is a low-level signal and the second control signal is an initial trigger signal. The first display area A is not refreshed and keeps displaying the corresponding image of the first frame. The second display area B refreshes and displays the corresponding image of the next frame of the first frame. The refresh rate of the second display area B is twice that of the first display area A, and the area with a faster refresh rate is adjusted relative to the above embodiment.

[0069] In one embodiment, Figure 4 As shown, the display panel further includes a second selection circuit 230, and the gate drive module 100 further includes a third gate drive unit 130. The third gate drive unit 130 is used to control the refresh of the pixel rows in the third display area C. The second selection circuit 230 is electrically connected to the second gate drive unit 120 and the third gate drive unit 130, respectively. The second selection circuit 230 receives an inversion signal, a low-level signal, and the second scanning signal output by the second gate drive unit 120, and outputs the low-level signal or the second scanning signal output by the second gate drive unit 120 as a third control signal to the third gate drive unit 130 based on the inversion signal. When the third control signal is a low-level signal, the pixel rows controlled by the third gate drive unit 130, i.e., the third display area C, are not refreshed. When the third control signal is the second scanning signal output by the second gate drive unit 120, the pixel rows controlled by the third gate drive unit 130, i.e., the third display area C, are refreshed.

[0070] In one embodiment, Figure 4As shown, in the first frame, the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate drive unit 110, and the third control signal is a low-level signal. That is, the first display area A and the second display area B are refreshed to the corresponding image of the first frame, and the third display area C maintains the corresponding image of the previous frame of the first frame. In the next frame of the first frame, the first control signal is a low-level signal, the second control signal is the initial trigger signal, and the third control signal is the second scanning signal output by the second gate drive unit 120. That is, the first display area A maintains the corresponding image of the first frame, and the second display area B and the third display area C are refreshed to the corresponding image of the next frame of the first frame. That is, in two adjacent frames, the image of the second display area B is refreshed twice, and the images of the first display area A and the third display area C are refreshed once.

[0071] It should be noted that when the first frame is the first frame, that is, the first frame does not have the previous frame, the third display area C remains in a dark state when the first frame is written. Since this embodiment is applied to a high-refresh display panel and the third display area C is only a partial display area of ​​the display panel, the human eye cannot perceive the dark state of the third display area C of the first frame.

[0072] In the first frame, the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate drive unit 110, and the third control signal is the second scanning signal output by the second gate drive unit 120. This means that the first display area A, the second display area B, and the third display area C are all refreshed to the corresponding images of the first frame. In the frame following the first frame, when the first control signal is a low-level signal, the second control signal is the initial trigger signal, and the third control signal is a low-level signal, this means that the first display area A and the third display area C maintain the corresponding images of the first frame, while the second display area B is refreshed to the corresponding image of the frame following the first frame. In other words, in two adjacent frames, the image of the second display area B is refreshed twice, while the images of the first display area A and the third display area C are refreshed once.

[0073] In one embodiment, Figure 5 As shown, the display panel also includes a third selection circuit 240, and the gate driving module 100 also includes a fourth gate driving unit 140. The fourth gate driving unit 140 is used to control the refresh of the pixel rows of the fourth display area D. The third selection circuit 240 is electrically connected to the first gate driving unit 110, the second gate driving unit 120, and the fourth gate driving unit 140, respectively.

[0074] The third selection circuit 240 receives the inversion signal, the scan signal output by the second gate driving unit 120, and the scan signal output by the first gate driving unit 110, and outputs the scan signal output by the second gate driving unit 120 and the scan signal output by the first gate driving unit 110 as a fourth control signal to the fourth gate driving unit 140 according to the inversion signal.

[0075] When the initial trigger signal is the trigger signal of the first frame image, the control signal is the scanning signal output by the first gate driving unit 110, and the fourth control signal is the scanning signal output by the second gate driving unit 120, that is, the first display area A, the second display area B and the fourth display area D are all refreshed to the corresponding images of the first frame image.

[0076] When the initial trigger signal is the trigger signal for the next frame after the first frame, the control signal is a low-level signal, and the fourth control signal is the scanning signal output by the first gate drive unit 110. This means that the first display area A and the fourth display area D are refreshed to the corresponding images of the next frame after the first frame, while the second display area B maintains the corresponding image of the first frame. In other words, in two adjacent frames, the images of the first display area A and the fourth display area D are refreshed twice, and the image of the second display area B is refreshed once.

[0077] In one embodiment, the signal selection circuit 210, the first selection circuit 220, the second selection circuit 230, and the third selection circuit 240 in the above-described embodiment can be configured as the same selection circuit. Each circuit uses an inversion signal as the output signal, and the inversion signal alternates between adjacent frames. Therefore, the output signal also alternates between the two input signals. The signal selection circuit 210, the first selection circuit 220, the second selection circuit 230, and the third selection circuit 240 differ only in the two input signals. This embodiment uses the signal selection circuit 210 as an example for description, and the other selection circuits are not further described.

[0078] like Figure 6 As shown, the signal selection circuit 210 includes a first control module 211, a second control module 212 and an inverting module 213. The second control module 212 and the inverting module 213 are connected. The first control module 211 receives the scanning signal output by the first gate driving unit 110, the second control module 212 receives the low-level signal, and the first control module 211 and the inverting module 213 are connected to the inversion signal.

[0079] The inversion signal switches alternately between adjacent frames. In the first frame, the inversion signal is high, and the signal selection circuit 210 outputs the scanning signal output by the first gate driving unit 110. In the frame following the first frame, the inversion signal switches to a low level, and the signal selection circuit 210 outputs a low-level signal. In the next frame, the inversion signal switches to a high level, and the signal selection circuit 210 outputs the scanning signal output by the first gate driving unit 110, and this alternating cycle continues.

[0080] In one embodiment, the first control module 211 includes a first switching transistor, the gate of which is connected to an inversion signal, one of the source and drain terminals of the first switching transistor is connected to a scan signal output by the first gate driver 110, and the other of the source and drain terminals of the first switching transistor is connected to the second gate driver 120. One terminal of an inversion module is connected to the inversion signal, and the other terminal of the inversion module is connected to the second control module 212. The second control module 212 includes a second switching transistor, the gate of which is connected to the other terminal of the inversion module, one of the source and drain terminals of the second switching transistor is connected to a low-level signal, and the other of the source and drain terminals of the second switching transistor is connected to the second gate driver 120.

[0081] When the inversion signal is high, the inversion module outputs a low level to the gate of the second switch transistor, the second switch transistor is turned off, and the first switch transistor is turned on. The control signal is the scan signal output by the first gate driving unit 110.

[0082] When the inversion signal is at a low level, the inversion module outputs a high level to the gate of the second switch transistor, the second switch transistor is turned on, the first switch transistor is turned off, and the control signal is a low level signal.

[0083] In this embodiment, a selection circuit is set to enable partition control of the display panel. By controlling the partition display order, different refresh frequency controls can be achieved for different partitions, achieving higher resolution and higher frequency display, and compared with the same resolution, power consumption and transmission bandwidth requirements are reduced.

[0084] like Figure 7 As shown, with 4N*M resolution & Interlace driving as an example, the existing driving scheme is that after the driving circuit GOA receives the trigger signal STV0, it is transmitted from the G_1 level to the G4N level in sequence, and the display area data is refreshed synchronously, and the display area A is not partitioned.

[0085] like Figure 8As shown, the present application provides a display panel, which divides the driving circuit into the following division schemes: G_1 to GN are the first part (the first part is equivalent to the first gate driving unit), which controls the display area A; G_N+1 to 2GN are the second part, which controls the display B; G_2N+1 to G3N are the third part (the second and third parts are equivalent to the second gate driving unit), which controls the display area C; G_3N+1 to G4N are the fourth part (the fourth part is equivalent to the third gate driving unit), which controls the display area D; In addition, in order to achieve normal driving, it is necessary to add selection control circuits 1, 2, and 3. Control circuit 1 is the first selection circuit in the above embodiment, control circuit 2 is the signal selection circuit in the above embodiment, and control circuit 1 is the second selection circuit in the above embodiment. Control circuits 1, 2, and 3 all include control module 1 and control module 2.

[0086] Figure 9 Schematic diagram of the structure of the control circuit 1, STV generation module 1: a total of 14T2C, NTA1's gate and source are short-circuited and connected to the FHL signal, NT1A's drain is connected to the QA1 node; NT9A's gate is connected to the QA1 node, the source is connected to STV0, and the drain is connected to the circuit output terminal STV1; NT8A's gate and source are short-circuited and connected to VGH, and the drain is connected to the PA1 node; NT5A's gate is connected to the PA1 node, the source is connected to the QA1 node, and the drain is connected to VGL; NT6A's gate is connected to FHL, the source is connected to the PA1 node, and the drain is connected to VGL; NT10A's gate is connected to the PA1 node, the source is connected to Connected to VGL, with its drain connected to output terminal STV1. NT1B's gate and source are shorted and connected to the PC1 signal, with its drain connected to the QB1 node. NT9B's gate is connected to the QB1 node, its source is connected to VGL, and its drain is connected to the circuit output terminal STV1. NT8B's gate and source are shorted and connected to VGH, with its drain connected to the PB1 node. NT5B's gate is connected to the PB1 node, its source is connected to the QB1 node, and its drain is connected to VGL. NT6B's gate is connected to PC1, its source is connected to the PB1 node, and its drain is connected to VGL. NT10B's gate is connected to the PB1 node, its source is connected to VGL, and its drain is connected to output terminal STV1. NT6C and NT8C form an inverter, inputting a potential opposite to FHL into PC2.

[0087] Figure 10This is a structural diagram of the control circuit 2, STV generation module 2: a total of 14T2C, NTA1's gate and source are short-circuited and connected to the FHL signal, NT1A's drain is connected to the QA2 node; NT9A's gate is connected to the QA2 node, its source is connected to Gate_N, and its drain is connected to the circuit output terminal STV2; NT8A's gate and source are short-circuited and connected to VGH, its drain is connected to the PA2 node; NT5A's gate is connected to the PA2 node, its source is connected to the QA2 node, and its drain is connected to VGL; NT6A's gate is connected to FHL, its source is connected to the PA2 node, and its drain is connected to VGL; NT10A's gate is connected to the PA2 node, its source is connected to Connected to VGL, with its drain connected to output terminal STV2. NTB1's gate and source are shorted and connected to the PC2 signal. NT1B's drain is connected to the QB2 node. NT9B's gate is connected to the QB2 node, its source is connected to STV0, and its drain is connected to the circuit output terminal STV2. NT8B's gate and source are shorted and connected to VGH, with its drain connected to the PB2 node. NT5B's gate is connected to the PB2 node, its source is connected to the QB2 node, and its drain is connected to VGL. NT6B's gate is connected to PC2, its source is connected to the PB2 node, and its drain is connected to VGL. NT10B's gate is connected to the PB2 node, its source is connected to VGL, and its drain is connected to output terminal STV2. NT6C and NT8C form an inverter, inputting a potential opposite to FHL into PC2.

[0088] Figure 11 This is a structural diagram of the control circuit 3, STV generation module 3: a total of 14T2C, NTA1's gate and source are short-circuited and connected to the FHL signal, NT1A's drain is connected to the QA3 node; NT9A's gate is connected to the QA3 node, its source is connected to VGL, and its drain is connected to the circuit output terminal STV3; NT8A's gate and source are short-circuited and connected to VGH, and its drain is connected to the PA3 node; NT5A's gate is connected to the PA3 node, its source is connected to the QA3 node, and its drain is connected to VGL; NT6A's gate is connected to FHL, its source is connected to the PA3 node, and its drain is connected to VGL; NT10A's gate is connected to the PA3 node, and its source is connected to VG L, drain connected to output terminal STV3; NTB1's gate and source are shorted and connected to the PC3 signal; NT1B's drain is connected to the QB3 node; NT9B's gate is connected to the QB3 node, its source is connected to Gate_3N, and its drain is connected to the circuit output terminal STV3; NT8B's gate and source are shorted and connected to VGH, and its drain is connected to the PB3 node; NT5B's gate is connected to the PB3 node, its source is connected to the QB3 node, and its drain is connected to VGL; NT6B's gate is connected to PC3, its source is connected to the PB3 node, and its drain is connected to VGL; NT10B's gate is connected to the PB3 node, its source is connected to VGL, and its drain is connected to output terminal STV3. NT6C and NT8C form an inverter, inputting a potential opposite to FHL into PC2.

[0089] like Figure 12 and Figure 13As shown, when the inversion signal is H, the control circuit 1L / R outputs STV0, the control circuit 2L / R outputs GateN, and the control circuit 3L / R outputs VGL. When the control signal is L, the control circuit 1L / R outputs VGL, the control circuit 2L / R outputs STV0, and the control circuit 3L / R outputs Gate3N.

[0090] like Figure 14 and Figure 15 As shown in the figure, by controlling the input signal of the control circuit, it is possible to refresh the A / B / C area in the N_1th frame, but not the D area; and refresh the B / C / D area in the Nth frame, but not the A area. Alternatively, it is possible to refresh the B / C / D area in the N_1th frame, but not the A area; and refresh the A / B / C area in the Nth frame, but not the D area. In both cases, the refresh frequency of the B / C area is twice that of the A / D area, thereby achieving the goal of high frequency of the partitions.

[0091] Figure 16 This is a timing diagram of two adjacent frames. This embodiment adds an inversion signal FHL, which controls the display driver by inverting and inputting signals and selectively outputting signals. STV0 provides the initial trigger signal for the IC. By selecting control circuit 1, the output signal of control circuit 1 outputs a signal in phase with STV0 when FHL is high, and outputs a low level when FHL is low. The control circuit 2 is selected to output a signal in phase with GN when FHL is high, and outputs a signal in phase with the second frame STV0 when FHL is low. The control circuit 3 is selected: when FHL is high, no output is performed, and when FHL is low, a signal in phase with the G3N level output is output.

[0092] The present application provides a display device, which includes the display panel as described in any one of the above embodiments.

[0093] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0094] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display panel, characterized in that: include: a gate driving module, comprising a first gate driving unit and a second gate driving unit, wherein the first gate driving unit is configured to receive an initial trigger signal and output a scanning signal according to the initial trigger signal; a signal selection circuit, electrically connected to the first gate driving unit and the second gate driving unit, respectively, the signal selection circuit being configured to receive an inversion signal, a scanning signal output by the first gate driving unit, and a low-level signal, and output a control signal to the second gate driving unit, the control signal being the scanning signal output by the first gate driving unit or the low-level signal; When the initial trigger signal is a trigger signal for the first frame, the control signal is a scanning signal output by the first gate drive unit based on the inversion signal; when the initial trigger signal is a trigger signal for the next frame of the first frame, the control signal is the low-level signal based on the inversion signal.

2. The display panel according to claim 1, wherein The display panel further includes a first selection circuit electrically connected to the first gate driving unit, the first selection circuit being configured to receive the inversion signal, the initial trigger signal, and the low-level signal, and output a first control signal to the first gate driving unit, the first gate driving unit being configured to output a first scanning signal according to the first control signal, wherein the first control signal is the initial trigger signal or the low-level signal; The signal selection circuit is configured to receive the inversion signal, the first scanning signal output by the first gate driving unit, and the initial trigger signal, and output a second control signal to the second gate driving unit, wherein the second gate driving unit is configured to output a second scanning signal according to the second control signal, wherein the second control signal is the scanning signal output by the first gate driving unit or the initial trigger signal; When the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate driving unit; when the first control signal is the low-level signal, the second control signal is the initial trigger signal.

3. The display panel according to claim 2, wherein: The display panel further includes a second selection circuit, the gate driving module further includes a third gate driving unit, and the second selection circuit is electrically connected to the second gate driving unit and the third gate driving unit respectively; The second selection circuit is configured to receive the inversion signal, the low-level signal, and the second scanning signal output by the second gate driving unit, and output a third control signal to the third gate driving unit, where the third control signal is the low-level signal or the second scanning signal output by the second gate driving unit.

4. The display panel according to claim 3, wherein: When the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate driving unit, and the third control signal is the low-level signal; when the first control signal is the low-level signal, the second control signal is the initial trigger signal, and the third control signal is the second scanning signal output by the second gate driving unit; or, When the first control signal is the initial trigger signal, the second control signal is the first scanning signal output by the first gate driving unit, and the third control signal is the second scanning signal output by the second gate driving unit; when the first control signal is the low-level signal, the second control signal is the initial trigger signal, and the third control signal is the low-level signal.

5. The display panel according to claim 1, wherein The display panel further includes a third selection circuit, the gate driving module further includes a fourth gate driving unit, and the third selection circuit is electrically connected to the first gate driving unit, the second gate driving unit, and the fourth gate driving unit respectively; The third selection circuit is configured to receive the inversion signal, the scanning signal output by the second gate driving unit, and the scanning signal output by the first gate driving unit, and output a fourth control signal to the fourth gate driving unit, where the fourth control signal is the scanning signal output by the second gate driving unit or the scanning signal output by the first gate driving unit; When the initial trigger signal is a trigger signal for the first frame, the control signal is a scanning signal output by the first gate drive unit, and the fourth control signal is a scanning signal output by the second gate drive unit; when the initial trigger signal is a trigger signal for the next frame of the first frame, the control signal is the low-level signal, and the fourth control signal is a scanning signal output by the first gate drive unit.

6. The display panel according to claim 1, wherein: The signal selection circuit includes a first control module, a second control module and an inverting module, the second control module is connected to the inverting module, the first control module receives the scanning signal output by the first gate driving unit, the second control module receives the low-level signal, and the first control module and the inverting module are connected to the inversion signal; When the inversion signal is at a high level, the signal selection circuit outputs the scanning signal output by the first gate driving unit; when the inversion signal is at a low level, the signal selection circuit outputs the low level signal.

7. The display panel according to claim 6, wherein: The first control module includes a first switching transistor, wherein the gate of the first switching transistor is connected to the inversion signal, one of the source and drain of the first switching transistor is connected to the scanning signal output by the first gate driving unit, and the other of the source and drain of the first switching transistor is connected to the second gate driving unit; One end of the inverting module is connected to the inversion signal, and the other end of the inverting module is connected to the second control module; The second control module includes a second switching transistor, the gate of the second switching transistor is connected to the other end of the inverting module, one of the source and drain of the second switching transistor is connected to the low-level signal, and the other of the source and drain of the second switching transistor is connected to the second gate driving unit.

8. The display panel according to claim 1, wherein: The display panel includes a first display area and a second display area, the first gate driving unit controls the pixel rows in the first display area to refresh, and the second gate driving unit controls the pixel rows in the second display area to refresh; the first gate driving unit and the second gate driving unit each include at least one gate driving circuit, and the driving mode of the at least one gate driving circuit is any one of unilateral driving, bilateral driving and cross-bilateral driving.

9. The display panel according to claim 8, wherein: When the driving mode of the at least one gate driving circuit is bilateral driving or cross-bilateral driving, the signal selection circuit includes a first side selection circuit and a second side selection circuit, the first side selection circuit is respectively connected to the gate driving circuit on the first side of the first gate driving unit and the gate driving circuit on the first side of the second gate driving unit, and the second side selection circuit is respectively connected to the gate driving circuit on the second side of the first gate driving unit and the gate driving circuit on the second side of the second gate driving unit.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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