Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel, wherein the array substrate includes a plurality of pixels, a plurality of scan line groups, and a plurality of data lines arranged in an array on a substrate, wherein each pixel includes at least three sub-pixels, and the three sub-pixels are arranged along a first direction. The scan line group includes three sub-scan lines extending along the first direction and spaced apart along a second direction. A scan line group is arranged between every two adjacent pixel rows. At least two sub-pixels in each pixel are connected to two different sub-scan lines in the same scan line group. A plurality of data lines are spaced apart along the first direction, and each data line extends along the second direction. A pixel column is arranged between two adjacent data lines. At least two sub-pixels in each pixel of the pixel column are connected to the same data line. This can greatly reduce the number of data lines, reduce the use of source driver chips, and reduce costs, thereby alleviating the problem of high cost of existing liquid crystal display panels.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] A liquid crystal display (LCD) panel typically includes scan lines extending along the row direction and data lines extending along the column direction. The scan lines and data lines are insulated and cross-linked to define multiple pixel areas. Each pixel area is provided with a sub-pixel. In the row direction, every three adjacent sub-pixels constitute a pixel. All sub-pixels in the same row are connected to the same scan line, and all sub-pixels in the same column are connected to the same data line. In this way, each pixel needs to correspond to three data lines, resulting in the LCD panel requiring more data lines, and thus requiring the installation of more source driver chips, which in turn leads to a higher cost of the LCD panel. Summary of the Invention

[0003] The present application provides an array substrate and a display panel to alleviate the technical problem of high cost of existing liquid crystal display panels.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] A plurality of pixels are arranged in an array on the substrate, wherein the plurality of pixels are arranged into pixel rows in a first direction and into pixel columns in a second direction, each pixel includes at least three sub-pixels, and the three sub-pixels are arranged along the first direction;

[0008] a plurality of scan line groups disposed on the substrate, each scan line group comprising three sub-scan lines extending along the first direction and spaced apart along the second direction, one scan line group being disposed between every two adjacent pixel rows, and at least two sub-pixels in each pixel being connected to two different sub-scan lines in the same scan line group; and

[0009] A plurality of data lines are arranged on the substrate and spaced apart along the first direction, and each of the data lines extends along the second direction. A pixel column is arranged between two adjacent data lines, and at least two sub-pixels in each pixel of the pixel column are connected to the same data line.

[0010] In the array substrate provided in the embodiment of the present application, the array substrate further includes a color resist layer, the color resist layer includes color resist blocks arranged corresponding to the sub-pixels, and the color resist blocks corresponding to the three sub-pixels of the same pixel have different colors;

[0011] The colors of the color resist blocks corresponding to the sub-pixels connected to the same sub-scan line are the same, and the colors of the color resist blocks corresponding to the sub-pixels of the three sub-scan lines connected to the same scan line group are different. The three sub-scan lines include a first sub-scan line, a second sub-scan line, and a third sub-scan line arranged in sequence along the second direction. The colors of the color resist blocks corresponding to the sub-pixels connected to at most one of the two first sub-scan lines, the two second sub-scan lines, and the two third sub-scan lines in two adjacent scan line groups are the same.

[0012] In the array substrate provided in the embodiment of the present application, in each pixel located between two adjacent data lines, two adjacent sub-pixels are respectively connected to the two adjacent data lines.

[0013] In the array substrate provided in the embodiment of the present application, in two adjacent pixels located between two adjacent data lines, in the second direction, the two adjacent sub-pixels are respectively connected to the two adjacent data lines.

[0014] In the array substrate provided by the embodiment of the present application, the sub-pixels with the same color of the corresponding color-resistance blocks in the same pixel row are connected to the same sub-scanning line.

[0015] In the array substrate provided in the embodiment of the present application, each of the scan line groups is connected to less than all of the sub-pixels in two adjacent rows of pixels.

[0016] In the array substrate provided in the embodiment of the present application, in each pixel located between two adjacent scan line groups, two adjacent sub-pixels are respectively connected to the two adjacent scan line groups.

[0017] In the array substrate provided in the embodiment of the present application, in the first direction, two adjacent sub-pixels are respectively connected to two adjacent data lines, and two adjacent sub-pixels are respectively connected to two adjacent scan line groups; in the second direction, two adjacent sub-pixels are respectively connected to two adjacent data lines, and two adjacent sub-pixels are respectively connected to two adjacent scan line groups.

[0018] In the array substrate provided in an embodiment of the present application, the scan line group includes a first scan line group and a second scan line group arranged alternately, and the color of the color resist block corresponding to the sub-pixel connected to at most one of the two first sub-scan lines, the two second sub-scan lines and the two third sub-scan lines in the first scan line group and the second scan line group is the same.

[0019] In the array substrate provided in the embodiment of the present application, each of the pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the color resist blocks corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively a red color resist block R, a green color resist block G, and a blue color resist block B. In the second direction, the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the first scan line group are one of RGB, RBG, GRB, GBR, BGR, and BRG, and the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the second scan line group are one of RGB, RBG, GRB, GBR, BGR, and BRG.

[0020] In the array substrate provided in the embodiment of the present application, in the second direction, the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the first scan line group are RGB, and the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the second scan line group are RBG.

[0021] In the array substrate provided in the embodiment of the present application, the size of each sub-pixel in the first direction is smaller than the size in the second direction.

[0022] In the array substrate provided in the embodiment of the present application, each of the sub-pixels includes at least one transistor and a pixel electrode connected to the transistor, the pixel electrode extends along the second direction, the transistor includes a gate, a source and a drain, the gate of the transistor is connected to the corresponding sub-scan line, the source of the transistor is connected to the corresponding data line, and the drain of the transistor is connected to the corresponding pixel electrode; the transistor of each sub-pixel is located between the pixel electrode of the sub-pixel and the sub-scan line corresponding to the sub-pixel.

[0023] In the array substrate provided in an embodiment of the present application, the three transistors connected to the same scan line group are connected to the same data line. The array substrate also includes a first connecting line connected between the data line and the source, and the sources of the three transistors are connected to the same first connecting line.

[0024] In the array substrate provided in an embodiment of the present application, the pixel electrode includes a frame electrode and a first branch electrode and a second branch electrode, both ends of which are connected to the frame electrode. The frame electrode is provided with a notch at one end corresponding to the transistor, and the first branch electrode is located on a side of the second branch electrode away from the notch, and the first branch electrode and the second branch electrode are axially symmetrical with each other.

[0025] In the array substrate provided in the embodiment of the present application, the gate is integrally arranged with the corresponding sub-scan line, and in the three sub-scan lines of the same scan line group, the gates corresponding to two adjacent sub-scan lines at least partially overlap in the first direction.

[0026] In the array substrate provided in the embodiment of the present application, the array substrate further includes a first common electrode line extending along the second direction, and the first common electrode line is located between two adjacent sub-pixels in each pixel.

[0027] An embodiment of the present application further provides a display panel, which includes an array substrate and an opposing substrate arranged opposite to each other, wherein the array substrate includes:

[0028] substrate;

[0029] A plurality of pixels are arranged in an array on the substrate, wherein the plurality of pixels are arranged into pixel rows in a first direction and into pixel columns in a second direction, each pixel includes at least three sub-pixels, and the three sub-pixels are arranged along the first direction;

[0030] a plurality of scan line groups disposed on the substrate, each scan line group comprising three sub-scan lines extending along the first direction and spaced apart along the second direction, one scan line group being disposed between every two adjacent pixel rows, and at least two sub-pixels in each pixel being connected to two different sub-scan lines in the same scan line group; and

[0031] a plurality of data lines disposed on the substrate and spaced apart along the first direction, each of the data lines extending along the second direction, a pixel column disposed between two adjacent data lines, and at least two sub-pixels in each pixel of the pixel column being connected to the same data line;

[0032] The counter substrate includes a color resist layer, the color resist layer includes color resist blocks arranged corresponding to the sub-pixels, and the color resist blocks corresponding to the three sub-pixels of the same pixel have different colors;

[0033] The colors of the color resist blocks corresponding to the sub-pixels connected to the same sub-scan line are the same, and the colors of the color resist blocks corresponding to the sub-pixels of the three sub-scan lines connected to the same scan line group are different. The three sub-scan lines include a first sub-scan line, a second sub-scan line, and a third sub-scan line arranged in sequence along the second direction. The colors of the color resist blocks corresponding to the sub-pixels connected to at most one of the two first sub-scan lines, the two second sub-scan lines, and the two third sub-scan lines in two adjacent scan line groups are the same.

[0034] The beneficial effects of the present application are as follows: in the array substrate and display panel provided by the present application, the array substrate includes a plurality of pixels, a plurality of scan line groups and a plurality of data lines arranged in an array on a substrate, each pixel includes at least three sub-pixels, the three sub-pixels are arranged along the first direction, the scan line group includes three sub-scan lines extending along the first direction and spaced apart along the second direction, a scan line group is arranged between every two adjacent pixel rows, at least two sub-pixels in each pixel are connected to two different sub-scan lines in the same scan line group, a plurality of data lines are spaced apart along the first direction, and each data line extends along the second direction, a pixel column is arranged between two adjacent data lines, and at least two sub-pixels in each pixel in the pixel column are connected to the same data line, so that the number of data lines can be greatly reduced, the use of source driver chips can be reduced, and the cost can be reduced, thereby solving the technical problem of high cost of existing liquid crystal display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A schematic diagram of a pixel arrangement of an existing triple-gate liquid crystal display panel.

[0037] Figure 2 A schematic diagram of a pixel arrangement of an array substrate provided in an embodiment of the present application.

[0038] Figure 3 A schematic diagram of the detailed structure of a pixel provided in an embodiment of the present application.

[0039] Figure 4 Another pixel arrangement diagram of the array substrate provided in the embodiment of the present application

[0040] Figure 5 This is a schematic diagram of another pixel arrangement of the array substrate provided in an embodiment of the present application.

[0041] Figure 6 This is a schematic diagram of another pixel arrangement of the array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0043] In view of the problem that the existing liquid crystal display panel requires more data lines, and thus requires more source driver chips, which leads to higher costs for the liquid crystal display panel, the embodiment of the present application provides an array substrate to solve the problem of higher costs. Figure 2 , Figure 2 A schematic diagram of a pixel arrangement of an array substrate provided in an embodiment of the present application is shown. The array substrate 100 includes a substrate 10 and a plurality of pixels 20 , a plurality of scan line groups 40 , and a plurality of data lines 30 disposed on the substrate 10 .

[0044] A plurality of pixels 20 are arranged in an array on the substrate 10. The pixels 20 are arranged in pixel rows in a first direction X and in pixel columns in a second direction Y. Each pixel 20 includes at least three sub-pixels 21, and the three sub-pixels 21 are arranged along the first direction X. A plurality of scan line groups 40 are provided on the substrate 10. Each scan line group 40 includes three sub-scan lines extending along the first direction X and spaced apart along the second direction Y. A scan line group 40 is provided between every two adjacent pixel rows. At least two sub-pixels 21 in each pixel 20 are connected to two different sub-scan lines in the same scan line group 40. A plurality of data lines 30 are provided on the substrate 10 and are spaced apart along the first direction X. Each of the data lines 30 extends along the second direction Y. A pixel column is provided between two adjacent data lines 30. At least two sub-pixels 21 in each pixel 20 of the pixel column are connected to the same data line 30. This can greatly reduce the number of data lines, the use of source driver chips, and the cost, thereby solving the technical problem of high cost of existing liquid crystal display panels.

[0045] It should be noted that although there are technologies in the related art that can reduce the number of data lines and thus reduce the source driver chips to reduce costs, such as the tri-gate liquid crystal display panel, the tri-gate liquid crystal display panel in the related art has the problem of horizontal text aliasing. Regarding the horizontal text aliasing phenomenon, the inventors of this application found in their research that the liquid crystal display panel is composed of square pixels, and the characteristics of the square cause it to have raised stepped "burrs" on the edges of inclined lines, such as strokes such as "strokes" and "horizontal strokes". Common sub-pixels that can display the same color are generally arranged vertically. In the related art, there is an algorithm optimization "cleartype" for vertically arranged pixels to improve the text aliasing phenomenon, but the tri-gate liquid crystal display panel in the related art can display sub-pixels of the same color but are arranged horizontally. Specifically, referring to Figure 1 , Figure 1A schematic diagram of a pixel arrangement of a conventional triple-gate liquid crystal display panel is shown. The triple-gate liquid crystal display panel includes data lines DL spaced apart along a first direction X and extending along a second direction Y, and scan lines GL spaced apart along the second direction Y and extending along the first direction X. The triple-gate liquid crystal display panel has a plurality of pixels arranged in rows and columns, and is driven by three adjacent scan lines. Each pixel is composed of three sub-pixels arranged vertically. The multiple sub-pixels are arranged within the area defined by the scan lines GL and the data lines DL. The three sub-pixels correspond to color blocks of different colors, thereby causing the three sub-pixels to display different colors. For example, the three sub-pixels correspond to a red color block, a green color block, and a blue color block, respectively. The color blocks corresponding to the sub-pixels in any row are the same color, so that the sub-pixels capable of displaying the same color are arranged horizontally in a row.

[0046] However, the related art lacks algorithm optimization for horizontal pixel alignment, resulting in significant horizontal text aliasing on existing triple-gate LCD panels. Improving text aliasing is particularly important for products like notebooks (NBs) that primarily display text and are viewed from close distances.

[0047] To this end, the array substrate 100 provided in the present application reduces the number of data lines, reduces the use of source driver chips, and reduces costs. At the same time, by arranging the three sub-pixels 21 of each pixel 20 along the first direction X, and the sub-pixels 21 in the same column can display the same color, thereby improving the horizontal text aliasing phenomenon of the existing three-gate liquid crystal display panel.

[0048] In addition, for three-gate liquid crystal display panels, the "light and heavy load difference" caused by the pre-charging process of pixel driving is common. For the three-gate architecture, since the sub-pixels displaying the same color are placed horizontally, each data line DL will drive the sub-pixels displaying different colors, so the light and heavy load difference will further lead to the generation of mixed color color deviation. Moreover, the three-gate architecture has a short charging time and a low charging rate, which will further aggravate the risk of color deviation. After in-depth research, the inventors of the present application found that one way to solve the mixed color deviation is to make the number of light and heavy load pixels between the color barriers in a picture the same, so as to uniformize the color deviation, thereby visually eliminating the mixed color deviation, which requires increasing the driving sequence of sub-pixels displaying different colors. However, the conventional horizontal three-gate architecture has a single sub-pixel driving sequence, and it is difficult to achieve drive diversification.

[0049] To this end, the present application provides an array substrate and a display panel to solve the above problems.

[0050] Please refer to Figure 2 and Figure 3 , Figure 2 A schematic diagram of a pixel arrangement of an array substrate provided in an embodiment of the present application is shown. Figure 3 The detailed structural diagram of a pixel provided in the embodiment of the present application. The array substrate 100 includes a substrate 10 and a plurality of pixels 20 arrayed on the substrate 10. The plurality of pixels 20 are arranged in a first direction X into pixel rows (eg Figure 2 The first pixel row PH1, the second pixel row PH2, the third pixel row PH3 and the fourth pixel row PH4 are schematically shown, but the present application is not limited thereto. Figure 2 For illustration only, the array substrate 100 of the present application may also include more or fewer pixel rows), and the pixels are arranged in columns in the second direction Y (similarly, Figure 2 Three pixel columns are schematically shown, but the present application is not limited thereto. The array substrate 100 of the present application may also include more or fewer pixel columns, and the number of pixel columns may also be greater than the number of pixel rows).

[0051] Each pixel 20 includes at least three sub-pixels 21. For example, each pixel 20 includes a first sub-pixel 21-1, a second sub-pixel 21-2, and a third sub-pixel 21-3. The array substrate 100 also includes a color resist layer, which includes color resist blocks corresponding to the sub-pixels. The color resist blocks corresponding to the three sub-pixels 21 of the same pixel are different in color. For example, the color resist blocks corresponding to the first sub-pixel 21-1, the second sub-pixel 21-2, and the third sub-pixel 21-3 are red, green, and blue, respectively. The size of each sub-pixel 21 in the first direction X is smaller than the size in the second direction Y. The three sub-pixels 21 are arranged along the first direction X. In the first direction X, the color resist blocks corresponding to two adjacent sub-pixels 21 have different colors, while in the second direction Y, the color resist blocks corresponding to two adjacent sub-pixels 21 have the same color. The first direction X and the second direction Y are different. For example, the first direction X is a row direction, the second direction Y is a column direction, and the first direction X is perpendicular to the second direction Y.

[0052] The array substrate 100 further includes a plurality of data lines 30 and a plurality of scan line groups 40 disposed on the substrate 10. The plurality of data lines 30 are spaced apart along the first direction X and extend along the second direction Y. A pixel column is disposed between two adjacent data lines 30. In each pixel 20 of the pixel column, at least two sub-pixels 21 are connected to the same data line 30. Optionally, in other embodiments, three sub-pixels 21 in each pixel 20 of the pixel column are connected to the same data line 30.

[0053] A plurality of scan line groups 40 are arranged at intervals along the second direction Y and extend along the first direction X. Each scan line group 40 is arranged between two adjacent pixel rows, with one scan line group 40 arranged between each two adjacent pixel rows. At least two sub-pixels 21 in each pixel 20 are connected to two different sub-scan lines in the same scan line group 40. The data lines 30 and the scan line groups 40 are insulated and intersected to define a plurality of pixel regions, and each pixel 20 is located in a corresponding pixel region.

[0054] Optionally, the sub-pixels 21 with the same color of the corresponding color resist blocks in the same pixel row are connected to the same sub-scanning line. The voltage polarities on two adjacent data lines 30 are different. For example, the voltage polarity on one of the two adjacent data lines 30 is positive, and the voltage polarity on the other data line 30 is negative. For ease of description, in the following description, the two adjacent data lines 30 are defined as a first data line 30-1 and a second data line 30-2.

[0055] In each pixel 20 located between two adjacent data lines 30, two adjacent sub-pixels 21 are respectively connected to the two adjacent data lines 30. For example, in the same pixel 20, a first sub-pixel 21-1 and a second sub-pixel 21-2 are adjacent to each other, the first sub-pixel 21-1 is connected to the second data line 30-2, and the second sub-pixel 21-2 is connected to the first data line 30-1. In addition, in two adjacent pixels 20 located between two adjacent data lines 30, two adjacent sub-pixels 21 are respectively connected to the two adjacent data lines 30 in the second direction Y. For example, in the second direction Y, of two adjacent first sub-pixels 21-1, one first sub-pixel 21-1 is connected to the first data line 30-1, and the other first sub-pixel 21-1 is connected to the second data line 30-2.

[0056] In this way, each data line 30 is connected to the three sub-pixels 21 corresponding to different color blocks in two adjacent pixels 20 in the same pixel column, and two adjacent data lines 30 are respectively connected to the three sub-pixels 21 corresponding to different color blocks in two adjacent pixels 20 in the same pixel column. For example, in the same pixel column, two adjacent pixels 20 include two first sub-pixels 21-1, two second sub-pixels 21-2, and two third sub-pixels 21-3, wherein the second sub-pixel 21-2 in the first pixel 20 and the first sub-pixel 21-1 and the third sub-pixel 21-3 in the second pixel 20 are connected to the first data line 30-1, and the first sub-pixel 21-1 and the third sub-pixel 21-3 in the first pixel 20 and the second sub-pixel 21-2 in the second pixel 20 are connected to the second data line 30-2.

[0057] Each scan line group 40 includes three sub-scan lines, all of which extend along the first direction X and are spaced apart along the second direction Y. The color resist blocks corresponding to the sub-pixels 21 connected to the same sub-scan line have the same color, and the color resist blocks corresponding to the sub-pixels 21 connected to the three sub-scan lines in the same scan line group 40 have different colors. The three sub-scan lines include a first sub-scan line 41, a second sub-scan line 42, and a third sub-scan line 43, which are sequentially arranged along the second direction. The sub-pixels 21 connected to at least two of the sub-scan lines in each scan line group 40 have color resist blocks that are different in color from the sub-pixels 21 connected to the corresponding sub-scan lines in the adjacent scan line group 40. That is, the color resist blocks corresponding to the sub-pixels 21 connected to at most one of the two first sub-scan lines 41, the two second sub-scan lines 42, and the two third sub-scan lines 43 in two adjacent scan line groups 40 have the same color.

[0058] In this embodiment, by arranging the sub-pixels 21 corresponding to the same color group block vertically, the algorithm in the related art can be used to optimize and improve the horizontal text aliasing phenomenon of the three-gate liquid crystal display panel, thereby solving the technical problem of the horizontal text aliasing phenomenon in the existing three-gate liquid crystal display panel. At the same time, at most one of the two first sub-scan lines 41, the two second sub-scan lines 42, and the two third sub-scan lines 43 in two adjacent scan line groups 40 is connected to the sub-pixels 21 corresponding to the same color. In this way, by adjusting the connection sequence of the sub-scan lines in the scan line group 40 and the sub-pixels 21 of different luminous colors, it is possible to achieve diversified driving sequences, so that when displaying a picture, the number of light-loaded and heavy-loaded pixels is the same, so that the color deviation is uniform, thereby visually eliminating color mixing and color deviation.

[0059] The connection relationship between the scanning line group 40 and the sub-pixel 21 will be described in detail below.

[0060] The scan line group 40 includes a first scan line group 40-1 and a second scan line group 40-2 arranged alternately. The colors of the color resist blocks corresponding to the sub-pixels 21 connected to at least two of the sub-scan lines in the first scan line group 40-1 are different from the colors of the color resist blocks corresponding to the sub-pixels 21 connected to the corresponding sub-scan lines in the second scan line group 40-2. That is, the colors of the color resist blocks corresponding to the sub-pixels 21 connected to at most one of the two first sub-scan lines 41 and 41', the two second sub-scan lines 42 and 42', and the two third sub-scan lines 43 and 43' in the first scan line group 40-1 and the second scan line group 40-2 are the same. For the convenience of description, in the following description, the three sub-scan lines of the first scan line group 40-1 are defined as the first sub-scan line 41, the second sub-scan line 42 and the third sub-scan line 43, and the three sub-scan lines of the second scan line group 40-2 are defined as the first sub-scan line 41', the second sub-scan line 42' and the third sub-scan line 43'. The first sub-scan line 41, the second sub-scan line 42, the third sub-scan line 43, the first sub-scan line 41', the second sub-scan line 42' and the third sub-scan line 43' are arranged in sequence in the second direction Y.

[0061] Optionally, each of the sub-scan lines in each of the scan line groups 40 is connected to the sub-pixels 21 corresponding to the same color group block in the same pixel row. For example, the first sub-scan line 41 is connected to the first sub-pixel 21-1 in the same pixel row, the second sub-scan line 42 is connected to the second sub-pixel 21-2 in the same pixel row, and the third sub-scan line 43 is connected to the third sub-pixel 21-3 in the same pixel row.

[0062] Each scan line group 40 is connected to less than all of the sub-pixels 21 in two adjacent pixel rows. For example, the first scan line group 40-1 is located between two adjacent pixel rows. In the first scan line group 40-1, the first sub-scan line 41 is connected to the first sub-pixel 21-1 in the first pixel row PH1, the second sub-scan line 42 is connected to the second sub-pixel 21-2 in the second pixel row PH2, and the third sub-scan line 43 is connected to the third sub-pixel 21-3 in the first pixel row PH1.

[0063] In each of the pixels 20 located between two adjacent scan line groups 40, the two adjacent sub-pixels 21 are respectively connected to the two adjacent scan line groups 40. For example, in the pixel 20 located between the first scan line group 40-1 and the second scan line group 40-2, in the adjacent first sub-pixel 21-1 and second sub-pixel 21-2, the first sub-pixel 21-1 is connected to the sub-scan line in the second scan line group 40-2, and the second sub-pixel 21-2 is connected to the sub-scan line in the first scan line group 40-1.

[0064] That is, in the first direction X, the two adjacent sub-pixels 21 are respectively connected to the two adjacent data lines 30, and the two adjacent sub-pixels 21 are respectively connected to the two adjacent scan line groups 40; in the second direction, the two adjacent sub-pixels 21 are respectively connected to the two adjacent data lines 30, and the two adjacent sub-pixels 21 are respectively connected to the two adjacent scan line groups 40.

[0065] Optionally, in the second direction Y, the color resist blocks corresponding to the sub-pixels 21 respectively connected to the three sub-scan lines in the first scan line group 40-1 are RGB, and the color resist blocks corresponding to the sub-pixels 21 respectively connected to the three sub-scan lines in the second scan line group 40-2 are RBG. Specifically, the first sub-scan line 41 in the first scan line group 40-1 is connected to the first sub-pixel 21-1 in the first pixel row PH1, the second sub-scan line 42 in the first scan line group 40-1 is connected to the second sub-pixel 21-2 in the second pixel row PH2, and the third sub-scan line 43 in the first scan line group 40-1 is connected to the third sub-pixel 21-3 in the first pixel row PH1. Then, the color resist blocks corresponding to the sub-pixels 21 respectively connected to the three sub-scan lines in the first scan line group 40-1 are RGB; correspondingly Specifically, the first sub-scan line 41' in the second scan line group 40-2 is connected to the first sub-pixel 21-1 in the second pixel row PH2, the second sub-scan line 42' in the second scan line group 40-2 is connected to the third sub-pixel 21-3 in the second pixel row PH2, and the third sub-scan line 43' in the second scan line group 40-2 is connected to the second sub-pixel 21-2 in the third pixel row PH3. Then, the color resist blocks corresponding to the sub-pixels 21 respectively connected to the three sub-scan lines in the second scan line group 40-2 are RBG.

[0066] Reference Figure 3Each sub-pixel 21 includes at least one transistor 1 and a pixel electrode 2 connected to the transistor 1. The pixel electrode 2 is located on a side of the transistor 1 away from the substrate 10 and extends along the second direction Y. The transistor 1 includes a gate 11, a source 12, and a drain 13. The gate 11 of the transistor 1 is connected to the corresponding sub-scan line, the source 12 of the transistor 1 is connected to the corresponding data line 30, and the drain 13 of the transistor 1 is connected to the corresponding pixel electrode 2. The transistor 1 of each sub-pixel 21 is located between the pixel electrode 2 of the sub-pixel 21 and the sub-scan line corresponding to the sub-pixel 21.

[0067] The three transistors 1 connected to the same scan line group 40 are connected to the same data line 30. The array substrate 100 also includes a first connecting trace 60 connected between the data line 30 and the source 12. The sources 12 of the three transistors 1 are connected to the same first connecting trace 60 to improve the aperture ratio. To further improve the aperture ratio, the pixel electrode 2 includes a frame electrode 22 and a first branch electrode 23 and a second branch electrode 24, both ends of which are connected to the frame electrode 22. The frame electrode 22 is provided with a notch at one end corresponding to the transistor 1. The first branch electrode 23 is located on the side of the second branch electrode 24 away from the notch. The first branch electrode 23 and the second branch electrode 24 are axially symmetrical with each other. The gate 11 is integrally provided with the corresponding sub-scan line. Among the three sub-scan lines in the same scan line group 40, the gates 11 corresponding to two adjacent sub-scan lines at least partially overlap in the first direction X.

[0068] The array substrate 100 further includes a first common electrode line 50 extending along the second direction Y. The first common electrode line 50 is located between two adjacent sub-pixels 21 in each pixel 20 .

[0069] The following will specifically explain the principle by which the present application can improve color cast.

[0070] Continue to refer to Figure 2 In the embodiment of the present application, a two-color mixed yellow image is used as an example to illustrate that to display a yellow image, the first sub-pixel 21-1 and the second sub-pixel 21-2 need to be turned on, and all the third sub-pixels 21-3 need not be turned on. The sub-scanning lines are sequentially turned on and scanned in a direction away from the second direction Y. Figure 2 The sub-scanning lines shown are used as an example, but the present application is not limited thereto. The array substrate of the present application may further include more or fewer scan line groups 40. Figure 2In the example, the sub-scan line connected to the third sub-pixel 21-3 in the fourth pixel row PH4 starts scanning first, and the third sub-pixel 21-3 in the fourth pixel row PH4 does not light up. Then, the sub-scan line connected to the first sub-pixel 21-1 in the fourth pixel row PH4 starts scanning, and the first sub-pixel 21-1 in the fourth pixel row PH4 is overloaded. Then, the sub-scan line connected to the third sub-pixel 21-3 in the third pixel row PH3 starts scanning, and the third sub-pixel 21-3 in the third pixel row PH3 does not light up. Next, the sub-scan line connected to the second sub-pixel 21-2 in the fourth pixel row PH4 starts scanning, and the second sub-pixel 21-2 in the fourth pixel row PH4 is heavily loaded. Next, the sub-scan line connected to the first sub-pixel 21-1 in the third pixel row PH3 starts scanning, and the first sub-pixel 21-1 in the third pixel row PH3 is lightly loaded. Next, the sub-scan line connected to the second sub-pixel 21-2 in the third pixel row PH3 starts scanning, and the second sub-pixel 21-2 in the third pixel row PH3 is lightly loaded. Then, the sub-scan line connected to the third sub-pixel 21-3 in the second pixel row PH2 starts scanning, and the third sub-pixel 21-3 in the second pixel row PH2 is not lit; then, the sub-scan line connected to the first sub-pixel 21-1 in the second pixel row PH2 starts scanning, and the first sub-pixel 21-1 in the second pixel row PH2 is overloaded; then, the sub-scan line connected to the third sub-pixel 21-3 in the first pixel row PH1 starts scanning, and the third sub-pixel 21-3 in the first pixel row PH1 is not lit; then, the sub-scan line connected to the second sub-pixel 21-2 in the second pixel row PH2 starts scanning, and the second sub-pixel 21-2 in the second pixel row PH2 is overloaded; then, the sub-scan line connected to the first sub-pixel 21-1 in the first pixel row PH1 starts scanning, and the first sub-pixel 21-1 in the first pixel row PH1 is lightly loaded; then, the sub-scan line connected to the second sub-pixel 21-2 in the first pixel row PH1 starts scanning, and the second sub-pixel 21-2 in the first pixel row PH1 is lightly loaded. That is, in Figure 2 In the display image shown, the first sub-pixel 21-1 and the second sub-pixel 21-2 of the first pixel row PH1 and the third pixel row PH3 are lightly loaded, and the first sub-pixel 21-1 and the second sub-pixel 21-2 of the second pixel row PH2 and the fourth pixel row PH4 are heavily loaded. In this way, the number of lightly loaded and heavily loaded pixels 20 is the same, making the color deviation uniform, thereby visually eliminating mixed color deviation.

[0071] In one embodiment, referring to Figures 2 to 4 , Figure 4This is a schematic diagram of another pixel arrangement for an array substrate provided in an embodiment of the present application. Unlike the above embodiment, in the second direction Y, the color resist blocks corresponding to the sub-pixels 21 connected to the three sub-scan lines in the first scan line group 40-1 are GBRs, while the color resist blocks corresponding to the sub-pixels 21 connected to the three sub-scan lines in the second scan line group 40-2 are GRBs. This also achieves an equal number of lightly loaded and heavily loaded pixels 20, uniformizing color shift and visually eliminating color mixing and color cast. For other explanations, please refer to the above embodiment and will not be repeated here.

[0072] In one embodiment, referring to Figures 2 to 5 , Figure 5 This is another pixel arrangement diagram for an array substrate provided in an embodiment of the present application. Unlike the above embodiment, the arrangement order of each pixel 20 in the first direction X is the second sub-pixel 21-2, the third sub-pixel 21-3, and the first sub-pixel 21-1. In the second direction Y, the color resist blocks corresponding to the sub-pixels 21 connected to the three sub-scan lines in the first scan line group 40-1 are GBRs, and the color resist blocks corresponding to the sub-pixels 21 connected to the three sub-scan lines in the second scan line group 40-2 are GRBs. This also achieves an equal number of lightly loaded and heavily loaded pixels 20, uniformizing color shift and visually eliminating color mixing and color cast. For other explanations, please refer to the above embodiment and will not be repeated here.

[0073] In one embodiment, referring to Figures 2 to 6 , Figure 6 This is another pixel arrangement diagram for an array substrate provided in an embodiment of the present application. Unlike the above embodiment, the arrangement order of each pixel 20 in the first direction X is the third sub-pixel 21-3, the second sub-pixel 21-2, and the first sub-pixel 21-1. In the second direction Y, the color resist blocks corresponding to the sub-pixels 21 connected to the three sub-scan lines in the first scan line group 40-1 are BGR, while the color resist blocks corresponding to the sub-pixels 21 connected to the three sub-scan lines in the second scan line group 40-2 are BRG. This also achieves the same number of lightly loaded and heavily loaded pixels 20, uniformizing color shift and visually eliminating color mixing and color cast. For other explanations, please refer to the above embodiment and will not be repeated here.

[0074] In other embodiments, in the second direction Y, the color resist blocks corresponding to the sub-pixels 21 to which the three sub-scan lines in the first scan line group 40-1 are respectively connected are one of RGB, RBG, GRB, GBR, BGR, and BRG, and the color resist blocks corresponding to the sub-pixels 21 to which the three sub-scan lines in the second scan line group 40-2 are respectively connected are one of RGB, RBG, GRB, GBR, BGR, and BRG.

[0075] Based on the same inventive concept, an embodiment of the present application further provides a display panel, the display panel comprising an array substrate and an opposing substrate arranged opposite to each other, the array substrate comprising:

[0076] substrate;

[0077] A plurality of pixels are arranged in an array on the substrate, wherein the plurality of pixels are arranged into pixel rows in a first direction and into pixel columns in a second direction, each pixel includes at least three sub-pixels, and the three sub-pixels are arranged along the first direction;

[0078] a plurality of scan line groups disposed on the substrate, each scan line group comprising three sub-scan lines extending along the first direction and spaced apart along the second direction, one scan line group being disposed between every two adjacent pixel rows, and at least two sub-pixels in each pixel being connected to two different sub-scan lines in the same scan line group;

[0079] a plurality of data lines disposed on the substrate and spaced apart along the first direction, each of the data lines extending along the second direction, a pixel column disposed between two adjacent data lines, and at least two sub-pixels in each pixel of the pixel column being connected to the same data line;

[0080] The opposing substrate includes a color resist layer, which includes color resist blocks arranged corresponding to the sub-pixels, and the colors of the color resist blocks corresponding to the three sub-pixels of the same pixel are different; the colors of the color resist blocks corresponding to the sub-pixels connected to the same sub-scan line are the same, and the colors of the color resist blocks corresponding to the sub-pixels of the three sub-scan lines connected to the same scan line group are different, the three sub-scan lines include a first sub-scan line, a second sub-scan line, and a third sub-scan line arranged in sequence along the second direction, and the color resist blocks corresponding to the sub-pixels connected to at most one of the two first sub-scan lines, the two second sub-scan lines, and the two third sub-scan lines in two adjacent scan line groups are the same in color.

[0081] According to the above embodiments, it can be seen that:

[0082] The present application provides an array substrate and a display panel, wherein the array substrate includes a plurality of pixels arranged in an array on a substrate and a scan line group arranged between two adjacent rows of pixels, each pixel including at least three sub-pixels, the three sub-pixels being arranged along a first direction, the colors of the color blocks corresponding to two adjacent sub-pixels being different in the first direction, and the colors of the color blocks corresponding to two adjacent sub-pixels being the same in the second direction, the scan line group including three sub-scan lines, each of the sub-scan lines connecting the sub-pixels corresponding to the same color color block, and each scan line group connecting the sub-pixels corresponding to three different color color blocks, thereby forming a vertical arrangement of sub-pixels corresponding to the same color color block. The invention relates to a three-gate liquid crystal display panel arranged in a horizontal direction, so that the algorithm in the related art can be used to optimize and improve the horizontal text aliasing phenomenon of the three-gate liquid crystal display panel, thereby solving the technical problem of the horizontal text aliasing phenomenon in the existing three-gate liquid crystal display panel; at the same time, the color of the sub-pixels connected to at most one of the two first scan lines, the two second scan lines, and the two third scan lines in two adjacent scan line groups is the same. In this way, by adjusting the connection sequence of the scan lines in the scan line group and the sub-pixels of different luminous colors, the driving sequence can be diversified, so that when displaying a picture, the number of light-loaded and heavy-loaded pixels is the same, the color deviation is uniform, and the mixed color deviation is visually eliminated.

[0083] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0084] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of pixels are arranged in an array on the substrate, wherein the plurality of pixels are arranged into pixel rows in a first direction and into pixel columns in a second direction, each pixel includes at least three sub-pixels, and the three sub-pixels are arranged along the first direction; a plurality of scan line groups disposed on the substrate, each scan line group comprising three sub-scan lines extending along the first direction and spaced apart along the second direction, one scan line group being disposed between every two adjacent pixel rows, and at least two sub-pixels in each pixel being connected to two different sub-scan lines in the same scan line group; as well as A plurality of data lines are arranged on the substrate and spaced apart along the first direction, and each data line extends along the second direction. A pixel column is arranged between two adjacent data lines, and at least two sub-pixels in each pixel of the pixel column are connected to the same data line; in each pixel located between two adjacent data lines, two adjacent sub-pixels along the first direction are respectively connected to two adjacent data lines, and in each adjacent two pixels located between two adjacent data lines, two adjacent sub-pixels along the second direction are respectively connected to two adjacent data lines.

2. The array substrate according to claim 1, wherein: The array substrate further includes a color resist layer, the color resist layer including color resist blocks arranged corresponding to the sub-pixels, and the color resist blocks corresponding to the three sub-pixels of the same pixel have different colors; The colors of the color resist blocks corresponding to the sub-pixels connected to the same sub-scan line are the same, and the colors of the color resist blocks corresponding to the sub-pixels of the three sub-scan lines connected to the same scan line group are different. The three sub-scan lines include a first sub-scan line, a second sub-scan line, and a third sub-scan line arranged in sequence along the second direction. The colors of the color resist blocks corresponding to the sub-pixels connected to at most one of the two first sub-scan lines, the two second sub-scan lines, and the two third sub-scan lines in two adjacent scan line groups are the same.

3. The array substrate according to claim 2, wherein: The sub-pixels with the same color of the corresponding color-resistance blocks in the same pixel row are connected to the same sub-scanning line.

4. The array substrate according to claim 3, wherein: Each of the scan line groups is connected to less than all of the sub-pixels in two adjacent pixel rows.

5. The array substrate according to claim 4, wherein: In each of the pixels located between two adjacent scan line groups, two adjacent sub-pixels are respectively connected to the two adjacent scan line groups.

6. The array substrate according to claim 2, wherein: In the first direction, two adjacent sub-pixels are connected to two adjacent scan line groups respectively; in the second direction, two adjacent sub-pixels are connected to two adjacent scan line groups respectively.

7. The array substrate according to any one of claims 2 to 6, characterized in that: The scan line group includes a first scan line group and a second scan line group arranged alternately, and the color of the color block corresponding to the sub-pixel connected to at most one of the two first sub-scan lines, the two second sub-scan lines and the two third sub-scan lines in the first scan line group and the second scan line group is the same.

8. The array substrate according to claim 7, wherein: Each of the pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The color resist blocks corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively a red color resist block R, a green color resist block G, and a blue color resist block B. In the second direction, the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the first scan line group are one of RGB, RBG, GRB, GBR, BGR, and BRG, and the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the second scan line group are one of RGB, RBG, GRB, GBR, BGR, and BRG.

9. The array substrate according to claim 8, wherein: In the second direction, the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the first scan line group are RGB, and the color resist blocks corresponding to the sub-pixels respectively connected to the three sub-scan lines in the second scan line group are RBG.

10. The array substrate according to claim 8, wherein: The size of each sub-pixel in the first direction is smaller than the size of each sub-pixel in the second direction.

11. The array substrate according to claim 10, wherein: Each of the sub-pixels includes at least one transistor and a pixel electrode connected to the transistor, the pixel electrode extends along the second direction, the transistor includes a gate, a source and a drain, the gate of the transistor is connected to the corresponding sub-scan line, the source of the transistor is connected to the corresponding data line, and the drain of the transistor is connected to the corresponding pixel electrode; the transistor of each sub-pixel is located between the pixel electrode of the sub-pixel and the sub-scan line corresponding to the sub-pixel.

12. The array substrate according to claim 11, wherein: The three transistors connected to the same scan line group are connected to the same data line. The array substrate further includes a first connecting wire connected between the data line and the source. The sources of the three transistors are connected to the same first connecting wire.

13. The array substrate according to claim 11, wherein: The pixel electrode includes a frame electrode and a first branch electrode and a second branch electrode, both ends of which are connected to the frame electrode. The frame electrode is provided with a notch at one end corresponding to the transistor. The first branch electrode is located on a side of the second branch electrode away from the notch. The first branch electrode and the second branch electrode are axially symmetrical with each other.

14. The array substrate according to claim 11, wherein: The gate electrode is integrally provided with the corresponding sub-scanning line. Among the three sub-scanning lines in the same scan line group, the gate electrodes corresponding to two adjacent sub-scanning lines at least partially overlap in the first direction.

15. The array substrate according to claim 11, wherein: The array substrate further includes a first common electrode line extending along the second direction, wherein the first common electrode line is located between two adjacent sub-pixels in each pixel.

16. A display panel, characterized in that: The array substrate comprises an array substrate and an opposing substrate which are arranged opposite to each other, and the array substrate comprises: substrate; A plurality of pixels are arranged in an array on the substrate, wherein the plurality of pixels are arranged into pixel rows in a first direction and into pixel columns in a second direction, each pixel includes at least three sub-pixels, and the three sub-pixels are arranged along the first direction; a plurality of scan line groups disposed on the substrate, each scan line group comprising three sub-scan lines extending along the first direction and spaced apart along the second direction, one scan line group being disposed between every two adjacent pixel rows, and at least two sub-pixels in each pixel being connected to two different sub-scan lines in the same scan line group; and a plurality of data lines disposed on the substrate and spaced apart along the first direction, each of the data lines extending along the second direction, a pixel column disposed between two adjacent data lines, and at least two sub-pixels in each pixel of the pixel column being connected to the same data line; The counter substrate includes a color resist layer, the color resist layer includes color resist blocks arranged corresponding to the sub-pixels, and the color resist blocks corresponding to the three sub-pixels of the same pixel have different colors; The colors of the color resist blocks corresponding to the sub-pixels connected to the same sub-scan line are the same, and the colors of the color resist blocks corresponding to the sub-pixels of the three sub-scan lines connected to the same scan line group are different. The three sub-scan lines include a first sub-scan line, a second sub-scan line, and a third sub-scan line arranged in sequence along the second direction. The colors of the color resist blocks corresponding to the sub-pixels connected to at most one of the two first sub-scan lines, the two second sub-scan lines, and the two third sub-scan lines in two adjacent scan line groups are the same; in each pixel located between two adjacent data lines, the two adjacent sub-pixels along the first direction are respectively connected to the two adjacent data lines, and in the two adjacent pixels located between the two adjacent data lines, the two adjacent sub-pixels along the second direction are respectively connected to the two adjacent data lines.

Images