Shared storage system, device and method for invalidating cache data

Abstract

The embodiment of the present application provides a shared storage system and a method for invalidating cached data, the shared storage system comprises a memory manager, a plurality of processors and a shared memory; a first processor in the plurality of processors is used for sending a request to the memory manager, the request indicating rewriting data in a first address, the first address being an address in the shared memory; the memory manager is used for sending a first signal to a second processor in the plurality of processors based on the request, the first signal indicating invalidating first data saved by the second processor, the first data being a copy of data in a first address space in the shared memory, and the first address being located in the first address space; and the second processor is used for invalidating the first data based on the first signal, so that the shared storage system and the method for invalidating cached data provided by the embodiment of the present application can improve the performance of the shared storage system.

Description

Technical Field

[0001] This application relates to the field of computer security, and more particularly to a shared storage system, apparatus, and method for invalidating cached data. Background Technology

[0002] In shared memory technology, multiple processors share the same memory space. This means that any processor connected to the shared memory system can request access to any address. Because these processors share the memory space, multiple processors requesting access to the same address will receive a copy of the same data. However, if one processor modifies this copy, the copies stored by other processors at that address will differ from the modified copies, resulting in a cache coherence problem.

[0003] To ensure cache consistency among multiple copies of the same data at the same address and among the original data, traditional techniques typically use the Snoopy protocol. When one processor writes to a specific address, the memory manager, responsible for maintaining the shared address space, sends a message to other processors holding the data at that address, notifying them that the data at that address is invalid. However, with increasing processor speeds, processors process more and more data per clock cycle, resulting in copies of the same large amount of data (i.e., data at multiple addresses) being cached across multiple processors. In the Snoopy protocol, when one processor rewrites this large amount of data, the memory manager needs to send the multiple addresses corresponding to that large amount of data to the other processors. Assuming this large amount of data resides in ten addresses, the memory manager needs to send all ten addresses to the other processors one by one, severely consuming bandwidth in the shared memory system's communication network. Furthermore, sending multiple addresses one by one to other processors means that other processors may only receive the information indicating that their stored copy is invalid after several clock cycles, resulting in latency issues. In summary, in shared storage systems where multiple processors store copies of the same large amount of data, the challenge lies in efficiently invalidating the copies stored by other processors when one processor rewrites that copy, thereby improving the performance of the shared storage system. Summary of the Invention

[0004] The shared memory system, apparatus, and method for invalidating cached data provided in this application can efficiently invalidate copies cached by other processors when one processor modifies data at a certain address. To achieve the above objective, this application adopts the following technical solution.

[0005] In a first aspect, embodiments of this application provide a shared storage system, comprising: a memory manager, multiple processors, and shared memory; a first processor among the multiple processors is configured to send a request to the memory manager, the request indicating that data at a first address be rewritten, the first address being an address in the shared memory; the memory manager, based on the request, sends a first signal to a second processor among the multiple processors, the first signal indicating that first data stored by the second processor is invalidated, the first data being a copy of data in a first address space in the shared memory, the first address being located in the first address space; the second processor, based on the first signal, invalidates the first data.

[0006] The memory manager can be a dedicated processor or integrated into the central processing unit along with the kernel. For example, a memory manager can be... Figure 1 The memory manager shown is 21, 22, 23, or 24. Multiple processors are, for example... Figure 1 The processors shown are 01, 02, 03, or 04. Shared memory is, for example,... Figure 1 The memory modules shown are 11, 12, 13, or 14. The memory manager is used to manage the coupled memory modules. For example... Figure 1 In the diagram, memory manager 21 manages memory 11, memory manager 22 manages memory 12, memory manager 23 manages memory 13, and memory manager 24 manages memory 14. Here, "management" can refer to recording which processors store data in each address space, and invalidating data in that address space stored in other processors before one processor rewrites data in that address space.

[0007] There can be multiple first addresses, all of which reside within a first address space. This first address space can be pre-allocated by the memory manager and may also be referred to as a declared address space region. In one alternative implementation, the size of the first address space can be dynamically adjusted. For example, the memory manager can first reclaim all address spaces allocated to each processor, readjust the size of the shared memory address space, and broadcast the adjusted address space size and its corresponding identifier to each processor.

[0008] The first signal can be implemented in several ways. In a first possible implementation, the first signal can include an address range of a first address space; in a second possible implementation, the first address space can be mapped to a preset identifier, and the first signal can include the preset identifier.

[0009] The first address space includes multiple addresses. In conventional technology, a memory manager used to manage shared memory needs to send multiple signals to the first processor when it needs to invalidate a copy of data in the first address space stored in the first processor; each signal indicates the invalidation of data in one address. This severely consumes the bandwidth of the interconnect network. The memory manager provided in this application can invalidate the copy of data in the first address space stored in the first processor by sending a first signal to the first processor. Compared with conventional technology, this can free up interconnect network bandwidth, improve bandwidth utilization, and thus improve the performance of the shared storage system.

[0010] Based on the first aspect, in one possible implementation, the second processor is specifically used to: decompose the first address space into multiple address ranges based on the first signal and the size of a preset data segment, to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment; and invalidate the multiple data segments.

[0011] Optionally, the second processor can invalidate multiple data segments simultaneously or in a time-sharing manner.

[0012] In traditional storage protocols (such as the Snoopy protocol), data is stored in the cache in the form of data segments, such as cache lines. The processor operates on the data in units of data segments, such as modifying the data's state, storing data, or retrieving data. One data segment typically corresponds to one address range. The first address space includes multiple address ranges, meaning it stores multiple data segments. After receiving information indicating that a copy of data in the first address space should be invalidated, the second processor decomposes the first address space into multiple address ranges to obtain multiple data segments, and then invalidates these multiple data segments. This allows the use of traditional storage protocols (such as the Snoopy protocol) to invalidate multiple data segments, thereby invalidating the first address space. This eliminates the need for additional hardware improvements in the second processor to invalidate data in the first address space, saving design costs.

[0013] Based on the first aspect, in one possible implementation, the second processor is specifically configured to: modify the state of at least some data segments to an invalid state when the state of some data segments among the plurality of data segments is either a shared state or an exclusive state.

[0014] Based on the first aspect, in one possible implementation, the second processor includes a cache manager and an invalidation manager; the invalidation manager generates multiple invalid signals based on the multiple address ranges, with one invalid signal corresponding to one address range; and transmits the multiple invalid signals to the cache manager in a time-division manner; the cache manager invalidates the multiple data segments based on the multiple invalid signals.

[0015] Both the cache manager and the invalidation manager can be implemented by hardware circuitry. Operations on cached data in the second processor (e.g., retrieving data from memory for caching, writing data to memory, and modifying the state of cached data) are all implemented by the cache manager. The cache manager operates on data segments. In conventional technology, without an invalidation manager, the memory manager provides multiple invalid signals corresponding to multiple address ranges to the cache manager in a time-sharing manner, severely consuming bandwidth. In this embodiment, by setting an invalidation manager, the invalidation manager replaces the memory manager, generating multiple invalid signals and providing them to the cache manager. Since the invalidation manager and the cache manager are located in the same processor, compared with existing technologies, it does not require consuming bandwidth of the processor's off-chip interconnect network and has a high transmission rate. Furthermore, the cache manager's structure does not need to be changed; it can still receive signals according to traditional storage protocols and operate on data segments, saving design costs.

[0016] Based on the first aspect, in one possible implementation, the invalidation manager is further configured to decompose the first address space into multiple address ranges based on the first signal and the size of a preset data segment.

[0017] Based on the first aspect, in one possible implementation, the cache manager is further configured to send multiple responses to the invalidation manager for the plurality of signals, wherein one response corresponds to a data segment, and a first response among the plurality of responses indicates that a first data segment among the plurality of data segments has not been overwritten; the invalidation manager is further configured to transmit a second signal to the memory manager based on the plurality of responses, the second signal indicating that invalidation of the first data has been completed.

[0018] In conventional technologies, without an invalidation manager, the cache manager needs to transmit multiple response signals to the memory manager, consuming bandwidth of the communication network. In this embodiment, when the invalidation manager receives multiple responses, and all responses indicate that the corresponding data segment has not been overwritten, it transmits a signal to the memory manager indicating that the invalidation of the first data is complete. That is, the invalidation manager only needs to transmit one signal to the memory manager. Compared with the prior art of transmitting multiple response signals, this reduces the bandwidth of the communication network and improves bandwidth utilization.

[0019] Based on the first aspect, in one possible implementation, the second response among the plurality of responses includes a second data segment among the plurality of data segments; the invalidation manager is further configured to write the second data segment back to the corresponding address range in the shared memory.

[0020] In this embodiment, the data in the second data segment is overwritten, and the cache manager needs to write the overwritten data back to memory. The cache manager transmits a second response carrying the second data segment to the invalidation manager, thereby the invalidation manager writes the second data segment back to memory.

[0021] Based on the first aspect, in one possible implementation, a first invalid signal among the plurality of invalid signals indicates that the first data segment is invalid; and the cache manager is specifically configured to: write the first data segment back to the shared memory before receiving the first invalid signal; and in response to a third signal sent by the memory manager, the third signal indicating that the first data segment has been stored, send the first response to the invalidation manager.

[0022] Based on the first aspect, in one possible implementation, the memory manager is further configured to: send a fourth signal to the first processor, the fourth signal indicating that the first processor is permitted to rewrite the data at the first address.

[0023] Based on the first aspect, in one possible implementation, a third processor among the plurality of processors is configured to send a request to the memory manager, the request indicating that data at a second address, the second address being an address in the shared memory, be rewritten; the memory manager, based on the request, sends a fifth signal to the cache manager, the fifth signal indicating that second data stored by the cache manager is invalidated, the second data being a copy of the data at the second address; the cache controller, based on the fifth signal, sends a second response to the memory manager, the second response indicating whether the second data has been modified or not.

[0024] In this implementation, if the second address is outside the range of the first address, or if the amount of data corresponding to the second address is exactly one data segment, the memory manager can directly transmit a signal indicating an invalid copy of the data in the second address to the cache controller. In this case, it is not necessary to decompose the address range through the invalidation manager, which can improve the signal transmission speed and the working efficiency of the shared memory system.

[0025] Secondly, embodiments of this application provide an apparatus including a memory manager, the memory manager being configured to: receive a first request from a first processor, the first request indicating that data at a first address be rewritten, the first address being an address in shared memory, the shared memory being managed by the memory manager; and based on the first request, send a first signal to a second processor, the first signal indicating that first data stored by the second processor is invalidated, the first data being a copy of data in a first address space in the shared memory, the first address being located in the first address space, wherein the shared memory is managed by the memory manager and the address space in the shared memory is accessible to both the first processor and the second processor.

[0026] The apparatus provided in this application embodiment may only have a memory manager dedicated to managing shared memory. Optionally, the apparatus provided in this application embodiment may be a processor, which, in addition to the memory manager, may also include, for example, a processor core.

[0027] The first address space includes multiple addresses. In conventional technology, a memory manager used to manage shared memory needs to send multiple signals to the first processor when it needs to invalidate a copy of data in the first address space stored in the first processor; each signal indicates the invalidation of data in one address. This severely consumes the bandwidth of the interconnect network. The memory manager provided in this application can invalidate the copy of data in the first address space stored in the first processor by sending a first signal to the first processor. Compared with conventional technology, this can free up interconnect network bandwidth, improve bandwidth utilization, and thus improve the performance of the shared storage system.

[0028] Based on the second aspect, in one possible implementation, the memory manager is further configured to: receive a second signal from the second processor, the second signal indicating completion of invalidation of the first data; and based on the second signal, send a third signal to the first processor, the third signal indicating permission for the first processor to rewrite the data at the first address.

[0029] Based on the second aspect, in one possible implementation, the memory manager is further configured to: monitor the second processor storing a first data segment in the shared memory, the first data segment being a segment of the first data; and in response to the completion of the storage of the first data segment, send a fourth signal to the second processor, the fourth signal indicating that the storage of the first data segment is complete.

[0030] Based on the second aspect, in one possible implementation, the memory manager is further configured to: receive a second request from a third processor, the second request indicating that data at a second address be rewritten, the second address being an address in the shared memory; and based on the second request, send a fifth signal to the second processor, the fifth signal indicating that the second data is invalid, the second data being a copy of the data at the second address.

[0031] Thirdly, embodiments of this application provide an apparatus including a processor, the processor being configured to: receive a first signal from a memory manager, the first signal being configured to indicate invalidation of stored first data, the first data being a copy of data in a first address space in shared memory, the first address being located in the first address space, the shared memory being managed by the memory manager; and invalidate the first data based on the first signal.

[0032] Based on the third aspect, in one possible implementation, the processor is specifically used to: decompose the first address space into multiple address ranges based on the first signal and the size of a preset data segment, to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment; and invalidate the multiple data segments.

[0033] Based on the third aspect, in one possible implementation, the processor is specifically configured to: modify the state of at least some of the data segments to an invalid state when the state of at least some of the data segments is either a shared state or an exclusive state.

[0034] Based on the third aspect, in one possible implementation, the processor includes a cache manager and an invalidation manager; the invalidation manager generates multiple invalid signals based on the multiple address ranges, with one invalid signal corresponding to one address range; and transmits the multiple invalid signals to the cache manager in a time-division manner; the cache manager invalidates the multiple data segments based on the multiple invalid signals.

[0035] Based on the third aspect, in one possible implementation, the cache manager is further configured to send multiple responses to the invalidation manager for the multiple invalidation signals, wherein one response corresponds to a data segment, and a first response among the multiple responses indicates that a first data segment among the multiple data segments has not been overwritten; the invalidation manager is further configured to transmit a second signal to the memory manager based on the multiple responses, the second signal indicating that invalidation of the first data has been completed.

[0036] Based on the third aspect, in one possible implementation, the second response among the plurality of responses carries a second data segment among the plurality of data segments, the second data segment being in a rewritten state; the invalidation manager is further configured to write the second data segment back to the corresponding address range in the shared memory when the second data segment is in a rewritten state.

[0037] Based on the third aspect, in one possible implementation, a first invalid signal among the plurality of invalid signals indicates that the first data segment is invalid; and the cache manager is specifically configured to: write the first data segment back to the shared memory before receiving the first invalid signal; and send the first response to the invalidation manager in response to a fourth signal sent by the memory manager, the fourth signal indicating that the first data segment has been stored.

[0038] Based on the third aspect, in one possible implementation, the cache controller is further configured to: receive a fifth signal from the memory manager, the fifth signal indicating invalidation of second data stored by the cache manager, the second data being a copy of data at a second address; and in response to the fifth signal, send a third response to the memory manager, the third response indicating whether the second data has been modified or not.

[0039] Fourthly, embodiments of this application provide a method for invalidating cached data. The method for invalidating cached data includes: receiving a first request from a first processor, the first request indicating that data in a first address be rewritten, the first address being an address in shared memory; and based on the first request, sending a first signal to a second processor, the first signal indicating that first data stored by the second processor be invalidated, the first data being a copy of data in a first address space in the shared memory, the first address being located in the first address space.

[0040] Based on the fourth aspect, in one possible implementation, the method further includes: receiving a second signal from the second processor, the second signal indicating completion of invalidation of the first data; and sending a third signal to the first processor based on the second signal, the third signal indicating permission for the first processor to rewrite the data in the first address.

[0041] Fifthly, embodiments of this application provide a method for invalidating cached data. The method for invalidating cached data includes: receiving a first signal from a memory manager, the first signal indicating invalidation of stored first data, the first data being a copy of data in a first address space in shared memory, the first address being located in the first address space; and invalidating the first data based on the first signal.

[0042] Based on the fifth aspect, in one possible implementation, invalidating the first data based on the first signal includes: decomposing the first address space into multiple address ranges based on the first signal and the size of a preset data segment to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment; and invalidating the multiple data segments.

[0043] Based on the fifth aspect, in one possible implementation, invalidating the plurality of data segments includes: when at least some of the data segments are in a shared state or an exclusive state, modifying the state of the at least some data segments to an invalid state.

[0044] Based on the fifth aspect, in one possible implementation, the method further includes: transmitting a second signal to the memory manager when the state of each of the plurality of data segments is invalid, the second signal indicating that the invalidation of the first data has been completed.

[0045] Based on the fifth aspect, in one possible implementation, before transmitting the second signal to the memory manager, the method further includes: when the state of the first data segment among the plurality of data segments is a rewritten state, writing the second data segment back to the corresponding address range in the shared memory.

[0046] It should be understood that the second to fifth aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of a hardware structure of a shared storage system provided in an embodiment of this application;

[0049] Figure 2 This is a schematic diagram illustrating the memory-to-global address space mapping relationship provided in an embodiment of this application;

[0050] Figure 3 This is a schematic diagram showing the multiple address ranges divided into the address space of memory 11 provided in this application embodiment;

[0051] Figure 4This is a flowchart illustrating the interaction between various components in the shared storage system provided in this application embodiment;

[0052] Figure 5 This is another hardware structure diagram of the shared storage system provided in the embodiments of this application;

[0053] Figure 6 The embodiments provided in this application are as follows Figure 5 A flowchart illustrating the interactions between components in a shared storage system.

[0054] Figure 7 The embodiments provided in this application are as follows Figure 5 This is another flowchart illustrating the interaction between components in a shared storage system.

[0055] Figure 8 The embodiments provided in this application are as follows Figure 5 This is another flowchart illustrating the interaction between components in a shared storage system.

[0056] Figure 9 This is a flowchart of a method for invalid cached data provided in an embodiment of this application;

[0057] Figure 10 This is yet another flowchart of a method for invalid cached data provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0059] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one. Terms such as "connection" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect, equivalent to connectivity in a broad sense.

[0060] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. For example, multiple processors means two or more processors.

[0061] The shared storage system 100 described in this application embodiment can be a symmetrical multiprocessing (SMP) system. The shared storage system 100 includes multiple processors, such as two or three, etc., and this application embodiment does not specifically limit this. These multiple processors can be central processing units (CPUs) or dedicated processors (e.g., image signal processors, artificial intelligence processors, or neural network processors, etc.), and this application embodiment does not specifically limit the form of the processors. The components (e.g., processors and memory) connected to the shared storage system 100 can communicate through an interconnection network, which can be, for example, including but not limited to, one of the following: a single bus, multiple buses, or a crossbar switch. In addition, the shared storage system 100 also includes memory, such as, but not limited to, SDRAM, DDR, etc. This memory can be independently configured and managed by a dedicated memory manager, or it can be coupled to one of the processors and managed by that processor, or it can be divided into multiple parts and distributed and coupled to multiple processors, with each part managed by its coupled processor. This memory forms a globally unified address space, which is shared by all processors in the shared storage system 100, and each processor can initiate a request to access any address space. Accessing any address space as mentioned here refers to reading instructions or data from the accessed address space, or writing data to the accessed address space. Processors that issue requests to read the same address space will receive the same data. The aforementioned memory management refers to recording which processors store data in each address space, and invalidating data stored in other processors in that address space before one processor rewrites data in that address space. This application embodiment uses a shared memory system 100 including four processors, with each processor having its own memory module, as an example. Figure 1 The shared storage system 100 provided in the embodiments of this application will be described in detail.

[0062] Please refer to Figure 1 , Figure 1This is a schematic diagram of the hardware structure of a shared storage system 100 provided in an embodiment of this application. Figure 1 In this embodiment, the shared storage system 100 includes four processors: processor 01, processor 02, processor 03, and processor 04. These four processors are interconnected via an interconnect network. It should be noted that processors 01 to 04 can be integrated into one or more chips. For example, processors 01 to 04 can be integrated into different chips; alternatively, they can be integrated into a single chip. This embodiment describes processors 01 to 04 as independent processors integrated into different chips, but this is not intended to limit the scope of the solution.

[0063] Each processor is equipped with one memory module. That is, processor 01 is coupled to memory 11, processor 02 to memory 12, processor 03 to memory 13, and processor 04 to memory 14. Each memory module can also be selectively integrated into the same chip as its coupled processor. Memory modules 11 to 14 form the global address space of the shared memory system 100, shared by processors 01 to 04. Memory modules 11 to 14 are each mapped to a specific block in the global address space. Figure 2 As shown, Figure 2 A schematic diagram illustrating the mapping relationship between various memory locations and the global address space is provided. Figure 2 In this context, the storage space of memory 11 is mapped to 0x0000~0x4000 in the global address space, the storage space of memory 12 is mapped to 0x4001~0x8000 in the global address space, the storage space of memory 13 is mapped to 0x8000~0x1201 in the global address space, and the storage space of memory 14 is mapped to 0x1200~0x1600 in the global address space.

[0064] Each processor contains one or more processor cores. These cores retrieve instructions and data from the global address space to perform various processing tasks. For example... Figure 1 The diagram schematically shows that processor 01 has a core c2, processor 02 has a core c2, processor 03 has a core c3, and processor 04 has a core c4.

[0065] Each processor also integrates a memory manager, which can also be called a home agent. Processor 01 integrates memory manager 21, processor 02 integrates memory manager 22, processor 03 integrates memory manager 23, and processor 04 integrates memory manager 24. Each memory manager can be implemented by hardware circuitry. Each memory manager manages the memory it is coupled to. Taking memory manager 21 as an example, memory manager 21 is used to record... Figure 2 The diagram shows which processors store data in address spaces 0x0000 to 0x4000, and how processors 02 through 04 invalidate data in a given address space stored by other processors before rewriting it. Assume that processors 02 and 03 both store data at address 0x3800. Before processor 02 rewrites the data at address 0x3800, processor 01 transmits a signal to processor 03 indicating that the data at address 0x3800 should be invalidated. This ensures cache coherency in the shared memory system 100. It should be noted that each memory manager can communicate directly with other processors (or components within the processor, such as the processor core, the data invalidation manager, and the cache manager, as described below) via an interconnect network, and directly with components within the internal processor (such as the processor core, cache manager, and data invalidation manager) via an internal bus.

[0066] Furthermore, in this embodiment, each memory manager can pre-divide its managed space region into multiple address spaces, which can be divided at the page level, for example. At least a portion of these multiple address spaces are declared address spaces. That is, when a processor needs to read data from one (or more) addresses in a declared address space, the memory manager provides all data in the address space corresponding to that declared address space to the processor; additionally, when a processor needs to rewrite data from one (or more) addresses in a declared address space, if other processors have copies of the data in that declared address space, those other processors need to invalidate all the data they have stored in that declared address space. The following uses... Figure 2 Taking the address space mapped by memory 11 shown as an example, combined with Figure 3 This describes the multiple address spaces that are divided into address spaces. For example... Figure 2The address space 0x0000~0x4000 mapped by memory 11 shown can be further divided into four address spaces. These four address spaces can be, for example, address spaces 0x0000~0x1000, 0x1001~0x2000, 0x2001~0x3000, and 0x3001~0x4000. Address spaces 0x0000~0x1000, 0x1001~0x2000, and 0x2001~0x3000 are declared address spaces, denoted as address space p1, address space p2, and address space p3, respectively. Assuming processor 02 sends a signal to memory manager 21 to read data from addresses 0x0000 to 0x0800, and processor 03 sends a signal to memory manager 21 to read data from addresses 0x3000 to 0x0900, then memory manager 21 will provide all the data in address space p1 to processor 02 and processor 03 respectively. Figure 3 The memory 11 shown is divided into four address spaces. Taking the processor 02 further requesting the memory manager 21 to rewrite the data in addresses 0x0000 to 0x0800 as an example, combined with... Figure 4 The interactive flow shown describes the way the copy is stored in the memory manager 21 invalid processor 03.

[0067] Step 401, processor 02 sends request q1 to memory manager 21. Request q1 is used to request the rewriting of data in addresses 0x0000 to 0x0800.

[0068] Step 402: Memory manager 21 sends signal s1 to processor 03 based on request q1. Specifically, after receiving request q1, memory manager 21 first determines that addresses 0x0000 to 0x0800 are located in address space p1. Then, memory manager 21 can determine that processor 03 holds a copy of the data in address space p1. Finally, memory manager 21 sends signal s1 to processor 03, indicating that processor 03 invalidates the copy of the data in address space p1. In one optional implementation, memory manager 21 can directly send the address range 0x0000 to 0x1000 corresponding to the address space to processor 03. In another possible implementation, each declared address space can be mapped to a preset identifier, and each processor can store the mapping relationship between declared address spaces and preset identifiers. For example, the preset identifiers corresponding to address spaces p1, p2, and p3 are page1, page2, and page3, respectively; memory manager 21 can send the preset identifier page1 corresponding to address space p1 to processor 03.

[0069] In step 403, processor 03 invalidates the copy of data stored in address space p1 based on signal s1. Typically, the copy of data in address space p1 stored by processor 03 may include multiple data segments, one of which may be a cache line. Each data segment is configured with status information indicating its state, which may include, but is not limited to, the following: modified, exclusive, shared, and invalid. Invalidating the copy of data stored in address space p1, as mentioned above, means that when the status information of a data segment is one of modified, exclusive, or shared, processor 03 modifies the status information to invalid.

[0070] based on Figure 1 The shared memory system 100 shown in the diagram traditionally communicates between processors based on the Snoopy protocol. In the Snoopy protocol, processors typically operate on data at the data segment level (e.g., reading data, writing data, or modifying the corresponding flag bits). That is, assuming processor 03 stores data in addresses 0x3000 to 0x0800, and the granularity of data it can operate on each time is 0x0100, when processor 02 performs a write operation on data in addresses 0x0000 to 0x0800, memory manager 21, based on the Snoopy protocol, decomposes addresses 0x0000 to 0x0800 into eight address ranges with a granularity of 0x0100, according to the granularity of data operations in the processors. Then, memory manager 21 transmits a signal to processor 03 each time indicating that data in one address range is invalid; that is, memory manager 21 needs to transmit eight signals to processor 03, severely consuming the bandwidth of the interconnect network. Furthermore, sending each of the eight address ranges to processor 03 individually results in processor 03 receiving a signal indicating that data within a certain address range is invalid only after multiple clock cycles, leading to latency issues. In this embodiment, by pre-setting a declared address space, when a large amount of data within that declared address space needs to be invalidated, the memory manager managing that declared address space range can provide a signal indicating the invalidation of a copy of the data in that declared address space to other processors holding that copy. Compared to the memory manager needing to send multiple signals, this embodiment can invalidate a large amount of data with a single signal, freeing up bandwidth in the interconnect network and improving bandwidth utilization.

[0071] based on Figure 1 The structure of the shared storage system 100 shown is as follows: Figure 4 Please refer to the interaction flow 400 shown below. Figure 5 , Figure 5This is a more detailed structural diagram of the shared storage system 100 provided in this application embodiment. Figure 1 Based on the shared storage system 100 shown, Figure 5 Each processor in the shared memory system 100 shown further includes a cache manager. The cache manager can also be called a cache agent. The cache manager contains a cache and a cache controller. Based on the control of the cache controller, the cache can retrieve the instructions and data required for processor core execution from the global address space in the shared memory system 100 for storage; and write data—dirty data generated by processor execution and pre-stored in the cache—to any address space in the global address space. That is, if a processor has a copy that needs to be invalidated, that copy is stored in the cache manager. Figure 1 The diagram schematically illustrates cache manager 31 in processor 01, cache manager 32 in processor 02, cache manager 33 in processor 03, and cache manager 34 in processor 04. Each cache manager can be implemented by hardware circuitry. Typically, the cache manager operates on data at the data segment level, based on the Snoopy protocol. In one optional implementation, the cache manager performs invalidation operations on multiple data segments included in the copy to be invalidated, at the data segment level. The invalidation operation here refers to modifying the state of a data segment to invalid when its state is one of modified, unique, or shared.

[0072] like Figure 5As shown, each processor may also be equipped with an invalidation manager, which can also be called a flush engine. Processor 01 has an invalidation manager 41, processor 02 has an invalidation manager 42, processor 03 has an invalidation manager 43, and processor 04 has an invalidation manager 44. Each invalidation manager can be a hardware circuit. The invalidation manager obtains a signal from the memory manager indicating that a copy of data in a certain declared address space should be invalidated. Based on this signal, the invalidation manager decomposes the declared address space to be invalidated into multiple address ranges according to the granularity of data processing in the cache manager (e.g., data segments), with each address range corresponding to a data segment. The invalidation manager then provides these multiple address ranges to the cache manager. For example, suppose invalidation manager 43 receives a signal from memory manager 21 indicating that data in address space p1 should be invalidated; suppose the granularity for storing data in cache manager is 0x0100, invalidation manager 43, based on the received signal, decomposes the addresses in address space p1 into 10 addresses: 0x0000~0x0100, 0x0101~0x0200, ..., 0x0901~0x1000, and then provides these ten addresses to cache manager 33 in a time-sharing manner. This allows cache manager 33 to invalidate the data in these ten addresses.

[0073] This application embodiment, by setting up an invalidation manager, allows the memory manager, which manages that address space, to provide a signal indicating invalidation of the data in that address space when invalidating a large amount of data within that address space. The invalidation manager then further decomposes the address regions corresponding to that address space and provides the decomposed address ranges to the on-chip cache manager. Therefore, compared to conventional technologies where the memory manager needs to send multiple signals to the cache manager, this application embodiment can invalidate a large amount of data with a single signal, freeing up interconnect network bandwidth and improving bandwidth utilization. Furthermore, since the invalidation manager and cache manager reside in the same processor, decomposing the address range through the invalidation manager and providing multiple address ranges to the cache manager reduces signal transmission latency compared to the memory manager needing to transmit multiple signals to an off-chip cache manager. In summary, the shared storage system 100 provided in this application embodiment can improve the bandwidth utilization of the interconnect network, reduce signal latency, and thus improve the performance of the shared storage system 100.

[0074] In this embodiment, when a data copy stored in a processor is invalidated, if the data is dirty, the processor's cache manager needs to write the dirty data back to memory. Based on this, in an optional implementation of this embodiment, when the invalidated data is dirty, the cache manager can also transfer the dirty data to an on-chip invalidation manager. The invalidation manager then writes the dirty data back to memory. It should be noted that after the memory manager initiates the invalidation of a data copy in a certain address space stored in a processor, and before the processor returns an indication that the invalidation is complete to the memory manager, the memory manager locks that address space, meaning that no other processor can access that address space.

[0075] Figure 5 In the shared storage system 100, when the memory manager needs to invalidate a large amount of data in a declared address space stored in the cache manager, a signal instructing the cache manager to invalidate the declared data copy is transmitted to the cache manager. In an optional implementation of this application embodiment, if the memory manager needs invalidated data stored outside the declared address space (e.g., memory manager 21 needs to invalidate...), the data is stored in a different address space. Figure 3 When the number of data to be invalidated (e.g., the data in addresses 0x3100 to 0x3200 shown) is the same as the number specified in the Snoopy protocol (e.g., the data of a data segment), the memory manager can directly transmit a signal to the cache manager indicating that data in a certain address range should be invalidated. Additionally, if the cache manager detects dirty data stored in that address range based on this signal, it can directly write the dirty data back to the corresponding address range in memory.

[0076] based on Figure 5 The shared storage system 100 shown Figure 2 The diagram showing the mapping relationship between memory and global address space and Figure 3 The address space of memory 11 is shown below. Taking the example where both cache manager 32 and cache manager 33 cache address space p1 in memory 11, and cache manager 32 requests to rewrite the data in address space p1, we will... Figure 5 The interaction flow between the components in the shared storage system 100 shown is described below. Please refer to... Figure 6 , Figure 6 For example Figure 5 The interaction process 600 between the components in the shared storage system 100 shown includes the following steps:

[0077] In step 601, cache manager 32 sends request q2 to memory manager 21, which instructs to rewrite the data in address range A.

[0078] In step 602, memory manager 21 sends signal s2 to invalidation manager 43 based on request q2. Specifically, after receiving request q2, memory manager 21 first determines that the address range R is located in address space p1. Then, memory manager 21 can determine that cache manager 32 holds a copy of the data in address space p2. Finally, memory manager 21 sends signal s2 to invalidation manager 43, indicating an invalid copy of the data in address space p1.

[0079] Step 603: The invalidation manager 43 generates invalid signals i1, i2, and i3 based on signal s2, the pre-set data segment size, and address space p1. Step 604: The invalidation manager 43 provides invalid signals i1, i2, and i3 to the cache manager in a time-sharing manner. Specifically, the invalidation manager 43 divides address space p1 into three address ranges: address range a1, address range a2, and address range a3, based on the preset data segment size. The data volume in each address range is a data segment. This data segment represents the granularity of data operations performed by the cache manager. Invalid signal i1 indicates a copy of the data in invalid address range a1, invalid signal i2 indicates a copy of the data in invalid address range a2, and invalid signal i3 indicates a copy of the data in invalid address range a3. It should be noted that... Figure 6 The diagram shows that the invalidation manager 43 transmits three signals to the cache manager. It is understood that the embodiments of this application are limited to this. In specific scenarios, the number of address ranges divided and the number of signals generated can be adjusted based on the size of the address space and the size of the data segment.

[0080] In step 605, based on signal i1, cache manager 33 detects that the data segment in address range a1 has not been overwritten (i.e., the data segment's status information is one of unique, shared, or invalid), and transmits response r1 to invalidation manager 43, indicating that the data segment in address range a1 has not been overwritten; based on signal i2, cache manager 33 detects that the data segment in address range a2 has not been overwritten, and transmits response r2 to invalidation manager 43, indicating that the data segment in address range a2 has not been overwritten; based on signal i3, cache manager 33 detects that the data segment in address range a3 has not been overwritten, and transmits response r3 to invalidation manager 43, indicating that the data segment in address range a3 has not been overwritten. It should be noted that if the status information of the data segments in address ranges a1 to a3 is unique or shared, cache manager 33 needs to change the status information from "unique" or "shared" to "invalid" before transmitting the response.

[0081] It should be noted that steps 604 and 605 above are not intended to limit the time sequence. For example, in the first clock cycle, invalidation manager 43 sends invalid signal i1 to cache manager 33; in the second clock cycle, invalidation manager 43 sends invalid signal i2 to cache manager 33, and cache manager 33 generates response r1 based on invalid signal i1 and transmits it to invalidation manager 43; in the third clock cycle, invalidation manager 43 sends invalid signal i3 to cache manager 33, and cache manager 33 generates response r2 based on invalid signal i2 and transmits it to invalidation manager 43; in the fourth clock cycle, cache manager 33 generates response r3 based on invalid signal i3 and transmits it to invalidation manager 43.

[0082] In step 606, invalidation manager 43 transmits signal s3 to memory manager 21 based on responses r1, r2, and r3. Signal s3 indicates that invalidation of the data copy in address space p1 is complete. In this step, invalidation manager 43 transmits signal s3 to memory manager 21 only after receiving all responses and each response indicating that the data segment in the address range has not been overwritten.

[0083] In step 607, memory manager 21 sends signal s4 to cache manager 32, which indicates that cache manager 32 is allowed to rewrite data in address range A.

[0084] Figure 6 In step 605 of the interactive flow 600 shown, the cache manager 33 detects that the status information of the data in address ranges a1 to a3 is one of unique, shared, or invalid. In one possible implementation of this application embodiment, the status information of the data segments in at least a portion of the address ranges a1 to a3 is modified, that is, there is dirty data in at least a portion of the address ranges a1 to a3. When dirty data exists, it is also necessary to write the dirty data back to memory 11. The following is a description of... Figure 7 The interactive process shown in 700 is described in detail.

[0085] exist Figure 7 In the middle, steps 701 to 704 and Figure 6 Steps 601 to 604 shown are the same; please refer to the following for details. Figure 6 The relevant descriptions of steps 601 to 604 are not repeated here.

[0086] In step 705, based on signal i1, cache manager 33 detects that the data segment in address range a1 has not been modified, and transmits response r4 to invalidation manager 43, indicating that the data segment in address range a1 has not been modified; based on signal i2, cache manager 33 detects that the data segment in address range a2 has not been modified, and transmits response r2 to invalidation manager 43, indicating that the data segment in address range a2 has not been modified; based on signal i3, cache manager 33 detects that the status information of the data segment in address range a3 has not been modified, and transmits response signal r3 to invalidation manager 43, the response signal r3 including data segment D1 in address range an.

[0087] Step 706: Invalid manager 43 writes data segment D1 back to address range an in memory 11.

[0088] In step 707, memory manager 21 detects that data segment D1 has been stored in memory 11 and sends signal S5 to invalidation manager 43. Signal S5 indicates that the storage of data segment D1 is complete.

[0089] Steps 708 to 709 and Figure 6 Steps 606 to 607 shown are the same; please refer to the following for details. Figure 6 The relevant descriptions of steps 606 to 607 are not repeated here.

[0090] based on Figure 6 and Figure 7 The interactive flow shown, in one scenario, is... Figure 6 Step 601 shown (or Figure 7 Before step 701), as shown, cache manager 33 transfers the data segment in address range a1 to memory 11. However, when cache manager 33 receives invalid signal i1 in step 605, the data in address range a1 has not yet been completely transferred. Based on this scenario, please refer to... Figure 8 , Figure 8 This is another interaction process 800 of the shared storage system 100 provided in this application embodiment. This interaction process 800 includes the following steps:

[0091] Step 801: Cache manager 33 writes data segment D2 in address range a1 to memory 11.

[0092] Steps 802 to 805 and Figure 6 Steps 601 to 604 shown are the same; please refer to the following for details. Figure 6 The relevant descriptions of steps 601 to 604 are not repeated here.

[0093] In step 806, based on signal i2, cache manager 33 detects that the data segment in address range a2 has not been modified, and transmits response r2 to invalidation manager 43, indicating that the data segment in address range a2 has not been modified; based on signal i3, cache manager 33 detects that the data segment in address range a3 has not been modified, and transmits response r3 to invalidation manager 43, indicating that the data segment in address range a3 has not been modified.

[0094] In step 807, memory manager 21 transmits signal S6 to cache manager 33, signal S6 indicating that the storage of data segment D2 is complete.

[0095] In step 808, the cache manager 33 transmits a response r1 to the invalidation manager 43 based on signal i1 and signal S6. The response r1 indicates that the data segment in address range a1 has not been modified.

[0096] Steps 809 to 810 and Figure 6 Steps 606 to 607 shown are the same; please refer to the following for details. Figure 6 The relevant descriptions of steps 606 to 607 are not repeated here.

[0097] Based on the same inventive concept, embodiments of this application also provide a method for invalidating cached data, which can be applied to, for example... Figure 1 In any of the memory managers shown. Please continue reading. Figure 9 This document illustrates a flow 900 of a method for invalidating cached data provided in an embodiment of this application. It includes the following steps: Step 901, receiving a first request from a first processor, the first request indicating that data at a first address be rewritten, the first address being an address in shared memory; Step 902, based on the first request, sending a first signal to a second processor, the first signal indicating that first data stored by the second processor be invalidated, the first data being a copy of data in a first address space in the shared memory, the first address being located in the first address space.

[0098] It should be noted that the memory manager for execution flow 900 can be set to... Figure 1 In any of the processors shown, the memory manager of execution flow 900 is designated as the third processor. The first processor, second processor, and third processor are all different processors. For example, in... Figure 1 In this processor, the first processor is processor 01, the second processor is processor 02, and the third processor is processor 03. The third processor 03 includes a memory manager 33, which is used for execution... Figure 9 The process shown is 900.

[0099] In one possible implementation, the method further includes: receiving a second signal from the second processor, the second signal indicating that invalidation of the first data has been completed; and, based on the second signal, sending a third signal to the first processor, the third signal indicating that the first processor is allowed to rewrite the data in the first address.

[0100] Based on the same inventive concept, embodiments of this application also provide a method for invalidating cached data, which can be applied to, for example... Figure 1 In any of the processors shown. Please continue reading. Figure 10 This document illustrates a flowchart 1000 of a method for invalidating cached data provided in an embodiment of this application. It includes the following steps: Step 1001, receiving a first signal from a memory manager, the first signal indicating invalidation of stored first data, the first data being a copy of data in a first address space in shared memory, the first address being located in the first address space; Step 1002, invalidating the first data based on the first signal.

[0101] In one possible implementation, invalidating the first data based on the first signal includes: decomposing the first address space into multiple address ranges based on the first signal and the size of a preset data segment to obtain multiple data segments corresponding to the first data, wherein one address range corresponds to one data segment; and invalidating the multiple data segments.

[0102] In one possible implementation, invalidating the plurality of data segments includes: when at least some of the data segments are in a shared state or an exclusive state, modifying the state of the at least some data segments to an invalid state.

[0103] In one possible implementation, the method further includes: transmitting a second signal to the memory manager when each of the plurality of data segments is in an invalid state, the second signal indicating that the invalidation of the first data has been completed.

[0104] In one possible implementation, before transmitting the second signal to the memory manager, the method further includes: when the state of the first data segment among the plurality of data segments is overwritten, writing the second data segment back to the corresponding address range in the shared memory.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A shared storage system, characterized in that, This includes a memory manager, multiple processors, and shared memory; The first processor among the plurality of processors is configured to send a first request to the memory manager, the first request indicating that data in a first address be rewritten, the first address being an address in the shared memory; The memory manager, based on the first request, sends a first signal to a second processor among the plurality of processors. The first signal indicates that the first data stored by the second processor is invalid. The first data is a copy of the data in the first address space of the shared memory, and the first address is located in the first address space. The second processor includes a cache manager and an invalidation manager; The invalid manager, based on the first signal and the size of a preset data segment, decomposes the first address space into multiple address ranges to obtain multiple data segments corresponding to the first data, with one address range corresponding to one data segment; The invalidation manager generates multiple invalid signals based on the multiple address ranges, with one invalid signal corresponding to one address range; And the multiple invalid signals are transmitted to the cache manager in a time-division manner; The cache manager invalidates the multiple data segments based on the multiple invalid signals.

2. The shared storage system according to claim 1, characterized in that, The second processor is specifically used for: When at least some of the data segments are in a shared state or an exclusive state, the state of the at least some data segments is changed to an invalid state.

3. The shared storage system according to claim 1, characterized in that, The cache manager is also configured to send multiple responses to the invalidation manager for the multiple invalid signals, wherein one response corresponds to a data segment, and the first response among the multiple responses indicates that the first data segment among the multiple data segments has not been overwritten; The invalidation manager is further configured to transmit a second signal to the memory manager based on the plurality of responses, the second signal indicating that the invalidation of the first data has been completed.

4. The shared storage system according to claim 3, characterized in that, The second response among the plurality of responses carries the second data segment among the plurality of data segments, and the state of the second data segment is a rewritten state; The invalidation manager is also used to write the second data segment back to the corresponding address range in the shared memory.

5. The shared storage system according to claim 3, characterized in that, The first invalid signal among the plurality of invalid signals indicates that the first data segment is invalid; and the cache manager is specifically used for: Before receiving the first invalid signal, write the first data segment back to the shared memory; In response to a third signal sent by the memory manager, the first response is sent to the invalidation manager, the third signal indicating that the first data segment has been stored.

6. The shared storage system according to claim 3, characterized in that, The memory manager is also used for: Based on the second signal, a fourth signal is sent to the first processor, the fourth signal indicating that the first processor is allowed to rewrite the data in the first address.

7. The shared storage system according to any one of claims 1-6, characterized in that, A third processor among the plurality of processors is configured to send a second request to the memory manager, the second request instructing to rewrite data at a second address, the second address being an address in the shared memory; Based on the second request, the memory manager sends a fifth signal to the cache manager, the fifth signal indicating that the second data stored by the cache manager is invalid, the second data being a copy of the data at the second address; In response to the fifth signal, the cache manager sends a third response to the memory manager, the third response indicating whether the second data has been modified or not.

8. An apparatus for invalid cached data, characterized in that, Includes a second processor, the second processor being used for: The system receives a first signal from the memory manager, which is sent by the memory manager based on a first request sent by the first processor to the memory manager. The first request instructs the memory manager to rewrite data at a first address, which is an address in shared memory. The first signal is used to indicate invalid stored first data, which is a copy of data in a first address space in shared memory. The first address is located in the first address space. The shared memory is managed by the memory manager. The processor includes a cache manager and an invalidation manager; The invalid manager, based on the first signal and the size of a preset data segment, decomposes the first address space into multiple address ranges to obtain multiple data segments corresponding to the first data, with one address range corresponding to one data segment; The invalidation manager generates multiple invalid signals based on the multiple address ranges, with one invalid signal corresponding to one address range; And the multiple invalid signals are transmitted to the cache manager in a time-division manner; The cache manager invalidates the multiple data segments based on the multiple invalid signals.

9. The apparatus according to claim 8, characterized in that, The processor is specifically used for: When at least some of the data segments are in a shared state or an exclusive state, the state of the at least some data segments is changed to an invalid state.

10. The apparatus according to claim 8, characterized in that, The cache manager is also configured to send multiple responses to the invalidation manager for the multiple invalid signals, wherein one response corresponds to a data segment, and the first response among the multiple responses indicates that the first data segment among the multiple data segments has not been overwritten; The invalidation manager is further configured to transmit a second signal to the memory manager based on the plurality of responses, the second signal indicating that the invalidation of the first data has been completed.

11. The apparatus according to claim 10, characterized in that, The second response among the plurality of responses carries the second data segment among the plurality of data segments, and the state of the second data segment is a rewritten state; The invalidation manager is also configured to write the second data segment back to the corresponding address range in the shared memory when the state of the second data segment is overwritten.

12. The apparatus according to claim 10 or 11, characterized in that, The first invalid signal among the plurality of invalid signals indicates that the first data segment is invalid; and the cache manager is specifically used for: Before receiving the first invalid signal, write the first data segment back to the shared memory; In response to a fourth signal sent by the memory manager, the first response is sent to the invalidation manager, the fourth signal indicating that the first data segment has been stored.

13. A method for invalid cached data, characterized in that, The method is applied to a second processor and includes: Receive a first signal from the memory manager, the first signal being sent by the memory manager based on a first request, the first request being sent by the first processor to the memory manager, the first request instructing the memory manager to rewrite data at a first address, the first address being an address in shared memory, the first signal being used to indicate invalid stored first data, the first data being a copy of data in a first address space in shared memory, the first address being located in the first address space; The second processor includes a cache manager and an invalidation manager; The invalid manager, based on the first signal and the size of a preset data segment, decomposes the first address space into multiple address ranges to obtain multiple data segments corresponding to the first data, with one address range corresponding to one data segment; The invalidation manager generates multiple invalid signals based on the multiple address ranges, with one invalid signal corresponding to one address range; and transmits the multiple invalid signals to the cache manager in a time-division manner. The cache manager invalidates the multiple data segments based on the multiple invalid signals.

14. The method according to claim 13, characterized in that, The invalidation of the first data based on the first signal includes: Based on the first signal and the size of the preset data segment, the first address space is decomposed into multiple address ranges to obtain multiple data segments corresponding to the first data, with one address range corresponding to one data segment; The aforementioned data segments are invalid.

15. The method according to claim 13, characterized in that, The invalid data segments include: When at least some of the data segments are in a shared state or an exclusive state, the state of the at least some data segments is changed to an invalid state.

16. The method according to claim 14 or 15, characterized in that, The method further includes: When each of the plurality of data segments is in an invalid state, a second signal is transmitted to the memory manager, the second signal indicating that the invalidation of the first data has been completed.

17. The method according to claim 16, characterized in that, Before transmitting the second signal to the memory manager, the method further includes: When the first data segment among the plurality of data segments is in a rewritten state, the first data segment is written back to the corresponding address range in the shared memory.

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