Data transmission method, data link layer, chip interconnection interface and electronic device

Abstract

Embodiments of the present disclosure provide a data transmission method, a data link layer, a chip interconnection interface, and an electronic device. The data transmission method is applied to the data link layer of the chip interconnection interface, the data link layer communicates with the system bus and the physical layer, the system bus operates in a first clock domain, and the physical layer operates in a second clock domain or in a second clock domain and a third clock domain. The method includes: the data link layer performs packet processing on the first data received from the system bus to obtain second data, and provides the second data to the physical layer; or, the data link layer performs unpacking processing on the third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus, wherein the data link layer partially operates in the third clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data transmission method, a data link layer, a chip interconnection interface, and an electronic device, and more particularly to a data transmission method, a data link layer, a chip interconnection interface, a chip, and an electronic device. Background Art

[0002] A chiplet is a unit chip with specific functions and internal interconnect interfaces. It is the latest development in chip design technology. Chiplet technology uses multiple chiplets to implement chip design, which not only reduces costs but also improves chip performance.

[0003] Figure 1 The framework of the chiplet interconnection interface in the prior art is shown. Figure 1 In [1], the core 100 comprises a protocol layer, a data link layer, and a physical layer. The protocol layer is related to the specific service type it carries, supporting things like SOC (System on Chip) bus protocols, high-bandwidth storage services, and custom protocols. The data link layer provides reliable data transmission between communicating parties. The physical layer provides bitstream transmission services that conform to the characteristics of the physical channel. The data link layer facilitates data transmission between the physical layer and the protocol layer. Summary of the Invention

[0004] In a first aspect, at least one embodiment of the present disclosure provides a data transmission method, which is applied to the data link layer of a chip interconnection interface, wherein the data link layer communicates with a system bus and a physical layer, wherein the system bus operates in a first clock domain, and the physical layer operates in a second clock domain or operates in the second clock domain and a third clock domain, and the method includes: the data link layer performs packet processing on the first data received from the system bus to obtain second data, and provides the second data to the physical layer, or the data link layer performs unpacking processing on the third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus, wherein the data link layer partially operates in a third clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

[0005] For example, in a method provided according to at least one embodiment of the present disclosure, before the data link layer performs packet processing on the first data received from the system bus to obtain the second data, the method further includes: the data link layer asynchronously receives the first data from the system bus according to a third clock signal, wherein the first data is sent by the system bus according to the first clock signal.

[0006] For example, in the method provided according to at least one embodiment of the present disclosure, before the data link layer unpacks the third data received from the physical layer to obtain the fourth data, the method further includes: the data link layer obtains the third data from the physical layer according to the third clock signal; or, when the data link layer is still partially working in the first clock domain, the data link layer obtains the third data from the physical layer according to the first clock signal; or, when the data link layer is still partially working in the second clock domain, the data link layer obtains the third data from the physical layer according to the second clock signal; wherein the third data is sent by the physical layer according to the second clock signal.

[0007] For example, in a method provided according to at least one embodiment of the present disclosure, the data link layer performs packet processing on the first data received from the system bus to obtain the second data, including: the data link layer performs packet processing on the first data according to the third clock signal to obtain the second data.

[0008] For example, in the method provided according to at least one embodiment of the present disclosure, providing the second data to the physical layer includes: the data link layer synchronously or asynchronously providing the second data to the physical layer according to a third clock signal.

[0009] For example, in a method provided according to at least one embodiment of the present disclosure, the data link layer unpacks the third data received from the physical layer to obtain fourth data, including: when the data link layer obtains the third data according to the first clock signal, the data link layer unpacks the third data according to the first clock signal to obtain fourth data; when the data link layer obtains the third data according to the third clock signal, the data link layer unpacks the third data according to the third clock signal to obtain fourth data.

[0010] For example, in the method provided according to at least one embodiment of the present disclosure, the data link layer obtains the third data from the physical layer according to the third clock signal, including: the data link layer asynchronously receives the third data from the physical layer according to the third clock signal; or, the data link layer obtains the third data from the physical layer according to the first clock signal, including: the data link layer asynchronously receives the third data from the physical layer according to the first clock signal; or, the data link layer obtains the third data from the physical layer according to the second clock signal, including: the data link layer synchronously receives the third data from the physical layer according to the second clock signal.

[0011] For example, in a method provided according to at least one embodiment of the present disclosure, the data link layer receives third data from the physical layer according to the second clock signal, including: the data link layer determines and receives multiple data segments of the third data from the data signal sent by the physical layer according to the second clock signal, wherein the third data is composed of multiple data segments.

[0012] For example, in a method provided according to at least one embodiment of the present disclosure, after receiving multiple data segments, the method also includes: the data link layer asynchronously obtains the multiple data segments according to the first clock signal, or the data link layer asynchronously obtains the multiple data segments according to the third clock signal, so that the third data enters the first clock domain or the third clock domain.

[0013] For example, in a method provided according to at least one embodiment of the present disclosure, the data link layer asynchronously receives the third data from the physical layer according to the first clock signal, including: the data link layer asynchronously receives multiple data segments of the third data according to the first clock signal; or, the data link layer asynchronously receives the third data from the physical layer according to the third clock signal, including: the data link layer asynchronously receives multiple data segments of the third data according to the third clock signal; wherein the third data is composed of multiple data segments.

[0014] For example, in a method provided according to at least one embodiment of the present disclosure, providing the fourth data to the system bus includes: the data link layer synchronously providing the fourth data to the system bus according to the first clock signal; or, the data link layer asynchronously providing the fourth data to the system bus according to the third clock signal.

[0015] For example, in a method provided according to at least one embodiment of the present disclosure, the method further includes: the data link layer performs a loopback test on multiple data paths corresponding to the data link layer according to a third clock signal, wherein the multiple data paths are connected to the data link layer via the physical layer.

[0016] For example, in a method provided according to at least one embodiment of the present disclosure, the data link layer performs a loopback test on multiple data paths corresponding to the data link layer according to a third clock signal, including: the data link layer generates at least one test data according to a preset loopback test data pattern; the data link layer asynchronously or synchronously sends at least one test data to the physical layer according to the third clock signal, so as to send it to multiple data paths; the data link layer obtains at least one test return data from the physical layer according to the first clock signal, the second clock signal or the third clock signal, and the at least one test return data corresponds one-to-one to the at least one test data; the data link layer detects the at least one test return data according to the loopback test data pattern to complete the loopback test.

[0017] In a second aspect, at least one embodiment of the present disclosure further provides a data link layer, which is applied to a chip interconnection interface, wherein the data link layer communicates with a system bus and a physical layer, the system bus operates in a first clock domain, the physical layer operates in a second clock domain or in a second clock domain and a third clock domain, and the data link layer at least partially operates in a third clock domain. The data link layer includes: a system bus interface, connected to the system bus, configured to receive first data from the system bus; a packet assembly module, connected to the system bus interface, configured to perform packet assembly processing on the first data and obtain second data; a physical layer interface, connected to the packet assembly module The unpacking module is connected to the physical layer and configured to provide the second data to the physical layer and obtain the third data from the physical layer; the unpacking module is connected to the physical layer interface and configured to unpack the third data and obtain the fourth data, and the fourth data is provided to the system bus by the unpacking module or the system bus interface; and the local clock is connected to the system bus interface, the packetization module, the unpacking module and the physical layer interface, and configured to generate a third clock signal included in the third clock domain; wherein the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes the first clock signal, and the second clock domain includes the second clock signal.

[0018] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the system bus interface is configured to asynchronously receive first data from the system bus according to a third clock signal, wherein the first data is sent by the system bus according to the first clock signal.

[0019] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the physical layer interface is further configured to obtain third data from the physical layer according to a third clock signal; or, when the data link layer is also partially operating in the first clock domain, the physical layer interface is further configured to obtain third data from the physical layer according to the first clock signal; or, when the data link layer is also partially operating in the second clock domain, the physical layer interface is further configured to obtain third data from the physical layer according to the second clock signal; wherein the third data is sent by the physical layer according to the second clock signal.

[0020] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the packetization module is configured to perform packetization processing on the first data according to the third clock signal to obtain the second data.

[0021] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the physical layer interface is configured to provide the second data to the physical layer synchronously or asynchronously according to the third clock signal.

[0022] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the unpacking module is configured to, when the third data is obtained according to the first clock signal, unpack the third data according to the first clock signal to obtain fourth data; and when the third data is obtained according to the third clock signal, unpack the third data according to the third clock signal to obtain fourth data.

[0023] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the physical layer interface is configured to: asynchronously receive the third data from the physical layer according to the first clock signal; or, asynchronously receive the third data from the physical layer according to the third clock signal; or, synchronously receive the third data from the physical layer according to the second clock signal.

[0024] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the physical layer interface is also configured to determine and receive multiple data segments of third data from the data signal sent by the physical layer based on the second clock signal, wherein the third data is composed of multiple data segments.

[0025] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the physical layer interface is also configured to, after receiving multiple data segments, asynchronously obtain multiple data segments according to a first clock signal, or asynchronously obtain multiple data segments according to a third clock signal, so that the third data enters the first clock domain or the third clock domain.

[0026] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the physical layer interface is configured to asynchronously receive multiple data segments of the third data according to a first clock signal, or to asynchronously receive multiple data segments of the third data according to a third clock signal, wherein the third data is composed of the multiple data segments.

[0027] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the depacketization module or the system bus interface is further configured to synchronously provide the fourth data to the system bus according to the first clock signal; or, asynchronously provide the fourth data to the system bus according to the third clock signal.

[0028] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the data link layer further includes a first buffer memory connected to the system bus interface or the packet assembly module and configured to store the first data according to the third clock signal.

[0029] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the data link layer also partially operates in the first clock domain and the second clock domain, or the data link layer also partially operates in the second clock domain, and the physical layer interface includes a second buffer memory, which is connected to the physical layer and the unpacking module, and is configured to perform write operations according to the second clock signal, and perform read operations according to the first clock signal or the third clock signal, wherein the second buffer memory stores the third data in the form of data segments.

[0030] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the data link layer also includes: a data detection module, connected to the unpacking module and the second buffer memory, configured to detect the data segments in the second buffer memory, and when multiple data segments constituting the third data are detected, send the multiple data segments to the unpacking module, and when multiple data segments constituting the third data are not detected, adjust the second buffer memory to obtain multiple data segments.

[0031] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the data link layer also includes: a loopback test module, which is connected to the physical layer interface and the packet assembly module, and is configured to perform a loopback test on multiple data paths corresponding to the data link layer according to a third clock signal, wherein the multiple data paths are connected to the data link layer via the physical layer.

[0032] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the loopback test module includes a loopback test generator and a loopback test checker, the loopback test generator is connected to the packet assembly module, and the loopback test checker is connected to the physical layer interface, wherein the loopback test transmitter is configured to generate at least one test data according to a preset loopback test data pattern, and provide the at least one test data to the physical layer via the packet assembly module and the physical layer interface according to a third clock signal, so as to be sent to multiple data paths; the loopback test checker is configured to receive at least one test return data from the physical layer via the physical layer interface according to the third clock signal, the at least one test return data corresponding one-to-one to the at least one test data, and detect the at least one test return data according to the loopback test data pattern to complete the loopback test.

[0033] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the system bus interface is an asynchronous FIFO memory.

[0034] For example, in the data link layer provided according to at least one embodiment of the present disclosure, the first buffer memory is an asynchronous elastic FIFO memory.

[0035] In a third aspect, at least one embodiment of the present disclosure further provides a chiplet interconnection interface configured to execute any of the methods in the first aspect above.

[0036] In a fourth aspect, at least one embodiment of the present disclosure further provides a chip interconnection interface, comprising a data link layer as described in any one of the second aspects.

[0037] In a fifth aspect, at least one embodiment of the present disclosure further provides a chip comprising a plurality of core particles, wherein any two of the plurality of core particles are connected via a core particle interconnection interface as in the fourth aspect.

[0038] In a sixth aspect, at least one embodiment of the present disclosure provides an electronic device comprising the chip according to the fifth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0040] Figure 1 The framework of the chiplet interconnection interface in the prior art is shown;

[0041] Figure 2 A flowchart of a data transmission method provided according to at least one embodiment of the present disclosure is shown;

[0042] Figure 3a-3d A schematic diagram of the structure of a data link layer provided according to at least one embodiment of the present disclosure is shown;

[0043] Figure 4a and Figure 4b A schematic diagram of the structure of a data link layer provided according to at least one embodiment of the present disclosure is shown;

[0044] Figure 5 Another structural diagram of a data link layer provided according to at least one embodiment of the present disclosure is shown;

[0045] Figure 6 A schematic diagram of a chip provided by at least one embodiment of the present disclosure is shown;

[0046] Figure 7 A schematic diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0047] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0049] The physical layer includes a transmit data path, a receive data path, and a sideband path. The number of paths in the transmit data path is greater than or equal to 1, the number of paths in the receive data path is greater than or equal to 1, and the number of paths in the sideband path is typically 1. One end of the physical layer is connected to the data link layer, and the other end of the physical layer is connected to the outside world, such as the physical layer of another core. The transmit data path, receive data path, and sideband path can be combined into a path group called a Macro. Optionally, the physical layer can include multiple path groups, such as 8 or 16.

[0050] The data link layer and the physical layer can be connected in a variety of ways. For example, if the service bandwidth managed by the data link layer is smaller than the bandwidth of a single channel group, the data link layer can be divided into multiple links, which share a single channel group for transmission. The bandwidth of each link can be greater or less than the bandwidth of a single data channel. A single data channel consists of a transmit data channel and a receive data channel.

[0051] For another example, when the bandwidth demand of a single link exceeds the bandwidth of a single path group, multiple path groups can be connected to achieve greater bandwidth. For example, each link can be connected to 1-8 path groups. Each link can also be connected to more than 8 path groups, with the number of connected path groups determined based on actual needs. It is understood that multiple path groups still belong to the same physical layer, and there is a one-to-one correspondence between the data link layer and the physical layer.

[0052] The data link layer implements a variety of functions, including transmission error detection and correction mechanisms, link state and low-power state transition management, transmission message format definition, and multi-data channel binding. Transmission error detection and correction mechanisms include CRC (Cyclic Redundancy Check) generation and verification, data retransmission, and ECC (Error Checking and Correcting).

[0053] The data link layer implements data transmission between the protocol layer and the physical layer. The data link layer is typically connected directly to the physical layer, which in turn is connected to the protocol layer via a system bus. The system bus typically has a bus clock, while the physical layer also has a local clock. Therefore, the data link layer needs to coordinate data transmission between these different clocks. Current practices impose restrictions on the system bus clock and the physical layer clock. For example, the system bus clock frequency is related to the physical layer clock frequency and the physical layer's serial ratio. This prevents the physical layer and system bus clock signals from being highly matched, which in turn affects data transmission efficiency and stability. Furthermore, to enable data transmission, the frequency of the system bus clock signal is constrained by the physical layer clock signal, which limits the setting of the system bus clock frequency and imposes constraints on the chip design.

[0054] Based on this, the present disclosure provides a data transmission method, a data link layer, a chip interconnection interface and an electronic device to solve the above problems.

[0055] At least one embodiment of the present disclosure provides a data transmission method, which is applied to the data link layer of a chip interconnect interface, wherein the data link layer communicates with a system bus and a physical layer, wherein the system bus operates in a first clock domain, and the physical layer operates in a second clock domain, and the method includes: the data link layer performs packet processing on first data received from the system bus to obtain second data, and provides the second data to the physical layer, or the data link layer performs unpacking processing on third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus, wherein the data link layer at least partially operates in a third clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

[0056] At least one embodiment of the present disclosure further provides a data link layer, which is applied to a chip interconnect interface, wherein the data link layer communicates with a system bus and a physical layer, the system bus operates in a first clock domain, the physical layer operates in a second clock domain, and the data link layer operates at least partially in a third clock domain, and the data link layer includes: a system bus interface, connected to the system bus, and configured to receive first data from the system bus; a packetization module, connected to the system bus interface, and configured to packetize the first data to obtain second data; a physical layer interface, connected to the packetization module and the physical layer, and configured to provide the second data to the physical layer, and to obtain third data from the physical layer; an unpacking module, connected to the physical layer interface, and configured to unpack the third data to obtain fourth data, and the fourth data is provided to the system bus by the unpacking module or the system bus interface; and a local clock, connected to the system bus interface, the packetization module, the unpacking module, and the physical layer interface, and configured to generate a third clock signal included in the third clock domain; wherein the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes the first clock signal, and the second clock domain includes the second clock signal.

[0057] At least one embodiment of the present disclosure further provides a chiplet interconnection interface, including the above-mentioned data link layer.

[0058] At least one embodiment of the present disclosure further provides a chip, comprising a plurality of core particles, wherein any two core particles among the plurality of core particles are connected via the core particle interconnection interface.

[0059] At least one embodiment of the present disclosure provides an electronic device including the above chip.

[0060] Figure 2 A flow chart of a data transmission method provided according to an embodiment of the present disclosure is shown.

[0061] The data transmission method 200 is applied to the data link layer of the chiplet interconnect interface. The data transmission method 200 includes the following steps:

[0062] In step S210 , the data link layer performs packetization processing on the first data received from the system bus to obtain second data, and provides the second data to the physical layer.

[0063] In step S220, the data link layer depackets the third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus. The data link layer operates partially in a third clock domain, and the first clock domain is different from the second clock domain and the third clock domain. The first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

[0064] In this embodiment, the data link layer communicates with the system bus and the physical layer. The system bus operates in the first clock domain, the physical layer operates in the second clock domain, or the physical layer operates in the second and third clock domains, while the data link layer partially operates in the third clock domain. For example, part of the data link layer operates in the third clock domain, part operates in the second clock domain, and still part operates in the first clock domain. By separating the first clock domain of the system bus and the second clock domain of the physical layer by the third clock domain of the data link layer, the problem of the clock signals of the physical layer and the system bus not being highly matched, which in turn affects the efficiency and stability of data transmission, can be solved. It can also solve the problem that the frequency of the system bus clock signal is constrained by the clock signal of the physical layer. This can improve data transmission efficiency, eliminate the frequency bottleneck of the system bus clock, support multiple system bus clocks, and increase the flexibility of the core particle implementation method.

[0065] In this embodiment, the data link layer is responsible for data transmission between the system bus and the physical layer. The data link layer needs to exchange data with both the system bus and the physical layer. These data exchange processes cannot completely avoid clock domain switching, and thus the data link layer cannot operate entirely in the third clock domain. If these data exchange processes are excluded from the data link layer, the data link layer can operate exclusively in the third clock domain.

[0066] In this embodiment, step S210 and step S220 are not connected by an arrowed line because there is no restriction on the order in which steps S210 and S220 are executed, and the two steps can be executed simultaneously. For example, data transmission from the system bus to the physical layer and data transmission from the physical layer to the system bus can be performed simultaneously.

[0067] Before executing step S210 , the data transmission method further includes: the data link layer asynchronously receiving first data from the system bus according to the third clock signal, wherein the first data is sent by the system bus according to the first clock signal.

[0068] For example, the data link layer can asynchronously receive first data based on the third clock signal, where the first data is carried by a data signal that is synchronized with the first clock signal. Asynchronously receiving the first data through the data link layer isolates the clock signals of the system bus and the physical layer.

[0069] When executing step S210, the data link layer performs packet processing on the first data according to the third clock signal to obtain the second data. The method of packet processing on the first data can refer to Figure 2 Related description.

[0070] When the physical layer operates only in the second clock domain, the data link layer asynchronously sends the second data to the physical layer based on the third clock signal. When the physical layer operates in both the second and third clock domains, the data link layer can synchronously provide the second data to the physical layer based on the third clock signal. For example, the data link layer uses a data signal synchronized with the third clock signal to carry the second data. The physical layer receives the second data using the second clock signal.

[0071] In some embodiments, the physical layer may not use the third clock signal. For example, the physical layer belongs only to the second clock domain, the third clock signal and the second clock signal are not synchronized. Using the third clock signal to send the second data and using the second clock signal to receive the second data is asynchronous data transmission.

[0072] Before executing step S220, the data transmission method also includes: the data link layer obtains the third data from the physical layer according to the third clock signal; or, when the data link layer is still partially working in the first clock domain, the data link layer obtains the third data from the physical layer according to the first clock signal; or, when the data link layer is still partially working in the second clock domain, the data link layer obtains the third data from the physical layer according to the second clock signal; wherein the third data is sent by the physical layer according to the second clock signal.

[0073] In embodiments of the present disclosure, the data link layer may operate in multiple clock domains, for example, the data link layer may partially operate in the third clock domain and partially operate in the first clock domain, or the data link layer may partially operate in the third clock domain and partially operate in the second clock domain, or the data link layer may partially operate in the third clock domain, partially operate in the first clock domain, and partially operate in the second clock domain. The data link layer "according to" or "using" a first clock signal indicates that the data link layer partially operates in the first clock domain, while the data link layer "according to" or "using" a second clock signal indicates that the data link layer partially operates in the second clock domain.

[0074] In this embodiment, when the data link layer obtains the third data from the physical layer, it may include synchronously receiving the third data, asynchronously receiving the third data, etc., that is, the operation of "obtaining" the third data in this embodiment is not equivalent to a single operation of "synchronously receiving" or "asynchronously receiving" the third data.

[0075] For example, the data link layer asynchronously receives the third data from the physical layer according to the first clock signal, or the data link layer asynchronously receives the third data from the physical layer according to the third clock signal. In another example, the data link layer synchronously receives the third data from the physical layer according to the second clock signal.

[0076] Optionally, when receiving the third data according to the second clock signal, the data link layer can determine and receive multiple data segments of the third data from the data signal sent by the physical layer according to the second clock signal, where the third data consists of multiple data segments.

[0077] For example, the physical layer sends a data signal based on a second clock signal. This data signal is synchronized with the second clock signal, allowing the data link layer to receive third data based on the second clock signal. The data signal carries multiple data segments that constitute the third data, so the positions of the data segments in the data signal must be determined to ensure accurate reception of the data segments.

[0078] After receiving the multiple data segments, the multiple data segments (i.e., the third data) still belong to the second clock domain. The data link layer can asynchronously obtain the multiple data segments based on the first clock signal or the third clock signal, so that the third data enters the first clock domain or the third clock domain accordingly. For example, after receiving the multiple data segments, they are temporarily stored in a memory, and then the multiple data segments are read from the memory based on the first clock signal or the third clock signal.

[0079] Optionally, when the data link layer asynchronously receives the third data according to the first clock signal, the data link layer may asynchronously receive multiple data segments of the third data according to the first clock signal, wherein the third data consists of multiple data segments. When the data link layer asynchronously receives the third data according to the third clock signal, the data link layer may asynchronously receive multiple data segments of the third data according to the third clock signal.

[0080] During step S220, the data link layer unpacks the third data, for example, by combining the payloads of the plurality of Flit data into fourth data in a format that complies with system bus transmission requirements or an upper layer protocol. For example, the data link layer unpacks the third data based on the first clock signal or the third clock signal.

[0081] In this embodiment, if the data link layer receives the third data based on the first clock signal, all subsequent operations use the first clock signal. If the data link layer receives the third data based on the third clock signal, all subsequent operations use the third clock signal. For example, when the data link layer receives the third data based on the first clock signal, the data link layer depackets the third data based on the first clock signal to obtain the fourth data. When the data link layer receives the third data based on the third clock signal, the data link layer depackets the third data based on the third clock signal to obtain the fourth data.

[0082] When executing step S220 , the data link layer also provides the fourth data to the system bus synchronously according to the first clock signal; or, the data link layer also provides the fourth data to the system bus asynchronously according to the third clock signal.

[0083] In some embodiments, the data transmission method further includes: the data link layer performing a loopback test on multiple data paths corresponding to the data link layer according to the third clock signal, wherein the multiple data paths are connected to the data link layer via the physical layer.

[0084] In this embodiment, the data link layer needs to complete a loopback test according to the third clock signal. The loopback test is a closed loop, starting from the data link layer and ending at the data link layer.

[0085] For example, the data link layer performs a loopback test on multiple data paths corresponding to the data link layer according to the third clock signal, including: the data link layer generates at least one test data according to a preset loopback test data pattern; the data link layer asynchronously or synchronously sends at least one test data to the physical layer according to the third clock signal, so as to send it to multiple data paths; the data link layer obtains at least one test return data from the physical layer according to the first clock signal, the second clock signal or the third clock signal, and the at least one test return data corresponds one-to-one to the at least one test data; the data link layer detects the at least one test return data according to the preset loopback test data pattern to complete the loopback test.

[0086] In this embodiment, multiple data paths are transmitted in parallel, and each test data item is transmitted in parallel by multiple data paths. The data link layer generates test data and detects test return data using a third clock signal. The method for transmitting test data and test return data between the data link layer and the physical layer can be found in the method described in steps S210 and S220 and will not be further described here. Optionally, the data transmission method further includes: the data link layer determines whether multiple data segments are aligned based on the first clock signal or the third clock signal, and if misalignment is determined, adjusts the method for acquiring the multiple data segments so that the multiple data segments can be acquired simultaneously or synchronously. When acquiring multiple data segments based on the first clock signal or the third clock signal, if multiple data segments acquired in the same acquisition operation belong to the third data, then the multiple data segments are aligned. If the multiple data segments acquired in the same acquisition operation do not all belong to the third data, then the multiple data segments are misaligned. For example, if a test return data item corresponds to 16 data segments, it is necessary to ensure that all 16 data segments acquired in a single acquisition operation belong to the test return data item and not other data.

[0087] The present disclosure also provides a variety of possible structures of the data link layer. Figure 3a-3d 、 Figure 4a-4b as well as Figure 5 The data link layer is described for easier understanding.

[0088] Figure 3a A structural diagram of a data link layer provided according to at least one embodiment of the present disclosure is shown.

[0089] exist Figure 3a In

[15] , data link layer 300a communicates with system bus 310 and physical layer 320a. System bus 310 operates in the first clock domain, physical layer 320a operates only in the second clock domain, and data link layer 300a partially operates in the third clock domain. The first clock domain, second clock domain, and third clock domain are all different. The first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal. The first clock signal, the second clock signal, and the third clock signal are asynchronous with each other.

[0090] In this embodiment and the following embodiments, a box filled with slashes indicates operation in the first clock domain, a box filled with black indicates operation in the second clock domain, and a box filled with white indicates operation in the third clock domain. If a box has multiple fills, it indicates operation in multiple corresponding clock domains.

[0091] The data link layer 300a includes a system bus interface 301a, a packetization module 302, a physical layer interface 303a, a depacketization module 304, and a local clock 305. The system bus interface 301a is connected to the system bus 310 and the packetization module 302. The physical layer interface 303a is connected to the packetization module 302 and the physical layer 320a. The depacketization module 304 is connected to the physical layer interface 303a and the system bus interface 301a. The local clock 305 is connected to the system bus interface 301a, the packetization module 302, the physical layer interface 303a, and the depacketization module 304.

[0092] In the embodiments of the present disclosure, “connection” means direct connection or indirect connection. For example, the physical layer interface 303a is directly connected to the depacketization module 304. The physical layer interface 303a may also be connected to the depacketization module 304 via other components.

[0093] The data link layer 300 implements bidirectional data transmission between the system bus 310 and the physical layer 320a. Figure 3a In the example, the packet assembly module 302, the depacketization module 304, and the local clock 305 all operate in the third clock domain. The system bus interface 301a partially operates in the first clock domain, while the remaining portion operates in the third clock domain. The physical layer interface 303a partially operates in the second clock domain, while the remaining portion operates in the third clock domain.

[0094] The system bus interface 301a receives first data from the system bus 310. The first data is sent by the system bus 310 according to the first clock signal and is carried in a data signal that is synchronized with the first clock signal. For example, the system bus interface 301a receives the first data asynchronously according to the third clock signal and sends the first data to the packetization module 302.

[0095] The packetization module 302 performs packetization on the first data to obtain second data. A Flit (Flitflow Control Unit) can be used as the basic unit for any data transmission between the data link layer 300 and the physical layer 320. The packetization module 302 performs packetization on the first data to obtain at least one Flit. When the length of the first data is less than the length of the payload of a Flit, the first data can be placed in a Flit for transmission. For example, a Flit includes a header, a payload, and a tail, where the payload includes the first data and padding. When the length of the first data is greater than the length of the payload of a Flit, the first data can be split into N Flits for transmission, where the N Flits include a header Flit, a payload Flit, and a tail Flit. The header Flit is the first Flit among the multiple Flits and includes a header, a payload, and a tail. The payload Flit is the middle Flit and includes only the payload. The tail Flit is the Nth Flit and includes both the payload and the tail. N is greater than or equal to 3. The payload of the Flit trailer may consist solely of padding data. The Flit trailer is used to verify the correctness of the Flit data and supports a CRC or ECC check mechanism. For example, the Flit tail includes CRC or ECC check bits, the bit width of which is related to the bit width of the Flit data, for example, 6-32 bits. Accordingly, the second data includes at least one Flit.

[0096] The packetizing module 302 performs packetizing according to the third clock signal. The packetizing module 302 may be implemented by a logic circuit. After obtaining the second data, the packetizing module 302 sends the second data to the physical layer interface 303a.

[0097] For example, the physical layer interface 303a asynchronously sends the second data to the physical layer 320a according to the third clock signal.

[0098] Physical layer interface 303a also receives third data from physical layer 320a. For example, physical layer 320a sends the third data to physical layer interface 303a based on the second clock signal, and physical layer interface 303a asynchronously receives the third data based on the third clock signal. Physical layer interface 303a then provides the third data to depacketization module 304 based on the third clock signal. For example, physical layer interface 303a actively sends the third data, or depacketization module 304 obtains the third data from physical layer interface 303a. For example, physical layer interface 303a includes a memory that can store the third data for depacketization module 304 to obtain from physical layer interface 303a.

[0099] The unpacking module 304 unpacks the third data according to the third clock signal to obtain fourth data. Unpacking, in contrast to packetization, disassembles the Flit to obtain fourth data in a protocol layer data format. The third data includes at least one Flit. The non-padding portion of the Flit's payload is extracted to form the fourth data. If there is only one Flit, the non-padding portion of the payload in that Flit constitutes the fourth data. The unpacking module 304 sends the fourth data to the system bus interface 301a. The system bus interface 301a asynchronously sends the fourth data to the system bus 310 according to the third clock signal.

[0100] In some embodiments, the third data transmitted by the physical layer 320a may be parallel data. For example, the third data may consist of multiple data segments, which are transmitted in parallel. For example, if the physical layer 320a has 16 data channels, the third data may include 16 data segments. Accordingly, the physical layer interface 303a receives 16 parallel data segments, and the depacketization module 304 depacketizes these 16 data segments to obtain serial fourth data.

[0101] Figure 3b A structural diagram of another data link layer provided according to at least one embodiment of the present disclosure is shown.

[0102] exist Figure 3b In

[15] , data link layer 300b communicates with system bus 310 and physical layer 320b. System bus 310 operates in the first clock domain, physical layer 320b operates in the second and third clock domains, and part of data link layer 300b operates in the third clock domain. The first, second, and third clock domains are all different. The first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal. The first, second, and third clock signals are asynchronous with each other.

[0103] Data link layer 300b includes a system bus interface 301a, a packetization module 302, a physical layer interface 303b, a depacketization module 304, and a local clock 305. System bus interface 301a is connected to system bus 310 and packetization module 302. Physical layer interface 303b is connected to packetization module 302 and physical layer 320b. Depacketization module 304 is connected to physical layer interface 303b and system bus interface 301a. Local clock 305 is connected to system bus interface 301a, packetization module 302, physical layer interface 303b, and depacketization module 304.

[0104] Figure 3b The reference numerals of some boxes are the same as Figure 3a The boxes in the same format represent the same components, see Figure 3a The relevant description will not be repeated here.

[0105] Figure 3b The difference lies in the physical layer interface 303b and the physical layer 320b. The packetization module 302 sends the second data to the physical layer interface 303b based on the third clock signal. The physical layer interface 303b then synchronously sends the second data to the physical layer 320b based on the third clock signal. In this embodiment, the physical layer interface 303b transparently transmits the second data, so the packetization module 302 can be considered to be directly connected to the physical layer 320b. Alternatively, when the physical layer 320b operates in both the second and third clock domains, the packetization module 302 can be directly connected to the physical layer 320b.

[0106] Figure 3c A structural diagram of another data link layer provided according to at least one embodiment of the present disclosure is shown.

[0107] exist Figure 3c In

[15] , data link layer 300c communicates with system bus 310 and physical layer 320a. System bus 310 operates in the first clock domain, physical layer 320a operates only in the second clock domain, and data link layer 300c partially operates in the third clock domain. The first clock domain, second clock domain, and third clock domain are all different. The first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal. The first clock signal, second clock signal, and third clock signal are asynchronous to each other.

[0108] Data link layer 300c includes a system bus interface 301c, a packet assembly module 302, a physical layer interface 303c, a depacketization module 304c, and a local clock 305. System bus interface 301c is connected to system bus 310 and packet assembly module 302. Physical layer interface 303c is connected to packet assembly module 302 and physical layer 320a. Depacketization module 304c is connected to physical layer interface 303c and system bus interface 301c. Local clock 305 is connected to system bus interface 301c, packet assembly module 302, and physical layer interface 303c.

[0109] Figure 3c The reference numerals of some boxes are the same as Figure 3a or Figure 3b The boxes in the same format represent the same components, see Figure 3a and Figure 3b The relevant description will not be repeated here.

[0110] Figure 3c The differences lie in the system bus interface 301c, the physical layer interface 303c, and the depacketization module 304c. The physical layer interface 303c asynchronously receives the third data from the physical layer 320a according to the first clock signal. The depacketization module 304c obtains the third data from the physical layer interface 303c according to the first clock signal and depacketizes the third data according to the first clock signal to obtain the fourth data. The depacketization module 304c sends the fourth data to the system bus interface 301c according to the first clock signal. The system bus interface 301c then synchronously sends the fourth data to the system bus 310 according to the first clock signal. In this embodiment, the system bus interface 301c transparently transmits the fourth data, so the depacketization module 304c can be considered to be directly connected to the system bus 310. Optionally, when the depacketization module 304c operates according to the first clock signal, the depacketization module 304c can be directly connected to the system bus 310. Figure 3d A structural diagram of another data link layer provided according to at least one embodiment of the present disclosure is shown.

[0111] exist Figure 3d In [1], data link layer 300d communicates with system bus 310 and physical layer 320b. System bus 310 operates in the first clock domain, physical layer 320b operates in the second and third clock domains, and part of data link layer 300d operates in the third clock domain. The first, second, and third clock domains are all different. The first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal. The first, second, and third clock signals are asynchronous with each other.

[0112] Data link layer 300d includes a system bus interface 301c, a packetization module 302, a physical layer interface 303d, a depacketization module 304c, and a local clock 305. System bus interface 301c is connected to system bus 310 and packetization module 302. Physical layer interface 303d is connected to packetization module 302 and physical layer 320b. Depacketization module 304c is connected to physical layer interface 303d and system bus interface 301c. Local clock 305 is connected to system bus interface 301c, packetization module 302, and physical layer interface 303d.

[0113] Figure 3d The reference numerals of some boxes are the same as Figure 3a 、 Figure 3b or Figure 3c The boxes in the same format represent the same components, see Figure 3a-3c The relevant description will not be repeated here.

[0114] Figure 3d and Figure 3c The difference lies in the physical layer interface 303d and the physical layer 320b. The packetization module 302 sends the second data to the physical layer interface 303d according to the third clock signal, and the physical layer interface 303d sends the second data to the physical layer 320b synchronously according to the third clock signal.

[0115] Figure 4a Another structural diagram of a data link layer provided according to at least one embodiment of the present disclosure is shown.

[0116] The data link layer 400 communicates with the system bus 310 and the physical layer 320a. The system bus 310 operates in a first clock domain, the physical layer 320a operates in a second clock domain, and part of the data link layer 400 operates in a third clock domain. The first clock domain is different from the second and third clock domains. The first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal.

[0117] Data link layer 400 adds several components to data link layer 300a. It includes a system bus interface 301a, a packet assembly module 302, a physical layer interface 303a, a depacketization module 304, a local clock 305, a first buffer memory 306, a second buffer memory 307, and a data detection module 308. The system bus interface 301a connects to the system bus 310 and the packet assembly module 302. The physical layer interface 303a connects to the packet assembly module 302 and the physical layer 320a. The depacketization module 304 connects to the data detection module 308 and the system bus interface 301a. The local clock 305 connects to the system bus interface 301a, the packet assembly module 302, the physical layer interface 303a, the depacketization module 304, the first buffer memory 306, and the data detection module 308. The data detection module 308 connects to the second buffer memory 307, which is part of the physical layer interface 303a.

[0118] Figure 4a In the figure, the dotted line indicates that the first buffer memory 306 is connected to the system bus interface 301 a or the packet assembly module 302 .

[0119] The description of the system bus interface 301a, the packet assembly module 302, the depacketization module 304 and the local clock 305 can be found in Figure 3a The relevant description is not expanded here.

[0120] The first buffer memory 306 is used to store the first data for backup. In this embodiment, the first buffer memory 306 can be accessed based on the third clock signal. The first data can be stored in the first buffer memory 306 by the system bus interface 301a or the packaging module 302. The first buffer memory 306 can be any memory and is not limited herein. The first buffer memory 306 can also store second data. For example, after obtaining the second data, the packaging module 302 stores the second data in the first buffer memory 306.

[0121] In this embodiment, the system bus interface 301a can be implemented using an asynchronous FIFO memory, thereby enabling asynchronous data transmission. Alternatively, the system bus interface 301a can also be implemented using a multi-stage synchronizer, a handshake protocol, or the like.

[0122] The physical layer interface 303a synchronously receives third data from the physical layer 320a based on the second clock signal. The third data is sent by the physical layer 320a based on the second clock signal. In this embodiment, after receiving the third data, the physical layer interface 303a saves the data to the second buffer memory 307. For example, the physical layer interface 303a writes the third data to the second buffer memory 307 based on the second clock signal. The second buffer memory 307 may be an asynchronous FIFO memory, such as an asynchronous elastic FIFO memory. The read pointer and write pointer of the asynchronous elastic FIFO memory have a tracking relationship, for example, the read pointer and write pointer are fixedly separated by a preset number of storage spaces. For example, the read pointer points to the second entry and the write pointer points to the fourth entry. When the write pointer moves to the fifth entry, the read pointer moves to the third entry and reads the data stored in the third entry. Optionally, the second buffer memory 307 may be replaced with a multi-stage synchronizer or implemented using a handshake protocol.

[0123] In this embodiment, one end of the second buffer memory 307 for writing data belongs to the second clock domain, and one end for reading data belongs to the third clock domain. Therefore, after the third data is written into the second buffer memory 307 and read out, the third data completes the conversion from the second clock domain to the third clock domain.

[0124] Optionally, the physical layer interface 303a includes a data alignment module connected between the second buffer memory 307 and the physical layer 320a. The data alignment module operates in the second clock domain. The data alignment module is used to locate the third data within the data signal, or in other words, to find the third data from the data signal. For example, the data alignment module determines the starting position of the third data based on header information or an identifier, thereby obtaining the third data. The data alignment module receives the third data from the physical layer 320a synchronously based on the second clock signal.

[0125] In some embodiments, when parallel data transmission is used between cores, data belonging to the same command or operation is divided into multiple data segments, and the multiple data segments are transmitted in parallel by the physical layer. For example, if the physical layer has 16 data channels, the third data may be divided into 16 data segments and transmitted in each of the 16 data channels. Therefore, the third data transmitted by the physical layer 320a may include multiple data segments.

[0126] Optionally, before receiving the third data, physical layer interface 303a may further determine data segments of the third data from the data signal sent by physical layer 320a based on the second clock signal, where the third data consists of multiple data segments. Physical layer interface 303a obtains the multiple data segments based on the second clock signal and stores the multiple data segments in second buffer memory 307 based on the second clock signal.

[0127] For example, the physical layer interface 303a includes multiple data alignment modules, and the multiple data segments are sent to the multiple data alignment modules in parallel by the physical layer 320a. Each of the multiple data alignment modules sends one of the multiple data segments to the second buffer memory. For example, when there are multiple second buffer memories, the multiple data segments are sent to the multiple second buffer memories in a one-to-one correspondence. Alternatively, when there is only one second buffer memory, the multiple data segments are sent to different storage areas of the same second buffer memory, each storage area including multiple storage spaces, each of which can store one data segment.

[0128] The data detection module 308 accesses the second buffer memory 307 based on the third clock signal. The data detection module 308 detects the data segments in the second buffer memory 307. If multiple data segments constituting the third data are detected, the data detection module 308 sends the multiple data segments to the depacketization module 304. If multiple data segments constituting the third data are not detected, the data detection module 308 adjusts the second buffer memory 307 to obtain multiple data segments. For example, the module adjusts the relative relationship between the read and write pointers of the second buffer memory 307, adjusts the value of the read pointer alone, or adjusts the value of the write pointer alone. Alternatively, this adjustment function can be implemented by a separate module, such as an adjustment module. The data detection module 308 only detects whether the multiple data segments obtained this time constitute the multiple data segments of the third data. If the detection result is negative, the module issues an instruction to the adjustment module to adjust the second buffer memory. Further, optionally, the detection function of the data detection module 308 is only used during the data link training phase. After the data link training is completed, the data detection module 308 performs a transparent transmission operation and sends the third data or the multiple data segments constituting the third data to the depacketization module 304.

[0129] Optionally, the data link layer may further include a loopback test module. The loopback test module is connected to the physical layer interface and the packet assembly module, and is configured to perform a loopback test on multiple data paths corresponding to the data link layer according to a third clock signal, wherein the multiple data paths are connected to the data link layer via the physical layer. For example, the loopback test module includes a loopback test generator and a loopback test checker, the loopback test generator is connected to the packet assembly module, and the loopback test checker is connected to the physical layer interface, wherein the loopback test transmitter is configured to generate at least one test data according to a preset loopback test data pattern, and provide the at least one test data to the physical layer via the packet assembly module and the physical layer interface according to the third clock signal, so as to be sent to the multiple data paths; the loopback test checker is configured to receive at least one test return data from the physical layer via the physical layer interface according to the third clock signal, wherein the at least one test return data corresponds one-to-one with the at least one test data, and detect the at least one test return data according to the loopback test data pattern to complete the loopback test. For example, the loopback test generator is connected to the local clock 305 and the packetization module 302 , and the loopback test checker is connected to the local clock 305 and the second buffer memory 307 .

[0130] like Figure 4a The first buffer memory 306 in the embodiment can also be applied to Figure 3a-3d In the data link layer. Figure 4a The implementation of the depacketizing module 304, the data detecting module 308 and the second buffer memory 307 can also be adaptively applied to the following examples: Figure 3a-3d in the data link layer.

[0131] Figure 4b Another structural diagram of a data link layer provided according to at least one embodiment of the present disclosure is shown.

[0132] The implementation of the depacketizing module 304, the data detecting module 308 and the second buffer memory 307 can also be adaptively implemented as follows: Figure 3c The data link layer can be obtained Figure 4b structure.

[0133] exist Figure 4b In the embodiment, the data link layer 410 includes a system bus interface 301c, a packet assembly module 302, a physical layer interface 303c, a depacketization module 304c, a second buffer memory 307c and a data detection module 308c. The depacketization module 304c, the second buffer memory 307c and the data detection module 308c are connected to the system bus interface 301c, the packet assembly module 302, the physical layer interface 303c, the depacketization module 304c, the second buffer memory 307c and the data detection module 308c. Figure 4a The difference between the depacketization module 304, the second buffer memory 307 and the data detection module 308 is that they work in the first clock domain, that is, they do not use the third clock signal but use the first clock signal. The description of the remaining modules or components of the data link layer 410 can be found in Figure 3c and Figure 4a , I will not go into details here.

[0134] Figure 5 Another structural diagram of a data link layer provided according to at least one embodiment of the present disclosure is shown.

[0135] The data link layer 500 communicates with the system bus 310 and the physical layer 320a. The data link layer 500 is similar to the data link layer 400, except that the data link layer 500 includes a loopback generator 309 and a loopback checker 310.

[0136] The loopback test generator 309 is connected to the local clock 305 and the packet assembly module 302. The loopback test checker 310 is connected to the physical layer interface 303a or directly to the second buffer memory 307. The loopback test checker 310 is also connected to the local clock 305. Both the loopback test generator 309 and the loopback test checker 310 operate in the third clock domain.

[0137] The loopback test generator 309 and loopback test checker 310 can operate during the pre-shipment testing phase of a chip. They collaborate to check for issues with multiple data links within the chip. For example, the loopback test generator 309 generates test data in the same format as the first data. The packetization module 302 performs packetization on the test data and provides the processed test data to the physical layer 320a. The physical layer 320a sends the packetized test data to multiple data paths and then to the test equipment. The test equipment provides feedback on the test data. The physical layer 320a receives test return data via multiple data paths. The test return data passes through the physical layer interface 303a and arrives at the loopback test checker 310. The loopback test checker 310 then performs a test on the test return data to determine whether there are any data link issues and which data link the issue is affecting. During normal operation, the loopback test generator 309 and loopback test checker 310 are inactive.

[0138] In this embodiment, both the loopback test checker 310 and the data detection module 308 can access the second buffer memory 307. The second buffer memory 307 differs from other modules in that it operates in either the first or third clock domain, depending on the clock signal used when it is accessed. Because data reading from the second buffer memory 307 is accomplished by accessing the read pointer, and the "access" operation depends on the edge of the clock signal, either the first or third clock signal can be used for access. Therefore, the clock domain in which the second buffer memory 307 operates is not fixed.

[0139] Optionally, at least one embodiment of the present disclosure further provides a chiplet interconnect interface configured to execute any one of the methods in the above method embodiments.

[0140] Optionally, at least one embodiment of the present disclosure further provides a chiplet interconnection interface, including a data link layer as in the above-mentioned device embodiment.

[0141] Figure 6 A schematic diagram of a chip provided by at least one embodiment of the present disclosure is shown.

[0142] exist Figure 6 In FIG, chip 600 includes a core 610 and a core 620. Core 610 includes a data link layer 611 and a physical layer 612, and core 620 includes a data link layer 621 and a physical layer 622. Physical layer 612 is connected to physical layer 622, thereby realizing the interconnection between core 620 and core 610.

[0143] At least one embodiment of the present disclosure provides an electronic device, including the chip as described in the above embodiments.

[0144] Figure 7 A schematic diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0145] The electronic device 700 includes a chip 701. The chip 701 is, for example, Figure 6 The chip 600 is shown. The electronic device 700 can be any device with computing function, such as a computer, a server, a smart phone, a tablet computer, etc., and the embodiments of the present disclosure are not limited thereto.

[0146] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of this application. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit this application to necessarily being implemented using the above specific details.

[0147] It is worth noting that the step flow charts and the above method descriptions in this application are only illustrative examples and are not intended to require or imply that the steps of each embodiment must be performed in the order given. Some steps can be performed in parallel, independently of each other, or in other appropriate orders. In addition, words such as "secondly," "then," "next," etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods.

[0148] The block diagrams of the devices, apparatuses, equipment, and systems described in this application are intended only as illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. It should also be noted that in the apparatuses and methods of this application, the components or steps may be decomposed and / or recombined. Such decompositions and / or recombinations shall be considered equivalents of this application.

[0149] The following points need to be explained: (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures can refer to the general design. (2) In the absence of conflict, the embodiments of the present disclosure and the features therein can be combined with each other to obtain new embodiments. The above description is only an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A data transmission method, applied to the data link layer of a chiplet interconnection interface, wherein: The data link layer communicates with a system bus and a physical layer, wherein the system bus operates in a first clock domain, and the physical layer operates in a second clock domain and a third clock domain, and the method includes: The data link layer performs packet processing on first data received from the system bus to obtain second data, and provides the second data to the physical layer; or the data link layer performs depacketization on third data received from the physical layer to obtain fourth data, and provides the fourth data to the system bus. The data link layer partially operates in the third clock domain and partially operates in the first clock domain, and the first clock domain is different from the second clock domain and the third clock domain, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, and the third clock domain includes a third clock signal, and Before the data link layer performs packet processing on the first data received from the system bus to obtain second data, the method further includes: The data link layer asynchronously receives the first data from the system bus according to the third clock signal, wherein the first data is sent by the system bus according to the first clock signal; The providing the second data to the physical layer comprises: the data link layer synchronously providing the second data to the physical layer according to the third clock signal; and Providing the fourth data to the system bus includes: the data link layer synchronously providing the fourth data to the system bus according to the first clock signal.

2. The method according to claim 1, wherein Before the data link layer depacketizes the third data received from the physical layer to obtain the fourth data, the method further includes: The data link layer obtains the third data from the physical layer according to the third clock signal; or In a case where the data link layer still partially operates in the first clock domain, the data link layer obtains the third data from the physical layer according to the first clock signal; or In a case where the data link layer also partially operates in the second clock domain, the data link layer obtains the third data from the physical layer according to the second clock signal; The third data is sent by the physical layer according to the second clock signal.

3. The method according to claim 1, wherein The data link layer performs packet processing on the first data received from the system bus to obtain second data, including: The data link layer performs packetization processing on the first data according to the third clock signal to obtain the second data.

4. The method according to claim 1, wherein The providing the second data to the physical layer further comprises: The data link layer asynchronously provides the second data to the physical layer according to the third clock signal.

5. The method according to claim 2, wherein: The data link layer depacketizing the third data received from the physical layer to obtain fourth data, including: When the data link layer obtains the third data according to the first clock signal, the data link layer unpacks the third data according to the first clock signal to obtain the fourth data; When the data link layer obtains the third data according to the third clock signal, the data link layer unpacks the third data according to the third clock signal to obtain the fourth data.

6. The method according to claim 2, wherein: The data link layer acquiring the third data from the physical layer according to the third clock signal includes: the data link layer asynchronously receiving the third data from the physical layer according to the third clock signal; or The data link layer acquiring the third data from the physical layer according to the first clock signal includes: the data link layer asynchronously receiving the third data from the physical layer according to the first clock signal; or The data link layer acquiring the third data from the physical layer according to the second clock signal includes: the data link layer synchronously receiving the third data from the physical layer according to the second clock signal.

7. The method according to claim 6, wherein: The data link layer receives the third data from the physical layer according to the second clock signal, including: the data link layer determines and receives multiple data segments of the third data from the data signal sent by the physical layer according to the second clock signal, wherein the third data is composed of the multiple data segments.

8. The method according to claim 7, wherein: After receiving the plurality of data segments, the method further comprises: The data link layer asynchronously obtains the multiple data segments according to the first clock signal, or the data link layer asynchronously obtains the multiple data segments according to the third clock signal, so that the third data enters the first clock domain or the third clock domain.

9. The method according to claim 6, wherein: The data link layer asynchronously receives the third data from the physical layer according to the first clock signal, comprising: the data link layer asynchronously receives multiple data segments of the third data according to the first clock signal; or The data link layer asynchronously receives the third data from the physical layer according to the third clock signal, comprising: the data link layer asynchronously receiving a plurality of data segments of the third data according to the third clock signal; The third data is composed of the multiple data segments.

10. The method according to claim 1, wherein The providing the fourth data to the system bus further includes: The data link layer asynchronously provides the fourth data to the system bus according to the third clock signal.

11. The method according to claim 1, wherein The method further comprises: The data link layer performs a loopback test on a plurality of data paths corresponding to the data link layer according to the third clock signal, wherein the plurality of data paths are connected to the data link layer via the physical layer.

12. The method according to claim 11, wherein The data link layer performs a loopback test on a plurality of data paths corresponding to the data link layer according to the third clock signal, including: The data link layer generates at least one test data according to a preset loopback test data pattern; The data link layer sends the at least one test data to the physical layer asynchronously or synchronously according to the third clock signal, so as to send the test data to the plurality of data paths; The data link layer obtains at least one test return data from the physical layer according to the first clock signal, the second clock signal or the third clock signal, where the at least one test return data corresponds one-to-one to the at least one test data; The data link layer detects the at least one test return data according to the loopback test data pattern to complete the loopback test.

13. A data link layer, applied to a chip interconnection interface, wherein: The data link layer communicates with the system bus and the physical layer, the system bus operates in the first clock domain, the physical layer operates in the second clock domain and the third clock domain, the data link layer partially operates in the third clock domain and partially operates in the first clock domain, and the data link layer includes: a system bus interface connected to the system bus and configured to receive first data from the system bus; a packet assembly module connected to the system bus interface and configured to perform packet assembly on the first data to obtain second data; a physical layer interface connected to the packetization module and the physical layer, and configured to provide the second data to the physical layer and obtain third data from the physical layer; a depacketizing module connected to the physical layer interface and configured to depacketize the third data to obtain fourth data, wherein the fourth data is provided to the system bus by the depacketizing module or the system bus interface; and a local clock connected to the system bus interface, the packet assembly module, the depacketization module, and the physical layer interface, and configured to generate a third clock signal included in the third clock domain; The first clock domain, the second clock domain and the third clock domain are all different, the first clock domain includes a first clock signal, the second clock domain includes a second clock signal, Before performing packet processing on the first data to obtain the second data, the system bus interface is further configured to asynchronously receive the first data from the system bus according to the third clock signal, wherein the first data is sent by the system bus according to the first clock signal. When providing the second data to the physical layer, the physical layer interface is further configured to asynchronously provide the second data to the physical layer according to the third clock signal, and When providing the fourth data to the system bus, the depacketizing module or the system bus interface is further configured to synchronously provide the fourth data to the system bus according to the first clock signal.

14. The data link layer according to claim 13, wherein: The physical layer interface is further configured to obtain third data from the physical layer according to the third clock signal; or, In a case where the data link layer also partially operates in the first clock domain, the physical layer interface is further configured to obtain the third data from the physical layer according to the first clock signal; or In a case where the data link layer also partially operates in the second clock domain, the physical layer interface is further configured to obtain the third data from the physical layer according to the second clock signal; The third data is sent by the physical layer according to the second clock signal.

15. The data link layer according to claim 13, wherein: The packetizing module is configured to perform packetizing processing on the first data according to the third clock signal to obtain the second data.

16. The data link layer according to claim 13, wherein: The physical layer interface is further configured to asynchronously provide the second data to the physical layer according to the third clock signal.

17. The data link layer according to claim 14, wherein: The unpacking module is configured to, when the third data is obtained according to the first clock signal, unpack the third data according to the first clock signal to obtain the fourth data; and, when the third data is obtained according to the third clock signal, unpack the third data according to the third clock signal to obtain the fourth data.

18. The data link layer according to claim 14, wherein: The physical layer interface is configured to: asynchronously receive the third data from the physical layer according to the first clock signal; or, asynchronously receive the third data from the physical layer according to the third clock signal; or, synchronously receive the third data from the physical layer according to the second clock signal.

19. The data link layer according to claim 18, wherein: The physical layer interface is further configured to determine and receive a plurality of data segments of the third data from the data signal sent by the physical layer according to the second clock signal, wherein the third data is composed of the plurality of data segments.

20. The data link layer according to claim 19, wherein: The physical layer interface is also configured to, after receiving the multiple data segments, asynchronously obtain the multiple data segments according to the first clock signal, or asynchronously obtain the multiple data segments according to the third clock signal, so that the third data enters the first clock domain or the third clock domain.

21. The data link layer according to claim 18, wherein: The physical layer interface is configured to asynchronously receive multiple data segments of the third data according to the first clock signal, or asynchronously receive multiple data segments of the third data according to the third clock signal, wherein the third data is composed of the multiple data segments.

22. The data link layer according to claim 13, wherein: The depacketizing module or the system bus interface is further configured to: The fourth data is asynchronously provided to the system bus according to the third clock signal.

23. The data link layer according to claim 13, wherein: The data link layer further includes a first buffer memory connected to the system bus interface or the packet assembly module and configured to store the first data according to the third clock signal.

24. The data link layer according to claim 13, wherein: The data link layer also partially operates in the first clock domain and the second clock domain, or the data link layer also partially operates in the second clock domain, and the physical layer interface includes a second buffer memory, which is connected to the physical layer and the depacketization module and is configured to perform a write operation according to the second clock signal and a read operation according to the first clock signal or the third clock signal, wherein the second buffer memory stores the third data in the form of data segments.

25. The data link layer according to claim 24, wherein: The data link layer also includes: A data detection module is connected to the unpacking module and the second buffer memory, and is configured to detect the data segments in the second buffer memory, and when multiple data segments constituting the third data are detected, send the multiple data segments to the unpacking module; and when the multiple data segments constituting the third data are not detected, adjust the second buffer memory to obtain the multiple data segments.

26. The data link layer according to claim 13, wherein: The data link layer also includes: A loopback test module is connected to the physical layer interface and the packet assembly module, and is configured to perform a loopback test on multiple data paths corresponding to the data link layer according to the third clock signal, wherein the multiple data paths are connected to the data link layer via the physical layer.

27. The data link layer according to claim 26, wherein: The loopback test module includes a loopback test generator and a loopback test checker, wherein the loopback test generator is connected to the packet assembly module, and the loopback test checker is connected to the physical layer interface, wherein: The loopback test transmitter is configured to generate at least one test data according to a preset loopback test data pattern, and provide the at least one test data to the physical layer via the packetization module and the physical layer interface according to the third clock signal, so as to be sent to the multiple data paths; The loopback test checker is configured to receive at least one test return data from the physical layer via the physical layer interface according to the third clock signal, the at least one test return data corresponding one-to-one to the at least one test data, and detect the at least one test return data according to the loopback test data pattern to complete the loopback test.

28. The data link layer according to claim 13, wherein: The system bus interface is implemented using an asynchronous FIFO memory.

29. The data link layer according to claim 24, wherein: The second buffer memory is an asynchronous elastic FIFO memory.

30. A chiplet interconnection interface comprising the data link layer according to any one of claims 13 to 29.

31. A chip comprising a plurality of core particles, wherein: Any two of the plurality of core particles are connected via the core particle interconnection interface according to claim 30.

32. An electronic device comprising the chip according to claim 31.

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