Display panel and mobile terminal

Abstract

The present application discloses a display panel and a mobile terminal; the display panel includes a gate drive circuit, the gate drive circuit includes a first drive transistor and a second drive transistor arranged along a first direction, the first drive transistor includes a first source and a first drain, the second drive transistor includes a second source and a second drain, the first source and the second source are connected to the same control node, the first source, the first drain, the second source and the second drain are all arranged in parallel along the first direction, and the first source and the second source are arranged between the first drain and the second drain, and the first source and the second source at least partially overlap in the second direction; the present application reduces the size of the first drive transistor and the second drive transistor in the first direction by making the first source and the second source at least partially overlap in the second direction, so as to reserve some longitudinal space for arranging other devices, thereby improving the technical problem of the excessive longitudinal size of the gate drive circuit in the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a mobile terminal. Background Art

[0002] In existing display products, such as liquid crystal displays, organic light-emitting displays, and Mini LED and Micro LED displays, a gate drive circuit (Gate On Array, GOA) is generally used to transmit gate drive signals to sub-pixels in the display area to control the light emission of the sub-pixels.

[0003] Currently, commonly used drive architectures in gate drive circuits include the Tri-Gate drive architecture and the Data Line Sharing (DLS) drive architecture. Compared with conventional drive architectures, these two drive architectures can save certain costs, but the corresponding increase in the number of GOA units makes the vertical size of the gate drive circuit too large. Summary of the Invention

[0004] The present application provides a display panel and a mobile terminal to solve the technical problem that the vertical dimension of the gate driving circuit in the current display panel is too large.

[0005] To solve the above problem, the technical solution provided by this application is as follows:

[0006] The present application provides a display panel, characterized in that it includes a gate driving circuit along a display portion and arranged on one side of the display portion, the gate driving circuit includes N cascaded GOA units, the N GOA units are arranged along a first direction, and each of the GOA units includes a first driving transistor and a second driving transistor arranged adjacent to each other along a second direction;

[0007] The first driving transistor includes a first gate, a first source, and a first drain, and the second driving transistor includes a second gate, a second source, and a second drain, the first gate and the second gate are connected to a first control node, and the first source and the second source are connected to a second control node;

[0008] The first source, the first drain, the second source and the second drain are all arranged in parallel along the first direction, and the first source and the second source are arranged between the first drain and the second drain, the first source and the second source at least partially overlap in the second direction, and the angle between the second direction and the first direction is greater than 0° and less than or equal to 90°.

[0009] In the display panel of the present application, each of the GOA units includes a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintaining module, and the pull-up control module, the pull-up module, the pull-down module, and the pull-down maintaining module are all connected to the first control node;

[0010] The first driving transistor and the second driving transistor are arranged in the pull-down maintaining module.

[0011] In the display panel of the present application, the first source electrode includes a first main source electrode and a plurality of first branch source electrodes connected to the first main source electrode and spaced apart from each other; the second source electrode includes a second main source electrode and a plurality of second branch source electrodes connected to the second main source electrode and spaced apart from each other; the first main source electrode and the second main source electrode extend along the second direction; the plurality of first branch source electrodes and the plurality of second branch source electrodes extend along the first direction; and the first branch source electrodes and the second branch source electrodes have different orientations;

[0012] In which, the GOA unit also includes a source connection portion extending along the first direction, the source connection portion is arranged between the first source and the second source, and the first end of the source connection portion is electrically connected to the end of the first main source close to the second branch source, and the second end of the source connection portion is electrically connected to the end of the second main source close to the first branch source.

[0013] In the display panel of the present application, in the first direction, the width of the source connection portion is greater than the width of the first branch source, and the width of the source connection portion is greater than the width of the second branch source.

[0014] In the display panel of the present application, the first drain includes a first main drain and a plurality of first branch drains connected to the first main drain and spaced apart; the second drain includes a second main drain and a plurality of second branch drains connected to the second main drain and spaced apart; the first main drain and the second main drain extend along the second direction; the plurality of first branch drains extend from the first main drain toward the first main source; the plurality of second branch drains extend from the second main drain toward the second main source; the plurality of first branch drains and the plurality of first branch sources are alternately and sequentially spaced apart; and the plurality of second branch drains and the plurality of second branch sources are alternately and sequentially spaced apart;

[0015] The first driving transistor further includes a first channel, and the second driving transistor further includes a second channel. The first channel covers the gaps between the first branch drains and the first branch sources, and the second channel covers the gaps between the second branch drains and the second branch sources.

[0016] In the display panel of the present application, the first gate and the second gate both extend along the second direction, and the orthographic projections of the first channel, the first source and part of the first drain on the first gate are located within the first gate, and the orthographic projections of the second channel, the second source and part of the second drain on the second gate are located within the first gate.

[0017] In the display panel of the present application, the first low-potential line is located on a side of the first driving transistor away from the second driving transistor, and the first low-potential line extends along the first direction;

[0018] The display panel further includes a connecting segment, a first end of the connecting segment is electrically connected to the first main source electrode in the first source electrode, and a second end of the connecting segment is electrically connected to the first low-potential line.

[0019] In the display panel of the present application, the pull-down maintaining module further includes a third driving transistor and a fourth driving transistor connected to the first control node, the third driving transistor and the fourth driving transistor are adjacently arranged along the first direction, and the third driving transistor and the fourth driving transistor are located on a side of the second driving transistor away from the first driving transistor;

[0020] The third driving transistor includes a third channel, the fourth driving transistor includes a fourth channel, and the third channel and the fourth channel are arranged opposite to each other along the first direction.

[0021] In the display panel of the present application, the first driving transistor further includes a first channel, the second driving transistor further includes a second channel, and the length of the first channel and / or the second channel is smaller than the length of the third channel and the fourth channel.

[0022] The present application also proposes a mobile terminal, which includes the above-mentioned display panel.

[0023] Beneficial effects: The present application discloses a display panel and a mobile terminal; the display panel includes a gate drive circuit, the gate drive circuit includes a first drive transistor and a second drive transistor arranged along a first direction, the first drive transistor includes a first source and a first drain, the second drive transistor includes a second source and a second drain, the first source and the second source are connected to the same control node, the first source, the first drain, the second source and the second drain are all arranged in parallel along the first direction, and the first source and the second source are arranged between the first drain and the second drain, and the first source and the second source at least partially overlap in the second direction; the present application reduces the size of the first drive transistor and the second drive transistor in the first direction by making the first source and the second source at least partially overlap in the second direction, so as to reserve some longitudinal space for arranging other devices, thereby improving the technical problem of the excessive longitudinal size of the gate drive circuit in the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0025] Figure 1 A simplified structural diagram of the display panel of this application;

[0026] Figure 2 This is the circuit structure diagram of the GOA unit in the display panel of this application

[0027] Figure 3 This is a diagram showing the stacking structure of some film layers in the display panel of this application;

[0028] Figure 4 Patterning the film stack of the first drive transistor and the second drive transistor in the GOA unit of the present application;

[0029] Figure 5 The film stack of the third and fourth driver transistors in the GOA unit of the present application is patterned. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0031] See also Figures 1 to 5The present application proposes a display panel 100, which may include a display portion 200 and a gate driving circuit 300. The gate driving circuit 300 includes N cascaded GOA units 400. The N GOA units 400 are arranged along a first direction Y, and the display portion 200 and the gate driving circuit 300 are arranged along a second direction X.

[0032] In this embodiment, each GOA unit 400 may include a first driving transistor and a second driving transistor that are adjacent to each other, and the first driving transistor and the second driving transistor are arranged along a first direction Y.

[0033] In this embodiment, the first driving transistor T52 includes a first gate 210, a first source 220 and a first drain 230, and the second driving transistor T62 includes a second gate 310, a second source 320 and a second drain 330; the first gate 210 and the second gate 310 are connected to the first control node Q, and the first source 220 and the second source 320 are connected to the second control node.

[0034] In this embodiment, the second control node can be connected to a low potential line or a high potential line, for example Figure 4 The second control node is connected to the first low potential line VSSQ.

[0035] In this embodiment, the first source 220, the first drain 230, the second source 320 and the second drain 330 are all arranged along the first direction Y, and the first source 220 and the second source 320 are arranged between the first drain 230 and the second drain 330, and the first source 220 and the second source 320 at least partially overlap in the second direction X.

[0036] The present application reduces the size of the first driving transistor and the second driving transistor in the first direction Y by making the first source 220 and the second source 320 at least partially overlap in the second direction X, thereby reserving some longitudinal space for arranging other devices, thereby improving the technical problem of the gate driving circuit 300 in the display panel 100 being too large in the longitudinal direction.

[0037] It should be noted that the angle between the second direction X and the first direction Y is greater than 0° and less than or equal to 90°; for example, the second direction X and the first direction Y may be perpendicular, the first direction Y may be parallel to the scan line of the display panel 100, and N is a positive integer.

[0038] It should be noted that the first driving transistor further includes a first channel 240 , and the second driving transistor further includes a second channel 340 . In the second direction X, the first channel 240 and the second channel 240 at least partially overlap.

[0039] In this embodiment, each GOA unit 400 may include a pull-up control module 410, a pull-up module 420, a pull-down module 430, and a pull-down maintaining module 440. The pull-up control module 410, the pull-up module 420, the pull-down module 430, and the pull-down maintaining module 440 are all connected to a first control node Q. The first driver transistor and the second driver transistor may be two transistors of any one of the pull-up control module 410, the pull-up module 420, the pull-down module 430, and the pull-down maintaining module 440.

[0040] Alternatively, the display unit 200 may include a plurality of sub-pixel units, each of which includes a pixel circuit, and the first driving transistor and the second driving transistor may be disposed in the pixel circuit to reduce the space occupied by the driving transistors in the pixel circuit in each sub-pixel unit.

[0041] In this embodiment, the first driving transistor T52 and the second driving transistor T62 are disposed in the pull-down maintaining module 440, and the first driving transistor T52 and the second driving transistor T62 are connected to the first control node Q. In this application, by reducing the channel width of the first driving transistor T52 and the second driving transistor T62 connected to the first control node Q, that is, equivalent to reducing the size of the first driving transistor T52 and the second driving transistor T62 in the second direction X, the first source 220 and the second source 320 can partially overlap in the second direction X, thereby reducing the size of the first driving transistor T52 and the second driving transistor T62 in the first direction Y, reserving some longitudinal space for arranging other components, and improving the technical problem of the gate driving circuit 300 in the display panel 100 being too large in the longitudinal direction.

[0042] The technical solution of the present application will now be described in conjunction with a specific embodiment, taking the example of the first driving transistor T52 and the second driving transistor T62 being disposed in the pull-down maintaining module 440 .

[0043] See also Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA is provided with a display portion 200. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used to perform the display function, and is provided with multiple display units to achieve this display function. The non-display area NA may be a frame area of ​​the display panel 100, and may be provided with functional components that assist the display units in the display area AA in performing display functions.

[0044] See also Figure 1The lower side of the display area AA is provided with a binding terminal 500. The binding terminal 500 can be connected to an external circuit and transmits the signal input from the external circuit to the data line, thereby driving the display panel 100 to display the image. For example, the binding terminal 500 can be bound and connected to a chip or a flexible circuit board to provide power and driving signals to the display panel 100.

[0045] In this embodiment, the gate driving circuit 300 is disposed in the non-display area NA, and the gate driving circuit 300 can be disposed on both sides of the display area AA; the gate driving circuit 300 can include N cascaded GOA units 400, and the N GOA units 400 can be arranged along the second direction X. The structure of the GOA unit 400 can be various, for example Figure 2 The circuit structure in .

[0046] by Figure 2 Taking the structure of as an example, each GOA unit 400 may include a pull-up control module 410, a pull-up module 420, a pull-down module 430, a pull-down maintaining module 440 and a bootstrap capacitor Cb.

[0047] In this embodiment, the pull-up control unit includes a pull-up control transistor T11, the gate and drain of the pull-up control transistor T11 are connected to the stage transmission signal output terminal STn-6 of the n-6th stage, and the source of the pull-up control transistor T11 is connected to the first control node Q.

[0048] In this embodiment, a first end of the bootstrap capacitor Cb is connected to the first control node Q, and a second end of the bootstrap capacitor Cb is connected to the gate signal terminal Gn of the nth stage and the pull-down maintaining module 440 .

[0049] In this embodiment, the pull-up module 420 includes a first pull-up transistor T21 and a second pull-up transistor T22, the gate of the first pull-up transistor T21 is connected to the first control node Q, the drain of the first pull-up transistor T21 is connected to the clock signal terminal CK, and the source of the first pull-up transistor T21 is connected to the gate signal terminal Gn of the nth stage; the gate of the second pull-up transistor T22 is connected to the first control node Q, the drain of the second pull-up transistor T22 is connected to the clock signal terminal CK, and the source of the second pull-up transistor T22 is connected to the stage transmission signal terminal STn of the nth stage.

[0050] In this embodiment, the pull-down module 430 includes a first pull-down transistor T31 and a second pull-down transistor T41, the drain of the first pull-down transistor T31 is connected to the gate signal terminal Gn of the nth level, the drain of the second pull-down transistor T41 is connected to the first control node Q, the source of the first pull-down transistor T31 is connected to the second low potential line VSSG, the source of the second pull-down transistor T41 is connected to the first low potential line VSSQ, the gate of the first pull-down transistor T31 is connected to the gate signal terminal Gn+6 of the n+6th level, and the gate of the second pull-down transistor T41 is connected to the gate signal terminal Gn+8 of the n+8th level.

[0051] It should be noted that the potentials of the first low potential line VSSQ and the second low potential line VSSG can be equal, or the potential of the first low potential line VSSQ can be less than or greater than the potential of the second low potential line VSSG, which is not limited in this application.

[0052] In this embodiment, the pull-down maintaining module 440 may include a first pull-down maintaining unit 441 and a second pull-down maintaining unit 442 .

[0053] The first pull-down sustaining unit 441 includes a first driving transistor T52, a third driving transistor T54, a fifth driving transistor T51, a seventh driving transistor T53, a ninth driving transistor T42, and an eleventh driving transistor T32. The second pull-down sustaining unit 442 includes a second driving transistor T62, a fourth driving transistor T64, a sixth driving transistor T61, an eighth driving transistor T63, a tenth driving transistor T43, and a twelfth driving transistor T33.

[0054] In this embodiment, the gate and drain of the fifth driving transistor T51 are connected to the first high-voltage DC signal terminal LC1, and the source of the fifth driving transistor T51 is electrically connected to the drain of the first driving transistor T52 and the gate of the seventh driving transistor T53. The gate of the first driving transistor T52 is electrically connected to the first control node Q, and the source of the first driving transistor T52 is electrically connected to the first low-potential line VSSQ. The drain of the seventh driving transistor T53 is connected to the first high-voltage DC signal terminal LC1, and the source of the seventh driving transistor T53 is electrically connected to the drain of the third driving transistor T54, the gate of the ninth driving transistor T42, and the gate of the eleventh driving transistor T32. The gate of the third driving transistor T54 is electrically connected to the first control node Q, and the source of the third driving transistor T54 is electrically connected to the first low-potential line VSSQ. The source of the ninth driving transistor T42 is electrically connected to the first low-potential line VSSQ, and the drain of the ninth driving transistor T42 is electrically connected to the first control node Q. The source of the eleventh driving transistor T32 is electrically connected to the second low potential line VSSG, and the drain of the eleventh driving transistor T32 is electrically connected to the gate signal terminal Gn of the n-th stage.

[0055] In this embodiment, the gate and drain of the sixth driving transistor T61 are connected to the second high-voltage DC signal terminal LC2, and the source of the sixth driving transistor T61 is electrically connected to the drain of the second driving transistor T62 and the gate of the eighth driving transistor T63. The gate of the second driving transistor T62 is electrically connected to the first control node Q, and the source of the second driving transistor T62 is electrically connected to the first low-potential line VSSQ. The drain of the eighth driving transistor T63 is connected to the second high-voltage DC signal terminal LC2, and the source of the eighth driving transistor T63 is electrically connected to the drain of the fourth driving transistor T64, the gate of the tenth driving transistor T43, and the gate of the twelfth driving transistor T33. The gate of the fourth driving transistor T64 is electrically connected to the first control node Q, and the source of the fourth driving transistor T64 is electrically connected to the first low-potential line VSSQ. The source of the tenth driving transistor T43 is electrically connected to the first low-potential line VSSQ, and the drain of the tenth driving transistor T43 is electrically connected to the first control node Q. A source of the twelfth driving transistor T33 is electrically connected to the second low potential line VSSG, and a drain of the twelfth driving transistor T33 is electrically connected to the gate signal terminal Gn of the n-th stage.

[0056] The following is for Figure 3 The structure of the display panel 100 of the present application is described.

[0057] See also Figure 3 The display area AA and the non-display area NA of the display panel 100 can both be provided with a base substrate 110 and an array driving layer 120 provided on the base substrate 110. The following mainly describes the film layer structure in the non-display area NA.

[0058] See also Figure 3 The array driving layer 120 may include a plurality of thin film transistors, which may be of an etch-stop type or a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, and other structures according to the position of the gate electrode and the active layer 123, or may be classified into an N-type thin film transistor or a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 3 The thin film transistor does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of the various film layers of the display panel 100 of the present application.

[0059] See also Figure 3The array driving layer 120 may include a gate layer 121 disposed on the base substrate 110, a gate insulating layer 122 disposed on the gate layer 121, an active layer 123 disposed on the gate insulating layer 122, an inter-insulating layer 124 disposed on the active layer 123, a source-drain layer 125 disposed on the inter-insulating layer 124, and a passivation layer 126 disposed on the source-drain layer 125.

[0060] In this embodiment, the gate insulating layer 122, the inter-insulating layer 124 and the passivation layer 126 are mainly used to isolate the electrical connection between the upper metal structure and the lower metal structure. The materials of the gate insulating layer 122, the inter-insulating layer 124 and the passivation layer 126 may include compounds composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0061] In this embodiment, the active layer 123 may include a channel 123a and doped portions 123b arranged on both sides of the channel. The material of the active layer 123 may be one of oxide semiconductor, amorphous silicon or low-temperature polycrystalline silicon. The material of the active layer 123 of the present application may be indium gallium zinc oxide semiconductor.

[0062] In this embodiment, the gate layer 121 may include a gate, a scan line and a voltage transmission line, and the source-drain layer 125 may include a source, a drain and a data line. The materials of the gate layer 121 and the source-drain layer 125 may be copper, molybdenum or molybdenum-titanium alloy.

[0063] It should be noted that Figure 3 The structure of the thin film transistor in is only one of those listed in this application, and other thin film transistor structures are also applicable to this application.

[0064] The technical solution of the present application is described below using the structures of the first driving transistor T52 and the second driving transistor T62.

[0065] See also Figure 4 The first drain 230 is connected to the first internal node M of the pull-down maintenance module 440 , and the second drain 330 is connected to the second internal node N of the pull-down maintenance module 440 .

[0066] See also Figure 4 The first source 220 includes a first main source 221 and a plurality of first branch sources 222 connected to the first main source 221 and spaced apart. The second source 320 includes a second main source 321 and a plurality of second branch sources 322 connected to the second main source 321 and spaced apart. The first main source 221 and the second main source 321 extend along the second direction X, and the plurality of first branch sources 222 and the plurality of second branch sources 322 extend along the first direction Y. The first branch source 222 and the second branch source 322 have different orientations.

[0067] See also Figure 4 The first source 220 and the second source 320 are arranged in parallel along the second direction X, and the GOA unit 400 further includes a source connection portion 250 extending along the first direction Y, the source connection portion 250 is arranged between the first source 220 and the second source 320, and a first end of the source connection portion 250 is electrically connected to an end of the first main source 221 near the second branch source 322, and a second end of the source connection portion 250 is electrically connected to an end of the second main source 321 near the first branch source 222.

[0068] In this embodiment, the first main source electrode 221 and the second main source electrode 321 are arranged in parallel, and the two are not on the same straight line. The first branch source electrode 222 and the second branch source electrode 322 are electrically connected to the corresponding main source electrode, and the first branch source electrode 222 faces the extension section of the line segment where the second main source electrode 321 is located, and the second branch source electrode 322 faces the extension section of the line segment where the first main source electrode 221 is located. The plurality of first branch source electrodes 222 are arranged at intervals along the second direction X, and the plurality of second branch source electrodes 322 are arranged at intervals along the second direction X, and the first main source electrode 221 and the plurality of first branch source electrodes 222 are all located at the source electrode. On the first side of the connecting portion 250, the second main source 321 and the plurality of second branch sources 322 are all located on the second side of the source connecting portion 250, that is, the source connecting portion 250 of the present application separates the first source 220 and the second source 320, so that the first source 220 and the second source 320 that are relatively arranged in the first direction Y are changed to be arranged side by side in the second direction X, thereby reducing the size occupied by the first source 220 and the second source 320 in the first direction Y, reserving some longitudinal space for arranging other devices, and improving the technical problem of the excessive longitudinal size of the gate drive circuit 300 in the display panel 100.

[0069] See also Figure 4 The first drain 230 includes a first main drain 231 and a plurality of first branch drains 232 connected to the first main drain 231 and arranged at intervals. The second drain 330 includes a second main drain 331 and a plurality of second branch drains 332 connected to the second main drain 331 and arranged at intervals. The first main drain 231 and the second main drain 331 extend along the second direction X. The plurality of first branch drains 232 extend from the first main drain 231 to the first main source 221, and the plurality of second branch drains 332 extend from the second main drain 331 to the second main source 321.

[0070] In this embodiment, multiple first branch drains 232 and multiple first branch sources 222 are arranged alternately and in sequence, and the first channel 240 covers the gaps between the multiple first branch drains 232 and the multiple first branch sources 222. Multiple second branch drains 332 and multiple second branch sources 322 are arranged alternately and in sequence, and the second channel 340 covers the gaps between the multiple second branch drains 332 and the multiple second branch sources 322.

[0071] In this embodiment, the first main source 221 and the multiple first branch sources 222 are combined to form multiple U-shaped structures, the multiple first branch drains 232 extend into the corresponding U-shaped structures, and the multiple first branch drains 232 and the multiple first branch sources 222 are spaced apart; the second main source 321 and the multiple second branch sources 322 are combined to form multiple U-shaped structures, the multiple second branch drains 332 extend into the corresponding U-shaped structures, and the multiple second branch drains 332 and the multiple second branch sources 322 are spaced apart; in this embodiment, the spacing between the first branch drain 232 and the first branch source 222 can be equal to the spacing between the second branch drain 332 and the second branch source 322.

[0072] At the same time, the first channel 240 can be arranged between multiple first branch drains 232 and multiple first branch sources 222, and the second channel 340 can be arranged between multiple second branch drains 332 and multiple second branch sources 322. The first channel 240 and the second channel 340 can both be continuous channel structures, and the doped portions 123b on both sides of the first channel 240 and the second channel 340 can overlap with the adjacent branch sources and branch drains.

[0073] In this embodiment, the first channel 240 and the second channel 340 may be in a continuous wave shape.

[0074] See also Figure 4 , the first gate 210 and the second gate 310 both extend along the second direction X, and the orthographic projections of the first channel 240, the first source 220 and a portion of the first drain 230 on the first gate 210 are located within the first gate 210, and the orthographic projections of the second channel 340, the second source 320 and a portion of the second drain 330 on the second gate 310 are located within the first gate 210.

[0075] In this embodiment, the first gate 210 and the second gate 310 are arranged on the entire surface, and the first gate 210 and the second gate 310 are electrically connected to each other. The first gate 210 and the second gate 310 are equivalent to completely covering the corresponding first channel 240 and the second channel 340, thereby improving the driving force applied by the first gate 210 and the second gate 310 to the corresponding channel, and improving the conduction rate of the first driving transistor T52 and the second driving transistor T62.

[0076] See also Figure 4 In the first direction Y, the width of the source connecting portion 250 is greater than the width of the first branched source electrode 222, and the width of the source connecting portion 250 is greater than the width of the second branched source electrode 322. Since the first source electrode 220 and the second source electrode 320 are connected by the source connecting portion 250, and to prevent the source connecting portion 250 from breaking, the present application makes the width of the source connecting portion 250 greater than the widths of the first branched source electrode 222 and the second branched source electrode 322. At the same time, the source connecting portion 250 is respectively provided with the first channel 240 and the second channel 340. To prevent the first channel 240 and the second channel 340 from short-circuiting, the width of the source connecting portion 250 also needs to be greater than the widths of the first branched source electrode 222 and the second branched source electrode 322.

[0077] See also Figure 4 , the first low potential line VSSQ is located on a side of the first driving transistor T52 away from the second driving transistor T62, and the first low potential line VSSQ extends along the first direction Y; at the same time, the display panel 100 also includes a connecting segment 260, a first end of the connecting segment 260 is electrically connected to the first main source 221 in the first source 220, and a second end of the connecting segment 260 can be electrically connected to the first low potential line VSSQ through the electrical connection hole HL.

[0078] In this embodiment, the first low potential line VSSQ can be located in the same layer as the first gate 210 and the second gate 310, that is, the first low potential line VSSQ can be formed by the same metal layer as the first gate 210 and the second gate 310 in the same photomask process, thereby simplifying the process and saving wiring space.

[0079] See also Figure 5 , the pull-down maintaining module 440 further includes a third driving transistor T54 and a fourth driving transistor T64 connected to the first control node Q, the third driving transistor T54 and the fourth driving transistor T64 are adjacently arranged along the first direction Y, and the third driving transistor T54 and the fourth driving transistor T64 are located on a side of the second driving transistor T62 away from the first driving transistor T52; that is, Figure 5 The structure in can be set in Figure 4 On the right side of the figure, the sources of the first driving transistor T52, the second driving transistor T62, the third driving transistor T54 and the fourth driving transistor T64 can be directly connected, and the gates of the above four transistors can also be directly connected.

[0080] Meanwhile, the third driving transistor T54 includes a third channel 270 , and the fourth driving transistor T64 includes a fourth channel 280 , and the third channel 270 and the fourth channel 280 are disposed opposite to each other along the first direction Y.

[0081] In this embodiment, the first drive transistor T52 and the second drive transistor T62 are changed from being arranged opposite to each other in the first direction Y to being arranged side by side in the second direction X, thereby reducing the size occupied by the first drive transistor T52 and the second drive transistor T62 in the longitudinal direction. However, the widths of the first drive transistor T52 and the second drive transistor T62 are also reduced. Therefore, in order to ensure the performance of the gate drive circuit 300, the third drive transistor T54 and the fourth drive transistor T64 are not designed the same as the first drive transistor T52 and the second drive transistor T62. The third drive transistor T54 and the fourth drive transistor T64 are arranged opposite to each other in the first direction Y.

[0082] In this embodiment, the sizes of the first driving transistor T52 and the second driving transistor T62 in the second direction X and the sizes of the third driving transistor T54 and the fourth driving transistor T64 in the second direction X may be the same.

[0083] In this embodiment, in order to ensure that the device performance of the first driving transistor T52 and the second driving transistor T62 is as close as possible to the third driving transistor T54 and the fourth driving transistor T64, the length of the first channel 240 and / or the second channel 340 is less than the length of the third channel 270 and the fourth channel 280.

[0084] For example, the length of the first channel 240 is smaller than the length of the third channel 270 and the fourth channel 280, or the length of the second channel 340 is smaller than the length of the third channel 270 and the fourth channel 280, or the length of the first channel 240 and the second channel 340 is smaller than the length of the third channel 270 and the fourth channel 280; the reduction in the length of the first channel 240 and / or the second channel 340 can increase the conduction rate of the corresponding driving transistor, and thus can make the device performance of the first driving transistor T52 and the second driving transistor T62 the same as that of the third driving transistor T54 and the fourth driving transistor T64.

[0085] It should be noted that the width of the first channel 240 of the first driving transistor T52 is Figure 4 and Figure 5 The length of the first channel 240 from left to right is wavy, and the length of the first channel 240 of the first driving transistor T52 is Figure 4 and Figure 5 The distance between the first branch source 222 and the adjacent first branch drain 232, Figure 4 and Figure 5The first channel 240 in the figure is only a schematic diagram, and the specific length of the first channel 240 is the length of the area that is not ion-doped or not conductive; similarly, the width and length of the second channel 340, the third channel 270, and the fourth channel 280 are the same as the width and length of the first channel 240.

[0086] It should be noted that the third driving transistor T54 and the fourth driving transistor T64 can also be Figure 4 The first driving transistor T52 and the second driving transistor T62 are arranged in the same manner, and the longitudinal dimensions of the third driving transistor T54 and the fourth driving transistor T64 are reduced, so that longitudinal space can be further reserved for arranging other devices.

[0087] It should be noted that in Figure 4 and Figure 5 In the structure, the lateral metal lines on both sides of the driving transistor are metal lines in the same layer as the source and drain layer 125.

[0088] It should be noted that this application Figure 4 and Figure 5 The stack diagram is not a structural diagram of the final product. It is only a film stacking composition for the convenience of describing the technical solution of this application. The positions of different film layers vary depending on the type of transistor.

[0089] It should be noted that Figure 2 The circuit structure is only one of the embodiments of the present application. As long as the two transistors are arranged relative to each other in the second direction X, they are applicable to the present application.

[0090] This application also proposes a mobile terminal, which includes a terminal body and the display panel 100 described above, wherein the terminal body and the display panel 100 are integrated into one body. The terminal body can be a device such as a circuit board bound to the display panel, and a cover plate covering the display panel. The mobile terminal can include electronic devices such as mobile phones, televisions, and laptop computers.

[0091] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] The above is a detailed introduction to a display panel and a mobile terminal provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The gate drive circuit includes a gate drive circuit along a display portion and disposed on one side of the display portion, wherein the gate drive circuit includes N cascaded GOA units, the N GOA units are arranged along a first direction, and each of the GOA units includes a first drive transistor and a second drive transistor adjacently disposed along a second direction; The first driving transistor includes a first gate, a first source, and a first drain, and the second driving transistor includes a second gate, a second source, and a second drain, the first gate and the second gate are connected to a first control node, and the first source and the second source are connected to a second control node; The first source, the first drain, the second source and the second drain are all arranged along the first direction, and the first source and the second source are arranged between the first drain and the second drain, the first source and the second source at least partially overlap in the second direction, and the angle between the second direction and the first direction is greater than 0° and less than or equal to 90°.

2. The display panel according to claim 1, wherein: Each of the GOA units includes a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintaining module, wherein the pull-up control module, the pull-up module, the pull-down module, and the pull-down maintaining module are all connected to the first control node; The first driving transistor and the second driving transistor are arranged in the pull-down maintaining module.

3. The display panel according to claim 2, wherein: The first source electrode includes a first main source electrode and a plurality of first branch source electrodes connected to the first main source electrode and spaced apart from each other; the second source electrode includes a second main source electrode and a plurality of second branch source electrodes connected to the second main source electrode and spaced apart from each other; the first main source electrode and the second main source electrode extend along the second direction; the plurality of first branch source electrodes and the plurality of second branch source electrodes extend along the first direction; and the first branch source electrode and the second branch source electrode have different orientations; In which, the GOA unit also includes a source connection portion extending along the first direction, the source connection portion is arranged between the first source and the second source, and the first end of the source connection portion is electrically connected to the end of the first main source close to the second branch source, and the second end of the source connection portion is electrically connected to the end of the second main source close to the first branch source.

4. The display panel according to claim 3, wherein: In the first direction, a width of the source connection portion is greater than a width of the first branch source, and a width of the source connection portion is greater than a width of the second branch source.

5. The display panel according to claim 3, wherein: The first drain includes a first main drain and a plurality of first branch drains connected to the first main drain and spaced apart. The second drain includes a second main drain and a plurality of second branch drains connected to the second main drain and spaced apart. The first main drain and the second main drain extend along the second direction. The plurality of first branch drains extend from the first main drain to the first main source. The plurality of second branch drains extend from the second main drain to the second main source. The plurality of first branch drains and the plurality of first branch sources are alternately and sequentially spaced apart. The plurality of second branch drains and the plurality of second branch sources are alternately and sequentially spaced apart. The first driving transistor further includes a first channel, and the second driving transistor further includes a second channel. The first channel covers the gaps between the first branch drains and the first branch sources, and the second channel covers the gaps between the second branch drains and the second branch sources.

6. The display panel according to claim 5, wherein: Both the first gate and the second gate extend along the second direction, and the orthographic projections of the first channel, the first source and a portion of the first drain on the first gate are located within the first gate, and the orthographic projections of the second channel, the second source and a portion of the second drain on the second gate are located within the first gate.

7. The display panel according to claim 3, wherein: The first low potential line is located on a side of the first driving transistor away from the second driving transistor, and the first low potential line extends along the first direction; The display panel further includes a connecting segment, a first end of the connecting segment is electrically connected to the first main source electrode in the first source electrode, and a second end of the connecting segment is electrically connected to the first low-potential line.

8. The display panel according to claim 2, wherein: The pull-down maintaining module further includes a third driving transistor and a fourth driving transistor connected to the first control node, the third driving transistor and the fourth driving transistor are adjacently arranged along the first direction, and the third driving transistor and the fourth driving transistor are located on a side of the second driving transistor away from the first driving transistor; The third driving transistor includes a third channel, the fourth driving transistor includes a fourth channel, and the third channel and the fourth channel are arranged opposite to each other along the first direction.

9. The display panel according to claim 8, wherein: The first driving transistor further includes a first channel, and the second driving transistor further includes a second channel. The length of the first channel and / or the second channel is shorter than the length of the third channel and the fourth channel.

10. A mobile terminal, characterized in that: The mobile terminal includes the display panel according to any one of claims 1 to 9.

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