Display panel and method for eliminating coupling effect between adjacent gate lines in display panel

Abstract

This application discloses a display panel and a method for eliminating the coupling effect between adjacent gate lines in the display panel. The display panel includes: a timing controller for providing a drive signal; and a level shifter connected to the timing controller for receiving the drive signal and transmitting a low-level signal to the gate line of the (N+1)th row before the falling edge of the Nth timing sequence, and transmitting a high-level signal to the gate line of the (N+1)th row after the falling edge of the Nth timing sequence, wherein N ≥ 1. This structure eliminates the coupling effect of adjacent gate lines on the current sub-pixel, improving the display effect.

Description

Technical Field

[0001] This invention relates to the field of display panels, and in particular to display panels and a method for eliminating the coupling effect between adjacent gate lines in a display panel. Background Technology

[0002] In recent years, with the trend towards thinner displays, liquid crystal displays (LCDs) have been widely used in various electronic products, such as mobile phones, laptops, and color televisions.

[0003] However, when driving the panel, the various signal lines will exhibit capacitive coupling to the drive signal. Let's consider this: using water level to represent electrical potential and water volume to represent electrical charge. Figure 1 In the diagram, one electrode of each capacitor is connected. Initially, the voltage across each capacitor is fixed, so the potentials on the connected electrodes are the same. At a certain instant, the potential of the other electrode of one capacitor is lowered. As we know from circuit theory, the voltage across a capacitor must be continuous. At this instant, the potential of the capacitor whose electrode potential is lowered is lower than that of the other capacitors on the connected electrodes, while the potentials on the connected electrodes should be equal. Therefore, charge will flow out of the other capacitors, causing their potentials to decrease, while the potential of the capacitor whose potential is lowered will rise due to the inflow of charge. Finally, the potentials on the connected electrodes will become the same again, but the potentials will be lower than before.

[0004] There are three main sources of voltage variation on an LCD panel: gate driver voltage variation, source driver voltage variation, and common (COM) voltage variation. Specifically... Figure 2 As shown, the coupling capacitance includes the parasitic capacitance Cpg between the scan line (Gate n) and the pixel electrode, the parasitic capacitance Cpg' between the adjacent scan line (Gate n+1) and the pixel electrode, the capacitance Cpd between the pixel electrode and its own data line (Data n), the capacitance Cpd' between the pixel electrode and the adjacent data line (Data n+1), the storage capacitance Cst connecting the pixel electrode to the common electrode, the liquid crystal capacitor Clc, and the parasitic capacitance Cgs of the TFT, etc. Among these, the coupling effect caused by the driving voltage of the scan line has the greatest impact. Therefore, in large panels, the driving process needs to consider not only eliminating the influence of the scan line on the pixel electrode, but also the influence of adjacent scan lines on the pixel electrode. Summary of the Invention

[0005] This application provides a display panel and a method for eliminating the gate line coupling effect in the display panel, so as to eliminate the coupling effect of the gate line of the next row on the sub-pixel of the previous row and improve the grayscale display quality.

[0006] To address the aforementioned problems, a first aspect of this application provides a display panel, wherein a timing controller is configured to provide a drive signal; a level shifter is connected to the timing controller and configured to receive the drive signal, and transmit a low-level signal to the gate line of the (N+1)th row before the falling edge of the Nth timing sequence according to the drive signal, and transmit a high-level signal to the gate line of the (N+1)th row after the falling edge of the Nth timing sequence; wherein N≥1, and the Nth timing sequence includes a rising edge and a falling edge.

[0007] The timing controller is further configured to provide a scan signal; the level shifter receives the scan signal and sequentially transmits a scan voltage to the gate line of the Nth row in the Nth timing sequence according to the scan signal; wherein, N≥1.

[0008] The Nth timing sequence and the (N+1)th timing sequence partially overlap.

[0009] The Nth timing sequence includes a precharge timing sequence and a display timing sequence; the falling edge of the Nth timing sequence occurs at least before the display timing sequence of the N+1th timing sequence.

[0010] The driving signal includes a low-level signal and a high-level signal. The level shifter receives the low-level signal before the falling edge of the Nth timing sequence and transmits the low-level signal to the gate line of the N+1th row to turn off the scan signal of the N+1th row. After the falling edge of the Nth timing sequence, it receives the high-level signal and transmits the low-level signal to the gate line of the N+1th row to turn on the scan signal of the N+1th row.

[0011] The scanning signal includes a high-potential voltage, and the level shifter includes a high-potential signal line for transmitting the high-potential voltage, and a first type of switch connecting the gate line of the Nth row to the high-potential signal line. The level shifter turns on the first type of switch of the Nth row at the rising edge of the Nth timing sequence to turn on the pixel switch corresponding to the gate line of the Nth row; and turns off the first type of switch of the Nth row at the falling edge of the Nth timing sequence to turn off the pixel switch corresponding to the gate line of the Nth row.

[0012] The driving signal includes a switching signal; the level shifter closes the first type of switch in row N+1 before the falling edge of the Nth timing sequence according to the switching signal, so as to close the pixel switch corresponding to the gate line in row N+1; and opens the first type of switch in row N+1 after the falling edge of the Nth timing sequence, so as to open the pixel switch corresponding to the gate line in row N+1.

[0013] The scanning signal further includes a low potential voltage, and the level shifter further includes a low-level signal line for transmitting the low potential voltage, and a second type of switch connecting the gate line of the Nth row to the low-level signal line;

[0014] The level shifter opens the first type of switch in the Nth row and closes the second type of switch in the Nth row at the rising edge of the Nth timing sequence; closes the first type of switch in the Nth row and opens the second type of switch in the Nth row at the falling edge of the Nth timing sequence; the driving signal includes a switch signal; the level shifter closes the first type of switch in the Nth row and opens the second type of switch before the falling edge of the Nth timing sequence according to the driving signal; opens the first type of switch in the Nth row and closes the second type of switch at the falling edge of the Nth timing sequence.

[0015] A second aspect of this application also provides a method for eliminating the coupling effect between adjacent gate lines in a display panel, wherein the method includes: providing a drive signal; and controlling a scan signal input to the gate line of the (N+1)th row to be turned off before the falling edge of the Nth timing sequence and turned on after the falling edge of the Nth timing sequence, according to the drive signal.

[0016] The method further includes: providing a scan signal; and inputting a scan voltage to the gate line of the Nth row according to the scan signal in the Nth timing sequence.

[0017] The beneficial effects of this application are: by inserting a driving signal into the original scanning signal, the coupling effect of the next row gate line on the previous row sub-pixel can be avoided, thereby improving the quality of the grayscale display image, without increasing the in-plane hardware design cost. It is highly feasible and easy to implement. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the potential in the prior art;

[0020] Figure 2 This is a schematic diagram of the pixel equivalent capacitance in the prior art;

[0021] Figure 3 This is a schematic diagram of the structure of a display panel according to an embodiment of this application;

[0022] Figure 4 This is a timing diagram of an embodiment of the driving signal of this application;

[0023] Figure 5 This is a driving timing diagram of one embodiment of the gate line of this application;

[0024] Figure 6 This is a schematic diagram of the structure of a specific embodiment of the display panel of this application;

[0025] Figure 7 This is a schematic diagram of another specific embodiment of the display panel of this application;

[0026] Figure 8 This is a flowchart illustrating an embodiment of the method for eliminating the coupling effect between adjacent gate lines in a display panel according to this application.

[0027] 11 Timing controller; 12 Level shifter; G gate line; GE drive signal; K1 Type I switch; K2 Type II switch. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0030] It should be understood that the term "and / or" used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0031] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0033] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0034] This application provides a display panel; please refer to the details. Figure 3 , Figure 3 This is a schematic diagram of the structure of a display panel according to an embodiment of this application. Figure 3 As shown, the display panel includes a timing controller 11 and a level shifter 12.

[0035] The timing controller 11 is used to provide the drive signal GE, which is also called the timing control signal.

[0036] The level shifter 12, connected to the timing controller 11, is used to receive the drive signal GE, and transmit a low-level signal to the gate line of the N+1th row before the falling edge of the Nth timing according to the drive signal GE, and transmit a high-level signal to the gate line of the N+1th row after the falling edge of the Nth timing; wherein, N≥1, and the Nth timing includes the rising edge and the falling edge.

[0037] Specifically, please refer to Figure 4 , Figure 4 This is a timing diagram of an embodiment of the driving signal of this application. Figure 4As shown, the drive signal GE includes a high-level signal VGH and a low-level signal VGL. Before the falling edge of the Nth timing sequence, the drive signal GE transitions to a low-level signal VGL. The level shifter 12 receives this low-level signal VGL and transmits it to the gate line of the (N+1)th row to control the gate line of the (N+1)th row to turn off, thereby temporarily disabling the scan signal for the (N+1)th row. After the falling edge of the Nth timing sequence, the drive signal GE transitions to a high-level signal VGH. The level shifter 12 receives this high-level signal VGH and transmits it to the gate line of the (N+1)th row to control the gate line of the (N+1)th row to turn on again, thereby continuing the scan of the (N+1)th row.

[0038] Specifically, when N is 1, which corresponds to the first row, the driving process involves the following steps: Before the first row finishes charging, at the falling edge of the driving signal GE, the gate of the second row TFT is turned off. After the gate of the first row is turned off, the first row TFT is also off and in a state of charge conservation. At the rising edge of the driving signal GE, it turns on again, and the gate of the second row goes high, causing the signal of the first row to be upwardly coupled. When the second row finishes charging, its gate is turned off, and the gate goes low, causing the signal of the first row to be downwardly coupled. This effectively cancels out the upwardly coupled signal, thus eliminating the influence of the gate line of the second row on the pixels of the first row. This process is repeated for subsequent rows, thereby eliminating the coupling effect of the gate line transition of the (N+1)th row on the pixels of the Nth row.

[0039] It should be noted that, in one specific embodiment, Figure 4 In the diagram, 101 represents the timing diagram of the first row of scan signals, 102 represents the timing diagram of the second row of scan signals, and 103 represents the timing diagram of the third row of scan signals. In other embodiments, the display panel also includes a start signal STV, in which case 101 represents the start signal STV, 102 represents the timing diagram of the first row of scan signals, 103 represents the timing diagram of the second row of scan signals, and so on, without limitation here.

[0040] The beneficial effects of this embodiment are: by turning off the gate lines of the next row before the previous row is scanned, the coupling effect of the gate lines of the next row on the sub-pixels of the previous row is eliminated, greatly improving the quality of the grayscale display. At the same time, eliminating the coupling effect of the gate lines of the next row on the sub-pixels of the previous row by adjusting the output waveform does not increase the in-plane hardware design cost, making it highly feasible.

[0041] In this embodiment, the timing controller 11 further includes a scan signal. The level shifter 12 receives the scan signal and sequentially transmits scan voltages to the gate lines of the Nth row within the Nth timing interval according to the scan signal. Please refer to [link to details] for further information. Figure 5 , Figure 5This is a driving timing diagram of one embodiment of the gate line of this application, as shown below. Figure 5 As shown, the level shifter 12 transmits a scan voltage to the gate lines of the first row in a first timing sequence, to the gate lines of the second row in a second timing sequence, to the gate lines of the third row in a third timing sequence, and so on, transmitting a scan voltage to the gate lines of the Nth row in the Nth timing sequence. The scan voltage is a high-level voltage, which turns on the pixel transistor corresponding to the gate line, thereby initiating data writing to the pixel electrode. Each timing sequence includes a rising edge and a falling edge. At the rising edge, the level shifter 12 transmits a high-level signal to the gate line to turn on the pixel transistor corresponding to the gate line, initiating data writing to the pixel electrode; at the falling edge, it transmits a low-level signal to the gate line to turn off the pixel transistor corresponding to the gate line, thereby ending data writing to the pixel electrode.

[0042] There is some overlap between the Nth time sequence and the (N+1)th time sequence.

[0043] Specifically, the Nth implementation includes pre-charge implementation and display timing, and the falling edge of the Nth timing is at least before the display timing of the N+1th timing, so that the pixel electrode corresponding to the gate line of the Nth row is displayed normally during the display phase.

[0044] In other embodiments, the Nth and N+1th timing sequences can also be set non-overlapping, so that the scanning of the next row is carried out only after the scanning of the Nth row of gate lines is completed. However, this will greatly increase the scanning time of the display panel, which is not conducive to grayscale display of large panels.

[0045] The beneficial effect of this embodiment is that by charging the sub-pixels of the previous row while pre-charging the sub-pixels of the next row, the scanning time of the display panel is greatly reduced, making it suitable for large panel displays.

[0046] In a first specific embodiment, the scan signal includes a high-voltage signal and a low-voltage signal. In this embodiment, the low-level signal VGL of the drive signal GE is the same as the low-voltage signal of the scan signal, and the high-level signal VGH is the same as the high-voltage signal of the scan signal. This causes the pixel switch to be turned on under the high-voltage signal and the high-level signal VGH, and turned off under the low-voltage signal and the low-level signal VGL. In other embodiments, the low-level signal VGL and the low-voltage signal, as well as the high-level signal VGH and the high-voltage signal, may not be exactly the same; this is not limited here.

[0047] In other specific embodiments, the low-level signal VGL of the drive signal is twice the low-voltage signal of the scan signal, and the high-level signal VGH of the drive signal is twice the high-voltage signal of the scan signal. The drive signal is inserted into the scan signal so that after the drive signal is superimposed on the scan signal, when the drive signal transitions to the low-level signal VGL, the gate voltage of the gate line is at a low voltage, thereby turning off the pixel switch corresponding to the gate line; when the drive signal transitions to the high-level signal VGH, the gate voltage of the gate line is at a high voltage, thereby turning on the pixel switch corresponding to the gate line.

[0048] In the second specific embodiment, the scanning signal of the timing controller 11 includes a high-potential voltage VH and a first switching signal. The level shifter 12 includes a high-potential signal line L1 for transmitting the high-potential voltage VH and a first type of switch K1 connecting the gate line Gn of the Nth row with the high-potential signal line L1. For details, please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of the structure of a specific embodiment of the display panel of this application. Figure 6 As shown, the first type of switch K1 includes N switches, each controlling the voltage of the gate lines in N rows. Specifically, the level shifter 12 turns on the first type of switch K1 in the Nth row at the rising edge of the scan signal in the Nth timing sequence, thereby turning on the pixel switch corresponding to the gate line in the Nth row and charging the sub-pixel in the Nth row. At the falling edge of the Nth timing sequence, the first type of switch K1 in the Nth row turns off, thereby turning off the pixel switch corresponding to the gate line in the Nth row, ending the charging of the sub-pixel in the Nth row, and maintaining the written pixel voltage through the pixel capacitor.

[0049] In this embodiment, the driving signal includes a switching signal. The level shifter 12 turns off the first type of switch K1 in row N+1 before the falling edge of the Nth timing sequence, thereby turning off the pixel switch corresponding to the gate line of row N+1. After the falling edge of the Nth timing sequence, it turns on the first type of switch K1 in row N+1, thereby turning on the pixel switch corresponding to the gate line of row N+1, thus realizing data writing to the gate line of row N+1. Here, a pixel switch refers to a switching transistor in a sub-pixel used to control pixel data writing.

[0050] In the first embodiment, the driving signal includes not only a switching signal but also a high-level signal and a low-level signal. This embodiment, compared to the first embodiment, omits the need to set the potentials for the high-level and low-level signals in the driving signal.

[0051] In the above embodiment, after the first type of switch K1 is turned off, the gate line returns to a low level signal, which may specifically include grounding the gate line, but is not limited here.

[0052] This application also provides a structural schematic diagram of another specific embodiment of the display panel, please refer to the following for details. Figure 7 , Figure 7 This is a schematic diagram of another specific embodiment of the display panel of this application. Figure 7 As shown, the scan signal also includes a high-potential voltage VH. The level shifter 12 includes a low-potential signal line L2 for transmitting a low-potential voltage VL, and a second type of switch K2 connecting the low-potential signal line L2 to the gate line Gn of the Nth row. At the rising edge of the Nth timing sequence, the level shifter 12 opens the first type of switch K1 of the Nth row and closes the second type of switch K2 of the Nth row, thereby transmitting the high-potential voltage VH to the gate line of the Nth row at the rising edge of the Nth timing sequence; at the falling edge of the Nth timing sequence, the first type of switch K1 of the Nth row closes and the second type of switch K2 opens, thereby transmitting the low-potential voltage VL to the gate line of the Nth row at the falling edge of the Nth timing sequence.

[0053] In this specific embodiment, the driving signal includes a switching signal. The level shifter closes the first type of switch K1 in row N+1 and opens the second type of switch K2 in row N+1 before the falling edge of the Nth timing sequence according to the switching signal. This causes the low potential voltage VL to be transmitted to the gate line of row N+1 before the falling edge of the Nth timing sequence, thus turning off the pixel switch in row N+1. At the falling edge of the Nth timing sequence, the first type of switch K1 in row N+1 is opened and the second type of switch K2 in row N+1 is closed. This causes the high potential voltage VH to be transmitted to the gate line of row N+1 after the falling edge of the Nth timing sequence, thus turning on the pixel switch in row N+1.

[0054] In this embodiment, by controlling the conduction of the first type of switch and the second type of switch, the gate voltage on the gate line is controlled, thereby controlling the scan timing on the gate line. At the same time, by controlling the gate voltage on the gate line through the second type of switch, it can be restored to a low potential voltage during the non-scanning timing, thereby ending the scan of the current row.

[0055] This application also provides a method for eliminating the coupling effect between adjacent gate lines in a display panel. Please refer to the details below. Figure 8 , Figure 8 This is a schematic flowchart of an embodiment of the method for eliminating the coupling effect between adjacent gate lines in a display panel according to this application. Figure 8 As shown, the method includes:

[0056] Step S61: Provide a drive signal.

[0057] The driving signals include low-level signals and high-level signals.

[0058] Step S62: Control the scan signal input to the gate line of row N+1 to be turned off before the falling edge of the Nth timing sequence and turned on after the falling edge of the Nth timing sequence according to the drive signal.

[0059] Specifically, this includes inputting a low-level signal to the gate line of row N+1 before the falling edge of the Nth timing sequence to turn off the pixel switch corresponding to the gate line of row N+1; and inputting a high-level signal to the gate line of row N+1 after the falling edge of the Nth timing sequence to turn on the pixel switch corresponding to the gate line of row N+1. Here, the scan signal refers to a voltage signal that can turn on the pixel switch corresponding to the gate line and perform scanning, including a high-potential voltage that turns on the pixel switch on the gate line and a low-potential voltage that turns off the pixel switch on the gate, which is not limited here.

[0060] Step S62 further includes: providing a scan signal and inputting a scan voltage to the gate line of the Nth row within the Nth timing sequence according to the scan signal. The scan voltage is a high-potential voltage that can turn on the pixel switch. The scan signal is a signal in the display panel that controls the scanning of pixels. The scan signal input to the gate line within each timing sequence includes a rising edge and a falling edge. The rising and falling edges of two adjacent timing sequences partially overlap, thereby enabling pre-charging of the next row while the previous row is being charged. Specifically, the Nth timing sequence overlaps with the N+1th timing sequence. In other embodiments, the N+1th row can be scanned after the Nth row is scanned; this is not limited here.

[0061] The beneficial effects of this embodiment are: the scanning signal is the signal normally displayed in the display panel. By inserting a driving signal into the original scanning signal, this embodiment can completely avoid the coupling effect of the next row gate line on the previous row sub-pixel, thereby improving the quality of the grayscale display image. At the same time, it will not increase the in-plane hardware design cost. It is highly feasible and easy to implement.

[0062] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, the display panel comprising a plurality of parallel gate lines, characterized in that, The display panel also includes: A timing controller is used to provide drive signals; A level shifter, connected to the timing controller, is used to receive the drive signal and transmit a low-level signal to the gate line of the (N+1)th row before the falling edge of the Nth timing sequence, and transmit a high-level signal to the gate line of the (N+1)th row after the falling edge of the Nth timing sequence; wherein, N≥1, and the Nth timing sequence includes the rising edge and the falling edge.

2. The display panel according to claim 1, characterized in that, The timing controller is also used to provide scan signals; The level shifter receives the scan signal and sequentially transmits scan voltage to the gate line of the Nth row in the Nth time sequence according to the scan signal; where N≥1.

3. The display panel according to claim 2, characterized in that, The Nth timing sequence and the (N+1)th timing sequence partially overlap.

4. The display panel according to claim 3, characterized in that, The Nth timing sequence includes precharge timing and display timing; The falling edge of the Nth timing sequence must be at least before the display timing of the N+1th timing sequence.

5. The display panel according to claim 2, characterized in that, The driving signal includes a low-level signal and a high-level signal. The level shifter receives the low-level signal before the falling edge of the Nth timing sequence and transmits the low-level signal to the gate line of the N+1th row to turn off the scan signal of the N+1th row; after the falling edge of the Nth timing sequence, it receives the high-level signal and transmits the low-level signal to the gate line of the N+1th row to turn on the scan signal of the N+1th row.

6. The display panel according to claim 2, characterized in that, The scan signal includes a high-potential voltage, and the level shifter includes a high-potential signal line for transmitting the high-potential voltage, and a first-type switch connecting the gate line of the Nth row to the high-potential signal line. The level shifter turns on the first type of switch in the Nth row at the rising edge of the Nth timing, so as to turn on the pixel switch corresponding to the gate line in the Nth row. At the falling edge of the Nth timing, the first type of switch in the Nth row is turned off to turn off the pixel switch corresponding to the gate line of the Nth row.

7. The display panel according to claim 6, characterized in that, The driving signal includes a switching signal; The level shifter turns off the first type of switch in the N+1th row before the falling edge of the Nth timing according to the switch signal, so as to turn off the pixel switch corresponding to the gate line in the N+1th row. After the falling edge of the Nth timing, the first type of switch in the N+1th row is turned on to turn on the pixel switch corresponding to the gate line in the N+1th row.

8. The display panel according to claim 7, characterized in that, The scan signal also includes a low potential voltage, and the level shifter also includes a low-level signal line for transmitting the low potential voltage, and a second type of switch connecting the gate line of the Nth row to the low-level signal line; The level shifter opens the first type of switch in the Nth row and closes the second type of switch in the Nth row at the rising edge of the Nth timing sequence; and closes the first type of switch in the Nth row and opens the second type of switch in the Nth row at the falling edge of the timing sequence. The driving signal includes a switching signal; The level shifter closes the first type of switch in the Nth row and opens the second type of switch before the falling edge of the Nth timing according to the driving signal; At the falling edge of the Nth timing sequence, the first type of switch in the Nth row is turned on, and the second type of switch is turned off.

9. A method for eliminating the coupling effect between adjacent gate lines in a display panel, characterized in that, include: Provide drive signals; The scan signal input to the gate line of the (N+1)th row is controlled by the drive signal to be turned off before the falling edge of the Nth timing sequence and turned on after the falling edge of the Nth timing sequence.

10. The method for eliminating the coupling effect of adjacent gate lines in a display panel according to claim 9, characterized in that, The method further includes: Provide scanning signals; According to the scan signal, a scan voltage is input to the gate line of the Nth row in the Nth time sequence.

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