Pixel circuits and their driving methods, display substrates, display devices

Abstract

A pixel circuit and its driving method, display substrate, and display device are disclosed. The pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a light emission control sub-circuit, and a driving sub-circuit. The operation of the pixel circuit includes a first initialization stage (S1), a data writing stage (S2), a second initialization stage (S3), and a light emission stage (S4). The second node control sub-circuit is configured to provide a signal from the second initial signal terminal (INIT2) to the fourth node (N4) under the control of the second reset signal terminal (Reset2). The second initialization stage (S3) occurs between the data writing stage (S2) and the light emission stage (S4). The signal from the second reset signal terminal (Reset2) is an active level signal during the second initialization stage (INIT2). During the second initialization stage (S3), the signal from the second reset signal terminal (Reset2) and the signal from the light emission signal terminal (EM) are inverted signals.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a pixel circuit and its driving method, a display substrate, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a pixel circuit configured to drive a light-emitting element to emit light. The pixel circuit includes: a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit. The working process of the pixel circuit includes: a first initialization stage, a data writing stage, a second initialization stage, and a light-emitting stage.

[0005] The first node control sub-circuit is electrically connected to the first power supply terminal, the first reset signal terminal, the first initial signal terminal, the scan signal terminal, the data signal terminal, the first node, the second node, and the third node, respectively. It is configured to provide the first initial signal terminal to the first node under the control of the first reset signal terminal, provide the third node to the first node under the control of the scan signal terminal, and provide the data signal terminal to the second node.

[0006] The second node control sub-circuit is electrically connected to the second reset signal terminal, the second initial signal terminal, and the fourth node, respectively, and is configured to provide the signal of the second initial signal terminal to the fourth node under the control of the second reset signal terminal;

[0007] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the first node and the second node;

[0008] The light-emitting control sub-circuit is electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node under the control of the light-emitting signal terminal.

[0009] The light-emitting element is electrically connected to the fourth node and the second power supply terminal, respectively.

[0010] The second initialization phase occurs between the data writing phase and the light emission phase. The signal at the second reset signal terminal is an active level signal during the second initialization phase. During the second initialization phase, the signal at the second reset signal terminal and the signal at the light emission signal terminal are inverse signals of each other.

[0011] In some possible implementations, the second node control sub-circuit is also electrically connected to the third node and is further configured to provide a signal from the second initial signal terminal to the third node under the control of the second reset signal terminal.

[0012] In some possible implementations, the first reset signal terminal is an active level signal during the first initialization phase, the scan signal terminal is an active level signal during the data writing phase, and the light emission signal terminal is an active level signal during the light emission phase.

[0013] When the signal at the second reset signal terminal is a valid level signal, the signal at the light emission signal terminal is an invalid level signal; when the signal at the light emission signal terminal is a valid level signal, the signal at the second reset signal terminal is an invalid level signal.

[0014] The frequency of the effective level signal at the light-emitting signal terminal is the same as the frequency of the effective level signal at the second reset signal terminal.

[0015] In some possible implementations, the first node control sub-circuit includes: a first transistor, a second transistor, a fourth transistor, and a capacitor, the capacitor including: a first electrode and a second electrode; the driving sub-circuit includes: a third transistor; and the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor.

[0016] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0017] The control electrode of the second transistor is electrically connected to the scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0018] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0019] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0020] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0021] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0022] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0023] In some possible implementations, the second node control sub-circuit includes: a seventh transistor;

[0024] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0025] In some possible implementations, the second node control sub-circuit includes: a seventh transistor and an eighth transistor;

[0026] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0027] The control terminal of the eighth transistor is electrically connected to the second reset signal terminal, the first terminal of the eighth transistor is electrically connected to the second initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the third node.

[0028] In some possible implementations, the first node control sub-circuit includes: a first transistor, a second transistor, a fourth transistor, and a capacitor, the capacitor including: a first plate and a second plate; the driving sub-circuit includes: a third transistor; the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; and the second node control sub-circuit includes: a seventh transistor.

[0029] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0030] The control electrode of the second transistor is electrically connected to the scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0031] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0032] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0033] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0034] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0035] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0036] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0037] In some possible implementations, the first node control sub-circuit includes: a first transistor, a second transistor, a fourth transistor, and a capacitor, the capacitor including: a first electrode and a second electrode; the driving sub-circuit includes: a third transistor; the light-emitting control sub-circuit includes: a fifth transistor and a sixth transistor; and the second node control sub-circuit includes: a seventh transistor and an eighth transistor.

[0038] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0039] The control electrode of the second transistor is electrically connected to the scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

[0040] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node.

[0041] The control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0042] The control electrode of the fifth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0043] The control electrode of the sixth transistor is electrically connected to the light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0044] The control terminal of the seventh transistor is electrically connected to the second reset signal terminal, the first terminal of the seventh transistor is electrically connected to the second initial signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node.

[0045] The control terminal of the eighth transistor is electrically connected to the second reset signal terminal, the first terminal of the eighth transistor is electrically connected to the second initial signal terminal, and the second terminal of the eighth transistor is electrically connected to the third node.

[0046] The first plate of the capacitor is electrically connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0047] Secondly, this disclosure also provides a display substrate, comprising: a substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate, wherein the light-emitting structure layer comprises: a light-emitting element, and the circuit structure layer comprises: the aforementioned pixel circuits arranged in an array.

[0048] In some possible implementations, it further includes: a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of scan signal lines, a plurality of light emission signal lines, a plurality of first initial signal lines and a plurality of second initial signal lines extending along a first direction and arranged along a second direction, as well as a plurality of first power lines and a plurality of data signal lines extending along the second direction and arranged along the first direction; the first direction intersects the second direction;

[0049] The pixel circuit has a first reset signal terminal electrically connected to a first reset signal line, a second reset signal terminal electrically connected to a second reset signal line, a scan signal terminal electrically connected to a scan signal line, a light emission signal terminal electrically connected to a light emission signal line, a first initial signal terminal electrically connected to a first initial signal line, a second initial signal terminal electrically connected to a second initial signal line, a first power supply terminal electrically connected to a first power supply line, and a data signal terminal electrically connected to a data signal line.

[0050] In some possible implementations, when the pixel circuit includes: a first transistor to an eighth transistor and a capacitor, the circuit structure layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a planarization layer and a fourth conductive layer, which are sequentially stacked on the substrate.

[0051] The semiconductor layer includes: an active layer of a first transistor to an active layer of an eighth transistor located in at least one pixel circuit;

[0052] The first conductive layer includes: a first reset signal line, a second reset signal line, a scan signal line, a light emission signal line, and a first electrode of a capacitor located in at least one pixel circuit and the control electrode of a first transistor to the control electrode of an eighth transistor;

[0053] The second conductive layer includes: a first initial signal line, a second initial signal line, and a second plate of a capacitor located in at least one pixel circuit, wherein the second plates of capacitors of adjacent pixel circuits located in the same row are connected.

[0054] The third conductive layer includes: the first and second terminals of the first transistor, the first terminal of the second transistor, the first terminal of the fourth transistor, the first terminal of the fifth transistor, the second terminal of the sixth transistor, the first and second terminals of the seventh transistor, and the first and second terminals of the eighth transistor;

[0055] The fourth conductive layer includes: a first power line and a data signal line.

[0056] In some possible implementations, the active layer of the transistor includes: a channel region and a first electrode connection portion and a second electrode connection portion located on both sides of the channel region, respectively;

[0057] The first electrode connection portion of the active layer of the third transistor is multiplexed as the first electrode of the third transistor, the second electrode of the fourth transistor, and the second electrode of the fifth transistor;

[0058] The second electrode connection portion of the active layer of the third transistor is multiplexed as the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode of the sixth transistor.

[0059] In some possible implementations, the first reset signal line and the scan signal line connected to the pixel circuit are located on the same side of the first electrode plate of the pixel circuit, and the first reset signal line is located on the side of the scan signal line away from the first electrode plate of the pixel circuit.

[0060] The light-emitting signal line and the second reset signal line connected to the pixel circuit are located on the side of the first electrode plate of the pixel circuit away from the scan signal line, and the second reset signal line is located on the side of the light-emitting signal line away from the first electrode plate of the pixel circuit.

[0061] The first initial signal line and the second initial signal line connected to the pixel circuit are respectively located on opposite sides of the second plate of the capacitor of the pixel circuit. The second initial signal line connected to the pixel circuit of the (i-1)th row is located between the first initial signal line connected to the pixel circuit of the i-th row and the second plate of the capacitor of the pixel circuit of the i-th row.

[0062] The orthographic projection of the first reset signal line connected to the i-th row pixel circuit on the substrate is located between the orthographic projection of the first initial signal line connected to the i-th row pixel circuit on the substrate and the orthographic projection of the second initial signal line connected to the (i-1)-th row pixel circuit on the substrate.

[0063] The orthographic projection of the scan signal line connected to the i-th row pixel circuit on the substrate lies between the orthographic projection of the second initial signal line connected to the (i-1)-th row pixel circuit on the substrate and the orthographic projection of the second plate of the capacitor of the i-th row pixel circuit on the substrate.

[0064] In some possible implementations, the first initial signal line includes: a plurality of first initial main body portions and a plurality of first initial connecting portions spaced apart and arranged along a first direction, wherein the first initial connecting portions are configured to connect two adjacent first initial main body portions;

[0065] The length of the first initial main body portion along the second direction is greater than the length of the first initial connecting portion along the second direction;

[0066] The orthographic projection of the first initial main body portion on the substrate partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate, while the orthographic projection of the first initial connection portion on the substrate and the orthographic projection of the active layer of the first transistor on the substrate do not overlap.

[0067] In some possible implementations, the second initial signal line includes: a second initial body portion extending along a first direction, a first connecting portion located on a first side of the second initial body portion, and a second connecting portion and a third connecting portion located on a second side of the second initial body portion, wherein the first side and the second side are disposed opposite to each other, and the first side is a side of the capacitor of the pixel circuit connected to the second initial signal line.

[0068] The first connection portion extends along the second direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate;

[0069] The second connection portion extends along the second direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate;

[0070] The third connection portion extends along the second direction, and its orthographic projection on the substrate does not overlap with the orthographic projections of the active layer of the first transistor and the active layer of the second transistor on the substrate.

[0071] The orthographic projection of the third connection portion of the second initial signal line on the substrate is located between the orthographic projection of the first electrode of the second transistor on the substrate and the orthographic projection of the data signal line on the substrate.

[0072] In some possible implementations, the first insulating layer, the second insulating layer, and the third insulating layer are provided with a first via to an eighth via, the third via exposing the second electrode connection portion of the active layer of the third transistor, the fourth via exposing the active layer of the fourth transistor, and the eighth via exposing the active layer of the eighth transistor.

[0073] The second electrode of the eighth transistor includes: an electrode body portion and an electrode extension portion connected to each other, wherein the electrode body portion extends along a second direction, and the included angle between the electrode body portion and the electrode extension portion is greater than or equal to 90 degrees or less than 180 degrees;

[0074] The electrode body is electrically connected to the active layer of the eighth transistor through the eighth via, and its orthographic projection on the substrate overlaps with the orthographic projection of the light-emitting signal line and the second plate of the capacitor connected to the pixel circuit on the substrate.

[0075] The electrode extension is electrically connected to the second electrode connection portion of the active layer of the third transistor through a third via.

[0076] In some possible implementations, the adjacent pixel circuits located in the same row as the pixel circuits include: a first adjacent pixel circuit and a second adjacent pixel circuit, wherein the first adjacent pixel circuit is located on the side of the first power line connected to the pixel circuit away from the data signal line, and the second adjacent pixel circuit is located on the side of the data signal line connected to the pixel circuit away from the first power line.

[0077] A virtual straight line extending along the second direction passes through the active layer of the eighth transistor of the pixel circuit and the fourth via of the first adjacent pixel circuit, respectively.

[0078] A virtual straight line extending along the second direction passes through the electrode body of the pixel circuit and the fourth via of the first adjacent pixel circuit, respectively.

[0079] In some possible implementations, the orthographic projection of the first power line connected to the pixel circuit on the substrate is located between the orthographic projection of the data signal line connected to the pixel circuit on the substrate and the orthographic projection of the second electrode of the first transistor of the pixel circuit on the substrate.

[0080] The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the third connection portion of the second initial signal line on the substrate;

[0081] The orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projection of the electrode body of the first adjacent pixel circuit to which the data signal line is connected on the substrate.

[0082] In some possible implementations, at least one light-emitting element includes: an anode, an organic light-emitting layer, and a cathode; the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on the substrate; the anode layer includes: an anode, the organic structure layer includes: an organic light-emitting layer, and the cathode layer includes: a cathode;

[0083] The light-emitting element includes: a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element. The first light-emitting element emits red light, the second light-emitting element emits blue light, and the third and fourth light-emitting elements emit green light. The area of ​​the anode of the second light-emitting element is larger than the area of ​​the anode of the first light-emitting element, and the anodes of the third and fourth light-emitting elements are symmetrical about a virtual straight line extending along the first direction.

[0084] A virtual straight line extending along a first direction passes through the anode of the first light-emitting element and the anode of the second light-emitting element; a virtual straight line extending along a second direction passes through the anode of the first light-emitting element and the anode of the second light-emitting element; a virtual straight line extending along a first direction passes through the anode of the third light-emitting element and the anode of the fourth light-emitting element; a virtual straight line extending along a second direction passes through the anode of the third light-emitting element and the anode of the fourth light-emitting element; and four anodes of the second light-emitting elements, two anodes of the third light-emitting elements, and two anodes of the fourth light-emitting elements are arranged around the anode of the first light-emitting element.

[0085] The shape of the boundary of the anode of at least one second light-emitting element includes at least one rounded corner;

[0086] The pixel definition layer includes: a first anode via to a fourth anode via, wherein the first anode via exposes the anode of the first light-emitting element, the second anode via exposes the anode of the second light-emitting element, the third anode via exposes the anode of the third light-emitting element, and the fourth anode via exposes the anode of the fourth light-emitting element;

[0087] The shape of the boundary of the second anode via includes: multiple rounded corners, one of which is located on the side of the second anode via away from the first anode via it, and the rounded corners of the four second anode vias surrounding the first anode via that are away from the first anode via form the four rounded corners of a rounded rhombus, and the first anode via passes through the centerline of the rounded rhombus.

[0088] Thirdly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0089] Fourthly, this disclosure also provides a method for driving a pixel circuit, configured to drive the aforementioned pixel circuit, the method comprising:

[0090] During the first initialization phase, the first node control sub-circuit, under the control of the first reset signal terminal, provides the first initial signal terminal to the first node;

[0091] During the data writing phase, the first node control sub-circuit, under the control of the scanning signal terminal, provides the third node's signal to the first node and the data signal terminal's signal to the second node;

[0092] During the second initialization phase, the second node control sub-circuit, under the control of the second reset signal terminal, provides the signal of the second initial signal terminal to the fourth node;

[0093] During the light-emitting stage, the driving sub-circuit, under the control of the first and second nodes, provides driving current to the third node. Under the control of the light-emitting signal terminal, the light-emitting control sub-circuit provides the signal from the first power supply terminal to the second node and the signal from the third node to the fourth node.

[0094] In some possible implementations, the second node control sub-circuit, under the control of the second reset signal terminal, provides the second initial signal terminal to the third node during the second initialization phase.

[0095] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0096] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0097] Figure 1 This is a schematic diagram of the pixel circuit in the display substrate provided in an embodiment of the present disclosure;

[0098] Figure 2 A schematic diagram of a pixel circuit provided for an exemplary embodiment;

[0099] Figure 3 An equivalent circuit diagram of a pixel circuit provided for an exemplary embodiment;

[0100] Figure 4 An equivalent circuit diagram of a pixel circuit provided for another exemplary embodiment;

[0101] Figure 5 This is the timing diagram of the pixel circuit.

[0102] Figure 6 This is a schematic diagram after the semiconductor layer pattern has been formed;

[0103] Figure 7A This is a schematic diagram of the pattern of the first conductive layer;

[0104] Figure 7B This is a schematic diagram after the first conductive layer pattern has been formed;

[0105] Figure 8A This is a schematic diagram of the pattern of the second conductive layer;

[0106] Figure 8B This is a schematic diagram after the second conductive layer pattern has been formed;

[0107] Figure 9A This is a schematic diagram of the pattern of the third insulating layer;

[0108] Figure 9B This is a schematic diagram showing the formation of the third insulating layer pattern.

[0109] Figure 10A This is a schematic diagram of the pattern of the third conductive layer;

[0110] Figure 10B This is a schematic diagram after the third conductive layer pattern has been formed;

[0111] Figure 11A This is a schematic diagram of a planarization layer pattern;

[0112] Figure 11B This is a schematic diagram after the planarization layer pattern has been formed;

[0113] Figure 12A This is a schematic diagram of the pattern of the fourth conductive layer;

[0114] Figure 12B This is a schematic diagram after the fourth conductive layer pattern has been formed;

[0115] Figure 13A This is a schematic diagram of the anode layer pattern;

[0116] Figure 13B This is a schematic diagram after the anode layer pattern has been formed;

[0117] Figure 14AA schematic diagram defining a layer pattern for a pixel;

[0118] Figure 14B A schematic diagram after the pixel definition layer pattern has been formed. Detailed Implementation

[0119] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0120] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0121] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0122] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0123] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0124] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0125] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0126] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0127] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0128] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0129] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0130] The display device includes pixel circuits that drive light-emitting elements to emit light. The display panel of the display device has two driving modes: a first driving mode and a second driving mode. The refresh rate (also known as the display frequency) of the first driving mode is lower than that of the second driving mode. This first driving mode can be referred to as a low-frequency driving mode, and the second driving mode as a high-frequency driving mode. In the low-frequency driving mode, a display frame includes a refresh frame (also known as a write frame) and at least one hold frame. In this driving mode, the display panel refreshes display data in the refresh frame and holds the refreshed display data in the hold frame. When the display device switches from the high-frequency driving mode to the low-frequency driving mode, especially in low grayscale display, the large potential difference between some nodes in the pixel circuit during the write and hold frames causes inconsistent light emission brightness of the light-emitting elements, resulting in flickering and poor display quality.

[0131] Figure 1 This is a schematic diagram of the pixel circuit in a display substrate provided in an embodiment of this disclosure. Figure 1 As shown, the pixel circuit provided in this embodiment is configured to drive the light-emitting element to emit light. The pixel circuit includes: a first node control sub-circuit, a second node control sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit. The working process of the pixel circuit includes: a first initialization stage, a data writing stage, a second initialization stage, and a light-emitting stage.

[0132] In one exemplary embodiment, a first node control sub-circuit is electrically connected to a first power supply terminal VDD, a first reset signal terminal Reset1, a first initial signal terminal INIT1, a scan signal terminal Gate, a data signal terminal Data, a first node N1, a second node N2, and a third node N3, respectively. It is configured to provide the signal of the first initial signal terminal INIT1 to the first node N1 under the control of the first reset signal terminal Reset1, provide the signal of the third node N3 to the first node N1 under the control of the scan signal terminal Gate, and provide the signal of the data signal terminal Data to the second node N2; a second node control sub-circuit is electrically connected to a second reset signal terminal Reset2, a second initial signal terminal INIT1, a second initial signal terminal INIT1, a second initial signal terminal Gate ... The terminal INIT2 is electrically connected to the fourth node N4, and is configured to provide the signal of the second initial signal terminal INIT2 to the fourth node N4 under the control of the second reset signal terminal Reset2; the driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide the driving current to the third node N3 under the control of the first node N1 and the second node N2; the light emission control sub-circuit is electrically connected to the light emission signal terminal EM, the first power supply terminal VDD, the second node N2, the third node N3 and the fourth node N4 respectively, and is configured to provide the signal of the first power supply terminal VDD to the second node N2 and the signal of the third node N3 to the fourth node N4 under the control of the light emission signal terminal EM.

[0133] In this disclosure, the second initialization phase occurs between the data writing phase and the light emission phase, and the signal of the second reset signal terminal Reset2 is an effective level signal during the second initialization phase.

[0134] In this disclosure, during the second initialization phase, the signal of the second reset signal terminal Reset2 and the signal of the light-emitting signal terminal EM are inverted signals. That is, when the signal of the second reset signal terminal Reset2 is a high-level signal, the signal of the light-emitting signal terminal EM is a low-level signal, and when the signal of the second reset signal terminal Reset2 is a low-level signal, the signal of the light-emitting signal terminal EM is a high-level signal.

[0135] In one exemplary embodiment, the light-emitting element is electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0136] In one exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the second power supply terminal VSS continuously provides a low-level signal.

[0137] In one exemplary embodiment, the pixel circuit includes, during display of a frame, a first initialization phase, a data writing phase, multiple second initialization phases, and multiple light-emitting phases. The writing frame can be the time period during which the signal of the first light-emitting signal terminal EM is at an invalid level, meaning that data signals are written during the writing frame. The holding frame can be the time period during which the signals of the remaining light-emitting signal terminals EM are at an invalid level, meaning that no data signals are written during the holding frame.

[0138] In one exemplary embodiment, when the signal at the light-emitting signal terminal EM is at an active level, the second reset signal terminal is at an inactive level; when the light-emitting signal terminal is at an inactive level, the second reset signal terminal is at an active level.

[0139] In one exemplary embodiment, a second initialization phase occurs before each emission phase, whether in a write frame or a hold frame, where the frequency of the signal at the emission signal terminal being an effective level signal is the same as the frequency of the signal at the second reset signal terminal being an effective level signal.

[0140] In one exemplary embodiment, when the signal at the second reset signal terminal Reset2 is an active level signal, the signal at the light emission signal terminal EM is an inactive level signal.

[0141] In one exemplary embodiment, when the signal at the light-emitting signal terminal EM is a valid level signal, the signal at the second reset signal terminal Reset2 is an invalid level signal. When the signal at the light-emitting signal terminal EM is an invalid level signal, the signal at the second reset signal terminal Reset2 is a valid level signal during a first time period, wherein the first time period is within the duration during which the signal at the light-emitting signal terminal EM is an invalid level signal, and the duration of the first time period is less than the duration during which the signal at the light-emitting signal terminal EM is an invalid level signal.

[0142] In one exemplary embodiment, during the first initialization phase, the signal of the first reset signal terminal Reset1 is an active level signal, while the signals of the second reset signal terminal Reset2, the scan signal terminal Gate, and the light emission signal terminal EM are inactive level signals.

[0143] In one exemplary embodiment, during the data writing phase, the signal at the Gate terminal is a valid level signal, while the signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the light emission signal terminal EM are invalid level signals.

[0144] In one exemplary embodiment, during the second initialization phase, the signals of the first reset signal terminal Reset1, the scan signal terminal Gate, and the light emission signal terminal EM are invalid level signals.

[0145] In one exemplary example, during the light emission stage, the signal at the light emission signal terminal EM is an active level signal, while the signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the scan signal terminal Gat are inactive level signals.

[0146] In one exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0147] In one exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0148] In one exemplary embodiment, the anode of the organic light-emitting diode is electrically connected to the fourth node N4, and the cathode of the organic light-emitting element is electrically connected to the second power supply terminal VSS.

[0149] The pixel circuit provided in this embodiment is configured to drive a light-emitting element to emit light. The pixel circuit includes: a first node control subcircuit, a second node control subcircuit, a light-emitting control subcircuit, and a driving subcircuit. The working process of the pixel circuit includes: a first initialization stage, a data writing stage, a second initialization stage, and a light-emitting stage. The first node control subcircuit is electrically connected to a first power supply terminal, a first reset signal terminal, a first initial signal terminal, a scan signal terminal, a data signal terminal, a first node, a second node, and a third node, respectively. It is configured to provide the first initial signal terminal signal to the first node under the control of the first reset signal terminal, provide the third node signal to the first node under the control of the scan signal terminal, and provide the data signal terminal signal to the second node. The second node control subcircuit is electrically connected to the second reset signal terminal, the second initial signal terminal, and a fourth node, respectively. The system is configured to provide a second initial signal to the fourth node under the control of the second reset signal terminal; a driving sub-circuit, electrically connected to the first node, the second node, and the third node respectively, is configured to provide a driving current to the third node under the control of the first node and the second node; a light-emitting control sub-circuit, electrically connected to the light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node respectively, is configured to provide a signal from the first power supply terminal to the second node and a signal from the third node to the fourth node under the control of the light-emitting signal terminal; and a light-emitting element, electrically connected to the fourth node and the second power supply terminal respectively. The second initialization phase occurs between the data writing phase and the light-emitting phase. The signal from the second reset signal terminal is an effective level signal during the second initialization phase. During the second initialization phase, the signal from the second reset signal terminal and the signal from the light-emitting signal terminal are inverse signals. In this disclosure, resetting the fourth node during the second initialization phase, which occurs between the data writing phase and the light-emitting phase, ensures the potential consistency of the fourth node in the writing frame and the holding frame, and ensures the uniformity of the brightness of the light-emitting elements of the display substrate in the writing frame and the holding frame, thereby improving the display effect of the display substrate.

[0150] Figure 2 A schematic diagram of a pixel circuit provided for an exemplary embodiment. (See diagram below.) Figure 2 As shown, in one exemplary embodiment, the second node control sub-circuit is also electrically connected to the third node N3, and is further configured to provide the signal of the second initial signal terminal INIT2 to the third node N3 under the control of the second reset signal terminal Reset2. In this disclosure, resetting the third node during the second initial stage, which occurs between the data writing stage and the light emission stage, ensures the potential consistency of the third node in the write frame and the hold frame, guarantees the uniformity of the brightness of the light-emitting elements of the display substrate in the write frame and the hold frame, and improves the display effect of the display substrate.

[0151] Figure 3 An equivalent circuit diagram of a pixel circuit is provided for an exemplary embodiment. Figure 4 An equivalent circuit diagram of a pixel circuit provided for another exemplary embodiment. (e.g.) Figure 3 and 4 As shown, in an exemplary embodiment, the first node control sub-circuit may include: a first transistor T1, a second transistor T2, a fourth transistor T4, and a capacitor C. The capacitor C includes: a first plate C1 and a second plate C2. Specifically, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the scan signal terminal Gate, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The first plate C1 of the capacitor C is electrically connected to the first node N1, and the second plate C2 of the capacitor C is electrically connected to the first power supply terminal VDD.

[0152] In one exemplary embodiment, the first node control sub-circuit may include two first transistors connected in series. The two first transistors can reduce the leakage current of the pixel circuit and prevent the pixel circuit from malfunctioning when one of the first transistors fails to work properly, thereby improving the reliability of the pixel circuit. The first node control sub-circuit may also include a first transistor, which can perform its function.

[0153] In one exemplary embodiment, the first node control sub-circuit may include two second transistors connected in series. The two second transistors can reduce the leakage current of the pixel circuit and prevent the pixel circuit from malfunctioning when one of the second transistors fails to work properly, thereby improving the reliability of the pixel circuit. The first node control sub-circuit may also include a second transistor, which can perform its function.

[0154] In one exemplary embodiment, such as Figure 3 and Figure 4 As shown, the driving sub-circuit may include a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.

[0155] The third transistor T3 can be called the driving transistor. The third transistor T3 determines the driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on the potential difference between its control terminal and the first terminal.

[0156] In one exemplary embodiment, such as Figure 3 and Figure 4 As shown, the light-emitting control sub-circuit may include a fifth transistor T5 and a sixth transistor T6. Specifically, the control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. Similarly, the control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0157] The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (LEDs). When the signal at the light-emitting signal terminal EM is at an active level, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a drive current path between the first power supply terminal VDD and the second power supply terminal VSS.

[0158] Figure 3 and Figure 4 The diagram illustrates an exemplary structure of the first node control subcircuit, the light-emitting control subcircuit, and the driving subcircuit. It will be readily understood by those skilled in the art that the implementation of the first node control subcircuit, the light-emitting control subcircuit, and the driving subcircuit is not limited to this.

[0159] In one exemplary embodiment, such as Figure 3 As shown, the second node control sub-circuit may include a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first terminal of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2, and the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4.

[0160] In one exemplary embodiment, such as Figure 4 As shown, the second node control sub-circuit may include a seventh transistor T7 and an eighth transistor T8. Specifically, the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. Similarly, the control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal Reset2, the first electrode of the eighth transistor T8 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3.

[0161] In one exemplary embodiment, such as Figure 3As shown, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Since the first transistor T1 to the seventh transistor T7 are of the same type, using the same type of transistor in the pixel circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves the product yield.

[0162] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0163] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon transistors.

[0164] In one exemplary embodiment, some of the transistors in the first transistor T1 to the seventh transistor T7 can be oxide transistors, and some transistors can be low-temperature polysilicon transistors. Oxide transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0165] In one exemplary embodiment, such as Figure 4 As shown, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Since the first transistor T1 to the eighth transistor T8 are of the same type, using the same type of transistor in the pixel circuit simplifies the process flow, reduces the manufacturing difficulty of the display substrate, and improves product yield.

[0166] In one exemplary embodiment, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0167] In one exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be low-temperature polysilicon transistors.

[0168] In one exemplary embodiment, some of the transistors, from the first transistor T1 to the eighth transistor T8, can be oxide transistors, and some can be low-temperature polysilicon transistors. Oxide transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0169] The following is through Figure 3 The operation of the example pixel circuit illustrates an exemplary embodiment of this disclosure.

[0170] Figure 5 This is the timing diagram for the pixel circuit. Figure 5 This explanation uses P-type transistors, from the first transistor T1 to the seventh transistor T7, as an example. Figure 3The pixel circuit includes transistors T1 to T7, a capacitor C, and nine signal terminals (Data signal terminal, Gate signal terminal, Reset1 first reset signal terminal, Reset2 second reset signal terminal, EM light emission signal terminal, INIT1 first initial signal terminal, INIT2 second initial signal terminal, VDD first power supply terminal, and VSS second power supply terminal). Figure 3 The operation of the pixel circuit can include:

[0171] In the first stage S1, also known as the first initialization stage, the first reset signal terminal Reset1 is low, while the signals of the scan signal terminal Gate, the second reset signal terminal Reset2, and the light-emitting signal terminal EM are all high. When the first reset signal terminal Reset1 is low, the first transistor T1 is turned on, and the signal of the first initial signal terminal INIT1 is provided to the first node N1 to initialize (reset) it, clearing its internal pre-stored voltage and completing the initialization. When the scan signal terminal Gate, the second reset signal terminal Reset2, and the light-emitting signal terminal EM are all high, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. During this stage, the light-emitting element L does not emit light.

[0172] The second stage, S2, is called the data writing stage or threshold compensation stage. During this stage, the signal at the Gate terminal is low, while the signals at the Reset1, Reset2, and EM terminals are high. The Data terminal outputs a data voltage. Because the first node N1 is low, the third transistor T3 is turned on. With the Gate terminal low, the second transistor T2 and the fourth transistor T4 are turned on. The second transistor T2 and the fourth transistor T4 ensure that the data voltage output from the Data terminal is supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the Data terminal and the threshold voltage of the third transistor T3 is charged into capacitor C until the voltage at the first node N1 is Vd - |Vth|, where Vd is the data voltage output from the Data terminal and Vth is the threshold voltage of the third transistor T3. The signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the light-emitting signal terminal EM are all high-level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are cut off. During this stage, the light-emitting element L does not emit light.

[0173] The third stage, S3, is called the second initialization stage. The second reset signal terminal Reset2 is low, while the scan signal terminal Gate, the first reset signal terminal Reset1, and the light-emitting signal terminal EM are all high. With the second reset signal terminal Reset2 low, the seventh transistor T7 is turned on, and the second initial signal terminal INIT2 is supplied to the fourth node N4 to initialize (reset) the first electrode of the light-emitting element, clearing its internal pre-stored voltage and completing the initialization. With the scan signal terminal Gate, the first reset signal terminal Reset1, and the light-emitting signal terminal EM all high, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. During this stage, the light-emitting element L does not emit light.

[0174] The fourth stage, S4, is called the light-emitting stage. The signal at the light-emitting signal terminal EM is low, while the signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the scan signal terminal Gate are high. With these signals high, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are off. With the light-emitting signal terminal EM low, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting element L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element L to emit light.

[0175] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is:

[0176] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0177] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0178] Figure 3The provided pixel circuit initializes the fourth node after the data writing stage, ensuring that the potential of the fourth node is initialized before the light emission stage. This makes the potential of the fourth node of the pixel circuit consistent in the writing frame and the holding frame, reducing the potential jump of the fourth node, ensuring the display uniformity of the writing frame and the holding frame, improving the flicker problem of the display substrate, and enhancing the display effect of the display substrate.

[0179] Figure 4 The provided pixel circuit timing is as follows Figure 5 As shown, Figure 4 The working process of the provided pixel circuit and Figure 3 The difference in the operation of the provided pixel circuits is that... Figure 4 In the second initialization phase, the provided pixel circuit turns on the eighth transistor T8, and the signal from the second initial signal terminal INIT2 is provided to the third node N3 to initialize (reset) the third node N3, clearing its internal pre-stored voltage and completing the initialization. Figure 4 In the second initialization phase, both the third node N3 and the fourth node N4 were initialized.

[0180] Figure 4 The provided pixel circuit initializes the third and fourth nodes after the data writing stage, ensuring that the potentials of the third and fourth nodes are initialized before the light emission stage. This makes the potentials of the third and fourth nodes consistent in both the write frame and the guard frame, reducing the potential jumps between the third and fourth nodes, ensuring the display uniformity of the write frame and the guard frame, improving the flicker problem of the display substrate, and enhancing the display effect of the display substrate.

[0181] After testing Figure 4 The provided pixel circuitry is more effective at improving the flicker problem of the display substrate than... Figure 3 The provided pixel circuit improves the flicker problem of the display substrate.

[0182] This disclosure also provides a display substrate, including: a substrate and a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate. The light-emitting structure layer includes: a light-emitting element, and the circuit structure layer includes: pixel circuits arranged in an array and configured to drive the light-emitting element to emit light.

[0183] The pixel circuit is the pixel circuit provided in any of the foregoing embodiments, and its implementation principle and effect are similar, so it will not be described again here.

[0184] In one exemplary embodiment, the display substrate may be a low-temperature polycrystalline oxide (LTPO) display substrate or a low-temperature polycrystalline silicon (LTPS) display substrate.

[0185] In one exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and conductive foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In one exemplary embodiment, the light-emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on the substrate; the anode layer includes an anode; the organic structure layer includes an organic light-emitting layer; and the cathode layer includes a cathode.

[0186] In one exemplary embodiment, the light-emitting element includes: a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element, wherein the first light-emitting element emits red light, the second light-emitting element emits blue light, and the third and fourth light-emitting elements emit green light; the area of ​​the anode of the second light-emitting element is larger than the area of ​​the anode of the first light-emitting element, and the anodes of the third and fourth light-emitting elements are symmetrical about a virtual straight line extending along the first direction.

[0187] In one exemplary embodiment, a virtual straight line extending along a first direction passes through the anodes of the first light-emitting element and the second light-emitting element; a virtual straight line extending along a second direction passes through the anodes of the first light-emitting element and the second light-emitting element; a virtual straight line extending along the first direction passes through the anodes of the third light-emitting element and the fourth light-emitting element; a virtual straight line extending along the second direction passes through the anodes of the third light-emitting element and the fourth light-emitting element; and four anodes of the second light-emitting element, two anodes of the third light-emitting element, and two anodes of the fourth light-emitting element are disposed around the anode of the first light-emitting element.

[0188] In one exemplary embodiment, the shape of the boundary of the anode of at least one second light-emitting element includes at least one rounded corner.

[0189] In one exemplary embodiment, the pixel definition layer includes: a first anode via to a fourth anode via, the first anode via exposing the anode of a first light-emitting element, the second anode via exposing the anode of a second light-emitting element, the third anode via exposing the anode of a third light-emitting element, and the fourth anode via exposing the anode of a fourth light-emitting element;

[0190] In one exemplary embodiment, the shape of the boundary of the second anode via includes: a plurality of rounded corners, one of which is located on the side of the second anode via away from the enclosed first anode via, the rounded corners of the four second anode vias surrounding the first anode via away from the first anode via forming the four rounded corners of a rounded prism, and the first anode via passing through the centerline of the rounded prism.

[0191] In one exemplary embodiment, the display substrate may further include: a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of scan signal lines, a plurality of light emission signal lines, a plurality of first initial signal lines and a plurality of second initial signal lines extending along a first direction and arranged along a second direction, as well as a plurality of first power lines and a plurality of data signal lines extending along the second direction and arranged along the first direction; the first direction intersects the second direction.

[0192] In one exemplary embodiment, the first reset signal terminal of the pixel circuit is electrically connected to the first reset signal line, the second reset signal terminal is electrically connected to the second reset signal line, the scan signal terminal is electrically connected to the scan signal line, the light emission signal terminal is electrically connected to the light emission signal line, the first initial signal terminal is electrically connected to the first initial signal line, the second initial signal terminal is electrically connected to the second initial signal line, the first power supply terminal is electrically connected to the first power supply line, and the data signal terminal is electrically connected to the data signal line.

[0193] In one exemplary embodiment, when the pixel circuit is Figure 4 When providing a pixel circuit, the circuit structure layer may include: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a planarization layer, and a fourth conductive layer, which are sequentially stacked on the substrate.

[0194] In one exemplary embodiment, the semiconductor layer may include: the active layer of the first transistor to the active layer of the eighth transistor located in at least one pixel circuit.

[0195] In one exemplary embodiment, the first conductive layer may include: a first reset signal line, a second reset signal line, a scan signal line, a light emission signal line, and a first electrode of a capacitor located in at least one pixel circuit and the control electrode of a first transistor to the control electrode of an eighth transistor.

[0196] In one exemplary embodiment, the second conductive layer may include: a first initial signal line, a second initial signal line, and a second plate of a capacitor located in at least one pixel circuit, wherein the second plates of capacitors in adjacent pixel circuits located in the same row are electrically connected.

[0197] In one exemplary embodiment, the third conductive layer may include: the first and second terminals of the first transistor, the first terminal of the second transistor, the first terminal of the fourth transistor, the first terminal of the fifth transistor, the second terminal of the sixth transistor, the first and second terminals of the seventh transistor, and the first and second terminals of the eighth transistor.

[0198] In one exemplary embodiment, the fourth conductive layer may include a first power line and a data signal line.

[0199] In one exemplary embodiment, the active layer of the transistor includes: a channel region and a first electrode connection portion and a second electrode connection portion located on both sides of the channel region. The first electrode connection portion of the active layer of the third transistor is multiplexed as the first electrode of the third transistor, the second electrode of the fourth transistor, and the second electrode of the fifth transistor; the second electrode connection portion of the active layer of the third transistor is multiplexed as the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode of the sixth transistor.

[0200] In one exemplary embodiment, the first reset signal line and the scan signal line connected to the pixel circuit are located on the same side of the first electrode plate of the pixel circuit, and the first reset signal line is located on the side of the scan signal line away from the first electrode plate of the pixel circuit.

[0201] In one exemplary embodiment, the light-emitting signal line and the second reset signal line connected to the pixel circuit are located on the side of the first electrode of the pixel circuit away from the scan signal line, and the second reset signal line is located on the side of the light-emitting signal line away from the first electrode of the pixel circuit.

[0202] In one exemplary embodiment, the first initial signal line and the second initial signal line connected to the pixel circuit are respectively located on opposite sides of the second plate of the capacitor of the pixel circuit, and the second initial signal line connected to the (i-1)th row pixel circuit is located between the first initial signal line connected to the i-th row pixel circuit and the second plate of the capacitor of the i-th row pixel circuit.

[0203] In one exemplary embodiment, the orthographic projection of the first reset signal line connected to the i-th row pixel circuit on the substrate is located between the orthographic projection of the first initial signal line connected to the i-th row pixel circuit on the substrate and the orthographic projection of the second initial signal line connected to the (i-1)-th row pixel circuit on the substrate.

[0204] In one exemplary embodiment, the orthographic projection of the scan signal line connected to the i-th row pixel circuit on the substrate is located between the orthographic projection of the second initial signal line connected to the (i-1)-th row pixel circuit on the substrate and the orthographic projection of the second plate of the capacitor of the i-th row pixel circuit on the substrate.

[0205] In one exemplary embodiment, the first initial signal line includes: a plurality of first initial main body portions and a first initial connecting portion arranged at intervals and along a first direction, wherein the first initial connecting portion is configured to connect two adjacent first initial main body portions.

[0206] In one exemplary embodiment, the length of the first initial main body portion along the second direction is greater than the length of the first initial connecting portion along the second direction.

[0207] In one exemplary embodiment, the orthographic projection of the first initial main body portion on the substrate partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate, while the orthographic projection of the first initial connection portion on the substrate and the orthographic projection of the active layer of the first transistor on the substrate do not overlap.

[0208] In one exemplary embodiment, the second initial signal line includes: a second initial body portion extending along a first direction, a first connecting portion located on a first side of the second initial body portion, and a second connecting portion and a third connecting portion located on a second side of the second initial body portion, wherein the first side and the second side are disposed opposite to each other, and the first side of the (i-1)th second initial signal line is the side closer to the i-th first initial signal line.

[0209] In one exemplary embodiment, the first connection portion extends along the second direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate.

[0210] In one exemplary embodiment, the second connection portion extends along a second direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate.

[0211] In one exemplary embodiment, the third connection portion extends along the second direction, and its orthographic projection on the substrate does not overlap with the orthographic projections of the active layers of the first transistor and the second transistor on the substrate.

[0212] In one exemplary embodiment, the orthographic projection of the third connection portion of the second initial signal line onto the substrate is located between the orthographic projection of the first electrode of the second transistor onto the substrate and the orthographic projection of the data signal line onto the substrate.

[0213] In one exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer are provided with a first via to an eighth via, the third via exposing the second electrode connection portion of the active layer of the third transistor, the fourth via exposing the active layer of the fourth transistor, and the eighth via exposing the active layer of the eighth transistor.

[0214] In one exemplary embodiment, the second electrode of the eighth transistor includes an electrode body portion and an electrode extension portion connected to each other, wherein the electrode body portion extends along a second direction, and the included angle between the electrode body portion and the electrode extension portion is greater than or equal to 90 degrees or less than 180 degrees.

[0215] In one exemplary embodiment, the electrode body is electrically connected to the active layer of the eighth transistor through an eighth via, and its orthographic projection on the substrate overlaps with the orthographic projection of the second electrode plate of the light-emitting signal line and capacitor connected to the pixel circuit on the substrate.

[0216] In one exemplary embodiment, the electrode extension is electrically connected to the second electrode connection portion of the active layer of the third transistor via a third via.

[0217] In one exemplary embodiment, the adjacent pixel circuits located in the same row as the pixel circuits include: a first adjacent pixel circuit and a second adjacent pixel circuit, wherein the first adjacent pixel circuit is located on the side of the first power line connected to the pixel circuit that is away from the data signal line, and the second adjacent pixel circuit is located on the side of the data signal line connected to the pixel circuit that is away from the first power line.

[0218] In one exemplary embodiment, a virtual straight line extending along a second direction passes through the active layer of the eighth transistor of the pixel circuit and the fourth via of the first adjacent pixel circuit, respectively.

[0219] In one exemplary embodiment, a virtual straight line extending along a second direction passes through the electrode body portion of the pixel circuit and the fourth via of the first adjacent pixel circuit, respectively.

[0220] This disclosure ensures the reliability of the display substrate through an alignment process by using a virtual straight line extending along a second direction to pass through the active layer of the eighth transistor of the pixel circuit and the fourth via of the first adjacent pixel circuit, and by using a virtual straight line extending along a second direction to pass through the electrode body of the pixel circuit and the fourth via of the first adjacent pixel circuit.

[0221] In one exemplary embodiment, the orthographic projection of the first power line connected to the pixel circuit on the substrate is located between the orthographic projection of the data signal line connected to the pixel circuit on the substrate and the orthographic projection of the second electrode of the first transistor of the pixel circuit on the substrate.

[0222] In one exemplary embodiment, the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the third connection portion of the second initial signal line on the substrate.

[0223] In one exemplary embodiment, the orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projection of the electrode body portion of the first adjacent pixel circuit to which the data signal line is connected on the substrate. The electrode body portion of the first adjacent pixel circuit in this disclosure can flatten the data signal line of the pixel circuit.

[0224] The structure of a display substrate is illustrated below using an example of the fabrication process of the display substrate. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying and spin coating; and etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0225] Figures 6 to 14B A schematic diagram of the fabrication process of a display substrate provided for an exemplary embodiment. Figures 6 to 14B This explanation uses a one-row, two-column pixel circuit as an example. For example... Figures 6 to 14B As shown, the manufacturing process of a display substrate provided in an exemplary embodiment may include:

[0226] (1) Forming a semiconductor layer pattern on a substrate, including: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer pattern, such as... Figure 6 As shown, Figure 6 This is a schematic diagram after the semiconductor layer pattern has been formed.

[0227] In one exemplary embodiment, such as Figure 6 As shown, the semiconductor layer includes: an active layer T11 of a first transistor, an active layer T21 of a second transistor, an active layer T31 of a third transistor, an active layer T41 of a fourth transistor, an active layer T51 of a fifth transistor, an active layer T61 of a sixth transistor, an active layer T71 of a seventh transistor, and an active layer T81 of an eighth transistor located in at least one pixel circuit.

[0228] In one exemplary embodiment, the active layer T11 of the first transistor to the active layer T81 of the eighth transistor can be an integrally formed structure.

[0229] In one exemplary embodiment, the active layer of the third transistor includes a first side, a second side, and a third side, wherein the first side and the second side are disposed opposite to each other. Specifically, the active layers T21 of the second transistor, T61 of the sixth transistor, and T81 of the eighth transistor are located on the first side of the active layer T31 of the third transistor; the active layers T41 of the fourth transistor and T51 of the fifth transistor are located on the second side of the active layer T31 of the third transistor; and the active layer T11 of the first transistor is located on the third side of the active layer T31 of the third transistor.

[0230] In one exemplary embodiment, the active layer T81 of the eighth transistor is located on the side of the active layer T71 of the seventh transistor away from the active layer T31 of the third transistor.

[0231] (2) Forming a first conductive layer pattern includes: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, such as... Figure 7A and Figure 7B As shown, where, Figure 7A This is a schematic diagram of the pattern of the first conductive layer. Figure 7B This is a schematic diagram after the first conductive layer pattern has been formed.

[0232] In one exemplary embodiment, such as Figure 7A As shown, the first conductive layer may include: a first electrode C1 of a capacitor located in at least one pixel circuit, which extends along a first direction and is arranged along a second direction, a plurality of first reset signal lines RL1, a plurality of first reset signal lines RL2, a plurality of scan signal lines GL, a plurality of light emission signal lines EL, a gate electrode T12 of a first transistor, a gate electrode T22 of a second transistor, a gate electrode T32 of a third transistor, a gate electrode T42 of a fourth transistor, a gate electrode T52 of a fifth transistor, a gate electrode T62 of a sixth transistor, a gate electrode T72 of a seventh transistor, and a gate electrode T82 of an eighth transistor. Figure 7A In the diagram, RL1(i) is the i-th first reset signal line, RL2(i) is the i-th second reset signal line, GL(i) is the i-th scan signal line, and EL(i) is the i-th light emission signal line.

[0233] In one exemplary embodiment, such as Figure 7A and Figure 7BAs shown, the first reset signal line RL1 and the scan signal line GL connected to the pixel circuit are located on the same side of the first electrode C1 of the pixel circuit, and the first reset signal line RL1 is located on the side of the scan signal line GL away from the first electrode C1 of the pixel circuit. The light emission signal line EL and the second reset signal line RL2 connected to the pixel circuit are located on the side of the first electrode C1 of the pixel circuit away from the scan signal line GL, and the second reset signal line RL2 is located on the side of the light emission signal line EL away from the first electrode C1 of the pixel circuit.

[0234] In one exemplary embodiment, such as Figure 7A and Figure 7B As shown, for the pixel circuit, the gate electrode T12 of the first transistor and the first reset signal line RL1 connected to the pixel circuit are integrally formed; the gate electrodes T22 and T42 of the second transistor and the scan signal line GL connected to the pixel circuit are integrally formed; the gate electrode T32 of the third transistor and the first plate C1 of the capacitor are integrally formed; the gate electrodes T52 and T62 of the fifth transistor and the light emission signal line EL connected to the pixel circuit are integrally formed; and the gate electrodes T72 of the seventh transistor and T82 of the eighth transistor and the second reset signal line RL2 connected to the pixel circuit are integrally formed.

[0235] In one exemplary embodiment, the gate electrode T12 of the first transistor is disposed across the active layer of the first transistor, the gate electrode T22 of the second transistor is disposed across the active layer of the second transistor, the gate electrode T32 of the third transistor is disposed across the active layer of the third transistor, the gate electrode T42 of the fourth transistor is disposed across the active layer of the fourth transistor, the gate electrode T52 of the fifth transistor is disposed across the active layer of the fifth transistor, the gate electrode T62 of the sixth transistor is disposed across the active layer of the first transistor, the gate electrode T72 of the seventh transistor is disposed across the active layer of the seventh transistor, and the gate electrode T82 of the eighth transistor is disposed across the active layer of the eighth transistor. That is, the extending direction of the gate electrode of at least one transistor is perpendicular to the extending direction of the active layer.

[0236] In one exemplary embodiment, the process further includes a conductor-enhancing process. The conductor-enhancing process involves, after forming the first conductive layer pattern, using the semiconductor layer in the control electrode shielding region of multiple transistors (i.e., the region where the semiconductor layer overlaps with the control electrode) as the channel region of the transistor, and processing the semiconductor layer in the region not shielded by the first conductive layer into a conductor-enhancing layer to form the first electrode connection portion and the second electrode connection portion of the transistor. For example... Figure 7BAs shown, the second electrode connection portion of the active layer of the third transistor can be reused as the first electrode T63 of the sixth transistor, the second electrode T24 of the second transistor, and the second electrode T34 of the third transistor. The second electrode connection portion of the active layer of the third transistor can be reused as the second electrode T54 of the fifth transistor, the first electrode T33 of the third transistor, and the second electrode T44 of the fourth transistor.

[0237] (3) Forming a second conductive layer pattern includes: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; and patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer. Figure 8A and Figure 8B As shown, Figure 8A This is a schematic diagram of the pattern of the second conductive layer. Figure 8B This is a schematic diagram after the second conductive layer pattern has been formed.

[0238] In one exemplary embodiment, such as Figure 8A and Figure 8B As shown, the second conductive layer may include: a plurality of first initial signal lines INL1 extending along a first direction and arranged along a second direction, a plurality of second initial signal lines INL2, and a second plate C2 of a capacitor located in at least one pixel circuit. Figure 8A In this context, INL1(i) is the i-th first initial signal line, and INL2(i) is the i-th second initial signal line.

[0239] In one exemplary embodiment, such as Figure 8A and Figure 8B As shown, the first initial signal line and the second initial signal line connected to the pixel circuit are located on opposite sides of the second plate of the capacitor of the pixel circuit, that is, the first initial signal line connected to the pixel circuit is located on one side of the second plate of the capacitor of the pixel circuit, and the second initial signal line connected to the pixel circuit is located on the other side of the second plate of the capacitor of the pixel circuit.

[0240] In one exemplary embodiment, the second initial signal line INL2(i-1) connected to the (i-1)th row pixel circuit is located between the first initial signal line INL1(i) connected to the i-th row pixel circuit and the second plate C2 of the capacitor of the i-th row pixel circuit.

[0241] In one exemplary embodiment, the orthographic projection of the first reset signal line connected to the i-th row pixel circuit on the substrate is located between the orthographic projection of the first initial signal line connected to the i-th row pixel circuit on the substrate and the orthographic projection of the second initial signal line connected to the (i-1)-th row pixel circuit on the substrate.

[0242] In one exemplary embodiment, the orthographic projection of the scan signal line connected to the i-th row pixel circuit on the substrate is located between the orthographic projection of the second initial signal line connected to the (i-1)-th row pixel circuit on the substrate and the orthographic projection of the second substrate of the capacitor of the i-th row pixel circuit on the substrate.

[0243] In one exemplary embodiment, the orthographic projection of the second plate of the capacitor in the pixel circuit onto the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor onto the substrate, and the second plate of the capacitor is provided with a via exposing the first plate of the capacitor.

[0244] In one exemplary embodiment, the second plates C2 of capacitors in adjacent pixel circuits located in the same row are connected. Electrical connection of the second plates C2 of capacitors in adjacent pixel circuits located in the same row can improve the uniformity of the display substrate display.

[0245] In one exemplary embodiment, the first initial signal line includes: a plurality of first initial main body portions INL1_M and a plurality of first initial connection portions INL1_C arranged at intervals along a first direction, wherein the first initial connection portions are configured to connect two adjacent first initial main body portions.

[0246] In one exemplary embodiment, the length of the first initial main body portion along the second direction is greater than the length of the first initial connecting portion along the second direction.

[0247] In one exemplary embodiment, the orthographic projection of the first initial main body portion on the substrate partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate, while the orthographic projection of the first initial connection portion on the substrate and the orthographic projection of the active layer of the first transistor on the substrate do not overlap.

[0248] In one exemplary embodiment, the second initial signal line includes: a second initial body portion INL2_M extending along a first direction, a first connecting portion INL2A located on a first side of the second initial body portion INL2_M, and a second connecting portion INL2B and a third connecting portion INL2C located on a second side of the second initial body portion INL2_M, wherein the first side and the second side are disposed opposite to each other. The first side is the side close to the second plate of the capacitor of the pixel circuit to which the second initial signal line is connected.

[0249] In one exemplary embodiment, the first connection portion INL2A extends along a second direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the first transistor on the substrate. This at least partial overlap ensures the stability of the current in the first transistor, thereby improving the display effect of the display panel.

[0250] In one exemplary embodiment, the second connection portion INL2B extends along a second direction, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate. This at least partial overlap ensures the stability of the current in the second transistor, thereby improving the display effect of the display panel.

[0251] In one exemplary embodiment, the third connection portion INL2C extends along the second direction, and its orthographic projection on the substrate does not overlap with the orthographic projections of the active layers of the first transistor and the second transistor on the substrate.

[0252] In one exemplary embodiment, the length of the first connecting portion INL2A along the second direction to the length of the third connecting portion INL2C along the second direction are both greater than the length of the second initial main body portion along the second direction.

[0253] (4) Forming a third insulating layer pattern includes: depositing a third insulating film on a substrate having the aforementioned pattern, and patterning the third insulating film using a patterning process to form a third insulating layer pattern covering the aforementioned pattern. The third insulating layer has multiple via patterns, such as... Figures 9A to 9B As shown, Figure 9A This is a schematic diagram of the pattern of the third insulating layer. Figure 9B This is a schematic diagram after the third insulating layer pattern has been formed.

[0254] In one exemplary embodiment, such as Figure 9A and Figure 9B As shown, the multiple via patterns include: first vias V1 to eighth vias V8 disposed in the first insulating layer, the second insulating layer and the third insulating layer, ninth vias V9 disposed in the second insulating layer and the third insulating layer, and tenth vias V10 to twelfth vias V12 disposed in the third insulating layer. Specifically, for at least one pixel circuit, a first via V1 exposes the active layer of the first transistor, a second via V2 exposes the active layer of the second transistor, a third via V3 exposes the second electrode connection portion of the active layer of the third transistor, a fourth via V4 exposes the active layer of the fourth transistor, a fifth via V5 exposes the active layer of the fifth transistor, a sixth via V6 exposes the active layer of the sixth transistor, a seventh via V7 exposes the active layer of the seventh transistor, an eighth via V8 exposes the active layer of the eighth transistor, a ninth via V9 exposes the first plate of a capacitor, a tenth via V10 exposes the first initial signal line connected to the pixel circuit, an eleventh via V11 exposes the second plate of a capacitor, and a twelfth via V12 exposes the second initial signal line connected to the pixel circuit.

[0255] In one exemplary embodiment, a virtual straight line extending along the second direction passes through the active layer of the eighth transistor of the pixel circuit and the fourth via of the first adjacent pixel circuit, respectively.

[0256] (5) Forming a third conductive layer pattern includes: depositing a third conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive thin film using a patterning process to form a first conductive layer pattern, such as... Figure 10A and Figure 10B As shown, Figure 10A This is a schematic diagram of the pattern of the third conductive layer. Figure 10B This is a schematic diagram after the third conductive layer pattern has been formed.

[0257] In one exemplary embodiment, such as Figure 10A and Figure 10B As shown, the third conductive layer may include: the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, and the first electrode T83 and the second electrode T84 of the eighth transistor.

[0258] In one exemplary embodiment, the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are integrally formed, the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor are integrally formed, and the first electrode T73 of the seventh transistor and the first electrode T83 of the eighth transistor are integrally formed.

[0259] In one exemplary embodiment, the first electrode T13 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the fifth transistor T53, and the first electrode T73 and the second electrode T74 of the seventh transistor all extend along a second direction.

[0260] In one exemplary embodiment, the orthographic projection of the first electrode T13 of the first transistor on the substrate overlaps with the orthographic projection portions of the first initial signal line and the first reset signal line connected to the pixel circuit on the substrate.

[0261] In one exemplary embodiment, the orthographic projection of the first electrode T23 of the second transistor on the substrate overlaps with the orthographic projection of the scan signal line connected to the pixel circuit and the first electrode plate of the capacitor on the substrate.

[0262] In one exemplary embodiment, the orthographic projection of the first electrode T43 of the fourth transistor on the substrate overlaps with the orthographic projection of the second initial signal line connected to the adjacent row pixel circuit on the substrate. Specifically, the orthographic projection of the first electrode T43 of the fourth transistor on the substrate overlaps with the orthographic projection of the second initial main body portion of the second initial signal line connected to the adjacent row pixel circuit on the substrate, but there is no overlap with the orthographic projection of the third connection portion of the second initial signal line connected to the adjacent row pixel circuit on the substrate.

[0263] In one exemplary embodiment, the orthographic projection of the fifth transistor T53 on the substrate overlaps with the orthographic projection of the light-emitting signal line connected to the pixel circuit and the second plate of the capacitor on the substrate.

[0264] In one exemplary embodiment, the orthographic projection of the first electrode T73 of the seventh transistor onto the substrate overlaps with the orthographic projections of the first initial signal line and the first reset signal line connected to the next row of pixel circuits onto the substrate.

[0265] In one exemplary embodiment, the orthographic projection of the second electrode T84 of the eighth transistor onto the substrate overlaps with the orthographic projection of the second electrode of the light-emitting signal line and capacitor connected to the pixel circuit onto the substrate.

[0266] In one exemplary embodiment, the second electrode T84 of the eighth transistor includes an electrode body portion T84A and an electrode extension portion T84B connected to each other, wherein the electrode body portion T84A extends along a second direction, and the included angle between the electrode body portion T84A and the electrode extension portion T84B is greater than or equal to 90 degrees or less than 180 degrees.

[0267] In one exemplary embodiment, the electrode body T84A is electrically connected to the active layer of the eighth transistor through the eighth via, and its orthographic projection on the substrate overlaps with the orthographic projection of the second electrode plate of the light-emitting signal line and capacitor connected to the pixel circuit on the substrate.

[0268] In one exemplary embodiment, the electrode extension T84B is electrically connected to the second electrode connection portion of the active layer of the third transistor via a third via.

[0269] In one exemplary embodiment, a virtual straight line extending along the second direction passes through the electrode body portion T84A of the pixel circuit and the fourth via of the first adjacent pixel circuit, respectively.

[0270] In one exemplary embodiment, the first electrode T13 of the first transistor is connected to the active layer of the first transistor through a first via V1 and is electrically connected to the first initial signal line connected to the pixel circuit through a tenth via V10. The first electrode T23 of the second transistor is electrically connected to the active layer of the second transistor through a second via and is electrically connected to the first plate of the capacitor through a ninth via. The second electrode of the eighth transistor is electrically connected to the active layer of the eighth transistor through an eighth via and is electrically connected to the second electrode connection portion of the active layer of the third transistor through a third via. The first electrode T43 of the fourth transistor is electrically connected to the active layer of the fourth transistor through a fourth via. The first electrode T53 of the fifth transistor is electrically connected to the active layer of the fifth transistor through a fifth via V5 and is electrically connected to the second plate of the capacitor through an eleventh via. The second electrode T64 of the sixth transistor is electrically connected to the active layer of the sixth transistor through a sixth via. The first electrode T73 of the seventh transistor is electrically connected to the active layer of the seventh transistor through a seventh via V7 and is electrically connected to the second initial signal line connected to the pixel circuit through a twelfth via.

[0271] (6) Forming a planarization layer pattern includes: coating a planarization film on a substrate having the aforementioned pattern, and patterning the planarization film using a patterning process to form a planarization layer pattern covering the aforementioned pattern, wherein the planarization layer has multiple via patterns, such as Figure 11A and Figure 11B As shown, Figure 11A This is a schematic diagram of a planarization layer pattern. Figure 11B This is a schematic diagram after the flattened layer pattern has been formed.

[0272] In one exemplary embodiment, such as Figure 11A and Figure 11B As shown, the multiple via patterns include thirteenth vias V13 to fifteenth vias V15 located in at least one pixel circuit through the fourth insulating layer. Specifically, thirteenth via V13 exposes the first terminal of the fourth transistor, fourteenth via V14 exposes the first terminal of the fifth transistor, and fifteenth via V15 exposes the second terminal of the sixth transistor.

[0273] (7) Forming a fourth conductive layer pattern includes: depositing a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second conductive film using a patterning process to form a second conductive layer pattern, such as... Figure 12A and Figure 12B As shown, Figure 12A This is a schematic diagram of the pattern of the fourth conductive layer. Figure 12B This is a schematic diagram after the fourth conductive layer pattern has been formed.

[0274] In one exemplary embodiment, such as Figure 12A and Figure 12BAs shown, the fourth conductive layer may include: multiple first power lines VDDL extending along a second direction and arranged along a first direction, multiple data signal lines DL, and a connecting electrode CL. The data signal lines connected to the pixel circuit are located on the side of the first power lines connected to the pixel circuit that is furthest from the connecting electrode.

[0275] In one exemplary embodiment, the length of the first power line VDDL along the first direction is greater than the length of the data signal line DL along the first direction.

[0276] In one exemplary embodiment, the orthographic projection of the third connection portion of the second initial signal line onto the substrate is located between the orthographic projection of the first electrode of the second transistor onto the substrate and the orthographic projection of the data signal line DL onto the substrate.

[0277] In one exemplary embodiment, the data signal line DL connected to the pixel circuit is electrically connected to the first electrode of the fourth transistor through the thirteenth via, the first power line VDDL connected to the pixel circuit is electrically connected to the first electrode of the fifth transistor through the fourteenth via, and the connection electrode CL is electrically connected to the second electrode of the sixth transistor through the fifteenth via.

[0278] In one exemplary embodiment, the orthographic projection of the first power line VDDL on the substrate at least partially overlaps with the orthographic projection of the third connection portion of the second initial signal line on the substrate.

[0279] In one exemplary embodiment, the orthographic projection of the data signal line DL on the substrate and the orthographic projection of the third connection portion of the second initial signal line on the substrate do not overlap.

[0280] In one exemplary embodiment, the orthographic projection of the data signal line DL on the substrate at least partially overlaps with the orthographic projection of the electrode body portion of the first adjacent pixel circuit to which the data signal line DL is connected on the substrate.

[0281] In one exemplary embodiment, the orthographic projection of the third connection portion of the second initial signal line onto the substrate is located between the orthographic projection of the first electrode of the second transistor onto the substrate and the orthographic projection of the data signal line onto the substrate. This location allows the third connection portion of the second initial signal line to shield both the first electrode of the second transistor and the data signal line, thereby improving the display effect of the display substrate.

[0282] (8) Forming an anode layer includes: coating a second planarization film on a substrate with the aforementioned pattern, patterning the second planarization film to form a second planarization layer pattern, depositing a transparent conductive film on the substrate with the aforementioned pattern, and patterning the transparent conductive film using a patterning process to form an anode layer pattern, such as... Figure 13A and Figure 13B As shown, Figure 13A This is a schematic diagram of the anode layer. Figure 13B This is a schematic diagram after the anode layer has been formed. Figure 13B This explanation will take the formation of the anode on two pixel circuits as an example.

[0283] In one exemplary embodiment, the anode layer includes: the anode RA of the first light-emitting element, the anode BA of the second light-emitting element, the anode GA1 of the third light-emitting element, and the anode GA2 of the fourth light-emitting element.

[0284] In one exemplary embodiment, such as Figure 13A As shown, the area of ​​the anode BA of the second light-emitting element is larger than the area of ​​the anode RA of the first light-emitting element, and the anode GA1 of the third light-emitting element and the anode GA2 of the fourth light-emitting element are symmetrical about a virtual straight line extending along the first direction.

[0285] In one exemplary embodiment, such as Figure 13A As shown, a virtual straight line extending along the first direction passes through the anode RA of the first light-emitting element and the anode BA of the second light-emitting element, and a virtual straight line extending along the second direction passes through the anode RA of the first light-emitting element and the anode BA of the second light-emitting element.

[0286] In one exemplary embodiment, a virtual straight line extending along a first direction passes through the anode GA1 of the third light-emitting element and the anode GA2 of the fourth light-emitting element. A virtual straight line extending along a second direction also passes through the anode GA1 of the third light-emitting element and the anode GA2 of the fourth light-emitting element.

[0287] In one exemplary embodiment, four anodes of first light-emitting elements, two anodes of third light-emitting elements, and two anodes of fourth light-emitting elements are disposed around the anode of the second light-emitting element.

[0288] In one exemplary embodiment, the shape of the boundary of the anode BA of at least one second light-emitting element includes at least one rounded corner CC1.

[0289] (9) Forming a pixel definition layer includes depositing a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer pattern that exposes the anode of the light-emitting element, such as... Figure 14A and Figure 14B As shown, Figure 14A A schematic diagram of a pixel-defined layer. Figure 14B This is a schematic diagram after the pixel definition layer has been formed. Figure 14B This explanation will be based on the example of forming pixel definition layers on two pixel circuits.

[0290] In one exemplary embodiment, such as Figure 14A As shown, the pixel definition layer includes: a first anode via RV, a second anode via BV, a third anode via GV1, and a fourth anode via GV2. Specifically, the first anode via RV exposes the anode of the first light-emitting element, the second anode via BV exposes the anode of the second light-emitting element, the third anode via GV1 exposes the anode of the third light-emitting element, and the fourth anode via GV2 exposes the anode of the fourth light-emitting element.

[0291] In one exemplary embodiment, such as Figure 14A As shown, the shape of the boundary of the second anode via includes: multiple rounded corners CC2, one of which is located on the side of the second anode via BV away from the first anode via RV it surrounds, and the rounded corners of the four second anode vias BV surrounding the first anode via RV that are away from the first anode via RV form the four rounded corners of the rounded rhombus L, and the second anode via BV passes through the centerline of the rounded rhombus.

[0292] (10) Form an organic structure layer and a cathode layer. On the substrate with the aforementioned pattern, an organic light-emitting material is coated. The organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode film is deposited. The cathode film is patterned by a patterning process to form a cathode layer.

[0293] In one exemplary embodiment, the organic structure layer may include an organic light-emitting layer of a light-emitting element.

[0294] In one exemplary embodiment, the cathode layer may include the cathode of a light-emitting element.

[0295] In one exemplary embodiment, the semiconductor layer may be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0296] In one exemplary embodiment, the first conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0297] In one exemplary embodiment, the second conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the second conductive layer may include molybdenum.

[0298] In one exemplary embodiment, the third conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the third conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0299] In one exemplary embodiment, the fourth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0300] In one exemplary embodiment, the anode layer may be made of a transparent conductive material, such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0301] In one exemplary embodiment, the cathode layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0302] In one exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The first insulating layer may be referred to as the first gate insulating layer, the second insulating layer may be referred to as the second gate insulating layer, and the third insulating layer may be referred to as the interlayer insulating layer.

[0303] In one exemplary embodiment, the planarization layer may be made of an organic material.

[0304] The display substrate described in this embodiment can be used in display products of any resolution.

[0305] This disclosure also provides a method for driving a pixel circuit. The method for driving a pixel circuit may include the following steps:

[0306] Step 100: In the first initialization phase, the first node control sub-circuit provides the first initial signal terminal to the first node under the control of the first reset signal terminal.

[0307] Step 200: During the data writing phase, the first node control sub-circuit provides the third node's signal to the first node under the control of the scanning signal terminal, and provides the data signal terminal's signal to the second node.

[0308] Step 300: In the second initialization phase, the second node control sub-circuit provides the second initial signal terminal to the fourth node under the control of the second reset signal terminal;

[0309] Step 400: During the light-emitting stage, the driving sub-circuit, under the control of the first and second nodes, provides driving current to the third node. The light-emitting control sub-circuit, under the control of the light-emitting signal terminal, provides the signal of the first power supply terminal to the second node and provides the signal of the third node to the fourth node.

[0310] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0311] In one exemplary embodiment, the driving method for the display substrate may further include: during a second initialization phase, a second node control sub-circuit provides a signal from a second initial signal terminal to a third node under the control of a second reset signal terminal.

[0312] This disclosure also provides a display device, including a display substrate.

[0313] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0314] In one exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0315] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0316] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0317] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel circuit configured to drive a light emitting element to emit light, the pixel circuit comprising: The first node control sub-circuit, the second node control sub-circuit, the light-emitting control sub-circuit and the driving sub-circuit; The working process of the pixel circuit comprises a first initialization stage, a data writing stage, a second initialization stage and a light-emitting stage. The first node control sub-circuit is electrically connected with a first power supply end, a first reset signal end, a first initial signal end, a scanning signal end, a data signal end, a first node, a second node and a third node respectively, and is configured to provide a signal of the first initial signal end to the first node under the control of the first reset signal end, provide a signal of the third node to the first node under the control of the scanning signal end, and provide a signal of the data signal end to the second node. The second node control sub-circuit is electrically connected with a second reset signal end, a second initial signal end and a fourth node respectively, and is configured to provide a signal of the second initial signal end to the fourth node under the control of the second reset signal end. The driving sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node under the control of the first node and the second node. The light-emitting control sub-circuit is electrically connected with a light-emitting signal end, the first power supply end, the second node, the third node and the fourth node respectively, and is configured to provide a signal of the first power supply end to the second node under the control of the light-emitting signal end, and provide a signal of the third node to the fourth node. The light-emitting element is electrically connected with the fourth node and a second power supply end respectively. The second initialization stage occurs between the data writing stage and the light-emitting stage, a signal of the second reset signal end is an effective level signal in the second initialization stage, and the signal of the second reset signal end and a signal of the light-emitting signal end are inverse signals of each other in the second initialization stage. The first reset signal end is an effective level signal in the first initialization stage, the scanning signal end is an effective level signal in the data writing stage, and the light-emitting signal end is an effective level signal in the light-emitting stage. When the signal of the second reset signal end is an effective level signal, the signal of the light-emitting signal end is an ineffective level signal, when the signal of the light-emitting signal end is an effective level signal, the signal of the second reset signal end is an ineffective level signal, and the frequency of the signal of the light-emitting signal end being an effective level signal is the same as the frequency of the signal of the second reset signal end being an effective level signal.

2. The pixel circuit of claim 1, wherein, The second node control sub-circuit is also electrically connected with the third node, and is further configured to provide a signal of the second initial signal end to the third node under the control of the second reset signal end.

3. The pixel circuit of claim 1, wherein, The first node control sub-circuit comprises a first transistor, a second transistor, a fourth transistor and a capacitor, the capacitor comprises a first pole plate and a second pole plate, the driving sub-circuit comprises a third transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor. The control pole of the first transistor is electrically connected with the first reset signal end, the first pole of the first transistor is electrically connected with the first initial signal end, and the second pole of the first transistor is electrically connected with the first node. The control electrode of the second transistor is electrically connected with the scan signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the scan signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node; The first electrode plate of the capacitor is electrically connected with the first node, and the second electrode plate of the capacitor is electrically connected with the first power supply end.

4. The pixel circuit of claim 1, wherein, The second node control subcircuit comprises a seventh transistor. The control electrode of the seventh transistor is electrically connected with the second reset signal end, the first electrode of the seventh transistor is electrically connected with the second initial signal end, and the second electrode of the seventh transistor is electrically connected with the fourth node.

5. The pixel circuit of claim 2, wherein, The second node control subcircuit comprises a seventh transistor and an eighth transistor. The control electrode of the seventh transistor is electrically connected with the second reset signal end, the first electrode of the seventh transistor is electrically connected with the second initial signal end, and the second electrode of the seventh transistor is electrically connected with the fourth node. The control electrode of the eighth transistor is electrically connected with the second reset signal end, the first electrode of the eighth transistor is electrically connected with the second initial signal end, and the second electrode of the eighth transistor is electrically connected with the third node.

6. The pixel circuit of claim 1, wherein, The first node control subcircuit comprises a first transistor, a second transistor, a fourth transistor and a capacitor, the capacitor comprises a first electrode plate and a second electrode plate, the driving subcircuit comprises a third transistor, the light-emitting control subcircuit comprises a fifth transistor and a sixth transistor, and the second node control subcircuit comprises a seventh transistor; The control electrode of the first transistor is electrically connected with the first reset signal end, the first electrode of the first transistor is electrically connected with the first initial signal end, and the second electrode of the first transistor is electrically connected with the first node; The control electrode of the second transistor is electrically connected with the scan signal end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the scan signal end, the first electrode of the fourth transistor is electrically connected with the data signal end, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node; A control electrode of the seventh transistor is electrically connected with the second reset signal terminal, a first electrode of the seventh transistor is electrically connected with the second initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the fourth node; A first plate of the capacitor is electrically connected with the first node, and a second plate of the capacitor is electrically connected with the first power supply terminal.

7. The pixel circuit of claim 2, wherein, The first node control sub-circuit comprises a first transistor, a second transistor, a fourth transistor and a capacitor, the capacitor comprises a first plate and a second plate, the driving sub-circuit comprises a third transistor, the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor, and the second node control sub-circuit comprises a seventh transistor and an eighth transistor; A control electrode of the first transistor is electrically connected with the first reset signal terminal, a first electrode of the first transistor is electrically connected with the first initial signal terminal, and a second electrode of the first transistor is electrically connected with the first node; A control electrode of the second transistor is electrically connected with the scan signal terminal, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the third node; A control electrode of the third transistor is electrically connected with the first node, a first electrode of the third transistor is electrically connected with the second node, and a second electrode of the third transistor is electrically connected with the third node; A control electrode of the fourth transistor is electrically connected with the scan signal terminal, a first electrode of the fourth transistor is electrically connected with the data signal terminal, and a second electrode of the fourth transistor is electrically connected with the second node; A control electrode of the fifth transistor is electrically connected with the light-emitting signal terminal, a first electrode of the fifth transistor is electrically connected with the first power supply terminal, and a second electrode of the fifth transistor is electrically connected with the second node; A control electrode of the sixth transistor is electrically connected with the light-emitting signal terminal, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the fourth node; A control electrode of the seventh transistor is electrically connected with the second reset signal terminal, a first electrode of the seventh transistor is electrically connected with the second initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the fourth node; A control electrode of the eighth transistor is electrically connected with the second reset signal terminal, a first electrode of the eighth transistor is electrically connected with the second initial signal terminal, and a second electrode of the eighth transistor is electrically connected with the third node; A first plate of the capacitor is electrically connected with the first node, and a second plate of the capacitor is electrically connected with the first power supply terminal.

8. A display substrate, comprising: The substrate, the circuit structure layer and the light-emitting structure layer arranged on the substrate in sequence, the light-emitting structure layer comprising a light-emitting element, and the circuit structure layer comprising the pixel circuit of any one of claims 3, 6 and 7 arranged in an array. 9.The display substrate of claim 8, further comprising: A plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of scan signal lines, a plurality of light-emitting signal lines, a plurality of first initial signal lines and a plurality of second initial signal lines extending along a first direction and arranged along a second direction, and a plurality of first power supply lines and a plurality of data signal lines extending along the second direction and arranged along the first direction; the first direction intersects the second direction. A plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of scan signal lines, a plurality of light-emitting signal lines, a plurality of first initial signal lines and a plurality of second initial signal lines extending along a first direction and arranged along a second direction, and a plurality of first power supply lines and a plurality of data signal lines extending along the second direction and arranged along the first direction; the first direction intersects the second direction. The first reset signal end of the pixel circuit is electrically connected with a first reset signal line, the second reset signal end is electrically connected with a second reset signal line, the scanning signal end is electrically connected with a scanning signal line, the light-emitting signal end is electrically connected with a light-emitting signal line, the first initial signal end is electrically connected with a first initial signal line, the second initial signal end is electrically connected with a second initial signal line, the first power supply end is electrically connected with a first power supply line, and the data signal end is electrically connected with a data signal line. 10.The display substrate of claim 9, wherein, When the pixel circuit comprises first to eighth transistors and a capacitor, the circuit structure layer comprises a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a planar layer and a fourth conductive layer which are sequentially stacked on the substrate; The semiconductor layer comprises active layers of the first to eighth transistors in at least one pixel circuit; The first conductive layer comprises a first reset signal line, a second reset signal line, a scanning signal line, a light-emitting signal line, a first plate of the capacitor in at least one pixel circuit and control electrodes of the first to eighth transistors; The second conductive layer comprises a first initial signal line, a second initial signal line and a second plate of the capacitor in at least one pixel circuit, wherein the second plates of the capacitors of adjacent pixel circuits in the same row are connected; The third conductive layer comprises a first electrode and a second electrode of the first transistor, a first electrode of the second transistor, a first electrode of the fourth transistor, a first electrode of the fifth transistor, a second electrode of the sixth transistor, a first electrode and a second electrode of the seventh transistor and a first electrode and a second electrode of the eighth transistor; The fourth conductive layer comprises a first power supply line and a data signal line. 11.The display substrate of claim 10, wherein, The active layer of the transistor comprises a channel region and a first electrode connecting part and a second electrode connecting part which are respectively located on two sides of the channel region; The first electrode connecting part of the active layer of the third transistor is multiplexed as a first electrode of the third transistor, a second electrode of the fourth transistor and a second electrode of the fifth transistor; The second electrode connecting part of the active layer of the third transistor is multiplexed as a second electrode of the second transistor, a second electrode of the third transistor and a first electrode of the sixth transistor. 12.The display substrate of claim 10, wherein, The first reset signal line and the scanning signal line connected with the pixel circuit are located on the same side of the first plate of the pixel circuit, and the first reset signal line is located on the side of the scanning signal line away from the first plate of the pixel circuit; The light-emitting signal line and the second reset signal line connected with the pixel circuit are located on the side of the first plate of the pixel circuit away from the scanning signal line, and the second reset signal line is located on the side of the light-emitting signal line away from the first plate of the pixel circuit; The first initial signal line and the second initial signal line connected with the pixel circuit are respectively located on two sides of the second plate of the capacitor of the pixel circuit, and the second initial signal line connected with the i-1th row of pixel circuits is located between the first initial signal line connected with the i th row of pixel circuits and the second plate of the capacitor of the i th row of pixel circuits. A normal projection of the first reset signal line connected with the i-th row of pixel circuits on the substrate is located between a normal projection of the first initial signal line connected with the i-th row of pixel circuits on the substrate and a normal projection of the second initial signal line connected with the i-1-th row of pixel circuits on the substrate; A normal projection of the scan signal line connected with the i-th row of pixel circuits on the substrate is located between a normal projection of the second initial signal line connected with the i-1-th row of pixel circuits on the substrate and a normal projection of the second plate of the capacitor of the i-th row of pixel circuits on the substrate. 13.The display substrate of claim 10, wherein, The first initial signal line comprises a plurality of first initial body parts and a plurality of first initial connecting parts arranged at intervals and along a first direction, and the first initial connecting parts are arranged to connect adjacent two first initial body parts; A length of the first initial body part along a second direction is greater than a length of the first initial connecting part along the second direction; A normal projection of the first initial body part on the substrate partially overlaps with a normal projection of the active layer of the first transistor on the substrate, and a normal projection of the first initial connecting part on the substrate does not overlap with a normal projection of the active layer of the first transistor on the substrate. 14.The display substrate of claim 13, wherein, The second initial signal line comprises a second initial body part extending along a first direction, and a first connecting part located at a first side of the second initial body part, and a second connecting part and a third connecting part located at a second side of the second initial body part, wherein the first side and the second side are oppositely arranged, and the first side is a side close to the second plate of the capacitor of the pixel circuit connected with the second initial signal line; The first connecting part extends along a second direction, and a normal projection of the first connecting part on the substrate at least partially overlaps with a normal projection of the active layer of the first transistor on the substrate; The second connecting part extends along the second direction, and a normal projection of the second connecting part on the substrate at least partially overlaps with a normal projection of the active layer of the second transistor on the substrate; The third connecting part extends along the second direction, and a normal projection of the third connecting part on the substrate does not overlap with normal projections of the active layer of the first transistor and the active layer of the second transistor on the substrate; A normal projection of the third connecting part of the second initial signal line on the substrate is located between a normal projection of the first electrode of the second transistor on the substrate and a normal projection of the data signal line on the substrate. 15.The display substrate of claim 10, wherein, The first insulating layer, the second insulating layer and the third insulating layer are provided with a first via hole to an eighth via hole, the third via hole exposes a second electrode connecting part of the active layer of the third transistor, the fourth via hole exposes the active layer of the fourth transistor, and the eighth via hole exposes the active layer of the eighth transistor; The second electrode of the eighth transistor comprises an electrode body part and an electrode extension part connected with each other, wherein the electrode body part extends along a second direction, and an included angle between the electrode body part and the electrode extension part is greater than or equal to 90 degrees or less than 180 degrees; The electrode body part is electrically connected with the active layer of the eighth transistor through the eighth via hole, and a normal projection of the electrode body part on the substrate partially overlaps with normal projections of the light-emitting signal line and the second plate of the capacitor connected with the pixel circuit on the substrate; The electrode extension part is electrically connected with the second electrode connecting part of the active layer of the third transistor through the third via hole. 16.The display substrate of claim 15, wherein, The adjacent pixel circuit located in the same row with the pixel circuit comprises a first adjacent pixel circuit and a second adjacent pixel circuit, the first adjacent pixel circuit is located on a side of a first power line connected with the pixel circuit away from a data signal line, and the second adjacent pixel circuit is located on a side of the data signal line connected with the pixel circuit away from the first power line; A virtual straight line extending in the second direction passes through the active layer of the eighth transistor of the pixel circuit and the fourth via hole of the first adjacent pixel circuit respectively; A virtual straight line extending in the second direction passes through the electrode main body part of the pixel circuit and the fourth via hole of the first adjacent pixel circuit respectively. 17.The display substrate of claim 16, wherein, The orthogonal projection of the first power line connected with the pixel circuit on the substrate is located between the orthogonal projection of the data signal line connected with the pixel circuit on the substrate and the orthogonal projection of the second electrode of the first transistor of the pixel circuit on the substrate; The orthogonal projection of the first power line on the substrate at least partially overlaps with the orthogonal projection of the third connection part of the second initial signal line on the substrate; The orthogonal projection of the data signal line on the substrate at least partially overlaps with the orthogonal projection of the electrode main body part of the first adjacent pixel circuit of the pixel circuit connected with the data signal line on the substrate. 18.The display substrate of claim 9, wherein, The at least one light emitting element comprises an anode, an organic light emitting layer and a cathode; the light emitting structure layer comprises an anode layer, a pixel definition layer, an organic structure layer and a cathode layer which are sequentially stacked on the substrate; the anode layer comprises an anode, the organic structure layer comprises an organic light emitting layer, and the cathode layer comprises a cathode; The light emitting element comprises a first light emitting element, a second light emitting element, a third light emitting element and a fourth light emitting element, the first light emitting element emits red light, the second light emitting element emits blue light, and the third light emitting element and the fourth light emitting element emit green light; the area of the anode of the second light emitting element is greater than the area of the anode of the first light emitting element, and the anode of the third light emitting element and the anode of the fourth light emitting element are symmetrical about a virtual straight line extending in the first direction; A virtual straight line extending in the first direction passes through the anode of the first light emitting element and the anode of the second light emitting element, a virtual straight line extending in the second direction passes through the anode of the first light emitting element and the anode of the second light emitting element, a virtual straight line extending in the first direction passes through the anode of the third light emitting element and the anode of the fourth light emitting element, and a virtual straight line extending in the second direction passes through the anode of the third light emitting element and the anode of the fourth light emitting element; the anode of the first light emitting element is surrounded by four anodes of the second light emitting element and two anodes of the third light emitting element and two anodes of the fourth light emitting element; The shape of the boundary of the anode of at least one second light emitting element comprises at least one rounded corner; The pixel definition layer comprises first to fourth anode via holes, the first anode via hole exposes the anode of the first light emitting element, the second anode via hole exposes the anode of the second light emitting element, the third anode via hole exposes the anode of the third light emitting element, and the fourth anode via hole exposes the anode of the fourth light emitting element; The shape of the border of the second anode via hole comprises a plurality of rounded corners, one of the plurality of rounded corners is located on a side of the second anode via hole away from the surrounded first anode via hole, four rounded corners of the second anode via hole away from the first anode via hole and surrounded by the first anode via hole form four rounded corners of a rounded cornered quadrilateral, and the first anode via hole passes through a middle line of the rounded cornered quadrilateral.

19. A display device comprising: The display substrate according to any one of claims 8 to 18.

20. A driving method of a pixel circuit, configured to drive the pixel circuit according to any one of claims 1 to 7, the method comprising: in a first initialization stage, the first node control sub-circuit providing a signal of the first initial signal terminal to the first node under control of the first reset signal terminal; in a data writing stage, the first node control sub-circuit providing a signal of the third node to the first node and a signal of the data signal terminal to the second node under control of the scan signal terminal; in a second initialization stage, the second node control sub-circuit providing a signal of the second initial signal terminal to the fourth node under control of the second reset signal terminal; in a light emitting stage, the driving sub-circuit providing a driving current to the third node under control of the first node and the second node, the light emitting control sub-circuit providing a signal of the first power supply terminal to the second node and a signal of the third node to the fourth node under control of the light emitting signal terminal.

21. The method of claim 20, further comprising: in a second initialization stage, the second node control sub-circuit providing a signal of the second initial signal terminal to the third node under control of the second reset signal terminal.

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