An ultra-high precision second pulse and 10 MHZ signal measurement circuit and method

Abstract

This invention discloses an ultra-high precision second pulse and 10MHz signal measurement circuit and method, relating to time unification technology and signal communication fields. The circuit includes a 10ps-level four-channel first and second TDC chip, a 10MHz high-stability reference clock module, a daisy-chain arrangement of the measurement signal input module, and a power supply ultra-clean module. The first TDC chip, second TDC chip, DC-DC circuit, first-stage clean circuit, and second-stage clean and filter circuit all utilize potted components. The test circuit achieves 10ps peak-to-peak measurement accuracy by selecting a 10ps-level measurement chip, employing power supply ultra-clean technology, high-stability reference clock technology, a daisy-chain arrangement of the measurement and reference clocks, and a device potting and temperature control method, thus improving upon the original device specifications. The method further improves measurement accuracy through measurement result fitting technology, optimizing the original 10ps peak-to-peak measurement accuracy to 6ps peak-to-peak measurement accuracy.

Description

Technical Field

[0001] This invention relates to the fields of time unification technology and signal communication, specifically to a high-precision second pulse and 10MHz signal measurement circuit and method. Background Technology

[0002] Equipment in the field of time synchronization requires ultra-high precision measurement methods to achieve ultra-high precision synchronization. Traditional high-precision time measurement (TDC) chips can achieve a maximum measurement accuracy of 37ps. The MS1022 is a high-precision time measurement (TDC) circuit that integrates analog comparators, analog switches, Schmitt triggers, and other components, simplifying the external circuitry. The MS1022 chip offers 75ps in dual-channel single-precision mode and 37ps in single-channel dual-precision mode, with a measurement range of 3.5ns (0ns) to 2.5μs, a minimum pulse interval of 20ns, and can receive up to 4 pulses. It also features an internal first-wave detection function, improving anti-interference capabilities. The internal comparator's offset is programmable within a range of ±35mV, enhancing sampling accuracy. Traditional time synchronization equipment relies on the performance of time difference measurement chips, achieving a maximum accuracy of only 37ps, which is insufficient for measurements below the 6ps level, hindering the monitoring and attainability of ultra-high precision synchronization (6ps level). Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide an ultra-high precision second pulse and 10MHz signal measurement circuit and method to complete ultra-high precision measurement when the device and the peer device are synchronized at the 6ps level and above.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] First aspect:

[0006] A high-precision second pulse and 10MHz signal measurement circuit includes:

[0007] Both the first and second TDC chips are 10ps-level four-channel time-to-digital converter chips.

[0008] The high-stability reference clock module includes a 10MHz high-stability reference clock generation circuit, and the 10MHz high-stability reference clock signal is connected to the first TDC chip and the second TDC chip through a daisy chain arrangement.

[0009] The measurement signal input module includes first to eighth reference 1PPS input signals arranged in a daisy chain. The first to fourth reference 1PPS input signals are respectively input to the STOP1-4 ports of the first TDC chip, and the fifth to eighth reference 1PPS input signals are respectively input to the STOP1-4 ports of the second TDC chip.

[0010] The power supply ultra-clean module includes a DC-DC circuit, a primary purification circuit, and a secondary purification and filtering circuit connected in sequence, and its output terminal is connected to the power input terminal of the first TDC chip and the second TDC chip.

[0011] The first TDC chip, the second TDC chip, the DC-DC circuit, the primary purification circuit, and the secondary purification and filtering circuit all use potting devices.

[0012] Furthermore, the primary purification circuit includes a wide-voltage buck converter chip (model TPP363080) and a low-dropout linear regulator chip (model TPL930ADJ-QF6R), used to purify the 15V DC input voltage and convert it into a 5V DC voltage.

[0013] Furthermore, the secondary purification and filtering circuit includes multiple TDC digital power modules for voltage purification and conversion of digital power, including a low dropout linear regulator of model TPL740ADJ-5TR.

[0014] Furthermore, the secondary purification and filtering circuit includes multiple TDC analog power supply modules for voltage purification and conversion of the analog power supply, including a low-noise linear regulator with model number TPL903233-S5TR.

[0015] Furthermore, the 10MHz high-stability reference clock generation circuit includes a low-noise power amplifier.

[0016] Furthermore, the high-stability reference clock input module also includes an inverter circuit and a D flip-flop circuit connected in sequence, used to shape the generated 10MHz high-stability reference clock signal.

[0017] The second aspect:

[0018] A method for measuring 1PPS / 10MHz with ultra-high precision, using an averaging algorithm based on the measurement results from an ultra-high precision second pulse and 10MHz signal measurement circuit as described in the first aspect, is as follows:

[0019] The measurement values ​​of the same signal, T1~T8, are obtained through the measurement results of 8 STOP1-8 channels;

[0020] Calculate the mean value Tavg from T1 to T8; obtain the high accuracy of a single measurement.

[0021] By statistically analyzing Tavg1 to Tavg1000 over 1000 seconds, a normal distribution is used for statistical analysis; the center value of the normal distribution TavgX is taken as the benchmark to correct the errors of each measurement channel and the measurement device itself, and the average correction error Tfix is ​​obtained.

[0022] The mean value of a single 8-channel measurement is obtained as Tavg-Tfix=Tfinal.

[0023] Furthermore, the formula for calculating the average correction error Tfix is: Tfix = Average(TavgN - TavgX), where N is 1 to 1000.

[0024] The beneficial effects of this invention are:

[0025] 1) The reference clock and measurement signals are arranged in a daisy chain and enter the multi-channel drive. The driving devices are potted and temperature controlled to avoid introducing more device difference jitter and improve the final measurement accuracy.

[0026] 2) The high-stability reference clock is obtained by using the nonlinear gain of the low-noise power amplifier (LNA) to obtain an ultra-low phase noise and high stability reference clock, which provides a low phase noise and high stability reference clock for the subsequent measurement chip, thereby realizing high-precision measurement.

[0027] 3) By fitting the average and correcting the error, the measurement result Tfinal is obtained, which can further optimize the original measurement chip's peak-to-peak measurement accuracy from 10ps to 6ps. Attached Figure Description

[0028] Figure 1 This is a block diagram of the ultra-high precision measurement circuit of the present invention;

[0029] Figure 2 This is a schematic diagram of the primary purification circuit of the present invention;

[0030] Figure 3 This is a schematic diagram of the digital power module circuit of the present invention;

[0031] Figure 4 This is a schematic diagram of the analog power supply module circuit of the present invention;

[0032] Figure 5 This is the first part of the circuit schematic diagram of the ultra-low phase noise and high stability 10MHz circuit of the present invention;

[0033] Figure 6 This is the second part of the circuit schematic diagram for the ultra-low phase noise and high stability 10MHz circuit of the present invention;

[0034] Figure 7 The schematic diagrams of the inverter circuit and D flip-flop circuit of this invention are shown below.

[0035] Figure 8 This is a daisy-chain connection circuit diagram for the measurement signal of the present invention;

[0036] Figure 9 This is a circuit diagram of the multi-channel real-time measurement circuit of the TDC measurement chip of the present invention. Detailed Implementation

[0037] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] See Figures 1-9 The present invention provides a technical solution:

[0039] To enable ultra-high precision measurement of devices in the time unification field when achieving synchronization with peer devices at the 6ps level or higher, the ultra-high precision measurement scheme adopted in this invention is based on power supply ultra-cleaning technology and high-stability reference clock technology. It adopts a daisy chain arrangement of measurement signals and temperature drift control by potting devices, and reduces the measurement error between channels and between devices by fitting multi-channel measurement results, thereby achieving ultra-high precision measurement.

[0040] Example 1:

[0041] A high-precision second pulse and 10MHz signal measurement circuit, the principle block diagram of which is shown below. Figure 1 As shown, it includes:

[0042] Both the first and second TDC chips are 10ps-level four-channel time-to-digital converter chips. The main features of the TDC chip are that it includes four 20ns pulse interval STOP channels, two 10ns pulse interval combination channels, a maximum SPI data transmission rate of 1.5MSPS, and an independent channel measurement single pulse accuracy of 20ps rms, a measurement accuracy of 10ps rms in high resolution mode, and an automatic calibration reference clock function.

[0043] The high-stability reference clock module includes a 10MHz high-stability reference clock generation circuit, and the 10MHz high-stability reference clock signal is connected to the first TDC chip and the second TDC chip through a daisy chain arrangement.

[0044] The measurement signal input module includes first to eighth reference 1PPS input signals arranged in a daisy chain. The first to fourth reference 1PPS (second pulse) input signals are respectively input to the STOP1-4 ports of the first TDC chip, and the fifth to eighth reference 1PPS (second pulse) input signals are respectively input to the STOP1-4 ports of the second TDC chip; for example... Figure 8 As shown, taking the first and second reference 1PPS (pulse per second) input signals as an example, the daisy-chain arrangement is a serial connection. The reference clock signal and the measurement signal are arranged in a daisy chain to enter the multi-channel drive, and the driving device is potted and temperature controlled. This is because a non-daisy-chain arrangement would introduce more device difference jitter, reducing the final measurement accuracy.

[0045] The power supply ultra-clean module includes a DC-DC circuit, a primary purification circuit, and a secondary purification and filtering circuit connected in sequence, and its output terminal is connected to the power input terminal of the first TDC chip and the second TDC chip.

[0046] The first TDC chip, the second TDC chip, the DC-DC circuit, the primary purification circuit, and the secondary purification and filtering circuit all use potting devices.

[0047] In this embodiment, the primary purification circuit includes a TPP363080 wide-voltage buck converter chip and a TPL930ADJ-QF6R low-dropout linear regulator chip, used to purify the 15V DC input voltage and convert it into a 5V DC voltage. The circuit diagram of the primary purification circuit is shown below. Figure 2 As shown, the input voltage VIN is 15V. The calculated output voltages are VOUT1 = (1 + R36 / R37) * 0.6 = (1 + 88.7 / 11) * 0.6 = 5.40V and VOUT2 = 0.8 * (1 + R48 / R50) = 0.8 * (1 + 24.9kk / 4.7kk) = 5.0V.

[0048] In this embodiment, the secondary purification and filtering circuit includes four TDC digital power modules for voltage purification and conversion of digital power. These modules include a low-dropout linear regulator (model TPL740ADJ-5TR), resistors, and capacitors. The resistor and capacitor values ​​in each TDC digital power module differ to allow for different voltage conversions as needed. For example, the circuit diagram of the TDC digital power module is shown below. Figure 3As shown, resistor R71 has a resistance of 47KΩ and resistor R73 has a resistance of 15KΩ. When the input voltage VIN is 5V, the calculated output voltage Vout = 0.8 * (1 + R71 / R73) = 0.8 * (1 + 47kΩ / 15kΩ) = 3.3V. By changing the resistance values ​​of resistors R71 and R73 at the corresponding positions, different voltage outputs can be achieved.

[0049] In this embodiment, the secondary purification and filtering circuit includes three TDC analog power supply modules for voltage purification and conversion of the analog power supply, including a low-noise linear regulator of model TPL903233-S5TR. The circuit schematic of the TDC analog power supply module is shown below. Figure 4 As shown.

[0050] In this embodiment, the 10MHz high-stability reference clock generation circuit includes a low-noise power amplifier, and the circuit schematic is shown below. Figure 5 and Figure 6 As shown ( Figure 5 A1 end and Figure 6 Connect to terminal A2. Figure 5 B1 end and Figure 6 (Connected to terminal B2), the low-noise power amplifier selected is the ZDH6018 RF gain amplifier. For example... Figure 5 , Figure 6 The 10MHz high-stability reference clock generation circuit utilizes the nonlinear gain of a low-noise power amplifier (LNA) to obtain an ultra-low phase noise and high stability reference clock. Test results at different locations of the circuit show that the phase noise in the circuit is attenuated by 7dB and eventually tends to stabilize. Therefore, the reference clock generated by the circuit has the characteristics of low phase noise and high stability.

[0051] In this embodiment, the high-stability reference clock input module further includes an inverter circuit and a D flip-flop circuit connected in sequence, used to shape the generated 10MHz high-stability reference clock signal. The schematic diagrams of the inverter circuit and the D flip-flop circuit are shown below. Figure 7 As shown, the inverter chip is model NC7SZU04P5X, and the D flip-flop chip is model 74LVC1G80GW. It outputs two high-stability clock signals, which are transmitted to the REFCLK ports of the first TDC chip and the second TDC chip, respectively. The D flip-flop is triggered by the rising edge of the signal, which can transmit the 10MHz high-stability reference clock signal more accurately.

[0052] The multi-channel real-time measurement circuit diagram of the TDC measurement chip of this invention is shown below. Figure 9 As shown, by selecting a 10ps (RMS) level measurement chip, using power supply ultra-clean technology, high-stability reference clock technology, measurement and reference clock daisy chain arrangement method, and device potting temperature control method, a 10ps peak-to-peak measurement accuracy can be obtained, which improves the original device technical specifications.

[0053] Example 2:

[0054] A high-precision 1PPS / 10MHz measurement method, using an averaging algorithm based on the measurement results from a high-precision second pulse and 10MHz signal measurement circuit as described in Example 1, is as follows:

[0055] The measurement values ​​of the same signal, T1~T8, are obtained through the measurement results of 8 STOP1-8 channels;

[0056] Calculate the mean value Tavg from T1 to T8; obtain the high accuracy of a single measurement.

[0057] By statistically analyzing Tavg1 to Tavg1000 over 1000 seconds, a normal distribution is used for statistical analysis; the center value of the normal distribution TavgX is taken as the benchmark to correct the errors of each measurement channel and the measurement device itself, and the average correction error Tfix is ​​obtained.

[0058] The mean value of a single 8-channel measurement is obtained as Tavg-Tfix=Tfinal.

[0059] Furthermore, the formula for calculating the average correction error Tfix is: Tfix = Average(TavgN - TavgX), where N is 1 to 1000.

[0060] The measurement result Tfinal is obtained by means of fitting average and error correction, which can further optimize the measurement accuracy of the original measurement chip from 10ps (peak-to-peak) to 6ps (peak-to-peak).

[0061] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A high-precision second pulse and 10MHz signal measurement circuit, characterized in that, include: Both the first and second TDC chips are 10ps-level four-channel time-to-digital converter chips. The high-stability reference clock module includes a 10MHz high-stability reference clock generation circuit, and the 10MHz high-stability reference clock signal is connected to the first TDC chip and the second TDC chip through a daisy chain arrangement. The measurement signal input module includes first to eighth reference 1PPS input signals arranged in a daisy chain. The first to fourth reference 1PPS input signals are respectively input to the STOP1-4 ports of the first TDC chip, and the fifth to eighth reference 1PPS input signals are respectively input to the STOP1-4 ports of the second TDC chip. The power supply ultra-clean module includes a DC-DC circuit, a primary purification circuit, and a secondary purification and filtering circuit connected in sequence, and its output terminal is connected to the power input terminal of the first TDC chip and the second TDC chip. The first TDC chip, the second TDC chip, the DC-DC circuit, the primary purification circuit, and the secondary purification and filtering circuit all use potting devices.

2. The ultra-high precision second pulse and 10MHz signal measurement circuit according to claim 1, characterized in that: The primary purification circuit includes a wide-voltage buck converter chip (model TPP363080) and a low-dropout linear regulator chip (model TPL930ADJ-QF6R), used to purify the 15V DC input voltage and convert it into a 5V DC voltage.

3. The ultra-high precision second pulse and 10MHz signal measurement circuit according to claim 2, characterized in that: The secondary purification and filtering circuit includes multiple TDC digital power modules for voltage purification and conversion of digital power, including a low dropout linear regulator of model TPL740ADJ-5TR.

4. The ultra-high precision second pulse and 10MHz signal measurement circuit according to claim 2, characterized in that: The secondary purification and filtering circuit includes multiple TDC analog power supply modules for voltage purification and conversion of analog power supplies, including a low-noise linear regulator of model TPL903233-S5TR.

5. The ultra-high precision second pulse and 10MHz signal measurement circuit according to claim 1, characterized in that: The 10MHz high-stability reference clock generation circuit includes a low-noise power amplifier.

6. The ultra-high precision second pulse and 10MHz signal measurement circuit according to claim 1, characterized in that: The high-stability reference clock module also includes an inverter circuit and a D flip-flop circuit connected in sequence, used to shape the generated 10MHz high-stability reference clock signal.

7. A method for measuring ultra-high precision second pulses and 10MHz signals, characterized in that: The fitting and averaging algorithm for the measurement results of the ultra-high precision second pulse and 10MHz signal measurement circuit as described in any one of claims 1-6 is as follows: The measurement values ​​of the same signal, T1~T8, are obtained through the measurement results of 8 STOP1-8 channels; Calculate the mean value Tavg from T1 to T8; obtain the high accuracy of a single measurement. By statistically analyzing Tavg1 to Tavg1000 over a period of 1000 seconds, a normal distribution was used for the statistical analysis. Taking the center value of the normal distribution TavgX as the benchmark, the average correction error Tfix is ​​obtained. The errors of each measurement channel and the measurement device itself are corrected according to the average correction error Tfix, and the average value of a single 8-channel measurement Tfinal = Tavg - Tfix is ​​obtained.

8. The method for measuring ultra-high precision second pulses and 10MHz signals according to claim 7, characterized in that: The formula for calculating the average correction error Tfix is: Tfix = Average(TavgN - TavgX), where N is 1 to 1000.

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