Data reading circuit and method for an otp memory cell

Abstract

The application provides a data reading circuit and method of an OTP storage unit, which comprises a sampling module, a signal processing module and an output module. The storage data of the OTP storage unit is sampled by the sampling module to obtain a sampling signal. A first transition signal is generated by the signal processing module based on a first enable signal and the sampling signal. A second transition signal is generated based on a second enable signal and the first transition signal. The second transition signal is inverted and buffered by the output module based on the falling edge of a pulse signal to obtain and output the storage data. The data reading circuit of the OTP storage unit provided by the application has simple structure and high reliability, and can improve the practicability of the novel OTP storage unit in actual application.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a data reading circuit and method for an OTP memory cell. Background Technology

[0002] Common analog and mixed-signal chips, such as temperature sensors, power management devices, and analog-to-digital converters, typically require calibration and adjustment to compensate for deviations caused by process and environmental variables, thereby ensuring chip performance. This necessitates memory to store calibration or adjustment data. The memory needs to be characterized by fast read speeds, high reliability, and compact storage arrays. Antifuse OTP memory is widely used in various integrated circuit chips due to these characteristics.

[0003] With the introduction of novel OTP memory cell structures, smaller and more compact memory arrays can be achieved, enabling the widespread application of high-capacity OTP memories in various precision circuits to store chip adjustment information and ensure system accuracy. However, current data reading circuits for these novel OTP memory cells have slow reading speeds, hindering the rapid display of data from the new OTP memory array and limiting their practical application.

[0004] Therefore, how to design a new type of data reading circuit for OTP memory cells is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the present invention provides a data reading circuit and method for an OTP storage unit to solve the above-mentioned technical problems.

[0006] To achieve the above and other related objectives, the technical solution provided in this application is as follows.

[0007] On one hand, this application provides a data reading circuit for an OTP storage unit, comprising:

[0008] The sampling module is connected to the OTP storage unit and samples the stored data in the OTP storage unit to obtain a sampling signal;

[0009] The signal processing module receives a first enable signal, a second enable signal, and the sampling signal. It generates a first transition signal based on the first enable signal and the sampling signal, and then generates a second transition signal based on the second enable signal and the first transition signal.

[0010] The output module is connected to the second transition signal and the pulse signal. When the falling edge of the pulse signal arrives, the second transition signal is inverted and buffered to obtain and output the stored data.

[0011] Optionally, the OTP memory cell includes an antifuse memory transistor and a first NMOS transistor. The gate of the antifuse memory transistor is connected to a word line. One end of the antifuse memory transistor is left floating, and the other end of the antifuse memory transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to a first power supply voltage, and the source of the first NMOS transistor is connected to a bit line.

[0012] Optionally, the sampling module includes a second NMOS transistor and a third NMOS transistor. The gate of the second NMOS transistor is connected to a first bias voltage, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to a second bias voltage. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the second NMOS transistor outputs the sampling signal.

[0013] Optionally, the signal processing module includes a first signal processing unit and a second signal processing unit. The first signal processing unit is connected to the first enable signal and the sampling signal, and generates a first transition signal based on the first enable signal and the sampling signal. The second signal processing unit is connected to the first transition signal and the second enable signal, and generates a second transition signal based on the second enable signal and the first transition signal.

[0014] Optionally, the first signal processing unit includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first inverter. The source of the first PMOS transistor is connected to a second power supply voltage, and the gate of the first PMOS transistor is connected to the first enable signal. The source of the second PMOS transistor is connected to the source of the first PMOS transistor, the drain of the first PMOS transistor is connected to the input terminal of the first inverter, the source of the second PMOS transistor is connected to the source of the first PMOS transistor, the gate of the second PMOS transistor is connected to the output terminal of the first inverter, and the drain of the second PMOS transistor is connected to the input terminal of the first inverter. The drain of the second PMOS transistor is also connected to the drain of the fifth NMOS transistor, the drain of the fifth NMOS transistor is also connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor is grounded, the source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the source of the seventh NMOS transistor is grounded. The gates of the first PMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor are connected to the first enable signal, the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to the sampling signal, and the output terminal of the first inverter outputs a first transition signal.

[0015] Optionally, the second signal processing unit includes a third PMOS transistor, an eighth NMOS transistor, and a fourth PMOS transistor. The source of the third PMOS transistor is connected to the second power supply voltage, the drain of the third PMOS transistor is connected to the drain of the eighth NMOS transistor, the source of the eighth NMOS transistor is grounded, the source of the fourth PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to the second enable signal, the gate of the eighth NMOS transistor is connected to the first transition signal, the gate of the fourth PMOS transistor is connected to the second inverted signal, and the second transition signal is output from the drain of the third PMOS transistor.

[0016] Optionally, the output module includes a trigger and a buffer. The data input terminal of the trigger is connected to the second transition signal, the clock input terminal of the trigger is connected to the pulse signal, the first output terminal of the trigger is connected to the input terminal of the buffer, the first output terminal of the trigger outputs the first inverted signal, the second output terminal of the trigger outputs the second inverted signal, and the output terminal of the buffer outputs the stored data.

[0017] Optionally, the trigger includes a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, and a ninth inverter. The output terminal of the second inverter is connected to the control terminal of the third inverter, and the output terminal of the second inverter is also connected to the control terminal of the seventh inverter. The output terminal of the third inverter is connected to the input terminal of the fifth inverter, and the output terminal of the third inverter is also connected to the output terminal of the fourth inverter. The output terminal of the fifth inverter is connected to the output terminal of the sixth inverter, and the output terminal of the fifth inverter is also connected to the input terminal of the fourth inverter. The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter, the output terminal of the eighth inverter is connected to the input terminal of the ninth inverter, and the output terminal of the eighth inverter is also connected to the input terminal of the seventh inverter. The input terminal of the second inverter, the control terminal of the fourth inverter, and the control terminal of the sixth inverter are the clock input terminals of the flip-flop. The input terminal of the third inverter is the data input terminal of the flip-flop. The output terminal of the ninth inverter is the first output terminal of the flip-flop, and the output terminal of the third inverter is the second output terminal of the flip-flop.

[0018] On the other hand, this application provides a data reading method for an OTP memory cell, applied to the data reading circuit of the OTP memory cell as described above, including:

[0019] The stored data in the OTP storage unit is sampled to obtain the sampled signal;

[0020] The first enable signal and the sampled signal are logically transformed to obtain the first transition signal; the second enable signal and the first transition signal are logically transformed to obtain the second transition signal.

[0021] The second transition signal is inverted and buffered based on the pulse signal to obtain the stored data.

[0022] Optionally, performing logical conversion on the first enable signal and the sampling signal to obtain the first transition signal, and performing logical conversion on the second enable signal and the first transition signal to obtain the second transition signal, includes: when the first enable signal is high and the sampling signal is high, the first transition signal is high, the second enable signal is high, and the second transition signal is low; when the first enable signal is high and the sampling signal is low, the first transition signal is low, the second enable signal is high, and the second transition signal is high.

[0023] This application provides a data reading circuit and method for an OTP memory cell. The circuit includes a sampling module, a signal processing module, and an output module. The sampling module samples the stored data of the OTP memory cell to obtain a sampling signal. The signal processing module generates a first transition signal based on a first enable signal and the sampling signal, and then generates a second transition signal based on a second enable signal and the first transition signal. The output module inverts and buffers the second transition signal based on the falling edge of a pulse signal to obtain and output the stored data. The data reading circuit for the OTP memory cell provided by this application has a simple structure and high reliability, which can improve the practicality of the new OTP memory in practical applications. Attached Figure Description

[0024] Figure 1 This is a circuit diagram of a 2×2 novel OTP memory array in an exemplary embodiment of this application;

[0025] Figure 2 This is a block diagram of the data reading circuit of the OTP storage unit in an exemplary embodiment of this application;

[0026] Figure 3 This is a detailed circuit diagram of the data reading circuit of the OTP storage unit in an exemplary embodiment of this application;

[0027] Figure 4 This is a specific circuit diagram of the trigger in an exemplary embodiment of this application;

[0028] Figure 5(a) shows the simulation results of the first transition signal net2 of the OTP memory cell data reading circuit reading "1" in an exemplary embodiment of this application;

[0029] Figure 5(b) shows the simulation results of the second transition signal net3 for reading "1" in the data read circuit of the OTP memory cell provided in an exemplary embodiment of this application;

[0030] Figure 5(c) shows the simulation results of the data reading circuit of the OTP memory cell provided in an exemplary embodiment of this application reading the stored data Q of "1";

[0031] Figure 6(a) shows the simulation results of the data reading circuit of the OTP memory cell provided in an exemplary embodiment of this application reading the first transition signal net2 of "0";

[0032] Figure 6(b) shows the simulation results of the second transition signal net3 for reading "0" in the data read circuit of the OTP memory cell provided in an exemplary embodiment of this application;

[0033] Figure 6(c) shows the simulation results of the data reading circuit of the OTP memory cell provided in an exemplary embodiment of this application reading the stored data Q of “0”;

[0034] Figure label:

[0035] 1-OTP storage unit, 2-sampling module, 3-signal processing module, 4-output module. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0037] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0039] Common analog and mixed-signal chips, such as temperature sensors, power management devices, and analog-to-digital converters, typically require calibration and adjustment to compensate for deviations caused by process and environmental variables, thereby ensuring chip performance. This necessitates memory to store calibration or adjustment data. The memory needs to be characterized by fast read speeds, high reliability, and compact storage arrays. Antifuse OTP memory is widely used in various integrated circuit chips due to these characteristics.

[0040] Please see Figure 1 , Figure 1 This is a circuit diagram of a 2×2 novel OTP memory array in an exemplary embodiment of this application.

[0041] like Figure 1 As shown, the 2×2 novel OTP memory array includes four memory cells: Cell0, Cell1, Cell2, and Cell3. The specific operation of programming the 2×2 novel OTP memory array is shown in the table below:

[0042] Table 1 Programming Relationships of the Novel 2×2 OTP Memory Array

[0043] storage unit VWL VBL Programming Cell 0 VPP 0V yes Cell 1 VPP VDD no Cell 2 0V 0V no Cell 3 0V VDD no

[0044] In Table 1 above, Cell 0-Cell 3 are the four cells of the 2×2 novel OTP memory array, VWL is the word line, and VBL is the bit line.

[0045] Please refer to Figure 1According to Table 1, applying a programming voltage VPP to the word line WL0 of the row containing the programming cell Cell 0 and applying 0V to the bit line BL0 will cause the antifuse transistor in Cell 0 to break down due to the programming voltage, resulting in a low-resistance state. Applying a power supply voltage VDD to the bit line BL1 of Cell 1 ensures that the selector of the non-programmable cell Cell 1 remains off, preventing Cell 1 from being programmed. Applying 0V to the word line WL1 of Cell 2 ensures that Cell 2 is not programmed. Simultaneously, reducing the gate voltage of the selector from VPP to VDD lowers the operating voltage of the selector in Cell 3 to VDD, reducing the likelihood of source and drain breakdown and shortening the channel length of the selector in Cell 3. Applying 0V to the word line WL1 of Cell 2 ensures that Cell 2 is not programmed.

[0046] With the introduction of novel OTP memory cell structures, smaller and more compact memory arrays can be achieved, enabling the widespread application of high-capacity OTP memories in various precision circuits to store chip adjustment information and ensure system accuracy. However, current data reading circuits for these novel OTP memory cells have slow reading speeds, hindering the rapid display of data from the new OTP memory array and limiting its practical application.

[0047] To solve the above problems, the sampling module samples the stored data of the OTP storage unit to obtain a sampling signal. The signal processing unit generates a first transition signal based on the first enable signal and the sampling signal, and then generates a second transition signal based on the second enable signal and the first transition signal. The output module inverts and buffers the second transition signal based on the falling edge of the pulse signal to obtain and output the stored data.

[0048] Please see Figure 2 , Figure 2 This is a block diagram of the data reading circuit of the OTP storage unit in an exemplary embodiment of this application.

[0049] like Figure 2 As shown, this application provides a data reading circuit for an OTP memory cell, comprising:

[0050] Sampling module 2 is connected to OTP storage unit 1 and samples the stored data in OTP storage unit 1 to obtain sampling signal net1;

[0051] Signal processing module 3 is connected to a first enable signal ENP1, a second enable signal ENP2 and a sampling signal net1. It generates a first transition signal net2 based on the first enable signal ENP1 and the sampling signal net1, and then generates a second transition signal net3 based on the second enable signal ENP2 and the first transition signal.

[0052] Output module 4 is connected to the second transition signal net3 and the pulse signal CPN. When the falling edge of the pulse signal CPN arrives, the second transition signal net3 is inverted and buffered to obtain and output the stored data Q.

[0053] Please see Figure 3 , Figure 3 This is a detailed circuit diagram of the data reading circuit of the OTP storage unit in an exemplary embodiment of this application.

[0054] In detail, such as Figure 3 As shown, the OTP memory cell 1 includes an antifuse memory transistor F and a first NMOS transistor N1. The gate of the antifuse memory transistor F is connected to the word line WL. One end of the antifuse memory transistor F is left floating, and the other end of the antifuse memory transistor F is connected to the drain of the first NMOS transistor N1. The gate of the first NMOS transistor N1 is connected to the first power supply voltage VDD, and the source of the first NMOS transistor N1 is connected to the bit line BL.

[0055] In detail, such as Figure 3 As shown, the sampling module 2 includes a second NMOS transistor N2 and a third NMOS transistor N3. The gate of the second NMOS transistor N2 is connected to a first bias voltage Vb1, the source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3, the source of the third NMOS transistor N3 is grounded, and the gate of the third NMOS transistor N3 is connected to a second bias voltage Vb2. The drain of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1, and the source of the second NMOS transistor N2 outputs a sampling signal net1.

[0056] In detail, such as Figure 3 As shown, the signal processing module includes a first signal processing unit and a second signal processing unit. The first signal processing unit is connected to a first enable signal ENP1 and a sampling signal net1, and generates a first transition signal net2 based on the first enable signal ENP1 and the sampling signal net1. The second signal processing unit is connected to the first transition signal net2 and a second enable signal ENP2, and generates a second transition signal net3 based on the second enable signal ENP2 and the first transition signal net2.

[0057] More in detail, such as Figure 3As shown, the first signal processing unit includes a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, a first PMOS transistor P1, a second PMOS transistor P2, and a first inverter INV1. The source of the first PMOS transistor P1 is connected to the second power supply voltage VPP. The source of the second PMOS transistor P2 is connected to the source of the first PMOS transistor P1. The drain of the first PMOS transistor P1 is connected to the input terminal of the first inverter INV1. The gate of the second PMOS transistor P2 is connected to the output terminal of the first inverter INV1. The drain of the second PMOS transistor P2 is connected to the input terminal of the first inverter INV1. The drain of the second PMOS transistor P2 is also connected to the fifth NMOS transistor N4. The drain of the S-channel transistor N5 is connected to the drain of the fourth NMOS transistor N4. The source of the fourth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the source of the sixth NMOS transistor N6 is grounded. The source of the fifth NMOS transistor N5 is connected to the drain of the seventh NMOS transistor N7, and the source of the seventh NMOS transistor N7 is grounded. The gates of the first PMOS transistor P1, the sixth NMOS transistor N5, and the seventh NMOS transistor N7 are connected to the first enable signal ENP1. The gates of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are connected to the sampling signal net1. The output of the first inverter INV1 outputs the first transition signal net2.

[0058] More in detail, such as Figure 3 As shown, the second signal processing unit includes a third PMOS transistor P3, an eighth NMOS transistor N8, and a fourth PMOS transistor. The source of the third PMOS transistor P3 is connected to the second power supply voltage VPP, the drain of the third PMOS transistor P3 is connected to the drain of the eighth NMOS transistor N8, the source of the eighth NMOS transistor N8 is grounded, the source of the fourth PMOS transistor P4 is connected to the source of the third PMOS transistor P3, and the drain of the fourth PMOS transistor P4 is connected to the drain of the third PMOS transistor P3. The gate of the third PMOS transistor P3 is connected to the second enable signal ENP2, the gate of the eighth NMOS transistor N8 is connected to the first transition signal net2, the gate of the fourth PMOS transistor is connected to the second inverted signal, and the drain of the third PMOS transistor P3 outputs the second transition signal net3.

[0059] In detail, such as Figure 3 As shown, the output module includes a flip-flop D1 and a buffer BUF. The data input terminal of the flip-flop D1 is connected to the second transition signal net3, the clock input terminal of the flip-flop D1 is connected to the pulse signal CPN, the first output terminal of the flip-flop D1 is connected to the input terminal of the buffer BUF, the first output terminal of the flip-flop D1 outputs the first inverted signal, the second output terminal of the flip-flop D1 outputs the second inverted signal, and the output terminal of the buffer BUF outputs the stored data Q.

[0060] Please see Figure 4 , Figure 4 This is a specific circuit diagram of the trigger in an exemplary embodiment of this application.

[0061] More in detail, such as Figure 4 As shown, the trigger includes a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, and a ninth inverter INV9. The output of the second inverter INV2 is connected to the control terminal of the third inverter INV3, and the output of the second inverter INV2 is also connected to the control terminal of the seventh inverter INV7. The output of the third inverter INV3 is connected to the input terminal of the fifth inverter INV5, and the output of the third inverter INV3 is also connected to the output terminal of the fourth inverter INV4. The output of the fifth inverter INV5 is connected to the output terminal of the sixth inverter INV6, and the output of the fifth inverter INV5 is also connected to the input terminal of the fourth inverter INV9. The input terminal of INV4, the output terminal of the sixth inverter INV6 is connected to the input terminal of the eighth inverter INV8, the output terminal of the sixth inverter INV6 is also connected to the output terminal of the seventh inverter INV7, the output terminal of the eighth inverter INV8 is connected to the input terminal of the ninth inverter INV9, and the output terminal of the eighth inverter INV8 is also connected to the input terminal of the seventh inverter INV7. Among them, the input terminal of the second inverter INV2, the control terminal of the fourth inverter INV4, and the control terminal of the sixth inverter INV6 are the clock input terminals of the flip-flop D1, the input terminal of the third inverter INV3 is the data input terminal of the flip-flop, the output terminal of the ninth inverter INV9 is the first output terminal of the flip-flop, and the output terminal of the third inverter INV3 is the second output terminal of the flip-flop.

[0062] like Figure 2-6(c) As shown, the specific principle of the data reading circuit of the OTP storage unit provided in this application is as follows:

[0063] When a voltage of VDD is applied to one of the word lines WL, the second NMOS transistor N2 is turned on, and the cell being read is defined in the OTP memory array. When the antifuse transistor F in the memory cell is broken down by the programming voltage, it exhibits a low-resistance state. The gate voltage VDD of the antifuse transistor F is 1.6V, and the on-resistance of the antifuse transistor F is set to 1KΩ. The gate voltage of the first NMOS transistor N1 is 1.6V, and the on-resistance of the first NMOS transistor N1 is 140KΩ. The gate voltage of the second NMOS transistor N2 is 1.6V, and the on-resistance of the second NMOS transistor N2 is 21.25KΩ. The gate voltage of the third NMOS transistor N3 is 0.5V, and the on-resistance of the third NMOS transistor N3 is 237KΩ. The first NMOS transistor N1 and the second NMOS transistor N2 are turned on, the third NMOS transistor N3 is turned on, the first transition signal is high level (0.9V), the fourth NMOS transistor N4 is turned on, and the fifth NMOS transistor N5 is turned on. The second power supply voltage VSS is 0.975V. Based on the simulation results in Figures 5(a), 5(b), and 5(c), the initial value of the first enable signal ENP1 is low, the first PMOS transistor P1 is turned on, the first transition signal net2 is low, and the second PMOS transistor P2 is turned on. When the first enable signal ENP1 is high, the first PMOS transistor P1 is turned off, and the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are turned on, making the first transition signal net2 high and the eighth NMOS transistor N8 turned on. When the second enable signal ENP2 is high, the third PMOS transistor P3 is turned off, and the second transition signal net3 is low. The flip-flop D1 is a falling edge flip-flop. When the falling edge of the pulse signal CPN arrives, both the first output port and the second output port of the flip-flop D1 output the inverted signal of the input data port. Therefore, when the falling edge of the pulse signal CPN arrives, the second transition signal net3 is at a low level, the fourth PMOS transistor P4 is turned off, and the high level output of the flip-flop D1 passes through the buffer BUF to store the 1-bit high level data "1" and output it.

[0064] When the antifuse transistor F in the memory cell is not broken down by the programming voltage, it exhibits a high-resistance state; the gate voltage of the antifuse transistor F is 1.6V, and the on-resistance of the antifuse transistor F is set to 800MΩ. The gate voltage of the first NMOS transistor N1 is 1.6V, and the on-resistance of the first NMOS transistor N1 is 2.7KΩ. The gate voltage of the second NMOS transistor N2 is 1.6V, and the on-resistance of the second NMOS transistor N2 is 1KΩ. The gate voltage of the third NMOS transistor N3 is 0.5V, and the on-resistance of the third NMOS transistor N3 is 15KΩ. The first NMOS transistor N1 and the second NMOS transistor N2 are turned on, the third NMOS transistor N3 is turned on, the first transition signal is low level (0V), the fourth NMOS transistor N4 is turned off, and the fifth NMOS transistor N2 is turned off. The second power supply voltage VSS is 0.975V. Based on the simulation results in Figures 6(a), 6(b), and 6(c), the initial value of the first enable signal ENP1 is low, the first PMOS transistor P1 is turned on, the first transition signal net2 is low, and the second PMOS transistor P2 is turned on. When the first enable signal ENP1 is high, the first PMOS transistor P1 is turned off, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are turned on, and the second PMOS transistor P2 is turned on. The first transition signal net2 is maintained at a low level through the second PMOS transistor P2, and the eighth NMOS transistor N8 is turned off. The initial value of the second enable signal ENP2 is low, the third PMOS transistor P3 is turned on, and the second transition signal net3 is high. Before the falling edge of the pulse signal CPN of flip-flop D1 arrives, i.e., when the pulse signal CPN is high, the second output port of flip-flop D1 outputs a low level, and the fourth PMOS transistor P4 is turned on. When the second enable signal ENP2 is high, the third PMOS transistor P3 is off, and the second transition signal net3 is maintained at a high level through the fourth PMOS transistor P4. Flip-flop D1 is a falling-edge flip-flop. When the falling edge of the pulse signal CPN arrives, both the first and second output ports of flip-flop D1 output the inverted signal of the input data port. Therefore, when the falling edge of the pulse signal CPN arrives, the second transition signal net3 is high, the fourth PMOS transistor P4 is turned on, and the low-level output of flip-flop D1, after passing through the buffer BUF, stores 1 bit of low-level data "0" and outputs it.

[0065] like Figure 4As shown, when the control input level of the third inverter INV3, fourth inverter INV4, sixth inverter INV6, and seventh inverter INV7 is low, the inverters operate. When the pulse signal CPN is high, the output CPP of the second inverter INV2 is low, and the third inverter INV3 and the seventh inverter INV7 are in the operating state. The second transition signal net3, after passing through the third inverter INV3, outputs the second inverted signal QN1. The fourth inverter INV4 and the sixth inverter INV6 are not operating, and the input of the eighth inverter INV8 is maintained through the seventh inverter INV7. The voltage level ensures that the first inverted signal QN output by the ninth inverter maintains its original level, while the second inverted signal QN1 is input to the fourth PMOS transistor P4. When the falling edge of the pulse signal CPN arrives, the third inverter INV3 and the seventh inverter INV7 are not working, while the fourth inverter INV4 and the sixth inverter INV6 are working. The fourth inverter INV4 maintains the voltage level at the input of the fifth inverter INV5. The second inverted signal QN1 passes through the fifth inverter INV5, the sixth inverter INV6, the eighth inverter INV8, and the ninth inverter INV9 to obtain the first inverted signal QN. In summary, flip-flop D1 is a falling edge flip-flop. When the falling edge of the pulse signal CPN arrives, both the first output port QN and the second output port QN1 of flip-flop D1 output the inverted signal of the input data port.

[0066] This application also provides a data reading method for an OTP memory cell, applied to the data reading circuit of the OTP memory cell as described above, including:

[0067] The stored data in the OTP storage unit is sampled to obtain a sampled signal;

[0068] The first enable signal and the sampled signal are logically converted to obtain the first transition signal. The second enable signal and the first transition signal are logically converted to obtain the second transition signal.

[0069] The second transition signal is inverted and buffered based on the pulse signal to obtain the stored data.

[0070] In detail, the first enable signal and the sampling signal are logically converted to obtain the first transition signal, and the second enable signal and the first transition signal are logically converted to obtain the second transition signal, including: when the first enable signal is high and the sampling signal is high, the first transition signal is high, the second enable signal is high, and the second transition signal is low; when the first enable signal is high and the sampling signal is low, the first transition signal is low, the second enable signal is high, and the second transition signal is high.

[0071] Combination such as Figure 3Figures 5(a), 5(b), 6(a), and 6(b) show that, specifically, when the first enable signal ENP1 is high and the sampling signal net1 is high, the first PMOS transistor P1 is turned on, the fourth NMOS transistor N4 is turned on, the fifth NMOS transistor N5 is turned on, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are turned on, pulling the input of the first inverter INV1 down to ground, determining that the first transition signal net2 is high. The rising edge of the second enable signal ENP2 changes synchronously with the rising edge of the first transition signal net2, and the second enable signal ENP2 is high. The third PMOS transistor P3 is turned off, determining that the second transition signal net3 is low. When the initial value of the first enable signal ENP1 is low and the sampling signal net1 is low, the first PMOS transistor P1 is turned on. When transistor P1 is turned on, the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are turned off. The first transition signal net2 is low, and the second PMOS transistor P2 is turned on. When the first enable signal ENP1 changes from low to high, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are turned on. The first transition signal net2 is maintained at a low level through the second PMOS transistor P2. The initial value of the second enable signal ENP2 is low. When the third PMOS transistor P3 is turned on, the second transition signal net3 is high. The initial value of the pulse signal CPN is high. The second output terminal QN1 of the flip-flop D1 is low. The fourth PMOS transistor P4 is turned on. When the second enable signal ENP2 changes to high, the second transition signal net3 is maintained at a high level through the fourth PMOS transistor P4.

[0072] This application provides a data reading circuit and method for an OTP memory cell. The circuit includes a sampling module, a signal processing module, and an output module. The sampling module samples the stored data of the OTP memory cell to obtain a sampling signal. The signal processing module generates a first transition signal based on a first enable signal and the sampling signal, and then generates a second transition signal based on a second enable signal and the first transition signal. The output module inverts and buffers the second transition signal based on the falling edge of a pulse signal to obtain and output the stored data. The data reading circuit for the OTP memory cell provided by this application has a simple structure and high reliability, which can improve the practicality of the new OTP memory in practical applications.

[0073] This invention can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

Claims

1. A data reading circuit for an OTP storage unit, characterized in that, include: The sampling module is connected to the OTP storage unit and samples the stored data in the OTP storage unit to obtain a sampling signal; The signal processing module receives a first enable signal, a second enable signal, and the sampling signal. It generates a first transition signal based on the first enable signal and the sampling signal, and then generates a second transition signal based on the second enable signal and the first transition signal. The output module is connected to the second transition signal and the pulse signal. When the falling edge of the pulse signal arrives, the second transition signal is inverted and buffered to obtain and output the stored data. The signal processing module includes a first signal processing unit and a second signal processing unit. The first signal processing unit is connected to the first enable signal and the sampling signal, and generates a first transition signal based on the first enable signal and the sampling signal. The second signal processing unit is connected to the first transition signal and the second enable signal, and generates a second transition signal based on the second enable signal and the first transition signal. The first signal processing unit includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a first inverter. The source of the first PMOS transistor is connected to a second power supply voltage, and the gate of the first PMOS transistor is connected to the first enable signal. The source of the second PMOS transistor is connected to the source of the first PMOS transistor. The drain of the first PMOS transistor is connected to the input terminal of the first inverter. The gate of the second PMOS transistor is connected to the output terminal of the first inverter. The drain of the second PMOS transistor is also connected to the input terminal of the first inverter. The drain of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded. The source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the source of the seventh NMOS transistor is grounded. The gates of the first PMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor are connected to the first enable signal. The gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to the sampling signal. The output of the first inverter outputs a first transition signal. The second signal processing unit includes a third PMOS transistor, an eighth NMOS transistor, and a fourth PMOS transistor. The source of the third PMOS transistor is connected to the second power supply voltage, the drain of the third PMOS transistor is connected to the drain of the eighth NMOS transistor, the source of the eighth NMOS transistor is grounded, the source of the fourth PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to the second enable signal, the gate of the eighth NMOS transistor is connected to the first transition signal, the gate of the fourth PMOS transistor is connected to the second inverted signal, and the drain of the third PMOS transistor outputs the second transition signal.

2. The data reading circuit of the OTP storage unit according to claim 1, characterized in that, The OTP memory cell includes an antifuse memory transistor and a first NMOS transistor. The gate of the antifuse memory transistor is connected to a word line. One end of the antifuse memory transistor is left floating, and the other end of the antifuse memory transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to a first power supply voltage, and the source of the first NMOS transistor is connected to a bit line.

3. The data reading circuit of the OTP storage unit according to claim 2, characterized in that, The sampling module includes a second NMOS transistor and a third NMOS transistor. The gate of the second NMOS transistor is connected to a first bias voltage, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to a second bias voltage. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the second NMOS transistor outputs the sampling signal.

4. The data reading circuit of the OTP storage unit according to claim 1, characterized in that, The output module includes a trigger and a buffer. The data input terminal of the trigger is connected to the second transition signal, the clock input terminal of the trigger is connected to the pulse signal, the first output terminal of the trigger is connected to the input terminal of the buffer, the first output terminal of the trigger outputs a first inverted signal, the second output terminal of the trigger outputs the second inverted signal, and the output terminal of the buffer outputs the stored data.

5. The data reading circuit of the OTP storage unit according to claim 4, characterized in that, The trigger includes a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, and a ninth inverter. The output terminal of the second inverter is connected to the control terminal of the third inverter, and the output terminal of the second inverter is also connected to the control terminal of the seventh inverter. The output terminal of the third inverter is connected to the input terminal of the fifth inverter, and the output terminal of the third inverter is also connected to the output terminal of the fourth inverter. The output terminal of the fifth inverter is connected to the output terminal of the sixth inverter, and the output terminal of the fifth inverter is also connected to the input terminal of the fourth inverter. The sixth inverter... The output terminal is connected to the input terminal of the eighth inverter. The output terminal of the sixth inverter is also connected to the output terminal of the seventh inverter. The output terminal of the eighth inverter is connected to the input terminal of the ninth inverter. The output terminal of the eighth inverter is also connected to the input terminal of the seventh inverter. The input terminal of the second inverter, the control terminal of the fourth inverter, and the control terminal of the sixth inverter are the clock input terminals of the flip-flop. The input terminal of the third inverter is the data input terminal of the flip-flop. The output terminal of the ninth inverter is the first output terminal of the flip-flop. The output terminal of the third inverter is the second output terminal of the flip-flop.

6. A data reading method for an OTP storage unit, applied to the data reading circuit of the OTP storage unit as described in claims 1-5, characterized in that, include: The stored data in the OTP storage unit is sampled to obtain the sampled signal; The first enable signal and the sampled signal are logically transformed to obtain the first transition signal; the second enable signal and the first transition signal are logically transformed to obtain the second transition signal. The second transition signal is inverted and buffered based on the pulse signal to obtain the stored data.

7. The data reading method for the OTP storage unit according to claim 6, characterized in that, The first enable signal and the sampled signal are logically transformed to obtain the first transition signal, and the second enable signal and the first transition signal are logically transformed to obtain the second transition signal, including: When the first enable signal is high and the sampling signal is high, the first transition signal is high, the second enable signal is high, and the second transition signal is low; When the first enable signal is high and the sampling signal is low, the first transition signal is low, the second enable signal is high, and the second transition signal is high.

Images