Underwater photon counting wireless optical communication synchronization method based on multi-sync header frame structure

Abstract

The application discloses a kind of underwater photon counting wireless optical communication synchronization methods based on multi-sync head frame structure, comprising: sending end sends data frame, the data frame mainly includes start sequence, clock synchronization sequence, frame synchronization sequence;Receive end generates multiple gate clock signals, and the threshold of decision is obtained by estimating channel parameters, for recovering time slot bit information;According to recovery information, identify start sequence;Using multiple gate clock signals to extract synchronization clock, and then obtain the pulse count value in each time slot of frame synchronization sequence;The autocorrelation operation is carried out to the obtained pulse count value, when the correlation operation value is maximum, then frame synchronization is completed.The application reduces the risk of data frame loss, and reduces the influence of decision threshold selection on system synchronization success rate, and has the characteristics of high precision, fast rate, simple realization, can satisfy the demand of underwater photon counting communication synchronization.

Description

Technical Field

[0001] This invention belongs to the field of underwater wireless optical communication and relates to optical communication synchronization methods, particularly an underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure. Background Technology

[0002] Underwater Wireless Optical Communication (UWOC) is a wireless communication technology that typically uses the blue-green light band (450nm-570nm) as the information carrier to transmit information underwater. Due to absorption, scattering, and turbulence effects, underwater channel characteristics are highly complex. Seawater significantly inhibits the transmission of most information carriers, leading to numerous communication problems in long-distance, weak-link scenarios, such as easy link interruption, high bit error rate, and frequent burst errors. Single-photon detectors typically possess high sensitivity and can detect extremely weak light signals. Using highly sensitive single-photon detectors instead of traditional photodiodes in underwater wireless optical communication can effectively solve the problem of limited underwater communication distance.

[0003] Photon counting detection is a light intensity detection technique with single-photon-limited sensitivity, commonly used in optical imaging, biomedicine, and aerospace measurement. In recent years, due to numerous communication problems in long-distance and weak-link wireless optical communication, photon counting detection technology has been applied in wireless optical communication.

[0004] In traditional underwater wireless optical communication systems, the detection of optical signals at the receiving end typically employs PIN photodiode detectors and APD detectors. However, in single-photon communication systems, the single-photon detector outputs discrete electrical pulse signals. This differs significantly from the continuous waveform signals output by traditional devices like PIN and APD detectors, thus requiring different signal synchronization and extraction methods. Due to the discrete and random nature of the electrical pulse signals output by single-photon detectors, the frame structure and synchronization methods of the photon counting communication system require special design.

[0005] Photon-count-based communication methods can be applied to underwater wireless optical communication, deep-space optical communication, and other communication applications requiring high receiver sensitivity. However, the synchronization problem in photon-count-based underwater wireless optical communication affects the performance of the communication system, thus limiting further research into this technology. Summary of the Invention

[0006] The purpose of this invention is to address the problem that existing signal synchronization methods are unsuitable for discrete pulse signals output by single-photon detectors. To solve this problem, this invention proposes an underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure.

[0007] The technical solution to achieve the objective of this invention is: The underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure includes two parts: the transmitting end process and the receiving end process. The transmitting process includes: encoding and modulating the data, then framing the symbols with multiple synchronization headers and transmitting the data stream by a laser; The frame structure includes a start sequence, synchronization header 1, and synchronization header 2; The startup sequence is used to obtain the threshold for time slot information recovery and to start the counter for synchronous clock extraction. The synchronization head 1 is a clock synchronization sequence, whose function is to extract the synchronization clock and complete the symbol synchronization; The synchronization header 2 is a frame synchronization sequence, the function of which is to complete frame synchronization; The receiving end process includes: the optical signal arrives at the single-photon detector, and the single-photon detector outputs a discrete sequence of electrical pulses; The receiving end generates Q gated clock signals SCLOCK1, SCLOCK2, SCLOCK3...SCLOCKQ; each of these gated clock signals is a square wave with a 50% duty cycle, and its period is twice the width of the time slot of the frame sequence at the transmitting end, that is, the frequency of the gated clock signal is half the data stream rate sent by the transmitting end; there is a phase difference between the multiple gated clock signals, and the phase difference between two adjacent gated clock signals is π / Q; The rising and falling edges of the gated clock signal correspond to the start or end position of any time slot in the current data frame sequence, and the correspondence is not fixed.

[0008] The pulse count value in each time slot of the data frame structure is counted under each gated clock signal, which is used to complete the decision on the start sequence, synchronization head 1 and synchronization head 2.

[0009] The pulse counting clock is one of the Q-channel gated clock signals. Therefore, when the rising edge of the pulse counting clock corresponds to the start position of a certain time slot for transmitting data, the first falling edge after that rising edge must correspond to the start position of the next time slot.

[0010] The electrical pulse sequence is processed, and the start sequence, synchronization head 1, and synchronization head 2 are judged in sequence according to the multi-synchronization head frame structure. S1: Initiate sequence decision, including the following steps: S1-1, Channel parameter estimation: The decision threshold for pulse counting is obtained by estimating the channel parameters. The number of pulses N in the first "1" time slot of the current data frame start sequence received by the single-photon detector at the receiving end is counted. The pulse counting clock is used to count the number of pulses within a time slot and is one of the Q-channel gated clock signals; At the receiving end, when using the first-channel gated clock signal SCLOCK1 as the pulse counting clock, the number of pulses N1 within the first "1" time slot in the current data frame start sequence is obtained; At the receiving end, when using the second-channel gated clock signal SCLOCK2 as the pulse counting clock, the number of pulses N2 within the first "1" time slot in the current data frame start sequence is obtained; At the receiving end, when using the third-channel gated clock signal SCLOCK3 as the pulse counting clock, the number of pulses N3 within the first "1" time slot in the current data frame start sequence is obtained; When obtaining the Q count values N1, N2... NQ under the Q-channel pulse counting clocks, take the maximum value Nmax of the counts among the Q channels and assign it to N, i.e., N = Nmax; Set the threshold M = k * N, where k is a proportionality coefficient, 0 < k < 1; this threshold is used to recover the bit information of each time slot; S1-2, start sequence recovery: According to the decision threshold and the pulse count values within each time slot, recover the bit stream corresponding to the start sequence: Count the number of pulses within each time slot in the current data frame start sequence received by the single photon detector at the receiving end and compare it with the above-obtained threshold M: If the number of pulses within the time slot is greater than the threshold M, then judge this time slot as a "1" time slot; if the number of pulses within the time slot is less than the threshold M, then judge this time slot as a "0" time slot; Obtain the bit data stream of the start sequence according to S1-1 to S1-2; Under the Q-channel gated clock signals, the bit data streams of the Q start sequences can be obtained; S1-3, start sequence matching: Match the recovered bit stream with the information within the data frame to complete the decision of the start sequence: Compare the obtained Q-channel bit data streams with the sequence information in the frame structure respectively. When at least one channel meets the matching requirements, it is considered that the start sequence decision is successful; When the start sequence decision is successful, continue with step S2: S2: Sync header 1 decision, including the following steps: S2-1, sync clock extraction: Extract the sync clock according to the multiple-channel gated clock signals: Count the number of pulses at the high level of the gated clock signal in the current data frame sync header 1; When the first gated clock signal CLOCK1 is high, the number of pulses in the current data frame synchronization header 1 is calculated to be Y1. With the second gated clock signal CLOCK2 at a high level, the number of pulses in the current data frame synchronization header 1 is calculated to be Y2. With the third gated clock signal CLOCK3 at a high level, the number of pulses in the current data frame synchronization header 1 is calculated to be Y3. Similarly, when the Q-th gated clock signal CLOCKQ is high, the number of pulses in the current data frame synchronization header 1 is calculated to be YQ. Obtain the pulse count values ​​Y1, Y2, Y3...YQ when the Q-channel gated clock signal is at a high level; Compare the obtained Q-channel count values ​​Y1, Y2, Y3…YQ to obtain the maximum value Ymax = Yi, i∈1,2,3…Q. Select the i-th gate clock signal corresponding to the maximum count value Yi as the synchronization clock SCLOCK. The synchronization clock SCLOCK is an important clock for the synchronization head 1 decision. S2-2, Clock synchronization sequence recovery: Based on the decision threshold and the pulse count values ​​in each time slot, the bit stream corresponding to the start sequence is recovered: The number of pulses in each time slot of the current data frame synchronization header 1 received by the single-photon detector at the receiving end is counted and compared with the threshold M obtained in S1-1: if the number of pulses in the time slot is greater than the threshold M, the time slot is judged as "1" time slot; if the number of pulses in the time slot is less than the threshold M, the time slot is judged as "0" time slot. The bit data stream of the clock synchronization sequence is obtained from S2-1 to S2-2; The bit data stream of the Q-channel clock synchronization sequence can be obtained under the Q-channel gated clock signal; S2-3, Clock synchronization sequence matching: The synchronization of synchronization header 1 is completed by matching the recovered bitstream with the information within the data frame. The Q-channel data streams obtained above are compared with the sequence information in the frame structure. If at least one channel meets the matching requirements, the synchronization header 1 decision is considered successful. After the synchronization header 1 decision is successful, continue with step S3: S3: Synchronization Header 2 Decision, including the following steps: S3-1, Synchronous clock edge detection: Edge detection is performed on the synchronous clock SCLOCK obtained in S2-1 to generate a signal clock CLK. The signal clock is a periodic pulse signal, and the position of the pulse corresponds to the rising edge and falling edge of the synchronous clock SCLOCK. S3-2, Pulse Count Statistics: Statistical analysis of pulse counts in each time slot corresponding to synchronization head 2 under synchronized clock conditions: Based on the synchronization clock SCLOCK and clock signal CLK, the number of pulses in each time slot of the current data frame synchronization header 2 received by the single-photon detector at the receiving end is counted. As the discrete pulse sequence and synchronization clock move, the pulse count value corresponding to each time slot in the data frame synchronization header 2 can be obtained. Due to the serial input operation of the data stream, the pulse count value corresponding to each time slot is constantly changing. S3-3, Correlation Filtering Operation: In S3-2, obtain the pulse count value in each time slot of the current frame synchronization header 2, and perform autocorrelation calculation on the pulse count value; Since the pulse count value in each time slot of the synchronization head 2 changes continuously as the clock progresses, the value obtained by performing autocorrelation calculation is also constantly updated. S3-4, Frame synchronization sequence matching: Using correlation filtering, find the moment when the autocorrelation value is maximum: The maximum autocorrelation value will be obtained at the end of the last time slot of the data frame synchronization header 2; In S3-3, the continuously updated autocorrelation value is obtained. The obtained autocorrelation values ​​are compared. When the largest autocorrelation value is obtained, the frame synchronization sequence is considered to be matched, and the synchronization head 2 synchronization is completed.

[0011] Technical features and significant effects of the present invention: In view of the signal characteristics of the single-photon detector output in underwater single-photon communication, this invention provides a simple, feasible, high-precision, and high-speed underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure.

[0012] This method introduces channel parameter estimation to obtain the decision threshold during the start sequence decision, significantly reducing the possibility of data frame loss. After the start sequence decision is completed, the counter used to extract the synchronization clock is activated, effectively avoiding interference from background noise and dark counting.

[0013] The synchronization clock is extracted using multiple gated clock signals in the synchronization head 1 decision, which is simple to operate and highly accurate. During synchronization clock extraction, the multiple gated clock signals are processed in parallel to reduce misjudgments of the synchronization condition in synchronization head 1.

[0014] In the decision of the synchronization head 2, the strong autocorrelation of the frame synchronization sequence is used to reduce the impact of the threshold on frame synchronization.

[0015] This invention can significantly reduce the possibility of data frame loss and minimize the impact of the decision threshold on the system synchronization success rate. This invention enhances the accuracy of synchronization clock extraction, thereby ensuring the reliability of subsequent frame synchronization processing and data demodulation.

[0016] This invention is a synchronization method for underwater photon counting wireless optical communication based on a multi-synchronization header frame structure. Addressing the problems of easy data frame loss and high synchronization complexity in underwater photon counting wireless optical communication, this invention features high synchronization accuracy, fast synchronization rate, simple implementation method, and strong practicality, and can well meet the synchronization requirements of underwater photon counting communication. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a system for implementing an underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure, as shown in the embodiment. Figure 2 This is a schematic diagram of the data frame structure for underwater photon counting wireless optical communication in the embodiment; Figure 3 This is a flowchart of the underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure in the embodiment. Figure 4 This is a schematic diagram illustrating the principle of obtaining the decision threshold under channel parameter estimation in the embodiment. Figure 5 This is a block diagram illustrating the principle of synchronous clock extraction in the embodiment; Figure 6 This is an example of the autocorrelation of the frame synchronization sequence in the embodiment. Detailed Implementation

[0018] The present invention will be further described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example

[0019] like Figure 1 As shown, a system for implementing an underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure includes a transmitter and a receiver. The transmitting end includes PC1, a transmitter, a laser driving circuit, a laser, and a laser attenuation mirror; The PC1 is sequentially connected to the transmitter, laser drive circuit, laser and attenuation mirror. The laser emitted by the laser passes through the attenuation mirror to reach the underwater channel. The transmitter includes a modulation module and a framing module. The modulation module is connected to the PC1, and the framing module is connected to the laser driving circuit. The receiving end includes PC2, a receiver, a single-photon detector, a narrowband filter, and a convex lens; The PC2, receiver, and single-photon detector are connected in sequence. The narrowband filter is positioned in front of the single-photon detector, and the convex lens is positioned in front of the narrowband filter, corresponding to the underwater channel. The receiver includes a synchronization module and a demodulation module connected in sequence. The synchronization module is connected to the single-photon detector, and the demodulation module is connected to the PC2.

[0020] The optical signal arriving through the underwater channel is focused by a convex lens, then passes through a narrowband filter, and finally reaches a single-photon detector. The single-photon detector outputs discrete pulse signals, which are then sent to a receiver for processing.

[0021] Both the transmitter and receiver use Field Programmable Gate Array (FPGA) as the main control chip, and in this embodiment, the EP3C series chip is selected.

[0022] The data frame structure in the underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure is as follows: Figure 2 As shown, the frame structure includes a start sequence, a silence period, a synchronization header 1, a silence period, a synchronization header 2, and data. The frame structure in this embodiment is merely an example.

[0023] In this sequence, synchronization header 1 is the clock synchronization sequence, and synchronization header 2 is the frame synchronization sequence. The start sequence is an 8-bit bitstream 10101010, and the clock synchronization sequence is a 128-bit bitstream 101010…10. Both the start sequence and the clock synchronization sequence are periodic sequences alternating between 1s and 0s, with an odd number of 0s between any two adjacent 1s. The lengths of the start sequence and the clock synchronization sequence can be set according to system requirements; this embodiment is merely an example.

[0024] The frame synchronization sequence is a 15-bit bitstream 010100001100100, and it features a sharp autocorrelation peak. The frame synchronization sequence can be selected according to system requirements; this embodiment is merely an example.

[0025] The silence time portion is an 8-bit bitstream of 00000000, and the length of the bitstream can be set according to system requirements. This embodiment is just an example.

[0026] The synchronization header 1 decision can only begin after the startup sequence decision is successful. Once the synchronization header 1 is synchronized, the synchronization clock will be extracted. The synchronization header 2 decision can only begin after the synchronization clock is extracted. Once the synchronization header 2 is completed, the system synchronization is complete.

[0027] like Figure 3 As shown, the underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure includes the following steps: Step A: Initiate sequence decision, including the following steps: Step A1, Channel parameter estimation: like Figure 4 As shown, Q gated clock signals SCLOCK1, SCLOCK2, SCLOCK3...SCLOCKQ are generated. These gated clock signals are all square waves with a duty cycle of 50%, and their period is twice the time slot width in the frame structure of the transmitting end. That is, the frequency of the gated clock signal is 1 / 2 of the data stream rate sent by the transmitting end. There is only a phase difference between the multiple gated clock signals, and the phase difference between two adjacent gated clock signals is π / Q. The rising and falling edges of the gated clock signal correspond to the start or end position of any time slot in the current data frame, and the correspondence is not fixed. When the rising edge of the pulse counting clock corresponds to the start position of a certain time slot, the first falling edge after that rising edge must correspond to the start position of the next time slot. The transmitting end sends an optical signal, and after the receiving end receives the optical signal, the single-photon detector converts the optical signal into a discrete electrical pulse signal. The receiving end single-photon detector first outputs the start sequence in the data frame structure, namely the start sequence 10101010. like Figure 4 As shown, the baseband signal is the discrete pulse signal received by the receiver in the receiving end. Based on the first "1" time slot in the start sequence, the channel parameter estimation is completed. Under the first gate clock signal SCLOCK1, the number of pulses N1 in the first "1" time slot of the baseband signal under the high level of the gate clock signal SCLOCK1 is counted. The statistical method is as follows: In the receiver FPGA, discrete pulse signals are counted using edge-triggered counting, meaning each pulse triggers the count. Simultaneously, the level of SCLOCK1 is checked: a high level indicates an active enable signal, while a low level indicates an inactive enable signal. A counter cnt1 is set; when a pulse arrives and the enable signal is active, cnt1 is incremented by 1. If a pulse arrives but the enable signal is inactive, cnt1 is reset to zero, ensuring normal counting when the next data frame arrives. When the data frame reaches the "0" slot after the first "1" slot in the start sequence, N1 is obtained. Similarly, the number of pulses N1, N2, N3...NQ in the first "1" time slot under the high level of the Q-channel gated clock signal can be obtained. Then, N1, N2, N3...NQ are compared, and the maximum value Nmax is assigned to N, that is, N = Nmax; Set the decision threshold M = k * N, where k is the proportionality coefficient, 0 <k<1; Step A2, Initiate sequence recovery: According to the pulse counting method described above, the number of pulses in each time slot of the current data frame start sequence received by the single-photon detector at the receiving end under the gated clock signal SCLOCK1 is counted. If the pulse count value within the obtained time slot is greater than the decision threshold M, then the time slot is judged as a "1" time slot; if the pulse count value within the obtained time slot is less than the decision threshold M, then the time slot is judged as a "0" time slot; the bit data stream of the start sequence is obtained according to steps A1-A2; Under the Q-channel gated clock signal, the bit data stream of the Q-channel start sequence can be obtained by parallel processing according to step A2; Step A3, Initiate sequence matching: In the data frame structure, the start sequence is connected to the silent time portion, and the two parts form a 16-bit bit stream 10101010_00000000; when matching the start sequence, it is not required that the bit data stream of a certain path of the Q-channel gated clock signal is exactly the same as the start sequence 10101010. Instead, it is considered that when the bit data stream of a certain path of the Q-channel gated clock signal is 10100000, the start sequence is considered to be matched, that is, the start sequence decision is completed. Under the Q-channel gated clock signal, if the start sequence is successfully matched in any channel, the start sequence decision is considered successful. When the start sequence decision is successful, the Stop_sel signal is pulled high, and the decision of the first synchronization step 1 is started to extract the synchronization clock. Step B: Synchronize Header 1 Decision, including the following steps: Step B1, Synchronization Clock Extraction: In step A1 of the sequence decision-making process in step A, Q gated clock signals are generated, and the synchronization clock is one of the Q gated clock signals. Count the number of pulses in the current data frame synchronization header 1 when the gated clock signal is high; For example, to count the number of pulses in the high level of the first gated clock signal SCLOCK1, a counter cnt1 is generated. The input signals of this counter include the gated clock signal SCLOCK1, the start sequence success decision signal Stop_sel, and the discrete pulse sequence Pulse. The discrete pulse sequence Pulse is the signal output by the single-photon detector after receiving one frame of data. Figure 4 The Pulse signal mentioned in the text; The working principle of timer cnt1 is: First, check if the Stop_sel signal is high. When the start sequence decision success signal Stop_sel is high, start timer cnt1 and cnt1 counts normally; otherwise, counter cnt1 does not work. Then, it is determined whether a pulse has arrived. The trigger signal for counter cnt1 is the discrete pulse sequence Pulse. When a pulse arrives in Pulse, counter cnt1 is incremented by 1. Finally, determine whether the gate clock signal SCLOCK1 is high. The gate signal SCLOCK1 is an enable signal, and the counting is valid when it is high, that is, cnt1 increments by 1.

[0028] When the first gated clock signal SCLOCK1 is high, the number of pulses in the current data frame synchronization header 1 is Y1. Similarly, when the second gated clock signal SCLOCK2 is high, a counter cnt2 is generated to count the number of pulses in the current data frame synchronization header 1, which is Y2. When the third gate clock signal SCLOCK3 is high, a counter cnt2 is generated to count the number of pulses in the current data frame synchronization header 1, which is Y3. When the Q-th gated clock signal SCLOCKQ is high, a counter cntQ is generated to count the number of pulses in the current data frame synchronization header 1 as YQ. Finally, the pulse count values ​​Y1, Y2, Y3...YQ under the high level of the Q-channel gated clock signal can be obtained.

[0029] like Figure 5 As shown, after obtaining each count value, the maximum count value needs to be obtained through a numerical comparator and a count value selector.

[0030] Compare the obtained Q-channel count values ​​Y1, Y2, Y3…YQ to obtain the maximum value Ymax = Yi, i∈1,2,3…Q. Select the i-th gated clock signal corresponding to the maximum count value Yi as the synchronization clock SCLOCK. The synchronization clock SCLOCK is an important clock for the synchronization head 2 decision. Step B2, clock synchronization sequence recovery: The number of pulses in each time slot of the current data frame synchronization header 1 received by the single-photon detector at the receiving end is counted and compared with the threshold M obtained in step A1: if the number of pulses in the time slot is greater than the threshold M, the time slot is judged as "1" time slot; if the number of pulses in the time slot is less than the threshold M, the time slot is judged as "0" time slot. The bit data stream of the clock synchronization sequence is obtained according to step B2; Under the Q-channel gated clock signal, parallel processing can obtain the bit data stream of the Q-channel clock synchronization sequence; Step B3, clock synchronization sequence matching: In the data frame structure, synchronization header 1 is connected to the silent time portion. The synchronization header is a periodic sequence of 10101010… with a variable length, and the silent time portion is the sequence 00000000. When matching the clock synchronization sequence, it is not required that the bit data stream of a certain path of the Q-channel gated clock signal be exactly the same as the clock synchronization sequence 10101010…. Instead, it is considered that when the bit data stream of a certain path of the Q-channel gated clock signal is 1010100000, the clock synchronization sequence is considered to be matched, that is, the synchronization header 1 decision is completed. The obtained Q-channel data streams are compared with the sequence information in the frame structure. If at least one channel meets the matching requirements, the synchronization head 1 decision is considered successful. Once the synchronization head 1 decision is successful, the Sel_en signal goes high, indicating that the synchronization clock extraction is complete and the frame synchronization operation can begin. Step C, Synchronizing Head 2 Decision, includes the following steps: Step C1, Synchronization clock edge detection: Edge detection is performed on the synchronous clock SCLOCK obtained in step B1 to generate the slave signal clock CLK; The generation method is as follows: Under the system clock of the FPGA, a first-level flip-flop is used to synchronize the synchronous clock SCLOCK to obtain signal CLK1. At this time, CLK1 and SCLOCK are out of phase by half a system clock cycle. After performing a NOT operation on SCLOCK, an OR operation is performed with CLK1 to obtain signal CLK2. After performing a NOT operation on CLK, an OR operation is performed with SCLOCK to obtain signal CLK3. Finally, an OR operation is performed on CLK2 and CLK3 to obtain the signal clock CLK. The signal clock is a pulse signal, and the position of the pulse corresponds to the rising or falling edge of the synchronous clock SCLOCK; Step C2, Pulse Count Statistics: Based on the synchronization clock SCLOCK and clock signal CLK, the number of pulses in each time slot of the current data frame synchronization header 2 received by the single-photon detector at the receiving end is counted. As the discrete pulse sequence and synchronization clock move, the pulse count value corresponding to each time slot in the data frame synchronization header 2 can be obtained. Due to the serial input operation of the data stream, the pulse count value corresponding to each time slot in the synchronization header 2 is constantly changing. Step C3, Correlation Filtering Operation: like Figure 6As shown, the frame synchronization sequence has strong autocorrelation, which is manifested in the image as a large peak at the horizontal coordinate of 0. In this embodiment, the frame synchronization sequence is 010_100_001_100_100. In step B, the pulse count value in each time slot of the current frame synchronization header 2 is obtained, and autocorrelation is performed on it; Since the pulse count value in each time slot of the synchronization head 2 changes continuously as the clock progresses, the value obtained by performing autocorrelation calculation is also constantly updated. Step C4, frame synchronization sequence matching: The maximum autocorrelation value will be obtained at the end of the last time slot of the data frame synchronization header 2.

[0031] exist Figure 6 In this context, the maximum value of the related operation is 5, which is set at the threshold ρ.

[0032] In step C, the continuously updated autocorrelation value is obtained. The obtained autocorrelation value is compared with ρ. When the maximum autocorrelation value is obtained and the maximum autocorrelation value is greater than or equal to ρ-1, the frame synchronization sequence is considered to be successfully matched and the synchronization head 2 is completed. At this time, the Frame_flag signal is pulled high, indicating that the synchronization head 2 is completed and data demodulation can begin.

[0033] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A synchronization method for underwater photon counting wireless optical communication based on a multi-synchronization header frame structure, characterized in that, It includes two parts: the sending process and the receiving process. The transmitting process includes: encoding and modulating the data, then framing the symbols with multiple synchronization headers and transmitting the data stream by a laser; The frame structure includes a start sequence, synchronization header 1, and synchronization header 2; The startup sequence is used to obtain the threshold for time slot information recovery and to start the counter for synchronous clock extraction. The synchronization head 1 is a clock synchronization sequence, whose function is to extract the synchronization clock and complete the symbol synchronization; The synchronization header 2 is a frame synchronization sequence, the function of which is to complete frame synchronization; The receiving end process includes: the optical signal arrives at the single-photon detector, and the single-photon detector outputs a discrete sequence of electrical pulses; The receiving end generates Q gated clock signals SCLOCK1, SCLOCK2, SCLOCK3...SCLOCKQ; each of these gated clock signals is a square wave with a 50% duty cycle, and its period is twice the width of the time slot of the frame sequence at the transmitting end, that is, the frequency of the gated clock signal is half the data stream rate sent by the transmitting end; there is a phase difference between the multiple gated clock signals, and the phase difference between two adjacent gated clock signals is π / Q; The electrical pulse sequence is processed, and the start sequence, synchronization head 1, and synchronization head 2 are judged in sequence according to the multi-synchronization head frame structure. S1: Initiate sequence decision, including the following steps: S1-1, by estimating the channel parameters, the decision threshold for pulse counting is obtained; S1-2, based on the decision threshold and the pulse count value in each time slot, recover the bit stream corresponding to the start sequence; S1-3, Match the recovered bit stream with the information within the data frame to complete the decision on the start sequence; After the start sequence decision is successful, continue with step S2: S2: Synchronization Header 1 Decision, including the following steps: S2-1, extracts the synchronization clock based on the multi-channel gated clock signal; S2-2, Based on the decision threshold and the pulse count value in each time slot, recover the bit stream corresponding to the start sequence; S2-3, Match the recovered bit stream with the information within the data frame to complete the synchronization of synchronization header 1; After the synchronization header 1 decision is successful, continue with step S3: S3: Synchronization Header 2 Decision, including the following steps: S3-1 performs edge detection on the synchronization clock and generates a signal clock. The signal clock is a periodic pulse signal, and the position of the pulse corresponds to the rising edge and falling edge of the synchronization clock. S3-2, Count the pulse count values ​​in each time slot corresponding to synchronization head 2 under the synchronous clock; S3-3, obtain the pulse count value in each time slot of the current frame synchronization header 2 in S3-2, and perform autocorrelation operation on the pulse count value; S3-4: Using correlation filtering, find the moment when the autocorrelation value is the largest, and synchronization head 2 is completed.

2. The underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure according to claim 1, characterized in that, S1 specifically includes the following steps: S1-1, Count the number of pulses N in the first "1" time slot of the current data frame start sequence received by the single-photon detector at the receiving end; The pulse counting clock is used to count the number of pulses within a time slot and is one of the Q-channel gated clock signals. At the receiving end, when using the first gated clock signal SCLOCK1 as the pulse counting clock, the number of pulses N1 within the first "1" time slot in the current data frame start sequence is obtained; At the receiving end, when using the second gated clock signal SCLOCK2 as the pulse counting clock, the number of pulses N2 within the first "1" time slot in the current data frame start sequence is obtained; At the receiving end, when using the third gated clock signal SCLOCK3 as the pulse counting clock, the number of pulses N3 within the first "1" time slot in the current data frame start sequence is obtained; When obtaining Q count values N1, N2... NQ under Q pulsed counting clocks, take the maximum value Nmax of the counts in the Q paths and assign it to N, that is, N = Nmax; Set the threshold M = k * N, where k is a proportionality coefficient, 0 < k < 1; this threshold is used to recover the bit information of each time slot; S1-2. Statistically count the number of pulses within each time slot in the current data frame start sequence received by the single-photon detector at the receiving end, and compare it with the above-obtained threshold M: If the number of pulses within the time slot is greater than the threshold M, then determine this time slot as a "1" time slot; if the number of pulses within the time slot is less than the threshold M, then determine this time slot as a "0" time slot; Obtain the bit data stream of the start sequence according to S1-1 to S1-2; Under Q gated clock signals, Q bit data streams of the start sequence can be obtained; S1-3. Compare the obtained Q bit data streams with the sequence information in the frame structure respectively. When at least one path meets the matching requirement, it is considered that the start sequence decision is successful.

3. The underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure according to claim 1, characterized in that, S2 specifically includes the following steps: S2-1. Statistically count the number of pulses under the high level of the gated clock signal in the current data frame sync header 1; Under the high level of the first gated clock signal CLOCK1, it is statistically obtained that the number of pulses in the current data frame sync header 1 is Y1; Under the high level of the second gated clock signal CLOCK2, it is statistically obtained that the number of pulses in the current data frame sync header 1 is Y2; Under the high level of the third gated clock signal CLOCK3, it is statistically obtained that the number of pulses in the current data frame sync header 1 is Y3; Similarly, under the high level of the Qth gated clock signal CLOCKQ, it is statistically obtained that the number of pulses in the current data frame sync header 1 is YQ; Obtain the pulse count values Y1, Y2, Y3... YQ under the high levels of Q gated clock signals; Compare the obtained Q count values Y1, Y2, Y3... YQ, and obtain the maximum value Ymax = Yi, i ∈ 1, 2, 3... Q. Select the ith gated clock signal corresponding to the maximum count value Yi as the synchronization clock SCLOCK. The synchronization clock SCLOCK is an important clock for the decision of sync header 1; S2-2. Statistically count the number of pulses within each time slot in the current data frame sync header 1 received by the single-photon detector at the receiving end, and compare it with the threshold M obtained in S1-1: If the number of pulses within the time slot is greater than the threshold M, then determine this time slot as a "1" time slot; if the number of pulses within the time slot is less than the threshold M, then determine this time slot as a "0" time slot; The bit data stream of the clock synchronization sequence is obtained from S2-1 to S2-2; The bit data stream of the Q-channel clock synchronization sequence can be obtained under the Q-channel gated clock signal; S2-3, compare the Q-channel data streams obtained above with the sequence information in the frame structure respectively. When at least one channel meets the matching requirements, the synchronization head 1 decision is considered successful.

4. The underwater photon counting wireless optical communication synchronization method based on a multi-synchronization header frame structure according to claim 1, characterized in that, S3 specifically includes the following steps: S3-1 performs edge detection on the synchronous clock SCLOCK obtained in S2-1 to generate a signal clock CLK. The signal clock is a periodic pulse signal, and the position of the pulse corresponds to the rising edge and falling edge of the synchronous clock SCLOCK. S3-2, based on the synchronization clock SCLOCK and clock signal CLK, count the number of pulses in each time slot of the current data frame synchronization header 2 received by the single-photon detector at the receiving end. As the discrete pulse sequence and synchronization clock move, the pulse count value corresponding to each time slot in the data frame synchronization header 2 can be obtained. Due to the serial input operation of the data stream, the pulse count value corresponding to each time slot is constantly changing. S3-3, obtain the pulse count value in each time slot of the current frame synchronization header 2 in S3-2, and perform autocorrelation operation on the pulse count value; Since the pulse count value in each time slot of the synchronization head 2 changes continuously as the clock progresses, the value obtained by performing autocorrelation calculation is also constantly updated. S3-4, at the end of the last time slot of the data frame synchronization header 2, the maximum autocorrelation value is obtained; In S3-3, the continuously updated autocorrelation value is obtained. The obtained autocorrelation values ​​are compared. When the largest autocorrelation value is obtained, the frame synchronization sequence is considered to be matched, and the synchronization head 2 synchronization is completed.

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