Photoelectric sensors and their manufacturing methods, as well as electronic devices

Abstract

A photoelectric sensor, a method for forming the same, and an electronic device are disclosed. The photoelectric sensor includes: an isolation structure located within a pixel substrate between photosensitive units, the isolation structure including a conductive layer; a plurality of interconnect structures distributed within the pixel substrate with ends exposed on a second surface, the interconnect structures including a first interconnect structure located in a first lead region and a second interconnect structure located in a second lead region, the second interconnect structure being electrically connected to the first interconnect structure; a metal grid located on the second surface and in contact with the conductive layer; a connection layer located on the second surface of the first lead region and in contact with the metal grid and the first interconnect structure; and a solder pad layer located on the second surface of the lead region, the thickness of the solder pad layer being greater than the thickness of the connection layer and the metal grid; the solder pad layer includes a first solder pad layer located in the second lead region, in contact with the end of the second interconnect structure facing the second surface. Embodiments of the present invention improve the performance of the photoelectric sensor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a photoelectric sensor and a method for forming the same, as well as an electronic device. Background Technology

[0002] A photoelectric sensor is a device that converts light signals into electrical signals. Its working principle is based on the photoelectric effect, which refers to the phenomenon where electrons in a substance absorb the energy of photons and produce corresponding electrical effects when light shines on them.

[0003] For example, CCD (Charge Coupled Device) image sensors and CMOS image sensors, widely used in digital cameras and other electro-optical devices, both utilize photoelectric conversion to convert optical images into electrical signals and output digital images. ToF (Time of Flight) distance sensors, such as DTOF (Direct Time of Flight) sensors, record the time between the emission and detection of a light pulse, converting the time difference into distance information. This technology can be used in various ranging scenarios, including autonomous driving, robotic vacuum cleaners, and VR (Virtual Reality) / AR (Augmented Reality) modeling.

[0004] In photoelectric sensors, the dark count of pixels can significantly impact the sensor's frame rate and performance. To reduce the dark count, one approach is to apply a voltage to the backside metal grid (BMG) on the back of the pixel wafer. The BMG is electrically connected to a deep trench isolation (DTI) structure to allow holes to accumulate at the interface between the DTI and the pixel substrate.

[0005] However, the performance of photoelectric sensors still needs to be improved. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a photoelectric sensor, a method for forming the same, and an electronic device, thereby improving the performance of the photoelectric sensor.

[0007] To address the aforementioned problems, embodiments of the present invention provide a photoelectric sensor, comprising a photosensitive area and a lead area surrounding the photosensitive area, the lead area including a first lead area and a second lead area surrounding the first lead area; the photoelectric sensor further comprising: a pixel substrate including opposing first and second surfaces; a plurality of photosensitive units formed within the pixel substrate of the photosensitive area; an isolation structure located within the pixel substrate between the photosensitive units and exposed on the second surface of the pixel substrate, the isolation structure including a conductive layer; and a plurality of interconnect structures distributed within the pixel substrate with ends exposed on the second surface, the interconnect structures including a first lead area located in the first lead area. An interconnect structure and a second interconnect structure located in the second lead region, the second interconnect structure being electrically connected to the first interconnect structure; a metal grid located on and in contact with the conductive layer on the second surface; a connection layer located on the second surface of the first lead region and in contact with the metal grid and the first interconnect structure, the connection layer being electrically connected to the metal grid and the first interconnect structure; a solder pad layer located on the second surface of the lead region, the thickness of the solder pad layer being greater than the thickness of the connection layer and the metal grid; the solder pad layer includes a first solder pad layer located in the second lead region, in contact with the end of the second interconnect structure facing the second surface.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a photoelectric sensor, comprising: providing a pixel substrate, including a first surface and a second surface opposite to each other, the pixel substrate including a photosensitive area and a lead area surrounding the photosensitive area, a plurality of photosensitive units being formed within the pixel substrate of the photosensitive area, the lead area including a first lead area and a second lead area surrounding the first lead area; forming an isolation structure within the pixel substrate between the photosensitive units, the ends of the isolation structure being exposed on the second surface, the isolation structure including a conductive layer; forming a plurality of interconnect structures distributed within the pixel substrate with their ends exposed on the second surface, the interconnect structures including a conductive layer located on the second surface. The system comprises a first interconnect structure in a first lead region and a second interconnect structure in a second lead region, wherein the second interconnect structure is electrically connected to the first interconnect structure; a solder pad layer is formed on a second surface of the lead region, including a first solder pad layer in the second lead region, the first solder pad layer being in contact with the end of the second interconnect structure facing the second surface; in the same step, a metal grid is formed on a conductive layer on the second surface, and a connection layer is formed on the second surface and in contact with the metal grid and the first interconnect structure, the metal grid being in contact with the conductive layer, and the connection layer being electrically connected to the metal grid and the first interconnect structure.

[0009] Accordingly, embodiments of the present invention also provide an electronic device, including the photoelectric sensor provided in embodiments of the present invention.

[0010] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0011] In the photoelectric sensor provided in this embodiment of the invention, the interconnect structure includes a first interconnect structure located in the first lead area and a second interconnect structure located in the second lead area. The second interconnect structure is electrically connected to the first interconnect structure. A connection layer is electrically connected to the metal grid and the first interconnect structure. A first solder pad layer in contact with the second interconnect structure is also provided in the second lead area. Thus, through the sequentially connected connection layer, the first interconnect structure, and the second interconnect structure, the metal grid can be connected to the first solder pad layer. Correspondingly, a voltage can be applied to the conductive layer in the isolation structure through the metal grid to reduce the dark count of the photoelectric sensor. Count); wherein the thickness of the pad layer is greater than the thickness of the connection layer and the metal grid, the pad layer includes a first pad layer located in the second lead area, the first pad layer can be formed in the same process as other pad layers located in the lead area, so that the thickness of the first pad layer is large and the height consistency between the first pad layer and other pad layers located in the lead area is high, avoiding the problems of inconsistent height between the first pad layer and other pad layers, and the first pad layer being too thin, which helps to reduce the process risks caused by inconsistent height of the pad layer and the first pad layer being too thin, thereby reducing the difficulty of packaging and testing, and improving the performance of the photoelectric sensor.

[0012] In the method for forming a photoelectric sensor provided in this embodiment of the invention, during the formation of the interconnect structure, the interconnect structure includes a first interconnect structure located in the first lead region and a second interconnect structure located in the second lead region, and the second interconnect structure is electrically connected to the first interconnect structure. During the formation of a pad layer on the second surface of the lead region, the pad layer includes a first pad layer located in the second lead region, and the first pad layer is in contact with the end of the second interconnect structure facing the second surface. Then, in the same step, a metal grid is formed on the conductive layer of the second surface, and a connection layer is formed on the second surface and in contact with the metal grid and the first interconnect structure. The metal grid is in contact with the conductive layer, and the connection layer... The metal grid and the first interconnect structure are electrically connected, thereby connecting the conductive layer in the isolation structure to the first pad layer through the sequentially connected metal grid, connection layer, first interconnect structure and second interconnect structure. Correspondingly, a voltage can be applied to the isolation structure through the metal grid to reduce the dark count of the photoelectric sensor. The first pad layer and the metal grid are formed in different steps. The first pad layer can be formed using the pad layer process of the lead area, so that the first pad layer has a large thickness and a high height consistency with other pad layers in the lead area. This helps to reduce the process risks caused by inconsistent height of the pad layer and the first pad layer being too thin, thereby reducing the difficulty of subsequent packaging and testing processes and improving the performance of the photoelectric sensor. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the cross-sectional structure of a photoelectric sensor.

[0014] Figure 2 This is a cross-sectional structural schematic diagram of an embodiment of the photoelectric sensor of the present invention.

[0015] Figures 3 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the photoelectric sensor of the present invention. Detailed Implementation

[0016] As the background technology shows, the performance of current photoelectric sensors still needs improvement. This paper analyzes the reasons why the performance of photoelectric sensors needs further improvement, using an example of a photoelectric sensor.

[0017] Figure 1 This is a schematic diagram of the cross-sectional structure of a photoelectric sensor.

[0018] refer to Figure 1The photoelectric sensor includes a photosensitive area 10p and a lead area 10n surrounding the photosensitive area 10p; the lead area 10n includes a first lead area 10n1 and a second lead area 10n2 from the inside out; the photoelectric sensor includes: a logic substrate 20, including a bonding surface 21, in which logic devices are formed; a pixel substrate 10, including a first surface 11 and a second surface 12 opposite to each other, the first surface 11 being bonded to the bonding surface 21 of the logic substrate 20, and a plurality of photosensitive units 13 being formed in the pixel substrate 10 of the photosensitive area 10p; an isolation structure (not shown) located in the pixel substrate 10 between the photosensitive units 13. The end of the isolation structure is exposed on the second surface 12. The isolation structure includes a conductive layer 14; a via interconnect structure 15 that penetrates the pixel substrate 10 of the second lead area 10n2 and is electrically connected to the logic device; a metal grid 16 that is located on the conductive layer 14 of the second surface 12 and is in contact with the conductive layer 14; a first pad layer 17 that is located on the end of the via interconnect structure 15 facing the second surface 12; and a second pad layer 18 that is located on the first lead area 10n1 of the second surface 12 and is connected to the metal grid 16. The top surfaces of the second pad layer 18 and the metal grid 16 are lower than the top surface of the first pad layer 17.

[0019] By connecting the second pad layer 18 to the metal grid 16, a voltage can be applied to the isolation structure on the back side of the pixel substrate 10 (i.e., the second surface 12) through the second pad layer 18 and the metal grid 16, so that holes are accumulated at the interface between the isolation structure and the pixel substrate 10, thereby reducing the dark count of the photoelectric sensor.

[0020] However, the second pad layer 18 is usually formed in the same process as the metal grid 16. Since the linewidth of the metal grid 16 is small and the metal grid 16 is usually thin to facilitate the patterning of the metal grid 16, the second pad layer 18 is also thin. As a result, the top surface of the second pad layer 18 and the metal grid 16 is lower than the top surface of the first pad layer 17, which leads to poor height consistency between the second pad layer 18 and the first pad layer 17. In addition, the thinness of the second pad layer 18 can easily increase the difficulty and process risk of subsequent packaging and testing, thereby resulting in poor performance of the photoelectric sensor.

[0021] To address the aforementioned technical problem, this invention provides a photoelectric sensor. The interconnect structure includes a first interconnect structure located in a first lead region and a second interconnect structure located in a second lead region. The second interconnect structure is electrically connected to the first interconnect structure. A connection layer electrically connects the metal grid and the first interconnect structure. Furthermore, a first solder pad layer in contact with the second interconnect structure is disposed in the second lead region. Thus, through the sequentially connected connection layer, the first interconnect structure, and the second interconnect structure, the metal grid can be connected to the first solder pad layer. Correspondingly, a voltage can be applied to the conductive layer in the isolation structure through the metal grid to reduce the dark count of the photoelectric sensor. Count); wherein the thickness of the pad layer is greater than the thickness of the connection layer and the metal grid, the pad layer includes a first pad layer located in the second lead area, the first pad layer can be formed in the same process as other pad layers located in the lead area, so that the thickness of the first pad layer is large and the height consistency between the first pad layer and other pad layers located in the lead area is high, avoiding the problems of inconsistent height between the first pad layer and other pad layers, and the first pad layer being too thin, which helps to reduce the process risks caused by inconsistent height of the pad layer and the first pad layer being too thin, thereby reducing the difficulty of packaging and testing, and improving the performance of the photoelectric sensor.

[0022] To address the aforementioned technical problem, this invention also provides a method for forming a photoelectric sensor. During the formation of an interconnect structure, the interconnect structure includes a first interconnect structure located in a first lead region and a second interconnect structure located in a second lead region, with the second interconnect structure electrically connected to the first interconnect structure. During the formation of a pad layer on the second surface of the lead region, the pad layer includes a first pad layer located in the second lead region, and the first pad layer contacts the end of the second interconnect structure facing the second surface. Subsequently, in the same step, a metal grid is formed on a conductive layer on the second surface, and a connection layer is formed on the second surface and contacts the metal grid and the first interconnect structure, with the metal grid in contact with the conductive layer. The connecting layer electrically connects the metal grid and the first interconnect structure. Through the sequential connection of the metal grid, connecting layer, first interconnect structure, and second interconnect structure, the conductive layer in the isolation structure is connected to the first pad layer. Correspondingly, a voltage can be applied to the isolation structure through the metal grid to reduce the dark count of the photoelectric sensor. The first pad layer and the metal grid are formed in different steps. The first pad layer can be formed using the pad layer process of the lead area, resulting in a larger thickness and higher height consistency between the first pad layer and other pad layers in the lead area. This helps reduce the process risks caused by inconsistent pad layer heights and excessively thin first pad layers, thereby reducing the difficulty of subsequent packaging and testing processes and improving the performance of the photoelectric sensor.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] refer to Figure 2 The diagram shows a cross-sectional structural schematic of an embodiment of the photoelectric sensor of the present invention.

[0025] As an example, this embodiment uses a TOF (Time of Flight) sensor as the photoelectric sensor for illustration. More specifically, the photoelectric sensor can be a DTOF (Direct Time of Flight) sensor. In other embodiments, the photoelectric sensor can also be an iTOF (Indirect Time of Flight) sensor.

[0026] In other embodiments, the photoelectric sensor may also be other types of photoelectric sensors such as CCD (Charge Coupled Device) image sensors and CMOS image sensors.

[0027] like Figure 2 As shown, the photoelectric sensor includes a photosensitive area 100P and a lead area 100N surrounding the photosensitive area 100P. The lead area 100N includes a first lead area 100N1 and a second lead area 100N2 surrounding the first lead area 100N1.

[0028] A plurality of photosensitive units 110 are formed within the photosensitive area 100P. The photosensitive units 110 are used to receive optical signals so as to convert the optical signals into electrical signals. Specifically, the photosensitive area 100P is a pixel area, and the photosensitive units 110 are pixel units.

[0029] The lead area 100N is used for wiring and forming leads to achieve electrical connection between the photosensitive unit 110 or other device structures and external circuits. In this embodiment, the first lead area 100N1 surrounds the photosensitive area 100P, and the second lead area 100N2 surrounds the first lead area 100N1.

[0030] In this embodiment, the photoelectric sensor includes: a pixel substrate 100, including a first surface 101 and a second surface 102 facing each other; a plurality of photosensitive units 110 are formed in the pixel substrate 100 of the photosensitive area 100P; an isolation structure 160 is located in the pixel substrate 100 between the photosensitive units 110 and exposed on the second surface 102 of the pixel substrate 100, the isolation structure 160 including a conductive layer 140; a plurality of interconnect structures 60 are distributed in the pixel substrate 100 and their ends are exposed on the second surface 102, the interconnect structures 60 include a first interconnect structure 60(1) located in the first lead area 100N1 and a second interconnect structure 60(2) located in the second lead area 100N2, the second interconnect structure 60(2) and the first interconnect structure 60(1) are connected. Electrical connection between 0(1); metal grid 210, located on and in contact with the conductive layer 140 of the second surface 102; connection layer 220, located on the second surface 102 of the first lead region 100N1 and in contact with the metal grid 210 and the first interconnect structure 60(1), the connection layer 220 electrically connects the metal grid 210 and the first interconnect structure 60(1); solder pad layer 70, located on the second surface 102 of the lead region 100N, the thickness of the solder pad layer 70 is greater than the thickness of the connection layer 220 and the metal grid 210; the solder pad layer 70 includes a first solder pad layer 70(1) located in the second lead region 100N2, in contact with the end of the second interconnect structure 60(2) facing the second surface 102.

[0031] The pixel substrate 100 is used to provide an operating platform for the formation of the photoelectric sensor.

[0032] The photosensitive area 100P contains a plurality of photosensitive units 110, which are used to receive optical signals and convert them into electrical signals. Specifically, the photosensitive area 100P is a pixel area, and the photosensitive units 110 are pixel units.

[0033] As one embodiment, the photosensitive unit 110 includes an optoelectronic device 115. Specifically, a single-photon avalanche diode (SPAD) 115. In other embodiments, the photosensitive unit may also include other types of optoelectronic devices.

[0034] In this embodiment, the first surface 101 of the pixel substrate 100 is the front side, and the second surface 102 is the back side. Specifically, the pixel substrate 100 is a backside illumination (BSI) pixel wafer, and the second surface 102 of the pixel substrate 100 is the light-receiving surface.

[0035] In this embodiment, the pixel substrate 100 further includes a metal interconnect line 50 located on the side of the pixel substrate 100 close to the first surface 101 and in contact with the end of the first interconnect structure 60 (1) facing the first surface 101 and the end of the second interconnect structure 60 (2) facing the first surface 102. The metal interconnect line 50 is electrically connected to the first interconnect structure 60 (1) and the second interconnect structure 60 (2).

[0036] In this embodiment, along the direction from the first surface 101 to the second surface 102, the pixel substrate 100 includes a rear pixel interconnect layer 30 and a front pixel device layer 40 stacked sequentially.

[0037] The rear pixel interconnect layer 30 contains multiple interconnect layers (not shown) for electrical connections between device structures. The front pixel device layer 40 contains photosensitive units 110.

[0038] In this embodiment, the metal interconnect 50 is located in the back pixel interconnect layer 30.

[0039] The photoelectric sensor further includes: a logic substrate 200, including a bonding surface 201; the bonding surface 201 of the logic substrate 200 is bonded to the first surface 101 of the pixel substrate 100; and logic devices (not shown) are formed within the logic substrate 200.

[0040] The second substrate 200 serves as a logic wafer, used to analyze and process the electrical signals provided by the pixel substrate 100. Specifically, logic devices are formed within the second substrate 200, which are used to analyze and process the electrical signals provided by the pixel substrate 100.

[0041] The bonding surface 201 is used to achieve bonding with the pixel substrate 100.

[0042] In this embodiment, the logic substrate 200 includes a front-end logic device layer (not shown) and a back-end logic interconnect layer (not shown) located on the front-end logic device layer; the bonding surface 201 is the side of the back-end logic interconnect layer opposite to the front-end logic device layer.

[0043] The logic devices are formed in the front-end logic device layer. The back-end logic interconnect layer has multiple interconnect layers for electrical connections between the logic devices and external circuits or other device structures.

[0044] In this embodiment, by setting the pixel area (i.e., the photosensitive area) and the logic area on different substrates, and bonding the pixel substrate 100 and the logic substrate 200 together, it is beneficial to increase the pixel area, shorten the path of light to the photoelectric element, reduce light scattering, and make the light more focused, thereby improving the photoelectric sensor's light-sensing ability in low-light environments and reducing system noise and crosstalk.

[0045] As one embodiment, the bonding surface 201 of the logic substrate 200 and the first surface 101 of the pixel substrate 100 are bonded by a hybrid bonding method.

[0046] It should be noted that the above-described bonding method between the pixel substrate 100 and the logic substrate 200 is only an example, and the bonding method between the pixel substrate 100 and the logic substrate 200 is not limited to this. For example, in other embodiments, the bonding method between the pixel substrate and the logic substrate can also be direct bonding (e.g., fusion bonding and anodic bonding) or indirect bonding (e.g., metal eutectic bonding, hot-press bonding, and adhesive bonding), etc.

[0047] The isolation structure 160 is used to reduce optical and electrical crosstalk between adjacent photosensitive units 110. In this embodiment, the isolation structure 160 is a deep trench isolation (DTI) structure.

[0048] In this embodiment, the isolation structure 160 includes a conductive layer 140 so that a voltage can be applied to the conductive layer 140 to accumulate holes at the interface between the isolation structure 150 and the pixel substrate 100, which helps to reduce the dark count of the photoelectric sensor.

[0049] The end of the conductive layer 140 is exposed on the second surface 102 so that the metal grid 210 can contact the end of the conductive layer 140 exposed on the second surface 102, thereby allowing the electrical properties of the conductive layer 140 to be drawn out through the metal grid 210.

[0050] In this embodiment, the conductive layer 140 is made of a metallic material. The conductive layer 140 may be made of one or more of tungsten, titanium, titanium nitride, tantalum nitride, and copper. In this embodiment, the conductive layer 140 is made of tungsten. Compared to other metallic materials, tungsten is less prone to diffusion and has excellent hole-filling ability. Therefore, tungsten is more suitable for use in the deep trenches of photoelectric sensors. Furthermore, tungsten is an opaque metallic material, which can effectively block light, thus making the reduction of optical crosstalk between adjacent photosensitive units 110 by the isolation structure 160 more significant.

[0051] In this embodiment, the isolation structure 160 includes a conductive layer 140 and an insulating layer 150 located between the conductive layer 140 and the pixel substrate 100. The insulating layer 150 is used to achieve insulation between the conductive layer 140 and the pixel substrate 100.

[0052] In this embodiment, the material of the insulating layer 150 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, and tantalum oxide.

[0053] In this embodiment, an isolation trench (not shown) is formed within the pixel substrate 100 between the photosensitive units 110, and the isolation structure 160 is located within the isolation trench. The insulating layer 150 is located on the sidewalls and bottom of the isolation trench.

[0054] The interconnect structure 60 is used to realize the electrical connection between the film layer structure within the pixel substrate 100 and the external circuit. In this embodiment, the interconnect structure 60 penetrates the front pixel device layer 40 and is also located in the rear pixel interconnect layer 30, which has a certain thickness.

[0055] In this embodiment, the interconnect structure 60 is a through-silicon via (TSV) interconnect structure. The TSV interconnect structure enables circuit conduction in the vertical direction, maximizes the density of three-dimensional stacking, reduces the horizontal area of ​​the chip, and has the characteristics of short connection distance and high strength, which is beneficial for the thinning and miniaturization of devices, as well as reducing power consumption and improving operating speed.

[0056] In this embodiment, the interconnect structure 60 is made of a conductive material, such as one or more of copper, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0057] The second interconnect structure 60(2) is electrically connected to the first interconnect structure 60(1) to realize the electrical connection between the connection layer 200 and the first pad layer 70(1) located in the second lead area 100N2.

[0058] It should be noted that the number of second interconnect structures 60(2) corresponding to the first pad layer 70(1) can be one or more. When there are multiple second interconnect structures 60(2) corresponding to the first pad layer 70(1), the first pad layer 70(1) can simultaneously contact multiple second interconnect structures 60(2) to achieve electrical connection with the first interconnect structure 60(1), the connection layer 220, the metal grid 210 and the isolation structure 160, which is beneficial to reduce the resistance of the second interconnect structure 60(2) and improve the electrical connection efficiency between the first pad layer 70(1) and the isolation structure 160.

[0059] In this embodiment, both the first interconnect structure 60(1) and the second interconnect structure 60(2) are in contact with the metal interconnect line 50, and the first interconnect structure 60(1) and the second interconnect structure 60(2) are electrically connected through the metal interconnect line 50.

[0060] It should be noted that the distance d1 between the first interconnect structure 60(1) and the isolation structure 160 along the direction parallel to the first surface 101 should not be too small or too large. If the distance d1 is too small, it will easily increase the process difficulty of TSV and DTI fabrication and compress the safe process window; if the distance d1 is too large, it will not only waste chip area, but also easily lead to the problem of excessively long interconnect layer 220 and excessive resistance of interconnect layer 220. Therefore, in this embodiment, the distance d1 between the first interconnect structure 60(1) and the isolation structure 160 along the direction parallel to the first surface 101 is 10μm to 50μm.

[0061] It should also be noted that the distance d2 between the first interconnect structure 60(1) and the second interconnect structure 60(2) along the direction parallel to the first surface 101 should not be too small or too large. If the distance d2 is too small, it is easy to cause a short circuit between the first interconnect structure 60(1) and the first pad layer 70(1); if the distance d2 is too large, it is easy to cause problems such as the metal interconnect line 50 being too long and having too high resistance. Therefore, in this embodiment, the distance d2 between the first interconnect structure 60(1) and the second interconnect structure 60(2) along the direction parallel to the first surface 101 is 10 μm to 50 μm.

[0062] In this embodiment, the interconnect structure 60 further includes: a third interconnect structure 60 (3), located within the pixel substrate 100 of the second lead area 100N2, and spaced apart from the second interconnect structure 60 (2); the third interconnect structure 60 (3) is electrically connected to the logic device.

[0063] The third interconnect structure 60(3) is electrically connected to the logic device and is used to bring out the electrical properties of the logic device so as to realize the electrical connection between the logic device and the external circuit.

[0064] Along the direction parallel to the first surface 101, the distance d3 between the second interconnect structure 60(2) and the third interconnect structure 60(3) should not be too small or too large. If the distance d3 is too small, it will easily lead to the distance between the first pad layer 70(1) and the second pad layer 70(2) being too small, which will affect subsequent packaging and testing; if the distance d3 is too large, it will easily occupy too much chip area. Therefore, in this embodiment, along the direction parallel to the first surface 101, the distance d3 between the second interconnect structure 60(2) and the third interconnect structure 60(3) is 30μm to 100μm.

[0065] In practice, the third distance d3 also depends on the spacing between the solder pads, which in turn depends on the requirements of the packaging process.

[0066] The metal grid 210 is in contact with the conductive layer 140 to achieve an electrical connection between the conductive layer 140 and the connecting layer 220.

[0067] In this embodiment, the metal grid 210 is located on the second surface 103 and is in contact with the conductive layer 140 in the isolation structure 160. That is, the metal grid 210 is located on the back side of the pixel substrate 100, and the metal grid 210 is a backside metal grid (BMG).

[0068] The metal grid 210 is a grid structure used to separate pixels, which is equivalent to selecting the specific pixel to enter for each incident photon.

[0069] The metal grid 210 has a mesh structure, and the line width of the metal grid 210 is generally small. The process of forming the metal grid 210 includes a patterning process. In order to facilitate the patterning process of the metal grid 210 and form a metal grid 210 with a small line width and high dimensional accuracy, the thickness of the metal grid 210 is generally small in the direction perpendicular to the surface of the pixel substrate 100.

[0070] The metal grid 210 is made of a metallic material, such as one or both of aluminum and tungsten. The metal grid can also be other metals that can be etched.

[0071] The connecting layer 220 is in contact with the metal grid 210 and the first interconnect structure 60 (1), and the metal grid 210 is in contact with the conductive layer 140. Thus, through the sequentially connected metal grid 210, connecting layer 220, first interconnect structure 60 (1) and second interconnect structure 60 (2), the conductive layer 140 in the isolation structure 160 is connected to the first pad layer 70 (1). Accordingly, a voltage can be applied to the isolation structure 160 through the metal grid 210 to reduce the dark count of the photoelectric sensor.

[0072] Specifically, the isolation structure 160 is located within the isolation trench. During the formation of the photoelectric sensor, the isolation trench is typically formed by an etching process. During this etching process, etching defects are usually generated on the sidewalls and bottom wall of the isolation trench. Consequently, after the isolation structure 160 is formed, defects are prone to occur at the interface between the isolation structure 160 and the pixel substrate 100.

[0073] In this embodiment, by applying a suitable voltage to the isolation structure 160, more holes accumulate at the interface between the isolation structure 160 and the pixel substrate 100. When the photoelectric device (e.g., SPAD) in the photosensitive unit 110 is working, it helps to increase the distance between the depletion region of the photoelectric device and the interface between the isolation structure 160 and the pixel substrate 100, thereby reducing the contribution of defects at the interface to the dark count, which in turn helps to reduce the dark count of the photoelectric sensor and improve the performance of the photoelectric sensor.

[0074] In this embodiment, the connecting layer 220 and the metal grid 210 are formed in the same step, which helps to simplify the process flow and improve process integration. The connecting layer 220 and the metal grid 210 have the same thickness.

[0075] Accordingly, in this embodiment, the connecting layer 220 and the metal grid 210 are an integral structure, which is beneficial to improving the electrical connection performance of the connecting layer 220 and the metal grid 210 and reducing their resistance. Therefore, the connecting layer 220 and the metal grid 210 are made of the same material.

[0076] The pad layer 70 is used to realize the electrical connection between the photoelectric sensor and the external circuit or other device structure. The pad layer 70 is also used to provide a process basis for forming the electrical connection structure (e.g., wire bonding).

[0077] The pad layer 70 is made of a conductive material. Specifically, the pad layer 70 is made of a metal, including one or more of aluminum, titanium, gold, and ITO (Indium Tin Oxide). In this embodiment, the pad layer 70 is made of aluminum. Aluminum is an readily available metal, which helps to save costs. Moreover, aluminum is an easily etchable metal, making it easy to pattern to form the pad layer 70.

[0078] The first pad layer 70 (1) is in contact with the end of the second interconnect structure 60 (2) facing the second surface 102, thereby the conductive layer 140 in the isolation structure 160 is connected to the first pad layer 70 (1) through the sequentially connected metal grid 210, connecting layer 220, first interconnect structure 60 (1) and second interconnect structure 60 (2).

[0079] Furthermore, the first pad layer 70(1) and the metal grid are formed in different steps. The first pad layer 70(1) is formed using a pad layer process that can utilize a lead area of ​​100N, so that the first pad layer 70(1) has a larger thickness and a higher height consistency with other pad layers 70 in the lead area. This helps to reduce the process risks caused by inconsistent heights of the pad layers 70 and the excessive thinness of the first pad layer 70(1), thereby reducing the difficulty of the packaging and testing process and improving the performance of the photoelectric sensor.

[0080] In this embodiment, there are multiple solder pads 70; the solder pads 70 further include: a second solder pad 70 (2), which is located in the second lead area 100N2 and is in contact with the end of the third interconnect structure 60 (3) facing the second surface 102.

[0081] The second solder pad layer 70(2) is electrically connected to the third interconnect structure 60(3) to realize the electrical connection between the logic device and the external circuit or other device structure. The second solder pad layer 70(2) is spaced apart from the first solder pad layer 70(1).

[0082] In this embodiment, the photoelectric sensor further includes a passivation layer 230 located on the second surface 102 of the pixel substrate 100. The passivation layer 230 covers the connection layer 220 and the metal grid 210, and is also located between the pad layers 70. The top surface of the passivation layer 230 located in the second lead area 100N2 is higher than the top surface of the passivation layer 230 located in the first lead area 100N1 and the photosensitive area 100P.

[0083] The passivation layer 230 serves to protect the metal grid 210 and the connection layer 220.

[0084] In this embodiment, the passivation layer 230 also exposes the pad layer 70 in order to provide a process basis for forming an electrical connection structure in contact with the pad layer 70.

[0085] The top surface of the passivation layer 230 located in the second lead region 100N2 is higher than the top surface of the passivation layer 230 located in the first lead region 100N1 and the photosensitive region 100P. As a result, the dielectric material in the photosensitive region 100P and the first lead region 100N1 is thinner, which is beneficial to make the optical path in the pixel shorter, the light detection efficiency higher, and the performance of the photoelectric sensor improved accordingly.

[0086] As an example, the passivation layer 230 is a stacked structure, comprising: a first dielectric layer 170 located on the second surface 102 and below the pad layer 70, the connection layer 220, and the metal grid 210; a second dielectric layer 180 located on the first dielectric layer 170 of the second lead region 100N2, the second dielectric layer 180 being located between the pad layers 70; and a top dielectric layer 195 located on the second dielectric layer 180 and the first dielectric layer 170 of the first lead region 100N1 and the photosensitive region 100P, covering the metal grid 210 and the connection layer 220.

[0087] The first dielectric layer 170 and the second dielectric layer 180 constitute the bottom dielectric layer 190.

[0088] In this embodiment, the materials of the first dielectric layer 170, the second dielectric layer 180, and the top dielectric layer 195 include one or both of silicon oxide and silicon nitride.

[0089] Accordingly, the present invention also provides a method for forming a photoelectric sensor. Figures 3 to 10 This is a cross-sectional structural diagram of each step in one embodiment of the method for forming the photoelectric sensor of the present invention.

[0090] As an example, this embodiment uses a TOF (Time of Flight) sensor as the photoelectric sensor for illustration. More specifically, the photoelectric sensor can be a DTOF (Direct Time of Flight) sensor. In other embodiments, the photoelectric sensor can also be an iTOF (Indirect Time of Flight) sensor.

[0091] In other embodiments, the photoelectric sensor may also be other types of photoelectric sensors such as CCD (Charge Coupled Device) image sensors and CMOS image sensors.

[0092] The method for forming the photoelectric sensor in this embodiment will be described in detail below with reference to the accompanying drawings.

[0093] refer to Figure 3A pixel substrate 100 is provided, including a first surface 101 and a second surface 102 opposite to each other. The pixel substrate 100 includes a photosensitive area 100P and a lead area 100N surrounding the photosensitive area 100P. A plurality of photosensitive units 110 are formed in the pixel substrate 100P. The lead area 100N includes a first lead area 100N1 and a second lead area 100N2 surrounding the first lead area 100N1.

[0094] The pixel substrate 100 is used to provide an operating platform for subsequent process technology.

[0095] The pixel substrate 100 includes a photosensitive area 100P, within which a plurality of photosensitive units 110 are formed. The photosensitive units 110 are used to receive optical signals so as to convert the optical signals into electrical signals. Specifically, the photosensitive area 100P is a pixel area, and the photosensitive units 110 are pixel units.

[0096] As one embodiment, the photosensitive unit 110 includes an optoelectronic device 115. Specifically, a single-photon avalanche diode (SPAD) 115. In other embodiments, the photosensitive unit may also include other types of optoelectronic devices.

[0097] The lead area 100N is used for wiring and forming leads to realize the electrical connection between the photosensitive unit 110 or other device structures and the external circuit.

[0098] In this embodiment, the first lead area 100N1 surrounds the photosensitive area 100P, and the second lead area 100N2 surrounds the first lead area 100N1.

[0099] In this embodiment, the first surface 101 of the pixel substrate 100 is the front side, and the second surface 102 is the back side. Specifically, the pixel substrate 100 is a backside illumination (BSI) pixel wafer, and the second surface 102 of the pixel substrate 100 is the light-receiving surface.

[0100] In this embodiment, a metal interconnect 50 is also formed in the pixel substrate 100 near the first surface 101. Subsequently, a first interconnect structure is formed in the pixel substrate 100 of the first lead region 100N1, and a second interconnect structure is formed in the pixel substrate 100 of the second lead region 100N2. The metal interconnect 50 is used to realize the electrical connection between the first interconnect structure and the second interconnect structure.

[0101] In this embodiment, in the step of providing the pixel substrate 100, along the direction from the first surface 101 to the second surface 102, the pixel substrate 100 includes a rear pixel interconnect layer 30 and a front pixel device layer 40 stacked sequentially.

[0102] The rear pixel interconnect layer 30 contains multiple interconnect layers for electrical connections between device structures. The front pixel device layer 40 contains photosensitive units 110.

[0103] In this embodiment, the metal interconnect 50 is located in the back pixel interconnect layer 30.

[0104] refer to Figure 4 In this embodiment, the method for forming the photoelectric sensor further includes: after providing the pixel substrate 100, providing a logic substrate 200, the logic substrate 200 including a bonding surface 201; and forming logic devices (not shown) within the logic substrate 200.

[0105] The second substrate 200 serves as a logic wafer, used to analyze and process the electrical signals provided by the pixel substrate 100. Specifically, logic devices are formed within the second substrate 200, which are used to analyze and process the electrical signals provided by the pixel substrate 100.

[0106] The bonding surface 201 is used to achieve bonding with the pixel substrate 100.

[0107] In this embodiment, the logic substrate 200 includes a front-end logic device layer (not shown) and a back-end logic interconnect layer (not shown) located on the front-end logic device layer; the bonding surface 201 is the side of the back-end logic interconnect layer opposite to the front-end logic device layer.

[0108] The logic devices are formed in the front-end logic device layer. The back-end logic interconnect layer has multiple interconnect layers for electrical connections between the logic devices and external circuits or other device structures.

[0109] Continue to refer to Figure 4 This enables bonding between the bonding surface 201 of the logic substrate 200 and the first surface 101 of the pixel substrate 100.

[0110] By setting the pixel area (i.e., the photosensitive area) and the logic area on different substrates, and bonding the pixel substrate 100 and the logic substrate 200 together, it is beneficial to increase the pixel area, shorten the path of light to the photoelectric element, reduce light scattering, and make the light more focused, thereby improving the photoelectric sensor's light-sensing ability in low-light environments and reducing system noise and crosstalk.

[0111] As one embodiment, the bonding surface 201 of the logic substrate 200 and the first surface 101 of the pixel substrate 100 are bonded by a hybrid bonding method.

[0112] It should be noted that the above-described method for bonding between the pixel substrate 100 and the logic substrate 200 is only an example, and the bonding method between the pixel substrate 100 and the logic substrate 200 is not limited to this. For example, in other embodiments, the bonding method between the pixel substrate and the logic substrate can also be direct bonding (e.g., fusion bonding and anodic bonding) or indirect bonding (e.g., metal eutectic bonding, hot-press bonding, and adhesive bonding), etc.

[0113] It should also be noted that, in this embodiment, the method for forming the photoelectric sensor further includes: after bonding the bonding surface 201 of the logic substrate 200 with the first surface 101 of the pixel substrate 100, the second surface 102 of the pixel substrate 100 is thinned.

[0114] The second surface 102 of the pixel substrate 100 is thinned to reduce the thickness of the pixel substrate 100, thereby reducing the overall thickness of the photoelectric sensor.

[0115] As an example, the process of thinning the second surface 102 of the pixel substrate 100 includes a grinding process, a wet etching process, and a chemical mechanical planarization (CMP) process performed sequentially.

[0116] refer to Figure 5 An isolation structure 160 is formed within the pixel substrate 100 between the photosensitive units 110, and the end of the isolation structure 160 is exposed on the second surface 102. The isolation structure 160 includes a conductive layer 140.

[0117] The isolation structure 160 is used to reduce optical and electrical crosstalk between adjacent photosensitive units 110.

[0118] In this embodiment, the isolation structure 160 is a deep trench isolation (DTI) structure.

[0119] In this embodiment, the isolation structure 160 includes a conductive layer 140 so that a voltage can be applied to the conductive layer 140 to accumulate holes at the interface between the isolation structure 150 and the pixel substrate 100, which helps to reduce the dark count of the photoelectric sensor.

[0120] The end of the conductive layer 140 is exposed on the second surface 102 so that a metal grid that contacts the conductive layer 140 can be formed on the second surface 102, thereby allowing the electrical properties of the conductive layer 140 to be led out through the metal grid.

[0121] In this embodiment, the conductive layer 140 is made of a metallic material. The conductive layer 140 may be made of one or more of tungsten, titanium, titanium nitride, tantalum nitride, and copper. In this embodiment, the conductive layer 140 is made of tungsten. Compared to other metallic materials, tungsten is less prone to diffusion and has excellent hole-filling ability. Therefore, tungsten is more suitable for use in the deep trenches of photoelectric sensors. Furthermore, tungsten is an opaque metallic material, which can effectively block light, thus making the reduction of optical crosstalk between adjacent photosensitive units 110 by the isolation structure 160 more significant.

[0122] In this embodiment, the isolation structure 160 includes a conductive layer 140 and an insulating layer 150 located between the conductive layer 140 and the pixel substrate 100. The insulating layer 150 is used to achieve insulation between the conductive layer 140 and the pixel substrate 100.

[0123] In this embodiment, the material of the insulating layer 150 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, and tantalum oxide.

[0124] In this embodiment, the step of forming the isolation structure 160 includes: forming an isolation trench (not shown) in the pixel substrate 100 between adjacent photosensitive units 110; forming an insulating layer 150 on the sidewalls and bottom of the isolation trench, and a conductive layer 140 on the insulating layer 150 and filling the isolation trench.

[0125] Continue to refer to Figure 5 Multiple interconnect structures 60 are formed, distributed within the pixel substrate 100 and with their ends exposed on the second surface 102. The interconnect structure 60 includes a first interconnect structure 60(1) located in the first lead region 100N1 and a second interconnect structure 60(2) located in the second lead region 100N2, and the second interconnect structure 60(2) is electrically connected to the first interconnect structure 60(1).

[0126] The interconnect structure 60 is used to realize the electrical connection between the film layer structure within the pixel substrate 100 and the external circuit. In this embodiment, the interconnect structure 60 penetrates the front pixel device layer 130 and is also located in the rear pixel interconnect layer 120, which has a certain thickness.

[0127] In this embodiment, the interconnect structure 60 is a through-silicon via (TSV) interconnect structure. The TSV interconnect structure enables circuit conduction in the vertical direction, maximizes the density of three-dimensional stacking, reduces the horizontal area of ​​the chip, and has the characteristics of short connection distance and high strength, which is beneficial for the thinning and miniaturization of devices, as well as reducing power consumption and improving operating speed.

[0128] In this embodiment, the interconnect structure 60 is made of a conductive material, such as one or more of copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN).

[0129] The second interconnect structure 60(2) is electrically connected to the first interconnect structure 60(1) to realize the electrical connection between the subsequently formed connection layer and the first pad layer located in the second lead area 100N2.

[0130] Specifically, the subsequently formed first solder pad layer contacts the end of the second interconnect structure 60(2) facing the second surface 102. It should be noted that there are one or more second interconnect structures 60(2) corresponding to the first solder pad layer. When there are multiple second interconnect structures 60(2) corresponding to the first solder pad layer, the first solder pad layer can contact multiple second interconnect structures 60(2) simultaneously to achieve electrical connection with the first interconnect structure 60(1), the connection layer, the metal grid, and the isolation structure 160, which helps to reduce the resistance of the second interconnect structure 60(2) and improve the electrical connection efficiency between the first solder pad layer and the isolation structure 160.

[0131] In this embodiment, both the first interconnect structure 60(1) and the second interconnect structure 60(2) are in contact with the metal interconnect line 50, and the first interconnect structure 60(1) and the second interconnect structure 60(2) are electrically connected through the metal interconnect line 50.

[0132] It should be noted that the distance d1 between the first interconnect structure 60(1) and the isolation structure 160 along the direction parallel to the first surface 101 should not be too small or too large. If the distance d1 is too small, it will easily increase the process difficulty of TSV and DTI fabrication and compress the safe process window; if the distance d1 is too large, it will not only waste chip area, but also easily lead to the problem of excessively long interconnect layer 220 and excessive resistance of interconnect layer 220. Therefore, in this embodiment, the distance d1 between the first interconnect structure 60(1) and the isolation structure 160 along the direction parallel to the first surface 101 is 10μm to 50μm.

[0133] It should also be noted that the distance d2 between the first interconnect structure 60(1) and the second interconnect structure 60(2) along the direction parallel to the first surface 101 should not be too small or too large. If the distance d2 is too small, it is easy to cause a short circuit between the first interconnect structure 60(1) and the first pad layer 70(1); if the distance d2 is too large, it is easy to cause problems such as the metal interconnect line 50 being too long and having too high resistance. Therefore, in this embodiment, the distance d2 between the first interconnect structure 60(1) and the second interconnect structure 60(2) along the direction parallel to the first surface 101 is 10 μm to 50 μm.

[0134] In this embodiment, the interconnect structure 60 further includes a third interconnect structure 60(3) located within the pixel substrate 100 of the second lead area 100N2, and is spaced apart from the second interconnect structure 60(2); the third interconnect structure 60(3) is electrically connected to the logic device.

[0135] The third interconnect structure 60(3) is electrically connected to the logic device and is used to bring out the electrical properties of the logic device so as to realize the electrical connection between the logic device and the external circuit.

[0136] In this embodiment, in the step of forming the third interconnect structure 60(3), the first interconnect structure 60(1) and the second interconnect structure 60(2) are formed. Thus, the first interconnect structure 60(1) and the second interconnect structure 60(2) can be formed using the process of forming the third interconnect structure 60(3) without introducing additional process steps, reducing the modification of the existing process flow, which is beneficial to reducing process risk, simplifying the process flow, improving process integration, and saving process costs.

[0137] Along the direction parallel to the first surface 101, the distance d3 between the second interconnect structure 60(2) and the third interconnect structure 60(3) should not be too small or too large. If the distance d3 is too small, it will easily lead to the distance between the first pad layer 70(1) and the second pad layer 70(2) being too small, which will affect subsequent packaging and testing; if the distance d3 is too large, it will easily occupy too much chip area. Therefore, in this embodiment, along the direction parallel to the first surface 101, the distance d3 between the second interconnect structure 60(2) and the third interconnect structure 60(3) is 30μm to 100μm.

[0138] In practice, the third distance d3 also depends on the spacing between the solder pads, which in turn depends on the requirements of the packaging process.

[0139] In this embodiment, the step of forming the interconnect structure 60 includes: forming a plurality of interconnect vias (not shown) in the pixel substrate 100; and filling the interconnect structure 60 in the interconnect vias.

[0140] Accordingly, in the process of forming interconnect vias, only the pattern of the photomask for forming interconnect vias needs to be modified, so that the interconnect vias can include the first interconnect vias and the second interconnect vias corresponding to the first interconnect structure and the second interconnect structure. This makes it possible to form the first interconnect structure and the second interconnect structure without using an additional photomask, which helps to reduce process costs.

[0141] It should be noted that, in this embodiment, after forming the interconnect vias and before filling the interconnect vias with interconnect structures, the method for forming the photoelectric sensor further includes: forming an isolation layer (not shown) on the bottom and sidewalls of the interconnect vias. The isolation layer is used to achieve insulation between the interconnect structure 60 and the pixel substrate 100. As an example, the material of the isolation layer is silicon oxide, tantalum, or tantalum nitride.

[0142] refer to Figure 6 A pad layer 70 is formed on the second surface 102 of the lead region 100N, including a first pad layer 70(1) located in the second lead region 100N2, the first pad layer 70(1) being in contact with the end of the second interconnect structure 60(2) facing the second surface 102.

[0143] The pad layer 70 is used to realize the electrical connection between the photoelectric sensor and the external circuit or other device structure. The pad layer 70 is also used to provide a process basis for the subsequent formation of electrical connection structure (e.g., wire bonding).

[0144] The pad layer 70 is made of a conductive material. Specifically, the pad layer 70 is made of a metal, including one or more of aluminum, titanium, gold, and ITO (Indium Tin Oxide). In this embodiment, the pad layer 70 is made of aluminum. Aluminum is an readily available metal, which helps to save costs. Moreover, aluminum is an easily etchable metal, making it easy to pattern to form the pad layer 70.

[0145] The first pad layer 70 (1) is in contact with the end of the second interconnect structure 60 (2) facing the second surface 102, thereby forming a metal grid on the conductive layer of the second surface 102 and a connection layer on the second surface 102 that is in contact with the metal grid and the first interconnect structure 60 (1). The metal grid is in contact with the conductive layer 140, and the connection layer is electrically connected to the metal grid and the first interconnect structure 60 (1). Thus, the conductive layer 140 in the isolation structure 160 is connected to the first pad layer 70 (1) through the sequentially connected metal grid, connection layer, first interconnect structure 60 (1) and second interconnect structure 60 (2).

[0146] Furthermore, the first pad layer 70(1) and the metal grid are formed in different steps. The first pad layer 70(1) can be formed using a pad layer process that can utilize a lead area of ​​100N, so that the first pad layer 70(1) has a larger thickness and a higher height consistency with other pad layers 70 in the lead area. This helps to reduce the process risks caused by inconsistent heights of the pad layer 70 and the excessive thinness of the first pad layer 70(1), thereby reducing the difficulty of subsequent packaging and testing processes and improving the performance of the photoelectric sensor.

[0147] In this embodiment, in the step of forming the solder pad layer 70, the number of solder pad layers 70 is multiple; the solder pad layer 70 further includes a second solder pad layer 70(2) located in the second lead area 100N2, and the second solder pad layer 70(2) is in contact with the end of the third interconnect structure 60(3) facing the second surface 102.

[0148] The second solder pad layer 70(2) is electrically connected to the third interconnect structure 60(3) to realize the electrical connection between the logic device and the external circuit or other device structure. The second solder pad layer 70(2) is spaced apart from the first solder pad layer 70(1).

[0149] In this embodiment, the step of forming the pad layer 70 includes: forming a first dielectric layer 170 on the second surface 102 of the pixel substrate 100, covering the interconnect structure and the isolation structure 160; forming a groove in the first dielectric layer 170, including a first groove exposing the second interconnect structure 60 (2) and a second groove exposing the third interconnect structure 60 (3); forming a pad material layer (not shown) on the first dielectric layer 170 and in the groove; patterning the pad material layer, retaining the pad material layer located in the first groove as the first pad layer 70 (1), and retaining the pad material layer located in the second groove as the second pad layer 70 (2).

[0150] In this embodiment, during the formation of the pad layer 70, only the pattern of the photomask forming the groove and the pattern of the pad material layer needs to be modified to form the first pad layer in contact with the second interconnect structure. There is no need to use additional process steps and additional photomasks to form the first pad layer 70 (1). The changes to the existing process flow are small, which is conducive to simplifying the process flow, improving process integration and compatibility, and also helps to save process costs.

[0151] refer to Figure 6 In the step of forming the pad layer 70, a first dielectric layer 170 is also formed on the second surface 102 of the pixel substrate 100, covering the isolation structure 160 and the first interconnect structure 60 (1).

[0152] The first dielectric layer 170 is used to protect the isolation structure 160 and the first interconnect structure 60(1) during the formation of the pad layer 70.

[0153] In this embodiment, the material of the first dielectric layer 170 is one or both of silicon oxide and silicon nitride.

[0154] refer to Figure 7 The method for forming the photoelectric sensor further includes: after forming the pad layer 70, forming a second dielectric layer 180 on the first dielectric layer 170 to cover the pad layer 70, wherein the second dielectric layer 180 and the first dielectric layer 170 constitute a bottom dielectric layer 190.

[0155] The second dielectric layer 180 serves to protect the pad layer 70 during the subsequent formation of the connection layer and metal grid.

[0156] In this embodiment, the material of the second dielectric layer 180 is one or both of silicon oxide and silicon nitride.

[0157] refer to Figure 8 In the same step, a metal grid 210 is formed on the conductive layer 140 of the second surface 102, and a connection layer 220 is formed on the second surface 102 and in contact with the metal grid 210 and the first interconnect structure 60 (1). The metal grid 210 is in contact with the conductive layer 140, and the connection layer 220 is electrically connected to the metal grid 210 and the first interconnect structure 60 (1).

[0158] The connecting layer 220 is in contact with the metal grid 210 and the first interconnect structure 60 (1), and the metal grid 210 is in contact with the conductive layer 140. Thus, through the sequentially connected metal grid 210, connecting layer 220, first interconnect structure 60 (1) and second interconnect structure 60 (2), the conductive layer 140 in the isolation structure 160 is connected to the first pad layer 70 (1). Accordingly, a voltage can be applied to the isolation structure 160 through the metal grid 210 to reduce the dark count of the photoelectric sensor.

[0159] Specifically, in the formation process of the photoelectric sensor, the formation step of the isolation structure 160 includes: forming an isolation trench within the pixel substrate 100 between the photosensitive units 110; and forming the isolation structure 160 within the isolation trench. The isolation trench is typically formed by an etching process, during which etching defects are usually generated on the sidewalls and bottom wall of the isolation trench. Consequently, after the isolation structure 160 is formed, defects are easily generated at the interface between the isolation structure 160 and the pixel substrate 100.

[0160] In this embodiment, by applying a suitable voltage to the isolation structure 160, more holes accumulate at the interface between the isolation structure 160 and the pixel substrate 100. When the photoelectric device (e.g., SPAD) in the photosensitive unit 110 is working, it helps to increase the distance between the depletion region of the photoelectric device and the interface between the isolation structure 160 and the pixel substrate 100, thereby reducing the contribution of defects at the interface to the dark count, which in turn helps to reduce the dark count of the photoelectric sensor and improve the performance of the photoelectric sensor.

[0161] In this embodiment, the connecting layer 220 and the metal grid 210 are formed in the same step, which helps to simplify the process flow and improve process integration. The connecting layer 220 and the metal grid 210 have the same thickness.

[0162] In this embodiment, the metal grid 210 is located on the second surface 103 and is in contact with the conductive layer 140 in the isolation structure 160. That is, the metal grid 210 is located on the back side of the pixel substrate 100, and the metal grid 210 is a backside metal grid (BMG).

[0163] The metal grid 210 is a grid structure used to separate pixels, which is equivalent to selecting the specific pixel to enter for each incident photon.

[0164] The metal grid 210 has a mesh-like structure, and its linewidth is typically small. The process of forming the metal grid 210 includes a patterning process. To facilitate this process and achieve a smaller linewidth and higher dimensional accuracy, the metal grid 210 is typically thinner in the direction perpendicular to the pixel substrate 100 surface. The connecting layer 220 and the metal grid 210 are formed in the same step, and the connecting layer 220 is also typically thin.

[0165] In this embodiment, the first pad layer 70(1) and the metal grid 210 are formed in different steps. The first pad layer 70(1) can be formed using the pad layer 70 process of the lead area 100N, so that the first pad layer 70(1) has a large thickness and the height of the first pad layer 70 is highly consistent with the other pad layers 70 of the lead area 100N. This helps to reduce the process risks caused by the uneven height of the pad layer 70 and the excessive thinness of the first pad layer 70(1), thereby reducing the difficulty of subsequent packaging and testing processes and improving the performance of the photoelectric sensor.

[0166] Therefore, in this embodiment, the metal grid 210 and the connecting layer 220 are made of the same material. The materials of the metal grid 210 and the connecting layer 220 are metallic materials, such as one or both of aluminum and tungsten. The metal grid can also be other etchable metals.

[0167] The steps for forming the metal grid 210 and the connecting layer 220 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0168] like Figure 8 As shown, a portion of the dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1 is removed to expose the first interconnect structure 60(1) and the isolation structure 160.

[0169] Specifically, removing a portion of the thickness of the dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1 to expose the first interconnect structure 60(1) and the isolation structure 160 includes: performing a first etching process on the dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1; and after the first etching process, performing a second etching process on the dielectric layer 190 above the first interconnect structure 60(1) and the isolation structure 160 to expose the first interconnect structure 60(1) and the isolation structure 160.

[0170] In this process, a first etching process is performed to etch the entire dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1 downwards, thereby thinning the dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1, resulting in a shorter optical path and higher light detection efficiency within the pixel. In a specific implementation, the first etching process can almost completely etch away the entire thickness of the dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1, thereby further thinning the dielectric layer 190 and further shortening the optical path.

[0171] A second etching process is performed to open the area above the first interconnect structure 60(1) and the isolation structure 160 to expose the first interconnect structure 60(1) and the isolation structure 160 so that the subsequently formed connection layer can be connected to the metal grid, the connection layer can contact the first interconnect structure 60(1), and the metal grid can contact the conductive layer 140 of the isolation structure 160.

[0172] like Figure 8 As shown, after removing a portion of the dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1, a metal grid 210 is formed on the isolation structure 160 and in contact with the conductive layer 140, and a connection layer 220 is formed on the first interconnect structure 60 (1) and connected to the metal grid 210.

[0173] Specifically, a metal material layer is formed on the photosensitive area 100P and the first lead area 100N1, and the metal material layer is in contact with the first interconnect structure 60(1) and the conductive layer 140; the metal material layer is patterned to form a metal grid 210 on the isolation structure 160 and a connection layer 220 on the first interconnect structure 60(1) and connected to the metal grid 210.

[0174] In this embodiment, during the steps of forming the metal grid 210 and the connecting layer 220, a portion of the thickness of the bottom dielectric layer 190 of the photosensitive area 100P and the first lead area 100N1 is removed. Therefore, after forming the metal grid 210 and the connecting layer 220, the top surface of the bottom dielectric layer 190 of the second lead area 100N2 is higher than the top surface of the bottom dielectric layer 190 of the first lead area 100N1 and the photosensitive area 100P.

[0175] In this embodiment, the connection layer 220 and the metal grid 210 are an integral structure, which is beneficial to improving the electrical connection performance of the connection layer 220 and the metal grid 210 and reducing the resistance of the connection layer 220 and the metal grid 210.

[0176] refer to Figure 9In this embodiment, after forming the metal grid 210 and the connection layer 220, the method for forming the photoelectric sensor further includes: forming a passivation layer 230 covering the metal grid 210, the connection layer 220, and the pad layer 70.

[0177] The passivation layer 230 serves to protect the metal grid 210 and the connection layer 220.

[0178] Specifically, a top dielectric layer 195 is formed on the bottom dielectric layer 190. The top dielectric layer 195 covers the second dielectric layer 180 located in the second lead region 100N2, the metal grid 210 and the connecting layer 220, and the first dielectric layer 170 located in the first lead region 100N1 and the photosensitive region 100P. The top dielectric layer 195 and the bottom dielectric layer 190 are used to form the passivation layer 230.

[0179] The material of the top dielectric layer 195 includes one or both of silicon oxide and silicon nitride.

[0180] refer to Figure 10 The passivation layer 230 located on the solder pad layer 70 is removed, exposing the solder pad layer 70. The exposed solder pad layer 70 is used to facilitate the subsequent formation of electrical connection structures (e.g., wire bonding) on ​​the solder pad layer 70.

[0181] Specifically, the top dielectric layer 195 and the second dielectric layer 180 located on the first solder pad layer 70(1) and the second solder pad layer 70(2) are removed in order to expose the first solder pad layer 70(1) and the second solder pad layer 70(2).

[0182] In this embodiment, during the removal of the passivation layer 230 located on the pad layer 70, the first pad layer 70 (1) is exposed so that voltage can be applied to the metal grid 210 and the isolation structure 160 through the first pad layer 70 (1) in the future, thereby reducing the dark count of the photoelectric sensor and improving the performance of the photoelectric sensor. Furthermore, the first pad layer 70 (1) can be exposed by using the process of removing the passivation layer 230 located on the pad layer 70, so that no additional process or additional photomask is required. The changes to the existing process flow are small, which helps to simplify the process, improve the process integration, and save process costs.

[0183] Accordingly, embodiments of the present invention also provide an electronic device, including the photoelectric sensor provided in embodiments of the present invention.

[0184] The electronic device in this embodiment can be any electronic product or device with photoelectric sensing function, such as a mobile phone, tablet computer, laptop computer, navigator, camera, camcorder, robot vacuum cleaner, virtual reality device, augmented reality device, etc., or any intermediate product including the aforementioned photoelectric sensor.

[0185] As can be seen from the foregoing description, the photoelectric sensor provided in this embodiment has excellent performance. By using the photoelectric sensor provided in this embodiment, it is beneficial to improve the performance of electronic devices and enhance the user experience.

[0186] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A photoelectric sensor, characterized in that, The photoelectric sensor includes a photosensitive area and a lead area surrounding the photosensitive area, the lead area including a first lead area and a second lead area surrounding the first lead area; The photoelectric sensor includes: A pixel substrate includes opposing first and second surfaces; a plurality of photosensitive units are formed within the pixel substrate of the photosensitive area. An isolation structure is located within a pixel substrate between the photosensitive units and exposed on a second surface of the pixel substrate, the isolation structure including a conductive layer; Multiple interconnect structures are distributed within the pixel substrate and have their ends exposed on the second surface. The interconnect structures include a first interconnect structure located in the first lead area and a second interconnect structure located in the second lead area. The second interconnect structure is electrically connected to the first interconnect structure. A metal grid is located on and in contact with the conductive layer of the second surface; A connection layer is located on the second surface of the first lead area and is in contact with the metal grid and the first interconnect structure, the connection layer being electrically connected to the metal grid and the first interconnect structure; A solder pad layer is located on the second surface of the lead area, and the thickness of the solder pad layer is greater than the thickness of the interconnect layer and the metal grid; the solder pad layer includes a first solder pad layer located in the second lead area, which is in contact with the end of the second interconnect structure facing the second surface.

2. The photoelectric sensor as described in claim 1, characterized in that, The second surface of the pixel substrate is a light-receiving surface; the photoelectric sensor further includes: a logic substrate, including a bonding surface; the bonding surface of the logic substrate is bonded to the first surface of the pixel substrate; logic devices are formed within the logic substrate; The interconnect structure further includes: a third interconnect structure located within the pixel substrate of the second lead area and spaced apart from the second interconnect structure; the third interconnect structure is electrically connected to the logic device; The number of the solder pads is multiple; the solder pads further include: a second solder pad, located in the second lead area and in contact with the end of the third interconnect structure facing the second surface.

3. The photoelectric sensor as described in claim 1, characterized in that, The isolation structure includes a conductive layer and an insulating layer located between the conductive layer and the pixel substrate.

4. The photoelectric sensor as described in claim 3, characterized in that, The conductive layer is made of one or more of tungsten, titanium, titanium nitride, tantalum nitride, and copper; the insulating layer is made of one or more of silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, and tantalum oxide.

5. The photoelectric sensor as described in claim 1, characterized in that, The photoelectric sensor further includes: a passivation layer located on the second surface of the pixel substrate, the passivation layer covering the connection layer and the metal grid, and also located between the pad layers; wherein the top surface of the passivation layer located in the second lead area is higher than the top surface of the passivation layer located in the first lead area and the photosensitive area.

6. The photoelectric sensor as described in claim 1, characterized in that, The pixel substrate further includes: a metal interconnect line located on the side of the pixel substrate close to the first surface and in contact with the end of the first interconnect structure facing the first surface and the end of the second interconnect structure facing the first surface, wherein the metal interconnect line is electrically connected to the first interconnect structure and the second interconnect structure.

7. The photoelectric sensor as described in claim 6, characterized in that, Along the direction from the first surface to the second surface, the pixel substrate includes a rear pixel interconnect layer and a front pixel device layer stacked sequentially; the interconnect structure penetrates the front pixel device layer and is also located in the rear pixel interconnect layer of a certain thickness, and the metal interconnect line is located in the rear pixel interconnect layer.

8. The photoelectric sensor as described in claim 1, characterized in that, Along a direction parallel to the first surface, the distance between the first interconnect structure and the isolation structure is 10 μm to 50 μm; Along a direction parallel to the first surface, the distance between the first interconnect structure and the second interconnect structure is 10 μm to 50 μm.

9. The photoelectric sensor as described in claim 2, characterized in that, Along a direction parallel to the first surface, the distance between the second interconnect structure and the third interconnect structure is 30 μm to 100 μm.

10. The photoelectric sensor as described in claim 1, characterized in that, The interconnect structure is a through-silicon via (TSV) interconnect structure.

11. The photoelectric sensor as described in claim 1, characterized in that, The number of second interconnect structures connected to each of the first solder pad layers is one or more.

12. The photoelectric sensor as described in claim 1, characterized in that, The connecting layer has the same thickness as the metal grid.

13. The photoelectric sensor as described in claim 1, characterized in that, The connecting layer and the metal grid are an integral structure.

14. The photoelectric sensor as described in claim 1, characterized in that, The materials of the interconnect structure include one or more of copper, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride; The material of the metal grid includes one or both of aluminum and tungsten; The material of the connecting layer includes one or both of aluminum and tungsten; The material of the pad layer includes one or more of aluminum, titanium, gold, and tin-doped indium oxide.

15. A method for forming a photoelectric sensor, characterized in that, include: A pixel substrate is provided, including a first surface and a second surface opposite to each other. The pixel substrate includes a photosensitive area and a lead area surrounding the photosensitive area. A plurality of photosensitive units are formed within the pixel substrate of the photosensitive area. The lead area includes a first lead area and a second lead area surrounding the first lead area. An isolation structure is formed within a pixel substrate between the photosensitive units, with the ends of the isolation structure exposed on the second surface, and the isolation structure includes a conductive layer; Multiple interconnect structures are formed, distributed within the pixel substrate and with their ends exposed on the second surface. The interconnect structures include a first interconnect structure located in the first lead area and a second interconnect structure located in the second lead area, and the second interconnect structure is electrically connected to the first interconnect structure. A solder pad layer is formed on the second surface of the lead area, including a first solder pad layer located in the second lead area, the first solder pad layer being in contact with the end of the second interconnect structure facing the second surface; In the same step, a metal grid is formed on the conductive layer of the second surface, and a connection layer is formed on the second surface and in contact with the metal grid and the first interconnect structure. The metal grid is in contact with the conductive layer, and the connection layer is electrically connected to the metal grid and the first interconnect structure.

16. The method for forming a photoelectric sensor as described in claim 15, characterized in that, The second surface of the pixel substrate is a light-receiving surface; the method for forming the photoelectric sensor further includes: after providing the pixel substrate and before forming the isolation structure, providing a logic substrate, the logic substrate including a bonding surface; and forming logic devices within the logic substrate. Achieving bonding between the bonding surface of the logical substrate and the first surface of the pixel substrate; In the step of forming the interconnect structure, the interconnect structure further includes a third interconnect structure located within the pixel substrate of the second lead region, and spaced apart from the second interconnect structure; the third interconnect structure is electrically connected to the logic device. In the step of forming the solder pad layer, the number of solder pad layers is multiple; the solder pad layer further includes a second solder pad layer located in the second lead area, and the second solder pad layer is in contact with the end of the third interconnect structure facing the second surface.

17. The method for forming a photoelectric sensor as described in claim 15, characterized in that, In the step of forming the pad layer, a first dielectric layer is also formed on the second surface of the pixel substrate, covering the isolation structure and the first interconnect structure; the method of forming the photoelectric sensor further includes: after forming the pad layer, forming a second dielectric layer on the first dielectric layer to cover the pad layer, wherein the second dielectric layer and the first dielectric layer constitute a bottom dielectric layer; The steps of forming the metal grid and the interconnect layer include: removing a portion of the thickness of the bottom dielectric layer of the photosensitive area and the first lead area to expose the first interconnect structure and the isolation structure; forming a metal grid located on the isolation structure and in contact with the conductive layer, and an interconnect layer located on the first interconnect structure and connected to the metal grid.

18. The method for forming a photoelectric sensor as described in claim 15, characterized in that, After forming the metal grid and the connection layer, the method for forming the photoelectric sensor further includes: forming a passivation layer covering the metal grid, the connection layer, and the pad layer; Remove the passivation layer located on the solder pad layer to expose the solder pad layer.

19. The method for forming a photoelectric sensor as described in claim 15, characterized in that, In the step of providing the pixel substrate, a metal interconnect is also formed in the pixel substrate near the side of the first surface; During the formation of the interconnect structure, both the first interconnect structure and the second interconnect structure are in contact with the metal interconnect line, and the first interconnect structure and the second interconnect structure are electrically connected through the metal interconnect line.

20. The method for forming a photoelectric sensor as described in claim 19, characterized in that, In the step of providing a pixel substrate, along the direction from the first surface to the second surface, the pixel substrate includes a rear pixel interconnect layer and a front pixel device layer stacked sequentially; the metal interconnect line is located in the rear pixel interconnect layer; In the step of forming the interconnect structure, the interconnect structure extends through the front pixel device layer and is also located in the rear pixel interconnect layer of a certain thickness.

21. The method for forming a photoelectric sensor as described in claim 15, characterized in that, In the step of forming the interconnect structure, the interconnect structure is a through-silicon via (TSV) interconnect structure.

22. An electronic device, characterized in that, include: The photoelectric sensor as described in any one of claims 1 to 14.

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