Non-real-time systems implementing hard real-time in hardware-in-the-loop simulation: systems and computers

Abstract

The application belongs to the technical field of software development for vehicles, and particularly relates to a system for realizing hard real-time of a non-real-time system in hardware-in-the-loop simulation and a computer, wherein the system for realizing hard real-time of the non-real-time system in hardware-in-the-loop simulation comprises: a computer device configured to execute a task creation module and a task thread setting module; wherein the task creation module is configured to create a real-time model task and form a task program; the task thread setting module is configured to make the task program automatically read computer configuration and judge the number Z of processor cores of the current computer device, when the number Z of processor cores does not exceed X, set the number n of threads as 1 to execute the real-time model task, otherwise set the number n of threads as (Z-X) / Y to execute the real-time model task, wherein Y represents the number of threads of one physical core of the processor.

Description

Technical Field

[0001] This invention belongs to the field of automotive software development technology, specifically relating to a system and computer for realizing hard real-time in a non-real-time system in hardware-in-the-loop simulation. Background Technology

[0002] To perform hardware-in-the-loop simulation tasks, it is often necessary to rely on a real-time system and deploy the task execution on the real-time system. The real-time system is located on another computer, not locally, and any action needs to be completed remotely. This causes problems such as the inability to directly observe the key signals that determine the function and performance of the algorithm. Summary of the Invention

[0003] The purpose of this invention is to provide a system and computer device for realizing hard real-time in a non-real-time system in hardware-in-the-loop simulation.

[0004] To address the aforementioned technical problems, this invention provides a system for implementing hard real-time in a non-real-time system during hardware-in-the-loop simulation, comprising: a computer device configured to execute a task creation module and a task thread setting module; wherein...

[0005] The task creation module is configured to create real-time model tasks and form task programs;

[0006] The task thread setting module is configured to enable the task program to automatically read the computer configuration and determine the number of processor cores Z of the current computer device. When the number of cores Z does not exceed X, the number of threads n = 1 is set to execute the real-time model task; otherwise, the number of threads is set to n = (ZX) / Y to execute the real-time model task.

[0007] Y represents the number of threads in one physical core of the processor.

[0008] In another aspect, the present invention also provides a computer device for implementing a hard real-time system in a non-real-time system during hardware-in-the-loop simulation, comprising a processor configured to execute the task creation module and the task thread setting module.

[0009] The beneficial effects of this invention are that it enables the execution of hardware-in-the-loop simulation tasks by directly running a virtual hard real-time environment on a personal computer to achieve hard real-time performance, i.e., without the need to purchase a real-time system, and since all operations are performed locally, it greatly improves development and testing efficiency.

[0010] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0011] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0012] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 The diagram illustrates the steps of a method for implementing hard real-time in a non-real-time system during hardware-in-the-loop simulation, as described in some embodiments.

[0014] Figure 2 The diagram illustrates the principle block diagram of a system that implements hard real-time in a non-real-time system in hardware-in-the-loop simulation according to some embodiments.

[0015] Figure 3 Block diagrams of electronic devices involved in some embodiments are shown. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Currently, similar software typically achieves hard real-time simulation through a real-time system when performing hardware-in-the-loop simulation tasks. This requires increased hardware investment and deployment costs. However, some embodiments involve methods for achieving hard real-time simulation in a non-real-time system without adding a real-time system, and hard real-time simulation can be achieved in a non-real-time system.

[0018] Specifically, some embodiments provide a method for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation, including: creating a real-time model task and forming a task program; the task program automatically reads the computer configuration and determines the number of processor cores Z of the current computer device; when the number of cores Z does not exceed X, the number of threads n = 1 is set to execute the real-time model task; otherwise, the number of threads is set to n = (ZX) / Y to execute the real-time model task, where Y represents the number of threads of one physical core of the processor.

[0019] Some embodiments of the method for achieving hard real-time simulation in a non-real-time system within a hardware-in-the-loop simulation enable the execution of hardware-in-the-loop simulation tasks in a virtual hard real-time environment directly on a personal computer. This eliminates the need to purchase a real-time system, and because all operations are performed locally, it significantly improves development and testing efficiency, and increases the flexibility of observing and modifying simulated signals. For example, if one wants to observe a specific local variable, the local program code can be modified at any time to add functions such as printing information, observation information, and curve plotting signal information. Once compiled locally, it can be run immediately, resulting in high efficiency. In contrast, the traditional approach requires designing input and output interfaces for this local variable, updating the simulation model interface table, compiling the entire code program, redeploying the real-time system software, and then remotely running the simulation model before observation.

[0020] The various non-limiting embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0021] like Figure 1 As shown, some embodiments provide a method for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation, including:

[0022] Step S101: Create a real-time model task and form a task program;

[0023] Step S102: The task program automatically reads the computer configuration and determines the number of processor cores Z of the current computer device. If the number of cores Z does not exceed X, the number of threads n = 1 is set to execute the real-time model task; otherwise, the number of threads is set to n = (ZX) / Y to execute the real-time model task.

[0024] Y represents the number of threads in one physical core of the processor.

[0025] Specifically, a real-time model task is a timed program. It is created by first creating a timer, then setting the timer period, such as 500 microseconds, and then calling the model's step function at regular intervals according to this period. The resulting task program is a code module used for real-time model task simulation.

[0026] The number of processor cores Z is determined by the processor model. Different processor models have completely different numbers of cores Z. For example, the Intel Xeon Platinum 9282 has 56 cores Z, while the Intel Core i5-2520M has 2 cores Z.

[0027] When Z does not exceed X, it indicates that the current computer performance is weak and it is not suitable to use multiple threads to execute the simulation. Otherwise, it will cause the local computer to freeze. In this case, it is suitable to execute the real-time model task with a single thread, that is, set the number of threads n=1 to execute the real-time model task.

[0028] When Z exceeds X, in order to prevent multi-threaded simulation execution under weak computer performance, it is necessary to limit the minimum value of X, that is, to limit the minimum value of the number of computer cores Z for multi-threaded simulation tasks. In the extreme case X=0, the number of threads n=Z / Y is exactly equal to the number of real physical cores. When X is non-zero, it means that X / Y real physical cores are reserved as proprietary cores. These proprietary cores do not participate in the simulation, thus ensuring the smooth operation of the software system and other software.

[0029] As one implementation of some embodiments, setting the number of threads to n=1 to execute real-time model tasks includes:

[0030] Define the real-time interval m for the execution of the real-time model task;

[0031] The thread obtains the current time t in real time and determines in real time whether the current time t is greater than the next execution time t_next.

[0032] When t > t_next, then t_next = t_next + m, and the real-time model task is executed simultaneously.

[0033] It should be noted that when the real-time model task is executed for the first time, t_next = m, t = 0.

[0034] Specifically, let's explain in detail, with examples, how to execute real-time model tasks when n=1:

[0035] With X=4, when the computer device's processor model is Intel Core i5-2520M, the number of cores Z=2, which is less than 4. This indicates that the current computer performance is weak and it is not suitable to use multiple threads to execute the simulation. Otherwise, it will cause the computer to freeze. In this case, it is suitable to execute the real-time model task with a single thread, that is, set the number of threads n=1 to execute the real-time model task.

[0036] Since only one thread executes the real-time model task, the operation of determining whether the current time t is greater than the next execution time t_next does not involve multi-threaded preemption. Therefore, there is no need to use critical sections or other means for thread synchronization, which can reduce the performance overhead caused by introducing critical sections. However, the inherent defects of single-threaded operation are also apparent. When the processor time slice of this thread is preempted due to operating system scheduling, the locking precision of the time t_next will decrease.

[0037] When executing a real-time model task in a single thread, the real-time time interval for the task is set to m = 500 microseconds. The pseudocode for this thread executing the real-time model task is as follows:

[0038]

[0039]

[0040] Among them, "is_running" is the simulation running enable flag. When the simulation is terminated by the user or exits naturally, this flag is false and the algorithm will no longer execute the while loop; "get_current_time_stamp_us()" is an internal function of the simulation system used to obtain the current time stamp in microseconds.

[0041] "run_model_task()" is an internal function of the simulation system used to periodically call the model's step function; "other_task()" is another task of the Windows system, in which Sleep(1) can be executed to reduce the current processor's consumption of processor time.

[0042] As another implementation of some embodiments, when the number of threads is n = (ZX) / Y, and the number of cores Z exceeds X, it indicates that the processor of the current computer device is suitable for enabling multi-threaded simulation. The method for executing real-time model tasks includes:

[0043] Define the real-time interval m for the execution of the real-time model task;

[0044] Each thread simultaneously obtains its current time t in real time and determines in real time whether the current time t is greater than the next execution time t_next;

[0045] When at least one thread detects that t > t_next, that thread attempts to enter the critical section. At this time, other threads are blocked from entering the critical section. Once the thread successfully enters the critical section, the flag indicating that t > t_next is invalidated. Therefore, the thread that successfully entered the critical section will execute the following content within the critical section:

[0046] Repeatedly retrieve the current time t and determine if the current time t is greater than the next execution time t_next:

[0047] If so, then t_next = t_next + m, and simultaneously execute the real-time model task and exit the critical section;

[0048] If not, the thread will exit the critical section directly.

[0049] Specifically, let's explain in detail, with examples, how to perform real-time model tasks when n = (ZX) / Y:

[0050] Given X=2 and Y=2, when the computer device's processor is an Intel Core i7-8700, the number of cores Z=6, which is greater than 2. Therefore, the number of threads n=(ZX) / Y=(6-2) / 2=2 to execute the real-time model task.

[0051] Define two threads, thread 0 and thread 1.

[0052] If the real-time time interval for executing the real-time model task is defined as m = 500 microseconds, then the pseudocode for each thread executing the model task is as follows:

[0053]

[0054] Among them, "is_running" is the simulation running enable flag. When the simulation is terminated by the user or exits naturally, this flag is false and the algorithm will no longer execute the while loop; "get_current_time_stamp_us()" is an internal function of the simulation system used to obtain the current time stamp in microseconds.

[0055] "EnterCriticalSection" is a Windows system API function that is used to enter a critical section.

[0056] "FSection" is a critical section object shared by multiple threads; "LeaveCriticalSection" is a Windows API function that exits the critical section; "run_model_task()" is an internal function of the simulation system used to periodically call the model's step function; "other_task()" is another task of the Windows system, in which Sleep(1) can be executed to reduce the current processor's time consumption.

[0057] The above pseudocode effectively alleviates the situation where simulation time accuracy decreases due to a single thread being deprived of processor time by system scheduling. In other words, the above method effectively ensures simulation time accuracy, thereby guaranteeing simulation real-time performance.

[0058] Threads that fail to enter the critical section are blocked from entering the critical section until the thread that entered the critical section leaves the critical section, at which point the next attempt will begin.

[0059] Taking the aforementioned method of executing real-time model tasks with n=2 threads as an example, when thread 0 fails to determine the next execution time t_next in time due to system scheduling, thread 1 has a high probability of determining the next execution time t_next. Upon recognizing t > t_next, it successfully enters the critical section and prioritizes the execution of the model task. At this point, thread 0 will be blocked in the code line entering the critical section. Only after thread 1 completes the real-time model task and exits the critical section will thread 0 begin determining whether the current time t is greater than the next execution time t_next. If thread 0 successfully enters the critical section at this point, it will update the current time t again (i.e., repeatedly obtain the current time t) and determine that the current time t is already less than the next execution time t_next (which has already been updated by thread 1). In this case, thread 0 will not execute the real-time model task but will immediately exit the critical section, waiting for the next determination.

[0060] The number of threads that successfully enter the critical section is determined by the critical section itself. In other words, the number of threads that successfully enter the critical section is randomly determined by the Windows system.

[0061] `t_next` is a shared global variable across all threads. This means multiple threads can access the same variable simultaneously. The fact that each thread can share access to the same variable ensures that if any thread detects that the current time `t` is greater than the next execution time `t_next`, it can immediately attempt to enter the critical section. This effectively mitigates the situation where a single thread is deprived of processor time due to system scheduling, thus preventing a decrease in simulation time accuracy and effectively guaranteeing simulation time precision.

[0062] Each thread occupies one physical core of the processor, including:

[0063] The physical core index of the processor occupied by each thread is equal to the value obtained by performing a modulo operation between the corresponding thread number index and the total number of physical cores of the processor.

[0064] Each thread can occupy one physical core of the processor to achieve the best performance of the computer device.

[0065] For example, if there are 10 threads and the total number of physical cores of the processor is 8, then the physical core index of the processor occupied by thread 0 is equal to the value obtained by performing a modulo operation between 0 and 8, which is 0; the physical core index of the processor occupied by thread 9 is equal to the value obtained by performing a modulo operation between 9 and 8, which is 1.

[0066] The method disclosed herein for achieving hard real-time in a non-real-time system during hardware-in-the-loop simulation enables the execution of hardware-in-the-loop simulation tasks by directly running a virtual hard real-time environment on a personal computer, thus achieving hard real-time performance without the need to purchase a real-time system. Furthermore, since all operations are performed locally, it greatly improves development and testing efficiency and increases the flexibility of observing and modifying simulation signals.

[0067] like Figure 2 As shown, some embodiments also provide a system for implementing hard real-time in a non-real-time system during hardware-in-the-loop simulation, including a computer device configured to execute a task creation module and a task thread setting module; wherein

[0068] The task creation module is configured to create real-time model tasks and form task programs;

[0069] The task thread setting module is configured to enable the task program to automatically read the computer configuration and determine the number of processor cores Z of the current computer device. When the number of cores Z does not exceed X, the number of threads n = 1 is set to execute the real-time model task; otherwise, the number of threads is set to n = (ZX) / Y to execute the real-time model task.

[0070] Y represents the number of threads in one physical core of the processor.

[0071] In some embodiments, the functions performed by the task creation module and the task thread setting module are implemented in a computer device. For details, please refer to the specific description of the method for implementing hard real-time in a non-real-time system in the aforementioned hardware-in-the-loop simulation, which will not be repeated here.

[0072] The electronic devices in some embodiments are described below from the perspective of hardware processing:

[0073] Some embodiments disclosed herein do not limit the specific implementation of the electronic device.

[0074] like Figure 3 As shown, this electronic device includes: a processor, a readable storage medium, a communication bus, and a communication interface; wherein the processor, the readable storage medium, and the communication interface communicate with each other through the communication bus; the readable storage medium is used to store a program for executing the method of implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation as described in this embodiment, the program causing the processor to execute the operation corresponding to the method of implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation.

[0075] In other embodiments, computer devices and industrial control computers can also be used as a type of electronic device.

[0076] Figure 3The structure shown does not constitute a limitation on the electronic device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0077] In some embodiments, the communication interface may be RS232, RS485, USB, or TYPE, and can be connected to an external bus adapter. It may also include a wired or wireless network interface, which may optionally include a wired interface and / or a wireless interface (such as a Wi-Fi interface, Bluetooth interface, etc.), typically used to establish communication connections between the computer device and other electronic devices.

[0078] The readable storage medium or computer-readable storage medium includes at least one type of memory, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, it can be an internal storage unit of a computer device, such as the hard disk of the computer device. In other embodiments, the memory can also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computer device. Furthermore, the memory can include both internal storage units and external storage devices of the computer device. The memory can be used not only to store application software and various types of data installed on the computer device, such as computer program code, but also to temporarily store data that has been output or will be output.

[0079] In some embodiments, a processor may be a processor, controller, microcontroller, microprocessor, or other data processing chip for running program code stored in memory or processing data, such as executing computer programs.

[0080] In some embodiments, the communication bus can also be an input / output bus, which may be a Peripheral Component Interconnect (PCI) bus or an Enhanced Industry Standard Architecture (EISA) bus, etc. This bus can be divided into address bus, data bus, control bus, etc.

[0081] Optionally, the computer device may also include a user interface, which may include a display, an input unit such as a keyboard, and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the computer device and to display a visual user interface.

[0082] When the processor executes the program, it implements the above. Figure 1 The steps in the embodiment of the method for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation shown are as follows: Figure 1 The steps S101 to S102 are shown. Alternatively, the processor executes the computer program to implement the functions of each module or unit in the above-described device embodiments.

[0083] In some embodiments, the processor is specifically configured to implement the following steps:

[0084] Create real-time model tasks and form task programs;

[0085] The task program automatically reads the computer configuration and determines the number of processor cores Z of the current computer device. If the number of cores Z does not exceed X, the number of threads n = 1 is set to execute the real-time model task; otherwise, the number of threads is set to n = (ZX) / Y to execute the real-time model task.

[0086] Y represents the number of threads in one physical core of the processor.

[0087] Optionally, as one possible implementation, the processor can also be used to implement the following steps:

[0088] Setting the number of threads to n=1 to execute real-time model tasks includes:

[0089] Define the real-time interval m for the execution of the real-time model task;

[0090] The thread obtains the current time t in real time and determines in real time whether the current time t is greater than the next execution time t_next.

[0091] When t > t_next, then t_next = t_next + m, and the real-time model task is executed simultaneously.

[0092] Optionally, as one possible implementation, the processor can also be used to implement the following steps:

[0093] When the real-time model task is executed for the first time, t_next = m, t = 0.

[0094] Optionally, as one possible implementation, the processor can also be used to implement the following steps:

[0095] Setting the number of threads to n = (ZX) / Y to execute real-time model tasks includes:

[0096] Define the real-time interval m for the execution of the real-time model task;

[0097] Each thread simultaneously obtains its current time t in real time and determines in real time whether the current time t is greater than the next execution time t_next;

[0098] When at least one thread detects that t > t_next, that thread attempts to enter the critical section. A thread that successfully enters the critical section will execute the following within the critical section:

[0099] Repeatedly retrieve the current time t and determine if the current time t is greater than the next execution time t_next:

[0100] If so, then t_next = t_next + m, and simultaneously execute the real-time model task and exit the critical section;

[0101] If not, the thread will exit the critical section directly.

[0102] Optionally, as one possible implementation, the processor can also be used to implement the following steps:

[0103] Threads that fail to enter the critical section are blocked from entering the critical section until the thread that entered the critical section leaves the critical section, at which point the next attempt will begin.

[0104] Optionally, as one possible implementation, the processor can also be used to implement the following steps:

[0105] The number of threads that successfully enter the critical section is determined by the critical section itself.

[0106] Optionally, as one possible implementation, the processor can also be used to implement the following steps:

[0107] t_next is a shared global variable for all threads.

[0108] Optionally, as one possible implementation, the processor can also be used to implement the following steps:

[0109] Each thread occupies one physical core of the processor, including:

[0110] The physical core index of the processor occupied by each thread is equal to the value obtained by performing a modulo operation between the corresponding thread number index and the total number of physical cores of the processor.

[0111] Some embodiments also provide a computer-readable storage medium configured to store a program for executing the method for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation as described in the preceding embodiments. When executed by a processor, the program can implement the specific steps of the method for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation. Please refer to the detailed description of the method for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation, which will not be repeated here.

[0112] Some embodiments also provide a computer program product, including a computer program or instructions, wherein when the computer program or instructions are executed on a computer, the computer is able to perform any of the above-described methods for implementing hard real-time systems in a non-real-time system in a hardware-in-the-loop simulation.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0114] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0115] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0116] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A system for implementing hard real-time operation in a non-real-time system during hardware-in-the-loop simulation, characterized in that, Includes a computer device configured to execute a task creation module and a task thread setting module; in The task creation module is configured to create real-time model tasks and form task programs; The task thread setting module is configured to automatically read the computer configuration and determine the number of processor cores Z of the current computer device. When the number of cores Z does not exceed X, the number of threads n=1 is set to execute the real-time model task; otherwise, Z is set to be greater than X, and X is not equal to 0, and the number of threads is set to n=(ZX) / Y to execute the real-time model task. Y represents the number of threads in one physical core of the processor; Setting the number of threads to n = (ZX) / Y to execute real-time model tasks includes: Define the real-time interval m for the execution of the real-time model task; Each thread simultaneously obtains its current time t in real time and determines in real time whether the current time t is greater than the next execution time t_next; When at least one thread detects that t > t_next, that thread attempts to enter the critical section. A thread that successfully enters the critical section will execute the following within the critical section: Repeatedly retrieve the current time t and determine if the current time t is greater than the next execution time t_next: If so, then t_next = t_next + m, and simultaneously execute the real-time model task and exit the critical section; If not, the thread will exit the critical section directly. Each thread occupies one physical core of the processor.

2. The system for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation according to claim 1, characterized in that, Setting the number of threads to n=1 to execute real-time model tasks includes: Define the real-time interval m for the execution of the real-time model task; The thread obtains the current time t in real time and determines in real time whether the current time t is greater than the next execution time t_next. When t > t_next, then t_next = t_next + m, and the real-time model task is executed simultaneously.

3. The system for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation according to claim 2, characterized in that, When the real-time model task is executed for the first time, t_next=m, t=0.

4. The system for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation according to claim 1, characterized in that, Threads that fail to enter the critical section are blocked from entering the critical section until the thread that entered the critical section leaves the critical section, at which point the next attempt will begin.

5. The system for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation according to claim 4, characterized in that, The number of threads that successfully enter the critical section is determined by the critical section itself.

6. The system for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation according to claim 1, characterized in that, t_next is a shared global variable for all threads.

7. The system for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation according to claim 1, characterized in that, Each thread occupies one physical core of the processor, including: The physical core index of the processor occupied by each thread is equal to the value obtained by performing a modulo operation between the corresponding thread number index and the total number of physical cores of the processor.

8. A computer device, characterized in that, A system for implementing hard real-time in a non-real-time system in hardware-in-the-loop simulation as described in any one of claims 1-7, comprising a processor configured to execute the task creation module and the task thread setting module.

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