Pixel driving circuit, display panel and device

Abstract

The present invention discloses a pixel driving circuit, a display panel, and a device, relating to the field of display technology. The first end of a pixel capacitor in the pixel driving circuit is connected to a gating unit, and the second end of the pixel capacitor is connected to a voltage offset unit and a common voltage line. When the gating unit is in an on state, it provides a data voltage to the first end; the common voltage line provides a common voltage to the second end. When the gating signal received by the gating unit changes from an on signal to an off signal, the voltage offset unit pulls the common voltage input to the second end down to a first preset voltage. Due to a coupling effect, the data voltage at the first end is pulled down to a second preset voltage, and the second preset voltage offsets at least a portion of the first preset voltage. The present invention is advantageous in preventing abnormal display phenomena.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit, a display panel and a device. Background Art

[0002] When the display panel is displaying, the pixel driving circuit in the display panel will input the conduction voltage through the GATE line to turn on the switch tube that charges the pixel. The SOUT line will give the output voltage to the first end of the pixel capacitor through the turned-on switch tube. At the same time, the common voltage of the common voltage end is directly input to the second end of the pixel capacitor, so that the pixel capacitor is charged according to the output voltage and the common voltage, thereby changing the deflection degree of the liquid crystal.

[0003] However, in the process of realizing the charging display of the above-mentioned pixels, it was found that the voltage output by the GATE line changed from the on-voltage to the off-voltage. During the pixel display process, the output voltage output to the switching tube would be pulled down by the voltage drop voltage caused by the electric field coupling, resulting in the abnormal display phenomenon of shaking head wrinkles. Summary of the Invention

[0004] The main purpose of the present invention is to provide a pixel driving circuit, a display panel and a device, aiming to solve the technical problem of display abnormality caused by voltage drop generated by electric field coupling.

[0005] To achieve the above object, the present invention provides a pixel driving circuit, which includes:

[0006] a pixel capacitor, wherein a first end of the pixel capacitor is connected to the gating unit, and a second end of the pixel capacitor is connected to the voltage offset unit and the common voltage line; the gating unit provides a data voltage to the first end when in a conductive state; and the common voltage line provides a common voltage to the second end;

[0007] When the selection signal connected to the selection unit changes from a turn-on signal to a turn-off signal, the voltage offset unit pulls down the common voltage input to the second end by a first preset voltage, and the data voltage of the first end is pulled down by a second preset voltage due to a coupling effect, and the second preset voltage offsets at least part of the first preset voltage.

[0008] Optionally, the pixel driving circuit further includes:

[0009] a plurality of gate voltage lines and a plurality of data lines, wherein the plurality of gate voltage lines extend in a row direction and are arranged in a column direction, and the plurality of data lines extend in a column direction and are arranged in a row direction;

[0010] A plurality of the gate voltage lines intersect with a plurality of the data lines to form a pixel area array;

[0011] Each pixel area in the pixel area array is provided with the pixel capacitor, the gating unit and the voltage compensation unit;

[0012] A plurality of common voltage lines extend along a row direction and are arranged in a column direction, and each common voltage line is connected to the pixel capacitors in the same row.

[0013] Optionally, the gating unit includes a thin film transistor;

[0014] The input end of the thin film transistor is connected to the data line, the control end of the thin film transistor is connected to the gate voltage line, and the output end of the thin film transistor is connected to the first end of the pixel capacitor.

[0015] Optionally, the voltage offset unit includes a first coupling capacitor;

[0016] One end of the first coupling capacitor is connected to the gate voltage line in the same pixel area, and the other end of the first coupling capacitor is connected to the common voltage line in the same pixel area.

[0017] Optionally, one of the gate voltage lines and one of the common voltage lines corresponding to the same row of pixel areas constitutes a signal line pair; a charging switch tube is provided between each pair of the signal lines, a control terminal of the charging switch tube is connected to the gate voltage line, input terminals of the plurality of charging switch tubes are connected to the same common voltage terminal, and an output terminal of each charging switch tube is connected to one of the common voltage lines;

[0018] The charging switch tube is used to access the common voltage input from the common voltage terminal when accessing the conduction signal input from the selection voltage line, and transmit the common voltage to each pixel capacitor arranged on the same signal line pair as the charging switch tube through the common voltage line.

[0019] Optionally, a second coupling capacitor is formed between the gate of the charging switch tube and the drain of the charging switch tube due to coupling effect, and a third coupling capacitor is formed between the gate of the thin film transistor and the drain of the thin film transistor due to coupling effect, and the total capacitance of the first coupling capacitor and the second coupling capacitor is the same as the capacitance of the third coupling capacitor.

[0020] Optionally, several common voltage lines are connected to different common voltage terminals.

[0021] Optionally, a third coupling capacitor is formed between the gate electrode of the thin film transistor and the drain electrode of the thin film transistor due to a coupling effect, and the capacitance of the third coupling capacitor is the same as the capacitance of the first coupling capacitor.

[0022] In addition, to achieve the above-mentioned purpose, the present invention further provides a display panel, which includes an array substrate provided with the above-mentioned pixel driving circuit.

[0023] The present invention further provides a display device comprising the display panel and a backlight module as described above, wherein the display panel is arranged on the light-emitting side of the backlight module.

[0024] The present invention designs a pixel driving circuit, which includes a pixel capacitor, wherein a first end of the pixel capacitor is connected to a gate unit, and a second end of the pixel capacitor is connected to a voltage compensation unit and a common voltage line. A coupling capacitor with the same specifications as the coupling capacitor on the gate unit is provided on the voltage compensation unit. Like the coupling capacitor on the gate unit, the coupling capacitor has one end connected to the gate voltage line and the other end connected to the common voltage line and the input end of the pixel capacitor. When the gate unit is in an on state, a data voltage is provided to the first end of the pixel capacitor, and the common voltage line provides a common voltage to the second end of the pixel capacitor. When the gate signal received by the gate unit changes from an on signal to an off signal, the voltage compensation unit pulls down the common voltage input to the second end by a first preset voltage. The data voltage at the first end is pulled down by a second preset voltage due to a coupling effect. The second preset voltage offsets at least a portion of the first preset voltage, so that the voltage at one end of the pixel capacitor during display is equal to the voltage at the other end of the pixel capacitor during charging, thereby avoiding the abnormal display phenomenon of shaking head stripes caused by the coupling capacitor on the switching tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the pixel architecture used in conventional TFT-LCDs;

[0026] Figure 2 Schematic diagram of the charging display waveform of an ideal pixel;

[0027] Figure 3 This is a schematic diagram of the actual pixel charging display waveform;

[0028] Figure 4 Schematic diagram of a module of a pixel driving circuit of the present invention;

[0029] Figure 5 Schematic diagram of the structure of the pixel driving circuit of the present invention in the first implementation scenario;

[0030] Figure 6 A schematic diagram of charging display waveforms that can be achieved by the pixel driving circuit of the present invention;

[0031] Figure 7 FIG. 4 is a schematic diagram of the architecture of the pixel driving circuit of the present invention in a second implementation scenario.

[0032] Description of Figure Numbers:

[0033]

[0034]

[0035] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0036] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0037] Reference Figure 1 and Figure 2 , the technical issues raised by the background technology are explained in detail.

[0038] Figure 1 This is the pixel architecture used by conventional TFT-LCD. Figure 2 For the ideal pixel charging display waveform, the charging display principle of the pixel capacitor is explained based on the pixel architecture and charging display waveform: the GATE line inputs a high voltage to the TFT, making the TFT conductive, and the input end of the conductive TFT is connected to the positive output voltage input by the SOUT line to the output end of the TFT, and then to one end of the pixel capacitor through the output end of the TFT. At the same time, the other end of the pixel capacitor is connected to the common voltage input by the VCOM line. The pixel capacitor is charged based on the positive output voltage and the common voltage. When charged to the appropriate positive frame voltage Vsout, the GATE line will reduce the output voltage and convert the high voltage into a low voltage. The voltage turns off the TFT, and the pixel capacitor maintains the liquid crystal deflection for one frame time according to the positive frame voltage Vsout. The GATE line then converts the low voltage into a high voltage, and the SOUT line transmits the negative output voltage to the pixel through the turned-on TFT to one end of the pixel capacitor. At the same time, the other end of the pixel capacitor is still connected to the common voltage transmitted by the VCOM line. The pixel capacitor is charged based on the negative output voltage and the common voltage. When charged to the appropriate negative frame voltage Vsout', the GATE line reduces the output voltage, converting the high voltage into a low voltage to turn off the TFT, and the pixel capacitor maintains the liquid crystal deflection for one frame time according to the negative frame voltage Vsout'.

[0039] However, in the actual pixel charging display process, there is an electric field coupling between the control terminal and the output terminal of the TFT. This electric field coupling will cause fluctuations in the voltage output to one end of the pixel capacitor. Figure 3It can be seen that no matter it is a positive output voltage or a negative output voltage, during the transition process of the GATE line from a high voltage to a low voltage, it will be pulled down by the voltage drop voltage VP generated by the electric field coupling, so that the positive frame voltage Vsout and the negative frame voltage Vsout' during display are lower than the voltage during charging, causing the pixels to be dark when displaying based on the positive frame voltage Vsout, and to be bright when displaying based on the negative frame voltage Vsout', resulting in an abnormal display phenomenon of shaking head wrinkles.

[0040] Reference Figure 4 , Figure 4 : is a module schematic diagram of a pixel driving circuit of the present invention, wherein the pixel driving circuit comprises:

[0041] a pixel capacitor pixel C, wherein a first end of the pixel capacitor pixel C is connected to a gating unit, and a second end of the pixel capacitor pixel C is connected to a voltage compensation unit and a common voltage line VCOM; the gating unit provides a data voltage to the first end when in an on state; and the common voltage line VCOM provides a common voltage to the second end;

[0042] When the selection signal connected to the selection unit changes from a turn-on signal to a turn-off signal, the voltage offset unit pulls down the common voltage input to the second end by a first preset voltage, and the data voltage of the first end is pulled down by a second preset voltage due to a coupling effect, and the second preset voltage offsets at least part of the first preset voltage.

[0043] For example Figure 3 The pixel architecture shown has a situation where the voltage at one end of the pixel capacitor pixel C changes due to the coupling capacitance on the TFT. This embodiment proposes a pixel driving circuit, which includes a pixel capacitor pixel C for displaying an image, a selection unit for controlling the charging of the pixel capacitor pixel C, and a voltage compensation unit for compensating for a second preset voltage generated by the coupling capacitance on the selection unit.

[0044] Specifically, a first preset voltage that is substantially the same as a second preset voltage generated by the coupling capacitor on the selection unit is generated by the voltage offset unit. The first preset voltage is used to pull down the common voltage for charging the second end of the pixel capacitor pixel C. Based on the voltage calculation formula that the voltage of the pixel capacitor pixel C is equal to the output voltage minus the common voltage, when the output voltage and the common voltage used to charge the pixel capacitor pixel C are both pulled down to the same preset voltage, the voltage change of the pixel capacitor pixel C caused by the first preset voltage is offset by the second preset voltage, so that the voltage of the pixel voltage during display and the voltage during charging remain unchanged, thereby avoiding the abnormal display phenomenon of shaking head patterns caused by the coupling capacitor on the switching tube.

[0045] Specifically, refer to Figure 5 As shown, the pixel driving circuit further includes:

[0046] a plurality of gate voltage lines GATE and a plurality of data lines SOUT, wherein the plurality of gate voltage lines GATE extend in a row direction and are arranged in a column direction, and the plurality of data lines SOUT extend in a column direction and are arranged in a row direction;

[0047] A plurality of the gate voltage lines GATE and a plurality of the data lines SOUT intersect to form a pixel area array;

[0048] Each pixel area in the pixel area array is provided with the pixel capacitor pixel C, the gating unit and the voltage compensation unit;

[0049] A plurality of common voltage lines VCOM extend along a row direction and are arranged in a column direction, and each common voltage line VCOM is connected to the pixel capacitor pixel C in the same row.

[0050] by Figure 5 As an example, the architecture of the pixel driving circuit in this example is composed of a gate voltage line GATE, a common voltage line VCOM and a data line SOUT. The gate voltage line GATE and the common voltage line VCOM extend one-to-one in the row direction and are arranged in the column direction. The data line SOUT intersects with the gate voltage line GATE and the common voltage line VCOM along the column direction to form a pixel area array composed of several pixel areas, and a pixel capacitor pixel C, a gate unit and a voltage compensation unit are set in each pixel area to achieve corresponding adjustment of the voltage change of the pixel capacitor pixel C in each pixel area.

[0051] Among them, gate is a selection signal terminal for outputting a selection signal, vcom is a common voltage terminal for outputting a common voltage, and sout is an output voltage terminal for outputting a voltage.

[0052] Furthermore, the gating unit includes a thin film transistor Q1;

[0053] The input end of the thin film transistor Q1 is connected to the data line SOUT, the control end of the thin film transistor Q1 is connected to the gate voltage line GATE, and the output end of the thin film transistor Q1 is connected to the first end of the pixel capacitor pixel C.

[0054] The gating unit in this example includes a thin film transistor Q1 for controlling the charging state of a pixel capacitor pixel C arranged in the same pixel area. The input end of the thin film transistor Q1 is connected to the data line SOUT constituting the pixel area, and is used to access the output voltage transmitted on the data line SOUT when turned on. The control end of the thin film transistor Q1 is connected to the gating voltage line GATE constituting the pixel area, and is used to access the gating signal transmitted on the gating voltage line GATE. The output end of the thin film transistor Q1 is connected to one end of the pixel capacitor pixel C arranged in the pixel area, and is used to transmit the output voltage accessed when turned on to the pixel capacitor pixel C, so as to charge the pixel capacitor pixel C, thereby realizing dynamic control of the charging state of the pixel capacitor pixel C.

[0055] Furthermore, the voltage offset unit includes a first coupling capacitor C1;

[0056] One end of the first coupling capacitor C1 is connected to the gate voltage line GATE in the same pixel area, and the other end of the first coupling capacitor C1 is connected to the common voltage line VCOM in the same pixel area.

[0057] A control-to-output capacitor is provided between the output terminal and the control terminal of each thin-film transistor Q1. In this example, where the output terminal is the drain and the control terminal is the gate, a gate-to-drain capacitor, i.e., a third coupling capacitor C3, is provided between the gate and drain of each thin-film transistor Q1. As described in the background art, when the selection signal connected to the thin-film transistor Q1 changes from an on signal to an off signal, for example, when the selection signal changes from a high level to a low level, electric field coupling between the third coupling capacitor C3 and the pixel capacitor pixel C generates a voltage drop, i.e., a second preset voltage. This second preset voltage lowers the output voltage input to the pixel capacitor pixel C via the thin-film transistor Q1, thereby causing the voltage of the pixel capacitor pixel C to fluctuate during this transition. Because the voltage of the pixel capacitor pixel C is the difference between the output voltage and the common voltage, after the thin-film transistor Q1 enters the off state and the pixel capacitor pixel C begins displaying, the voltage of the pixel capacitor pixel C is lower than the voltage when the thin-film transistor Q1 is in the on state.

[0058] In order to avoid the above situation, this example proposes to set a voltage compensation unit including a first coupling capacitor C1 on each pixel area. The specific implementation scenarios are described as follows:

[0059] The first implementation scenario: Reference Figure 5 , one gate voltage line GATE and one common voltage line VCOM corresponding to the same row of pixel areas form a signal line pair, a charging switch tube Q2 is provided between each pair of the signal lines, a control terminal of the charging switch tube Q2 is connected to the gate voltage line GATE, input terminals of multiple charging switch tubes Q2 are connected to the same common voltage terminal, and an output terminal of each charging switch tube Q2 is connected to one of the common voltage lines VCOM;

[0060] The charging switch tube Q2 is used to access the common voltage input from the common voltage terminal when receiving the conduction signal input from the gate voltage line GATE, and transmit the common voltage to each pixel capacitor pixel C set on the same pair of signal lines as the charging switch tube Q2 through the common voltage line VCOM.

[0061] When each common voltage line VCOM is connected to the same common voltage terminal, a charging switch tube Q2 can be added to avoid crosstalk between different common voltage lines. Specifically, when scanning the gate voltage line GATE row by row, for example, when the scanning of the gate voltage line GATE of the second row is about to end, the gate voltage line GATE of the second row undergoes a voltage jump. Due to the action of the first coupling capacitor C1 of the second row, the common voltage line VCOM of the second row will also undergo a voltage jump accordingly, thereby producing a canceling effect across the pixel capacitor pixel C, and the second row can maintain normal display. However, if the charging switch tube Q2 is not provided, since each common voltage line VCOM is connected to the same common voltage terminal, it is equivalent to all common voltage lines VCOM being electrically connected together. At this time, the jump of the common voltage line VCOM of the second row will cause the common voltage line VCOM of the first row to jump accordingly. However, since the gate voltage line GATE of the first row has completed scanning at this time, the gate voltage line GATE of the first row will not jump. Therefore, the voltage changes across the pixel capacitor pixel C of the first row are not consistent, and the first row will experience display abnormality. The charging switch tubes Q2 in each row will isolate different common voltage lines VCOM to avoid crosstalk between different common voltage lines VCOM.

[0062] Specifically, this example proposes disposing a charging switch tube Q2 between each pair of signal lines formed by a gate voltage line GATE and a common voltage line VCOM. The charging switch tube Q2 is disposed at the common voltage terminal vcom of each row. When the pixel capacitors pixel C on that row need to be charged, the control terminal of the charging switch tube Q2 is connected to a conduction signal transmitted from the gate voltage line GATE, and the charging switch tube Q2 is turned on. The input terminal of the charging switch tube Q2 is connected to a common voltage transmitted from the common voltage terminal, and the common voltage is inputted through the common voltage line VCOM through the output terminal to each pixel capacitor pixel C disposed on the same pair of signal lines as the charging switch tube Q2. When the connected gate signal is an off signal, the off charging switch tube Q2 cuts off the common voltage output to the pixel capacitor pixel C, thereby avoiding crosstalk between different common voltage lines VCOM.

[0063] However, because the charging switch tube Q2, like the thin-film transistor Q1, also has a gate-to-drain capacitor, i.e., a second coupling capacitor C2, between its gate and drain, and because the control terminal of the charging switch tube Q2 is also connected to the selection signal of the selection voltage line GATE, and its output terminal is also connected to the other end of the pixel capacitor pixel C, when the selected signal is changed from a high level to a low level, the electric field coupling between the second coupling capacitor C2 and the pixel capacitor pixel C will generate a voltage drop, causing the common voltage output to the other end of the pixel capacitor pixel C via the charging switch tube Q2 to be pulled down. Therefore, in order to keep the common voltage and the data voltage at both ends of the pixel capacitor pixel C pulled down to the same preset voltage, a calculation formula for the preset voltage generated by the electric field effect is shown in Formula 1:

[0064] V p =(Vgh-Vgl)*(Cgs / C 像素 )————Formula 1

[0065] Among them, V p Indicates the preset voltage, Vgh indicates the on-state signal, which is a high level in this example, Vgl indicates the off-state signal, which is a low level in this example, Cgs indicates the capacitance value of the coupling capacitor, C 像素 It represents the capacitor voltage of pixel capacitor pixel C. Therefore, it can be seen that the preset voltage caused by the coupling capacitor and pixel capacitor pixel C is related to the level difference between the high and low levels input by the gate voltage line GATE, the capacitor voltage of the pixel capacitor itself, and the capacitor voltage of pixel capacitor pixel C in the same pixel area.

[0066] So, according to Figure 5 In the case where the gate voltage line GATE to which the first coupling capacitor C1, the second coupling capacitor C2, and the third coupling capacitor C3 are respectively connected is the same. The level difference between the high level and the low level to which the first coupling capacitor C1, the second coupling capacitor C2, and the third coupling capacitor C3 are respectively connected is the same, and the first coupling capacitor C1, the second coupling capacitor C2, and the third coupling capacitor C3 involve the same pixel capacitor pixel C, and the capacitor voltages when coupled with the pixel capacitor pixel C are also the same, the capacitance values ​​of the first coupling capacitor C1, the second coupling capacitor C2, and the third coupling capacitor C3 can be set so that the second preset voltage pulled down by the data voltage input to the first end of the pixel capacitor pixel C is equal to the first preset voltage pulled down by the specification voltage input to the second end of the pixel capacitor pixel C, and the two preset voltages offset each other, thereby keeping the charging voltage of the pixel capacitor pixel C unchanged.

[0067] Specifically, the electric field coupling generated by the first coupling capacitor C1 and the second coupling capacitor C2 affects the common voltage input to the pixel capacitor pixel C, while the electric field coupling generated by the third coupling capacitor C3 affects the data voltage input to the pixel capacitor pixel C. Therefore, by setting the total capacitance of the first coupling capacitor C1 and the second coupling capacitor C2 to be the same as the capacitance of the third coupling, the first preset voltage generated by the electric field effect of the first coupling capacitor C1 and the second coupling capacitor C2 is equal to the second preset voltage generated by the electric field effect of the third coupling capacitor C3.

[0068] Assuming that when the thin film transistor Q1 is turned on, the output voltage output to the first end of the pixel capacitor pixel C (hereinafter referred to as the pixel electrode) is 12V, and the common voltage output to the second end of the pixel capacitor pixel C (hereinafter referred to as the common electrode) is 5V. It can be obtained that the charging voltage of the pixel capacitor pixel C in the on stage is 12V-5V=7V. In the conversion stage when the thin film transistor Q1 changes from the on stage to the off stage, the output voltage 12V output to the pixel electrode is pulled down by the second preset voltage 1V to 11V, and the common voltage 5V output to the common electrode is pulled down by the first preset voltage 1V to 4V. The charging voltage of the pixel capacitor pixel C in the conversion stage is 11V-4V=7V, which is the same as the charging voltage of the pixel capacitor pixel C in the on stage. In this way, after the thin film transistor Q1 enters the off stage, the charging voltage that drives the pixel capacitor pixel C to display is consistent with the charging voltage of the pixel capacitor pixel C when the thin film transistor Q1 is in the on stage.

[0069] Therefore, refer to Figure 6 At this time, the output voltage and the common voltage connected to the pixel capacitor pixel C are both pulled down by the same preset voltage, because the charging voltage of the pixel capacitor pixel C is equal to the voltage difference between the output voltage and the common voltage. Even if the second preset voltage VP2 generated by the electric field coupling still exists, the newly added voltage offset unit can generate a first preset voltage VP1 equal to the voltage value of the second preset voltage VP2 to offset the voltage difference between the voltage of the pixel capacitor pixel C during charging and the voltage of the pixel capacitor pixel C during display. Therefore, the voltage of the pixel capacitor pixel C at this time remains unchanged, that is, the voltage of the pixel capacitor pixel C during display is V b and the pixel voltage V during charging a This avoids the abnormal display phenomenon of shaking head wrinkles caused by the reduction of pixel voltage.

[0070] The second implementation scenario: refer to Figure 7, each common voltage line VCOM is connected to a different common voltage terminal, that is, the common voltage lines VCOM are isolated from each other. A voltage jump on one common voltage line VCOM will not cause a voltage jump on other common voltage lines VCOM. In this case, the crosstalk problem described in the first case does not exist. Therefore, there is no need to set a charging switch tube Q2 between the signal line pairs to avoid crosstalk.

[0071] So, according to Figure 7 , when the first coupling capacitor C1 and the third coupling capacitor C3 are respectively connected to the same gate voltage line GATE. The level difference between the high level and the low level respectively connected to the first coupling capacitor C1 and the third coupling capacitor C3 is the same, and the first coupling capacitor C1, the second coupling capacitor C2 and the third coupling capacitor C3 involve the same pixel capacitor pixelC, and the capacitor voltages when coupled with the pixel capacitor pixelC are also the same. By setting the capacitance values ​​of the first coupling capacitor C1 and the third coupling capacitor C3, the second preset voltage pulled down by the data voltage input to the first end of the pixel capacitor pixelC is equal to the first preset voltage pulled down by the specification voltage input to the second end of the pixel capacitor pixelC, and the two preset voltages offset each other, thereby keeping the charging voltage of the pixel capacitor pixelC unchanged.

[0072] Specifically, the electric field coupling generated by the first coupling capacitor C1 affects the common voltage input to the pixel capacitor pixel C, while the electric field coupling generated by the third coupling capacitor C3 affects the data voltage input to the pixel capacitor pixel C. Therefore, by setting the capacitance of the first coupling capacitor C1 to be the same as the capacitance of the third coupling, the first preset voltage generated by the electric field effect of the first coupling capacitor C1 is equal to the second preset voltage generated by the electric field effect of the third coupling capacitor C3.

[0073] In the above two implementation scenarios, pixel voltage stabilization is achieved by simply adding a first coupling capacitor C1, which not only avoids the high cost of adding multiple components, but also avoids a reduction in aperture ratio.

[0074] In addition, the present invention further provides a display panel, including an array substrate, wherein the array substrate is provided with the pixel driving circuit as described above.

[0075] The present invention further provides a display device, comprising the display panel and a backlight module as described above, wherein the display panel is arranged on the light-emitting side of the backlight module.

[0076] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0077] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0078] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of various embodiments of the present invention.

[0079] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A pixel driving circuit, characterized in that: The pixel driving circuit includes: a pixel capacitor, wherein a first end of the pixel capacitor is connected to the gating unit, and a second end of the pixel capacitor is connected to the voltage offset unit and the common voltage line; the gating unit provides a data voltage to the first end when in a conductive state; and the common voltage line provides a common voltage to the second end; When the gating signal input to the gating unit changes from a conducting signal to a cutting-off signal, the voltage offset unit pulls down the common voltage input to the second end to a first preset voltage, and the data voltage of the first end is pulled down to a second preset voltage due to a coupling effect, and the second preset voltage offsets at least a portion of the first preset voltage; The gating unit includes a thin film transistor, an input terminal of the thin film transistor is connected to the data line, a control terminal of the thin film transistor is connected to the gating voltage line, and an output terminal of the thin film transistor is connected to the first terminal of the pixel capacitor; The voltage offset unit includes a first coupling capacitor, one end of the first coupling capacitor is connected to the gate voltage line in the same pixel area, and the other end of the first coupling capacitor is connected to the common voltage line in the same pixel area; A third coupling capacitor is formed between the gate electrode of the thin film transistor and the drain electrode of the thin film transistor due to a coupling effect, and the capacitance of the third coupling capacitor is the same as that of the first coupling capacitor.

2. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes: a plurality of gate voltage lines and a plurality of data lines, wherein the plurality of gate voltage lines extend in a row direction and are arranged in a column direction, and the plurality of data lines extend in a column direction and are arranged in a row direction; A plurality of the gate voltage lines intersect with a plurality of the data lines to form a pixel area array; Each pixel area in the pixel area array is provided with the pixel capacitor, the gating unit and the voltage compensation unit; A plurality of common voltage lines extend along a row direction and are arranged in a column direction, and each common voltage line is connected to the pixel capacitors in the same row.

3. The pixel driving circuit according to claim 1, wherein: One of the gate voltage lines and one of the common voltage lines corresponding to the pixel areas in the same row constitutes a signal line pair; a charging switch tube is provided between each pair of the signal lines, a control terminal of the charging switch tube is connected to the gate voltage line, input terminals of the plurality of charging switch tubes are connected to the same common voltage terminal, and an output terminal of each charging switch tube is connected to one of the common voltage lines; The charging switch tube is used to access the common voltage input from the common voltage terminal when accessing the conduction signal input from the selection voltage line, and transmit the common voltage to each pixel capacitor arranged on the same signal line pair as the charging switch tube through the common voltage line.

4. The pixel driving circuit according to claim 3, wherein: A second coupling capacitor is formed between the gate of the charging switch tube and the drain of the charging switch tube due to coupling effect, and a third coupling capacitor is formed between the gate of the thin film transistor and the drain of the thin film transistor due to coupling effect. The total capacitance of the first coupling capacitor and the second coupling capacitor is the same as the capacitance of the third coupling capacitor.

5. The pixel driving circuit according to claim 1, wherein: A plurality of common voltage lines are connected to different common voltage terminals.

6. A display panel, characterized in that: include: An array substrate is provided with a pixel driving circuit according to any one of claims 1 to 5.

7. A display device, characterized in that: include: The display panel and backlight module according to claim 6, wherein the display panel is arranged on the light-emitting side of the backlight module.

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