Array substrate, display panel and display device

Abstract

An array substrate (10), a display panel (100) and a display device (1000), relating to the field of display technology; the array substrate (10) comprises a plurality of pixel driving circuits (11) arranged in an array and a plurality of data signal lines (DL), one data signal line (DL) being electrically connected to a column of pixel driving circuits (11), wherein the array substrate (10) comprises a display area (AA), the display area (AA) comprises a compensation area (Ca) and a non-compensation area (N-Ca), the number of pixel driving circuits (11) in each column in the non-compensation area (N-Ca) is the same and greater than the number of pixel driving circuits (11) in each column in the compensation area (Ca), the compensation area (Ca) comprises at least one compensation capacitor (12), the compensation capacitor (12) being configured to form a load element of the data signal line (DL) located in the compensation area (Ca).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] The display panel includes pixels arranged in an array, each pixel includes multiple sub-pixels, and the sub-pixels can display a single color, such as red, green or blue. Each column of pixels is electrically connected to a data line, which provides a data signal to the pixel. Under the control of the data signal, the pixel generates different grayscales. The full-color display of the display panel is achieved by adjusting the pixel grayscale, as well as color combination and superposition.

[0003] The display panel has an irregular shape, that is, the number of pixels in each column of the display panel is different, and accordingly, the number of pixels electrically connected to each data line is different.

[0004] Public Content

[0005] In one aspect, an array substrate is provided, comprising a display area, the display area being provided with a plurality of pixel driving circuits and a plurality of data signal lines arranged in an array, one data signal line being electrically connected to a column of pixel driving circuits, the display area comprising a compensation area and a non-compensation area, the compensation area being provided with a plurality of compensation devices, the plurality of compensation devices being configured to make the loads of the plurality of data signal lines located in the display area consistent.

[0006] The array substrate includes: a substrate, a first gate layer and a source-drain metal layer. The first gate layer is arranged on one side of the substrate, and the first gate layer includes a voltage-stabilizing plate pattern of at least one compensation device, and the voltage-stabilizing plate pattern is configured to receive a voltage-stabilizing signal. The source-drain metal layer is arranged on a side of the first gate layer away from the substrate, and the source-drain metal layer includes a plurality of data signal lines. The orthographic projection of a voltage-stabilizing plate pattern of a compensation device on the substrate overlaps with the orthographic projection of a data signal line on the substrate.

[0007] In some embodiments, the array substrate includes multiple pixel areas, each pixel area is provided with a pixel driving circuit, at least one pixel area is a compensation pixel area, a voltage stabilizing plate pattern is provided in the compensation pixel area, the voltage stabilizing plate pattern overlaps with the data signal line passing through the compensation pixel area, and the overlapping part of the two forms a compensation device.

[0008] In some embodiments, the voltage stabilizing plate pattern includes a first voltage stabilizing plate pattern. The first gate layer further includes an initialization signal line, and the first voltage stabilizing plate pattern is electrically connected to the initialization signal line.

[0009] In some embodiments, the pixel driving circuit includes a first enabling transistor and a second reset transistor. The array substrate also includes: a semiconductor layer and a second gate layer. The semiconductor layer includes a plurality of active patterns, each active pattern is located in a pixel region, and the active pattern includes at least an active layer of the first enabling transistor and an active layer of the second reset transistor. The second gate layer is disposed between the semiconductor layer and the first gate layer, and the second gate layer includes: a first gate signal line and a second gate signal line, wherein the first gate signal line overlaps with the active layer of the first enabling transistor, and the second gate signal line overlaps with the active layer of the second reset transistor. The orthographic projection of the first voltage stabilizing plate pattern on the substrate is located between the orthographic projections of the first gate signal line and the second gate signal line on the substrate.

[0010] In some embodiments, the width of the first gate signal line in the compensation area is smaller than the width of the first gate signal line in the non-compensation area. The width of the second gate signal line in the compensation area is smaller than the width of the second gate signal line in the non-compensation area.

[0011] In some embodiments, the overlapping portion of the data signal line with the first voltage stabilizing plate pattern serves as the first load plate pattern of the compensation device, and the orthographic projection area of ​​the first voltage stabilizing plate pattern on the substrate is larger than the orthographic projection area of ​​the first load plate pattern on the substrate.

[0012] In some embodiments, the voltage stabilizing plate pattern includes a second voltage stabilizing plate pattern. The source-drain metal layer also includes a power supply voltage signal line, and the second voltage stabilizing plate pattern is electrically connected to the power supply voltage signal line.

[0013] In some embodiments, the pixel driving circuit includes a write transistor and a first reset transistor. The active pattern includes at least an active layer of the first reset transistor and an active layer of the write transistor. The second gate layer includes: a third gate signal line and a fourth gate signal line, wherein the third gate signal line overlaps with the active layer of the first reset transistor, and the fourth gate signal line overlaps with the active layer of the write transistor. The orthographic projection of the second voltage stabilizing plate pattern on the substrate is located between the orthographic projections of the third gate signal line and the fourth gate signal line on the substrate.

[0014] In some embodiments, the width of the third gate signal line in the compensation area is smaller than the width of the third gate signal line in the non-compensation area. The width of the fourth gate signal line in the compensation area is smaller than the width of the fourth gate signal line in the non-compensation area.

[0015] In some embodiments, the portion of the data signal line that overlaps with the second voltage stabilizing plate pattern serves as the second load plate pattern of the compensation device. The orthographic projection area of ​​the second voltage stabilizing plate pattern on the substrate is larger than the orthographic projection area of ​​the second load plate pattern on the substrate.

[0016] In some embodiments, the array substrate further includes a peripheral area at least disposed on one side of the display area, the display area is further provided with a plurality of power supply voltage signal lines, and the peripheral area is provided with a power supply voltage bus and a plurality of data signal extension lines. The plurality of power supply voltage signal lines extend to the peripheral area and are electrically connected to the power supply voltage bus. The plurality of data signal lines extend to the peripheral area, each data signal line is electrically connected to a data signal extension line, and at least part of the plurality of data signal extension lines overlaps with the orthographic projection of the power supply voltage bus on the substrate.

[0017] In some embodiments, the pixel regions are arranged in an array, a data signal line passes through a column of pixel regions, and in a column of pixel regions in the compensation area, the compensation pixel regions and the non-compensation pixel regions other than the compensation pixel regions are alternately arranged.

[0018] In some embodiments, the orthographic projections of the plurality of active patterns of the semiconductor layer on the substrate do not overlap with the orthographic projections of the voltage stabilizing plate patterns on the substrate.

[0019] In some embodiments, the array substrate includes a plurality of pixel regions arranged in an array, each pixel region is provided with a pixel driving circuit, and along the column direction of the pixel array arrangement, the size of the pixel region located in the compensation region is smaller than the size of the pixel region located in the non-compensation region. A plurality of data signal lines extend along the column direction and pass through the display region, the compensation region includes a non-pixel region, and no pixel driving circuit is provided in the non-pixel region. At least one compensation device is provided in the non-pixel region of the compensation region.

[0020] On the other hand, a display panel is provided. The display panel comprises: an array substrate according to any one of the embodiments in the above-mentioned first aspect, a light-emitting device layer and an encapsulation layer. The array substrate comprises a substrate and a source-drain metal layer, the light-emitting device layer is arranged on a side of the source-drain metal layer away from the substrate, and the encapsulation layer is arranged on a side of the light-emitting device layer away from the substrate.

[0021] In another aspect, a display device is provided, comprising a display panel according to the embodiment in the above another aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0023] Figure 1 A structural diagram of a display device provided for some embodiments of the present disclosure;

[0024] Figure 2 A structural diagram of a display panel provided for some embodiments of the present disclosure;

[0025] Figure 3 A cross-sectional view of a display panel provided for some embodiments of the present disclosure;

[0026] Figure 4 A pixel driving circuit diagram provided for some embodiments of the present disclosure;

[0027] Figure 5A A structural diagram of a pixel driving circuit provided for some embodiments of the present disclosure;

[0028] Figure 5B A structural diagram of an active pattern of a pixel driving circuit provided for some embodiments of the present disclosure;

[0029] Figure 5C A structural diagram of an active pattern and a second gate layer of a pixel driving circuit provided for some embodiments of the present disclosure;

[0030] Figure 5D A structural diagram of an active pattern, a first gate layer, and a second gate layer of a pixel driving circuit provided for some embodiments of the present disclosure;

[0031] Figure 6 A structural diagram of another display panel provided for some embodiments of the present disclosure;

[0032] Figure 7 A structural diagram of an array substrate provided for some embodiments of the present disclosure;

[0033] Figure 8 A structural diagram of another array substrate provided for some embodiments of the present disclosure;

[0034] Fig. 9 A circuit diagram of a part of the peripheral area and a part of the display area of ​​an array substrate provided in some embodiments of the present disclosure;

[0035] Fig.10 A structural diagram of another array substrate provided for some embodiments of the present disclosure;

[0036] Fig.11 A structural diagram of another array substrate provided for some embodiments of the present disclosure;

[0037] Fig. 12A A structural diagram of pixel area arrangement provided for some embodiments of the present disclosure;

[0038] Fig. 12BAnother structural diagram of pixel area arrangement provided for some embodiments of the present disclosure;

[0039] Fig. 12C Another structural diagram of pixel area arrangement provided for some embodiments of the present disclosure;

[0040] Fig.13 Another circuit diagram of a part of the peripheral area and a part of the display area of ​​an array substrate provided for some embodiments of the present disclosure;

[0041] Fig.14 A structural diagram of another pixel driving circuit provided for some embodiments of the present disclosure;

[0042] Fig.15 A structural diagram of a first gate layer and a source-drain metal layer of another pixel driving circuit provided for some embodiments of the present disclosure;

[0043] Fig.16 A structural diagram of a first gate layer and a second gate layer of another pixel driving circuit provided for some embodiments of the present disclosure;

[0044] Fig.17 A structural diagram of a first gate layer and a second gate layer of a pixel driving circuit in a compensation area and a non-compensation area provided in some embodiments of the present disclosure;

[0045] Fig.18 A structural diagram of another pixel driving circuit provided for some embodiments of the present disclosure;

[0046] Fig.19 A structural diagram of a first gate layer and a second gate layer of another pixel driving circuit provided for some embodiments of the present disclosure;

[0047] Fig. 20 A structural diagram of a first gate layer and a second gate layer of another pixel driving circuit in a compensation area and a non-compensation area provided for some embodiments of the present disclosure;

[0048] Fig.21 A structural diagram of another pixel driving circuit provided for some embodiments of the present disclosure;

[0049] Fig. 22 Structural diagram of pixel regions and non-pixel regions provided for some embodiments of the present disclosure;

[0050] Fig.23 A structural diagram of another display panel provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0058] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0059] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more conditions or values ​​may, in practice, be based on additional conditions or beyond values.

[0060] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0061] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0062] Some embodiments of the present disclosure provide a display device, the outer contour of the display screen of the display device may include an arc line, for example, the display device may be a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a car computer, a wearable display device, etc. The embodiments of the present disclosure do not specifically limit the specific form of the display device. Specifically, Figure 1 As shown, the display device 1000 is a watch, and the display device 1000 includes a display panel 100, and the display panel 100 is circular.

[0063] In some embodiments, Figure 2 As shown, the display panel 100 includes a display area AA (Active Area, referred to as AA area; also referred to as an effective display area) and a peripheral area BB located at least on one side of the display area AA. The display area AA is provided with a plurality of sub-pixels P arranged in an array and a plurality of signal lines. The sub-pixel P is the smallest unit for the display panel 100 to display a picture. Each sub-pixel P can display a single color, such as red (R), green (G) or blue (B). By adjusting the brightness (grayscale) of the sub-pixels P of different colors, the display of multiple colors can be realized through color combination and superposition, thereby realizing full-color display of the display panel 100.

[0064] Each sub-pixel P includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. The pixel driving circuits included in the display panel 100 are arranged in an array.

[0065] Among them, the light-emitting device can be an organic light-emitting diode (OLED), a micro organic light-emitting diode (Micro OLED), a quantum dot organic light-emitting diode (QLED), a mini light-emitting diode (Mini LED) or a micro light-emitting diode (Micro LED).

[0066] In some embodiments, Figure 2As shown, the plurality of signal lines include a plurality of scan signal lines, a plurality of data signal lines DL, a plurality of reset signal lines, a plurality of enable signal lines, a plurality of initialization signal lines Vinit, and a plurality of power supply voltage signal lines VDD. Exemplarily, the plurality of scan signal lines, the plurality of enable signal lines, and the plurality of initialization signal lines Vinit are arranged along the row direction of the sub-pixels P, and the plurality of data signal lines DL and the plurality of power supply voltage signal lines VDD are arranged along the column arrangement direction of the sub-pixels P. Each pixel driving circuit is electrically connected to the scan signal lines, the data signal lines DL, the reset signal lines, the enable signal lines, the initialization signal lines Vinit, and the power supply voltage signal lines VDD.

[0067] In some embodiments, Figure 3 As shown, the display panel 100 includes an array substrate 10, a light-emitting device layer 20 and an encapsulation layer 30, wherein the array substrate 10 includes a plurality of pixel driving circuits 11 arranged in an array, the pixel driving circuit 11 includes a plurality of transistors and capacitors, and the light-emitting device layer 20 includes a plurality of light-emitting devices 21. The array substrate 10 includes: a substrate 1 and a pixel circuit layer 2 stacked on the substrate 1, the pixel circuit layer 2 includes a functional layer and an insulating layer located between adjacent functional layers. The functional layer may include a semiconductor layer 3, a first gate layer 4, a second gate layer 5, and a source-drain metal layer 6, etc. The semiconductor layer 3, the first gate layer 4, the second gate layer 5, and the source-drain metal layer 6 are used to form a plurality of pixel driving circuits 11 in the display panel 100, and the plurality of pixel driving circuits 11 may be formed in the display area of ​​the display panel 100. The insulating layer may include a first gate insulating layer 3', a second gate insulating layer 4', an interlayer dielectric layer 5' and a pixel flat layer 6', wherein the first gate insulating layer 3' is disposed between the semiconductor layer 3 and the first gate layer 4, the second gate insulating layer 4' is disposed between the first gate layer 4 and the second gate layer 5, the interlayer dielectric layer 5' is disposed between the second gate layer 5 and the source-drain metal layer 6, and the pixel flat layer 6' is disposed on the side of the source-drain metal layer 6 away from the substrate 1. The light emitting device 21 is disposed on the side of the pixel driving circuit 20 away from the substrate 1.

[0068] The pixel driving circuit may include a plurality of transistors and capacitors. For example, the transistor may be a thin film transistor (TFT), a field effect transistor (such as an oxide thin film transistor), or other switching devices with the same characteristics. In the embodiments of the present invention, thin film transistors are used as examples.

[0069] In some embodiments of the present disclosure, the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiments of the present invention can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0070] In some embodiments, the pixel driving circuit may include a 2T1C, 7T1C, or 6T1C circuit, where T represents a transistor, and the number before T represents the number of transistors, and C represents a capacitor, and the number before C represents the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor. The present disclosure takes a pixel driving circuit in a 7T1C mode as an example for introduction.

[0071] In some examples, such as Figure 4 As shown, the pixel driving circuit 11 of the 7T1C mode includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first enabling transistor T5, a second enabling transistor T6, a second reset transistor T7 and a first capacitor Cst.

[0072] Among them, the control electrode of the first reset transistor T1 is electrically connected to the first reset signal terminal r1, the first electrode of the first reset transistor T1 is electrically connected to the first initialization signal terminal v1, the second electrode of the first reset transistor T1 is electrically connected to the first node N1, the first reset signal terminal r1 is electrically connected to the first reset signal line Rst1, and the first initialization signal terminal v1 is electrically connected to the initialization signal line.

[0073] The control electrode of the compensation transistor T2 is electrically connected to the scan signal terminal g, the first electrode of the compensation transistor T2 is electrically connected to the third node N3, the second electrode of the compensation transistor T2 is electrically connected to the first node N1, and the scan signal terminal g is electrically connected to the scan signal line.

[0074] The control electrode of the driving transistor T3 is electrically connected to the first node N1 , the first electrode of the driving transistor T3 is electrically connected to the second node N2 , and the second electrode of the driving transistor T3 is electrically connected to the third node N3 .

[0075] The first plate Cst1 of the first capacitor Cst is electrically connected to the first node N1, the second plate Cst2 of the first capacitor Cst is electrically connected to the first voltage signal terminal vdd, and the first voltage signal terminal vdd is electrically connected to the power supply voltage signal line.

[0076] The control electrode of the write transistor T4 is electrically connected to the scan signal terminal g, the first electrode of the write transistor T4 is electrically connected to the data signal terminal d, the second electrode of the write transistor T4 is electrically connected to the second node N2, and the data signal terminal d is electrically connected to the data line.

[0077] The control electrode of the first enable transistor T5 is electrically connected to the light emitting control signal terminal em, the first electrode of the first enable transistor T5 is electrically connected to the first voltage signal terminal vdd, the second electrode of the first enable transistor T5 is electrically connected to the second node N2, and the light emitting control signal terminal em is electrically connected to the enable signal line.

[0078] The control electrode of the second enabling transistor T6 is electrically connected to the light emitting control signal terminal em, the first electrode of the second enabling transistor T6 is electrically connected to the third node N3 , and the second electrode of the second enabling transistor T6 is electrically connected to the anode of the light emitting device 30 .

[0079] The control electrode of the second reset transistor T7 is electrically connected to the second reset signal terminal r2, the first electrode of the second reset transistor T7 is electrically connected to the second initialization signal terminal v2, the second electrode of the second reset transistor T7 is electrically connected to the second electrode of the second enable transistor T6 and the connection point N4 of the anode of the light-emitting device 30, the cathode of the light-emitting device 30 is electrically connected to the second voltage signal terminal vss, the second initialization signal terminal v2 is electrically connected to the initialization signal line, the second reset signal terminal r2 is electrically connected to the second reset signal line, and the second voltage signal terminal vss is electrically connected to the second voltage signal line, wherein the second voltage signal line transmits a low-level signal, for example, the voltage of the low-level signal can be zero.

[0080] In some embodiments, Fig.10 As shown, the array substrate 10 includes a display area, the display area includes a plurality of pixel areas Pa, each pixel area Pa is provided with a pixel driving circuit 11, wherein the plurality of pixel areas Pa are arranged in an array, such as Figure 5A As shown, taking a pixel area as an example, in the layout of the pixel driving circuit 11 of the 7T1C mode, the array substrate 10 includes: a semiconductor layer 3, a first gate layer 4, a second gate layer 5 and a source-drain metal layer 6.

[0081] The semiconductor layer 3 is disposed on the substrate, and the semiconductor layer 3 includes a plurality of active patterns 7, wherein Figure 5B As shown, the active pattern 7 includes: an active layer S1 of a first reset transistor, an active layer S2 of a compensation transistor, an active layer S3 of a drive transistor, an active layer S4 of a write transistor, an active layer S5 of a first enable transistor, an active layer S6 of a second enable transistor, and an active layer S7 of a second reset transistor.

[0082] like Figure 3 and Figure 5DAs shown, the first gate layer 4 is disposed on one side of the substrate 1 , and the first gate layer 4 includes an initialization signal line Vinit, and the initialization signal line Vinit is electrically connected to the active layer S7 of the second reset transistor.

[0083] like Figure 3 and Figure 5C As shown, the second gate layer 5 is disposed between the semiconductor layer 3 and the first gate layer 4. The second gate layer 5 includes: a first gate signal line 51, a second gate signal line 52, a third gate signal line 53, a fourth gate signal line 54 and a first plate Cst1 of the first capacitor, wherein the first gate signal line 51 overlaps with the active layer S5 of the first enable transistor to form a first enable transistor; the first gate signal line 51 overlaps with the active layer S6 of the second enable transistor to form a second enable transistor; the second gate signal line 52 overlaps with the active layer S7 of the second reset transistor to form a second reset transistor; the third gate signal line 53 overlaps with the active layer S1 of the first reset transistor to form a first reset transistor; the fourth gate signal line 54 overlaps with the active layer S2 of the compensation transistor to form a compensation transistor; the fourth gate signal line 54 overlaps with the active layer S4 of the write transistor to form a write transistor; the first plate Cst1 of the first capacitor overlaps with the active layer S3 of the drive transistor to form a drive transistor.

[0084] It should be noted that, in the embodiment of the present disclosure, for the entire display area of ​​the display panel, a plurality of pixel driving circuits arranged in an array are provided in the display area, such as Figure 5B As shown, the active layers of each transistor in each pixel driving circuit form an active pattern, and the multiple active patterns included in the semiconductor layer are arranged in an array, and along the column direction of the multiple active patterns, the active patterns are arranged periodically. Figure 5B As shown, the active layer S7 of the second reset transistor in the active pattern of the pixel driving circuit in the previous row is connected to the active layer S1 of the first reset transistor in the active pattern of the pixel driving circuit in the current row, and the two have overlapping parts in the row direction. The active layer S1 of the first reset transistor in the active pattern 7 of the pixel driving circuit in the next row is connected to the active layer S7 of the second reset transistor in the active pattern 7 of the pixel driving circuit in the current row, and the two have overlapping parts in the row direction. Therefore, in the layout design, the first reset transistor S1 and the second reset transistor S7 in the pixel driving circuits of two adjacent rows pass over the same gate signal line, that is, the first reset transistor S1 and the second reset transistor S7 in the pixel driving circuits of two adjacent rows are controlled to be turned on or off by the same gate signal line.

[0085] Therefore, the display panel includes three types of gate signal lines, namely, first type of gate signal lines, second type of gate signal lines and third type of gate signal lines. The first type of gate signal lines, the second type of gate signal lines and the third type of gate signal lines are arranged periodically. Figure 5C In the present invention, a plurality of gate signal lines passing through a pixel region are named respectively based on a pixel region, so as to more clearly illustrate the positional relationship between each gate signal line and the active layer of each transistor in the active pattern.

[0086] The first type of gate signal line passes through the active layer S2 of the compensation transistor and the active layer S4 of the write transistor in the same row of pixel circuits. The first type of gate signal line is Figure 5C The fourth gate signal line 54 in the same row of pixel circuits; the second type of gate signal line passes through the active layer S5 of the first enabling transistor and the active layer S6 of the second enabling transistor, and the second type of gate signal line is Figure 5C The first gate signal line 51 in the third type of gate signal line passes through the active layer S1 of the first reset transistor and the active layer S7 of the second reset transistor in the pixel circuit of two adjacent rows, and the second type of gate signal line is Figure 5C In other words, the second gate signal line 52 or the third gate signal line 53 is actually the same type of gate signal line, transmitting the same signal.

[0087] like Figure 5A As shown, the source-drain metal layer 6 is arranged on the side of the first gate layer 4 away from the substrate, and the source-drain metal layer 6 includes multiple data signal lines DL and power voltage signal lines VDD, wherein the data signal lines DL are configured to transmit data signals, and the power voltage signal lines VDD are configured to transmit power voltage signals.

[0088] In some embodiments, the shape of the display area AA is not a standard rectangle. For example, Figure 2 As shown, the display area AA may be circular, or Figure 6 As shown, the display area AA may be a rounded rectangle. A plurality of sub-pixels P located in the display area AA are arranged in an array. Figure 2 In the display area AA shown in FIG. 1 , the number of sub-pixels P in each column close to the center O of the display area is relatively large, and the number of sub-pixels P in each column far from the center O of the display area is relatively small; Figure 6 In the display area AA shown, the number of sub-pixels P in each column in the middle area Oa of the display area AA is the same, and the number of sub-pixels P in each column in the edge areas SA on both sides of the middle area Oa (i.e., the two sides opposite to each other in the row direction of the array-arranged sub-pixels P) is different, and the number of sub-pixels P in each column in the middle area Oa is greater than the number of sub-pixels P in each column in the edge areas SA. Specifically, in the edge areas SA, the number of sub-pixels P in each column is inversely proportional to the distance between the sub-pixels P in each column and the middle area Oa, that is, as the distance between the sub-pixels P in each column and the middle area Oa increases, the number of sub-pixels P in each column decreases.

[0089] In some embodiments, Figure 7 or Figure 8As shown, the array substrate 10 includes a plurality of data signal lines DL, one data signal line DL is electrically connected to a column of pixel driving circuits 11, and the number of pixel driving circuits 11 electrically connected to each data signal line DL is different, such as Figure 7 As shown, the farther away from the center O of the display area, the fewer the number of pixel driving circuits 11 electrically connected to a data signal line DL. Figure 8 As shown, the number of pixel driving circuits electrically connected to each data signal line DL in the central area Oa is consistent, and the number of pixel driving circuits electrically connected to each data signal line DL in the edge area SA is lower than the number of pixel driving circuits electrically connected to each data signal line DL in the central area Oa.

[0090] Different data signal lines DL are electrically connected to different pixel driving circuits, that is, different data signal lines DL have different loads, which may cause the following situation: for example, taking the pixel driving circuit as a P-type transistor as an example, the same data signal is transmitted through the data signal lines DL with different loads, and the grayscale of the sub-pixel electrically connected to the data signal line DL with a lower load is lower than that of the sub-pixel electrically connected to the data signal line DL with a higher load. Overall, this situation may cause the display image of the display panel 100 to have distortion and uneven brightness.

[0091] In some embodiments, in order to solve the problem of different loads of different data signal lines DL, when the number of sub-pixels electrically connected to the data signal line DL is small, a compensation device can be added to the data signal line DL. For example, the compensation device can be a resistor, a capacitor, etc. In the following embodiments, the compensation device is a compensation capacitor as an example. Specifically, Figure 7 and Figure 8 As shown, in order to make the loads of multiple data signal lines DL of the display panel 100 relatively consistent and balanced, compensation capacitors 12 are added to the data signal lines DL connected to a smaller number of sub-pixels, wherein the area of ​​the display area AA through which the data signal lines DL provided with compensation capacitors 12 pass is the compensation area Ca, and the area of ​​the display area AA through which the data signal lines DL without compensation capacitors 12 pass is the non-compensation area N-Ca. Generally speaking, the number of pixel driving circuits per column in the non-compensation area is the same or substantially the same, and is higher than the number of pixel driving circuits per column in the compensation area. For example, Figure 7As shown, the number of pixel driving circuits connected to the multiple data signal lines DL located in the non-compensation area N-Ca is the largest, and the number of pixel driving circuits connected to each data signal line DL is the same, and the data signal line DL does not need to be provided with a compensation capacitor 12. The number of pixel driving circuits electrically connected to other data signal lines DL is less than the number of pixel driving circuits connected to the data signal lines DL located in the non-compensation area N-Ca. Therefore, the other data signal lines DL need to be provided with compensation capacitors 12 to balance the load so that the load amounts of all data signal lines DL are consistent or substantially consistent. Among them, the data signal lines DL that are close to the center O of the display area and have the same number of pixel driving circuits electrically connected, the area passing through the display area AA is the non-compensation area N-Ca, and the area where the other data signal lines DL pass through the display area AA is the compensation area Ca.

[0092] like Figure 8 As shown, the number of pixel driving circuits electrically connected to the multiple data signal lines DL located in the middle area Oa is consistent, and the number of pixel driving circuits electrically connected to the multiple data signal lines DL located in the edge area SA is less than the number of pixel driving circuits connected to the data signal lines DL located in the middle area Oa, and the load of the data signal lines DL located in the middle area Oa is higher than the load of the data signal lines DL located in the edge area SA. That is, the multiple data signal lines DL located in the edge area SA need to be provided with compensation capacitors 12 to balance the load so that the load of all data signal lines DL is consistent or substantially consistent. Among them, the middle area Oa is the non-compensation area N-Ca, and the edge area SA is the compensation area Ca.

[0093] That is to say, the array substrate 10 includes a display area AA and a peripheral area BB surrounding the display area AA, the display area AA includes a compensation area Ca and a non-compensation area N-Ca, the number of pixel driving circuits in each column in the non-compensation area N-Ca is consistent and higher than the number of pixel driving circuits in each column in the compensation area Ca.

[0094] In some embodiments, Figure 7 , Figure 8 and Fig. 9 As shown, Fig. 9 Can be Figure 7 or Figure 8 The structure diagram of the array substrate 10 shown in FIG. 1 is located in the display area AA and the peripheral area BB. The compensation capacitor 12 is arranged in the peripheral area BB, for example, Fig. 9As shown, multiple data signal lines extend to the peripheral area BB, and the array substrate also includes a metal layer arranged on one side of the source and drain metal layer where the multiple data lines are located. In the peripheral area BB, the metal layer includes a compensation pattern, and the compensation pattern overlaps with the data line that needs to be compensated. The overlapping part of the two forms a compensation capacitor 12. Since the compensation capacitor 12 is arranged in the peripheral area BB, the compensation pattern occupies a large area, which is not conducive to the compression of the width of the display panel frame. At the same time, the compensation capacitor 12 occupies the space of other circuits that need to be arranged in the peripheral area BB. For example, the compensation capacitor 12 may occupy the space of the gate drive circuit that needs to be arranged in the peripheral area BB. In order to reduce the display panel frame, the gate drive circuit may be compressed. Accordingly, the difficulty of the production process increases and the product cost increases.

[0095] Based on this, some embodiments of the present disclosure provide an array substrate 10, which includes a functional layer and an insulating layer, wherein the functional layer includes a substrate 1, a first gate layer 4, a second gate layer 5, and a source-drain metal layer 6, and the insulating layer includes a first gate insulating layer 3', a second gate insulating layer 4', an interlayer dielectric layer 5', and a pixel flat layer 6'. In this embodiment, the structure and position of each functional layer and the insulating layer disposed between the functional layers are consistent with the above-mentioned embodiments, and are not described in detail here.

[0096] Among them, Fig.10 , Fig.11 , Fig.14 , Fig.18 and Fig.21 As shown, Fig.14 , Fig.18 , Fig.21 Can be Fig.10 or Fig.11 The layout of a pixel driving circuit 11 in the compensation area Ca of the array substrate 10. The compensation area Ca of the array substrate 10 includes a plurality of compensation capacitors 12, and the plurality of compensation capacitors 12 are configured to make the loads of the plurality of data signal lines located in the display area consistent. The first gate layer 4 includes a voltage stabilizing plate pattern Ccs of at least one compensation capacitor 12, and the voltage stabilizing plate pattern Ccs is configured to receive a voltage stabilizing signal. The positive projection of the voltage stabilizing plate pattern Ccs of a compensation capacitor 12 on the substrate overlaps with the positive projection of a data signal line DL on the substrate 1.

[0097] In some examples, such as Fig.10As shown, the array substrate 10 includes a circular display area AA, the array substrate 10 includes a plurality of data signal lines DL, the plurality of data signal lines DL extend along the column direction, the display area AA includes a compensation area Ca and a non-compensation area N-Ca, and the boundary between the compensation area Ca and the non-compensation area N-Ca is parallel to the column direction, wherein the data signal lines DL close to the center O of the display area and electrically connected to the pixel driving circuits of the same number, the area passing through the display area AA is the non-compensation area N-Ca,, and the area where the other data signal lines DL pass through the display area AA is the compensation area Ca. Fig.11 As shown, the array substrate 10 includes a display area AA in the shape of a rounded rectangle. The array substrate 10 includes a plurality of data signal lines DL, and the plurality of data signal lines DL extend along a column direction. The display area AA includes a compensation area Ca and a non-compensation area N-Ca, and a boundary line between the compensation area Ca and the non-compensation area N-Ca is parallel to the column direction.

[0098] Among them, Fig.13 As shown, the compensation capacitor is arranged in the compensation area. Specifically, the voltage stabilizing plate pattern Ccs of the compensation capacitor is located in the first gate layer of the compensation area, and the voltage stabilizing plate pattern overlaps with the data line, and the voltage stabilizing plate pattern and the data line position form a compensation capacitor.

[0099] The compensation capacitor can be arranged in the compensation area to compensate the load of the data signal lines located in the compensation area, so that the load of all data signal lines is relatively balanced. Fig.13 As shown, the compensation capacitor can be set in the compensation area to give up part of the space of the peripheral area BB as other space for the circuit, which can reduce the process difficulty and production cost; and further reduce the border width of the display panel, providing a basis for the display panel with an ultra-narrow border.

[0100] It should be noted that the "overlap" in the present disclosure refers to the overlapping parts of the orthographic projections of the two on the substrate. For example, "the voltage stabilizing plate pattern Ccs overlaps with the data signal line DL" means that the orthographic projection of the voltage stabilizing plate pattern Ccs on the substrate overlaps with the orthographic projection of the data signal line DL on the substrate.

[0101] In some embodiments, Fig.13 As shown, Fig.13 The partial structural diagram of the array substrate is shown, including: a structural diagram of the partial peripheral area BB and a structural diagram of the partial display area AA.

[0102] The array substrate further includes a peripheral area BB at least arranged on one side of the display area, the display area AA is further provided with a plurality of power supply voltage signal lines VDD, and the peripheral area BB is provided with a power supply voltage bus VL and a plurality of data signal extension lines DL'. The plurality of power supply voltage signal lines VDD extend to the peripheral area BB and are electrically connected to the power supply voltage bus VL. The plurality of data signal lines DL extend to the peripheral area BB, each data signal line DL is electrically connected to a data signal extension line DL', and at least part of the plurality of data signal extension lines DL' overlaps with the orthographic projection of the power supply voltage bus VL on the substrate.

[0103] Exemplarily, a plurality of data signal lines DL are arranged in the source-drain metal layer, a plurality of data signal extension lines DL' are arranged in the second gate layer, and each data signal line DL is electrically connected to a data signal extension line DL' through a via. The power supply voltage bus VL is arranged in the source-drain metal layer, and the power supply voltage bus VL overlaps with the data signal extension line DL', that is, the power supply voltage bus VL and the data signal extension line DL' form a capacitor structure, which can be used as an auxiliary compensation device with a smaller load corresponding to the data signal line DL. In addition to multiple compensation devices, the capacitor structure can play an auxiliary compensation role. The capacitor structure can act as a load for the data signal lines DL that are connected to a small number of pixel driving circuits, which can reduce the occupancy of the peripheral area BB, and at the same time make full use of the free space in the peripheral area BB to achieve the purpose of reducing the border.

[0104] In some embodiments, Fig.10 , Fig.11 , Fig.17 and Fig. 20 As shown, the array substrate 10 includes a plurality of pixel areas Pa, each of which is provided with a pixel driving circuit 11, wherein the plurality of pixel areas Pa are arranged in an array, a plurality of data signal lines DL and a plurality of power supply voltage signal lines extend in a column direction, each data signal line DL passes through a plurality of pixel areas Pa arranged in a row, a plurality of scanning signal lines, a plurality of reset signal lines, a plurality of enable signal lines, and a plurality of initialization signal lines Vinit extend in a row direction, each scanning signal line passes through a plurality of pixel areas Pa arranged in a row, and other signal lines extending in the row direction all pass through a plurality of pixel areas Pa arranged in a row.

[0105] At least one pixel region Pa is a compensation pixel region Pa', in which a voltage stabilizing plate pattern Ccs is disposed, and the voltage stabilizing plate pattern Ccs overlaps with the data signal line DL passing through the compensation pixel region Pa', and the overlapping portion of the two forms a compensation capacitor 12. It can be understood that the compensation pixel region Pa' is located in the compensation area Ca.

[0106] In some examples, the outer contour of the compensation area Ca is an arc, and accordingly, the number of sub-pixels in each column of the compensation area Ca is different, that is, the number of sub-pixels electrically connected to each data signal line DL located in the compensation area Ca is different, that is, each data signal line DL located in the compensation area Ca has a different load amount, so in the compensation area Ca, each data signal line DL needs to be set with a different number of compensation capacitors 12.

[0107] The compensation area Ca includes a plurality of pixel areas Pa arranged in an array, each pixel area Pa is provided with a pixel driving circuit 11, each data signal line DL passes through a column of pixel areas Pa, and in a column of pixel areas Pa, a portion of the pixel areas Pa provided with compensation capacitors 12 is a compensation pixel area Pa', and each compensation pixel area Pa' is provided with at least one voltage stabilizing plate pattern Ccs. The voltage stabilizing plate pattern Ccs located in the compensation pixel area Pa' overlaps with the data signal line DL passing through the compensation pixel area Pa', and each overlapping portion is a compensation capacitor 12.

[0108] It should be noted that “passing” in the present disclosure means that the orthographic projections of the two on the substrate 1 overlap. For example, “the data signal line DL passes through a column of pixel areas Pa” means that the orthographic projection of the data signal line DL on the substrate 1 overlaps with the orthographic projection of a column of pixel areas Pa on the substrate 1.

[0109] In some embodiments, Fig.10 and Fig.11 As shown, the pixel areas Pa are arranged in an array, and a data signal line DL passes through a column of pixel areas Pa. In a column of pixel areas Pa in the compensation area Ca, compensation pixel areas Pa' and non-compensation pixel areas other than the compensation pixel areas Pa' are alternately arranged.

[0110] In some examples, the number of sub-pixels in each column of the compensation area Ca is different, and the number of compensation capacitors 12 required for each data signal line DL is different. One, two, or three compensation capacitors 12 can be set in one compensation pixel area Pa'. For example, one compensation capacitor 12 is set in one compensation pixel area Pa'.

[0111] For example, Fig. 12A As shown, in a column of pixel regions Pa, a plurality of compensation pixel regions Pa' are arranged between two adjacent non-compensation pixel regions Pa", and the number of compensation pixel regions Pa' between every two adjacent non-compensation pixel regions Pa" is the same.

[0112] Or, if Fig. 12BAs shown, in the middle area or both end areas of a column of pixel areas Pa, non-compensation pixel areas Pa" and compensation pixel areas Pa' are arranged alternately. For example, in the middle area of ​​a column of pixel areas Pa, non-compensation pixel areas Pa" and compensation pixel areas Pa' are arranged alternately.

[0113] Or, if Fig. 12C As shown, in the compensation area Ca, the array-arranged pixel area Pa includes a plurality of rows of non-compensation pixel areas Pa", and one or more rows of compensation pixel areas Pa' are arranged between two adjacent rows of non-compensation pixel areas Pa". By arranging the compensation pixel areas and the non-compensation pixel areas alternately, the compensation capacitors are evenly distributed in the compensation area of ​​the display area. For example, a non-compensation pixel area can be arranged between two compensation pixel areas Pa', and the load can be evenly distributed to the data signal lines located in the display area.

[0114] In some embodiments, Fig.14 , Fig.15 and Fig.16 The pattern of each film layer in a pixel area is shown. Fig.15 yes Fig.14 The structure diagram of the first gate layer 4 and the source-drain metal layer 6, Fig.16 yes Fig.14 The first gate layer 4 and the first gate layer 5 are structural diagrams. The voltage stabilizing plate pattern Ccs includes a first voltage stabilizing plate pattern Ccs1, and the semiconductor layer 3 includes a plurality of active patterns 7, each of which is located in a pixel region.

[0115] like Fig.14 As shown, the initialization signal line Vinit is electrically connected to the active layer S7 of the second reset transistor through the compensation pixel area, and the first voltage stabilizing plate pattern Ccs1 is electrically connected to the initialization signal line Vinit.

[0116] In some examples, the compensation capacitor 12 is disposed in the compensation pixel region, and the voltage stabilizing plate pattern Ccs of the compensation capacitor 12 is configured to receive a voltage stabilizing signal. In the pixel driving circuit 11 of the 7T1C mode, the initialization signal line Vinit transmits an initialization signal, which is a voltage constant signal, that is, the initialization signal can be transmitted to the voltage stabilizing plate pattern Ccs as a voltage stabilizing signal, and the initialization signal line Vinit is also configured to transmit a voltage stabilizing signal. The voltage stabilizing plate pattern Ccs electrically connected to the initialization signal line Vinit is a first voltage stabilizing plate pattern Ccs1, which achieves the purpose of receiving a voltage stabilizing signal.

[0117] In the layout of the pixel driving circuit 11 in the 7T1C mode, the initialization signal line Vinit passes through each compensation pixel region. Therefore, the first voltage stabilizing plate pattern Ccs1 can be electrically connected to the initialization signal line Vinit in the compensation pixel region without affecting the external layout structure.

[0118] In some embodiments, Fig.16 As shown, the orthographic projection of the first voltage stabilizing plate pattern Ccs1 on the substrate is located between the orthographic projections of the first gate signal line 51 and the second gate signal line 52 on the substrate 1 .

[0119] In some examples, the orthographic projection of the initialization signal line Vinit on the substrate is located between the orthographic projections of the first gate signal line 51 and the second gate signal line 52 on the substrate. The first voltage stabilizing plate pattern Ccs1 is electrically connected to the initialization signal line Vinit. To simplify the layout of the pixel driving circuit 11, the first voltage stabilizing plate pattern Ccs1 is close to the initialization signal line Vinit, that is, the first voltage stabilizing plate pattern Ccs1 is disposed on the first gate layer 4, and the orthographic projection of the first voltage stabilizing plate pattern Ccs1 on the substrate 1 is between the orthographic projections of the first gate signal line 51 and the second gate signal line 52 on the substrate 1.

[0120] In some embodiments, Fig.17 As shown, the width D1 of the first gate signal line 51 located in the compensation area Ca is smaller than the width D2 of the first gate signal line 51 located in the non-compensation area N-Ca. The width X1 of the second gate signal line 52 located in the compensation area Ca is smaller than the width X2 of the second gate signal line 52 located in the non-compensation area N-Ca.

[0121] In some examples, a first gate signal line 51 passes through a plurality of pixel regions Pa arranged in a row, wherein the plurality of pixel regions Pa arranged in a row include pixel regions Pa located in the compensation region Ca and pixel regions Pa located in the non-compensation region N-Ca, and the first gate signal line 51 passes through the compensation pixel region Pa'. The width of the first gate signal line 51 is the dimension of the first gate signal line 51 in a direction perpendicular to its extension direction, and the widths of the portions of the first gate signal line 51 located in different regions are different, wherein the width D1 of the portion of the first gate signal line 51 located in the compensation region Ca is smaller than the width D2 of the portion of the first gate signal line 51 located in the non-compensation region N-Ca.

[0122] A second gate signal line 52 passes through a plurality of pixel areas Pa arranged in a row, wherein the plurality of pixel areas Pa arranged in a row include a pixel area Pa located in the compensation area Ca and a pixel area Pa located in the non-compensation area N-Ca, and the second gate signal line 52 passes through the compensation pixel area Pa', and the width of the second gate signal line 52 is the dimension of the second gate signal line 52 in a direction perpendicular to its extension direction, and the widths of portions of the second gate signal line 52 located in different areas are different, wherein the width X1 of the portion of the second gate signal line 52 located in the compensation area Ca is smaller than the width X2 of the portion of the second gate signal line 52 located in the non-compensation area N-Ca.

[0123] A first voltage stabilizing plate pattern Ccs1 is disposed between the first gate signal line 51 and the second gate signal line 52 of the compensation pixel area Pa'. To facilitate the arrangement of the first voltage stabilizing plate pattern Ccs1 and to ensure that the first voltage stabilizing plate pattern Ccs1 does not overlap with the first gate signal line 51 and the second gate signal line 52, a larger space is required between the first gate signal line 51 and the second gate signal line 52. To widen the space between the first gate signal line 51 and the second gate signal line 52, the width of the first gate signal line 51 and the second gate signal line 52 in the compensation area Ca can be reduced, without significantly changing the overall layout and without affecting the display effect formed by the display panel.

[0124] In some embodiments, Fig.15 As shown, the overlapped portion of the data signal line DL with the first voltage stabilizing plate pattern Ccs1 serves as the first load plate pattern Cct1 of the compensation capacitor 12. The orthographic projection area of ​​the first voltage stabilizing plate pattern Ccs1 on the substrate is larger than the orthographic projection area of ​​the first load plate pattern Cct1 on the substrate.

[0125] In some examples, the data signal line DL overlaps with the first voltage stabilizing plate pattern Ccs1, wherein the overlapping portion of the data signal line DL and the first voltage stabilizing plate pattern Ccs1 is the first load plate pattern Cct1 of the compensation capacitor 12. The first load plate pattern Cct1 and the first voltage stabilizing plate pattern Ccs1 form the compensation capacitor 12, which has the function of compensating the load of the data signal line DL and can free up the occupied space of the peripheral area.

[0126] The area of ​​the orthographic projection of the first voltage stabilizing plate pattern Ccs1 on the substrate is larger than the area of ​​the orthographic projection of the first load plate pattern Cct1 on the substrate. For example, the area of ​​the orthographic projection of the first voltage stabilizing plate pattern Ccs1 on the substrate is twice the area of ​​the orthographic projection of the first load plate pattern Cct1 on the substrate. The first voltage stabilizing plate pattern Ccs1 has a larger area, which is beneficial for processing. The first voltage stabilizing plate pattern Ccs1 has sufficient margin to meet the requirements of the area size of the two plates facing the compensation capacitor 12. At the same time, the position of the first voltage stabilizing plate pattern Ccs1 can be offset within a certain range, which can effectively reduce the difficulty of the process.

[0127] In other embodiments, Fig.18 and Fig.19 As shown, the voltage stabilizing plate pattern Ccs includes a second voltage stabilizing plate pattern Ccs2, and the second voltage stabilizing plate pattern Ccs2 is electrically connected to the power supply voltage signal line VDD.

[0128] In some examples, the power supply voltage signal line VDD is electrically connected to the active layer S5 of the first enabling transistor, and the power supply voltage signal line VDD is configured to provide a power supply voltage signal to the pixel driving circuit, and the power supply voltage signal is a signal with a constant voltage. And the power supply voltage signal line VDD is electrically connected to the second voltage stabilizing plate pattern Ccs2, that is, the power supply voltage signal can be transmitted to the second voltage stabilizing plate pattern Ccs2 as a stabilizing signal, that is, the power supply voltage signal line VDD is also configured to transmit a stabilizing signal.

[0129] The compensation capacitor 12 is arranged in the compensation pixel area, and the voltage stabilizing plate pattern Ccs of the compensation capacitor 12 is configured to receive a voltage stabilizing signal. The power supply voltage signal line VDD is electrically connected to the active layer S5 of the first enabling transistor, and the power supply voltage signal line VDD is configured to provide a power supply voltage signal to the pixel driving circuit 11, wherein the power supply voltage signal is a constant voltage signal, that is, the power supply voltage signal can be transmitted to the voltage stabilizing plate pattern Ccs as a voltage stabilizing signal. The voltage stabilizing plate pattern Ccs electrically connected to the power supply voltage signal line VDD is a second voltage stabilizing plate pattern Ccs2, which achieves the purpose of receiving the voltage stabilizing signal.

[0130] In the layout of the pixel driving circuit 11 in the 7T1C mode, the power supply voltage signal line VDD passes through each compensation pixel area. Therefore, the second voltage stabilizing plate pattern Ccs2 can be electrically connected to the power supply voltage signal line VDD in the compensation pixel area without affecting the external layout structure.

[0131] In some embodiments, Fig.19 As shown, the orthographic projection of the second voltage stabilizing plate pattern Ccs2 on the substrate is located between the orthographic projections of the third gate signal line 53 and the fourth gate signal line 54 on the substrate.

[0132] In some examples, the first gate layer 4 includes an initialization signal line Vinit and a second plate Cct2 of the compensation capacitor 12, wherein the positive projection of the initialization signal line Vinit on the substrate is located between the positive projections of the first gate signal line 51 and the second gate signal line 52 on the substrate, and the second plate Cct2 of the compensation capacitor 12 is located between the positive projections of the first gate signal line 51 and the fourth gate signal line 54 on the substrate. In other words, a space for setting the second voltage stabilizing plate pattern Ccs2 is reserved between the third gate signal line 53 and the fourth gate signal line 54.

[0133] like Fig. 20 As shown, the second voltage stabilizing plate pattern Ccs2 is arranged in the compensation pixel area Pa', and the orthographic projection of the second voltage stabilizing plate pattern Ccs2 on the substrate is located between the orthographic projections of the third gate signal line 53 and the fourth gate signal line 54 on the substrate, and the orthographic projection of the second voltage stabilizing plate pattern Ccs2 on the substrate does not overlap with the orthographic projections of the third gate signal line 53 and the fourth gate signal line 54 on the substrate.

[0134] In some embodiments, Fig. 20 As shown, a third gate signal line 53 passes through a plurality of pixel regions Pa arranged in a row, wherein the plurality of pixel regions Pa arranged in a row include pixel regions Pa located in the compensation region Ca and pixel regions Pa located in the non-compensation region N-Ca, and the third gate signal line 53 passes through the compensation pixel region Pa'. The width of the third gate signal line 53 is the dimension of the third gate signal line 53 in a direction perpendicular to its extension direction, and the widths of the portions of the third gate signal line 53 located in different regions are different, wherein the width H1 of the portion of the third gate signal line 53 located in the compensation region Ca is smaller than the width H2 of the portion of the third gate signal line 53 located in the non-compensation region N-Ca.

[0135] A fourth gate signal line 54 passes through a plurality of pixel regions Pa arranged in a row, wherein the plurality of pixel regions Pa arranged in a row include pixel regions Pa located in the compensation region Ca and pixel regions Pa located in the non-compensation region N-Ca, and the fourth gate signal line 54 passes through the compensation pixel region Pa'. The width of the fourth gate signal line 54 is the dimension of the fourth gate signal line 54 in a direction perpendicular to its extension direction, and the widths of the portions of the fourth gate signal line 54 located in different regions are different, wherein the width B1 of the portion of the fourth gate signal line 54 located in the compensation region Ca is smaller than the width B2 of the portion of the third gate signal line 53 located in the non-compensation region N-Ca.

[0136] A second voltage stabilizing plate pattern Ccs2 is disposed between the third gate signal line 53 and the fourth gate signal line 54 of the compensation pixel area Pa'. To facilitate the arrangement of the second voltage stabilizing plate pattern Ccs2, and to ensure that the second voltage stabilizing plate pattern Ccs2 does not overlap with the third gate signal line 53 and the fourth gate signal line 54, a larger space is required between the third gate signal line 53 and the fourth gate signal line 54. To widen the space between the third gate signal line 53 and the fourth gate signal line 54, a method of reducing the width of the third gate signal line 53 and the fourth gate signal line 54 in the compensation area Ca can be adopted, without significantly changing the overall layout, and without affecting the display effect formed by the display panel.

[0137] In some embodiments, Fig.19 As shown, the overlapped portion of the data signal line DL with the second voltage stabilizing plate pattern Ccs2 serves as the second load plate pattern Cct2 of the compensation capacitor 12. The orthographic projection area of ​​the second voltage stabilizing plate pattern Ccs2 on the substrate is larger than the orthographic projection area of ​​the second load plate pattern Ccs2 on the substrate.

[0138] In some examples, the data signal line DL overlaps with the second voltage stabilizing plate pattern Ccs2, wherein the overlapping portion of the data signal line DL and the second voltage stabilizing plate pattern Ccs2 is the second load plate pattern Cct2 of the compensation capacitor 12. The second load plate pattern Cct2 and the second voltage stabilizing plate pattern Ccs2 form the compensation capacitor 12, which has the function of compensating the load of the data signal line DL and can free up the occupied space of the peripheral area.

[0139] Among them, the area of ​​the positive projection of the second voltage stabilizing plate pattern Ccs2 on the substrate is larger than the area of ​​the positive projection of the second load plate pattern Cct2 on the substrate. For example, the area of ​​the positive projection of the second voltage stabilizing plate pattern Ccs2 on the substrate is twice the area of ​​the positive projection of the second load plate pattern Cct2 on the substrate. The second voltage stabilizing plate pattern Ccs2 has a larger area, which is beneficial for processing. The second voltage stabilizing plate pattern Ccs2 has sufficient margin of activity, which can meet the requirements of the area size of the two plates facing the compensation capacitor 12. At the same time, the position of the second voltage stabilizing plate pattern Ccs2 can be offset within a certain range, which can effectively reduce the difficulty of the process.

[0140] In some embodiments, Fig.14 and Fig.18 As shown, the orthographic projections of the plurality of active patterns 7 of the semiconductor layer 3 on the substrate do not overlap with the orthographic projections of the voltage stabilizing plate patterns Ccs on the substrate.

[0141] In some examples, to avoid mutual influence between the compensation capacitor 12 and the active layers of each transistor, the orthographic projection of the voltage stabilizing plate pattern Ccs on the substrate does not overlap with the orthographic projection of the plurality of active patterns 7 of the semiconductor layer 3 on the substrate.

[0142] Exemplarily, the voltage stabilizing plate pattern Ccs can be a first voltage stabilizing plate pattern Ccs1, and the orthographic projection of the first voltage stabilizing plate pattern Ccs1 on the substrate is located between the orthographic projections of the first gate signal line 51 and the second gate signal line 52 on the substrate 1, and the orthographic projection of the first voltage stabilizing plate pattern Ccs1 on the substrate has no overlap with the orthographic projections of the active layer of the first enabling transistor, the active layer of the second enabling transistor, and the active layer S7 of the second reset transistor on the substrate.

[0143] Alternatively, the voltage-stabilizing plate pattern Ccs can be a second voltage-stabilizing plate pattern Ccs2, and the orthographic projection of the first voltage-stabilizing plate pattern Ccs2 on the substrate is located between the orthographic projections of the third gate signal line 53 and the fourth gate signal line 54 on the substrate, and the orthographic projection of the second voltage-stabilizing plate pattern Ccs2 on the substrate has no overlap with the orthographic projections of the active layer of the first reset transistor, the active layer of the compensation transistor, and the active layer of the write transistor on the substrate.

[0144] In other embodiments, Fig.21 As shown, two compensation capacitors 12 may be provided in the compensation pixel region, and the voltage stabilizing plate pattern Ccs includes a first voltage stabilizing plate pattern Ccs1 and a second voltage stabilizing plate pattern Ccs2. The orthographic projection of the first voltage stabilizing plate pattern Ccs1 on the substrate is located between the orthographic projections of the first gate signal line 51 and the second gate signal line 52 on the substrate; the orthographic projection of the second voltage stabilizing plate pattern Ccs2 on the substrate is located between the orthographic projections of the third gate signal line 53 and the fourth gate signal line 54 on the substrate.

[0145] In some other embodiments, Fig. 22 As shown, the array substrate 11 includes a plurality of pixel areas Pa arranged in an array, each pixel area Pa is provided with a pixel driving circuit 11, and along the column direction of the sub-pixel array arrangement, the size of the pixel area Pa located in the compensation area Ca is smaller than the size of the pixel area Pa located in the non-compensation area N-Ca. A plurality of data signal lines DL extend along the column direction and pass through the display area, and the compensation area Ca includes a non-pixel area NP, and the pixel driving circuit 11 is not provided in the non-pixel area NP. At least one compensation capacitor 12 is provided in the non-pixel area NP of the compensation area Ca.

[0146] In some examples, the compensation capacitor 12 is disposed in the compensation area Ca, wherein the display area includes a pixel area Pa, and at least one pixel driving circuit 11 is disposed in each pixel area Pa. The size of the pixel area Pa located in the compensation area Ca in the column direction is smaller than the size of the pixel area located in the non-compensation area N-Ca, so that in the column direction, the spacing between two adjacent pixel areas Pa located in the compensation area Ca is greater than the spacing between two adjacent pixel areas located in the non-compensation area N-Ca. The space between two adjacent pixel areas Pa located in the compensation area Ca is a non-pixel area NP, and the compensation capacitor 12 can be disposed in the non-pixel area NP.

[0147] Exemplarily, the compensation capacitor 12 includes a third stabilizing plate pattern Ccs3 , which may be disposed on the first gate layer 4 , and the third stabilizing plate pattern Ccs3 is located in the non-pixel region NP, and the third stabilizing plate pattern Ccs3 overlaps with a data signal line DL.

[0148] A voltage-stabilizing signal line CL is also provided in the non-pixel region NP provided with the third voltage-stabilizing plate pattern Ccs3. The voltage-stabilizing signal line CL is electrically connected to the third voltage-stabilizing plate pattern Ccs3 located in the same non-pixel region NP, wherein the voltage-stabilizing signal line CL is configured to transmit a voltage-stabilizing signal, specifically, the voltage-stabilizing signal line CL can be electrically connected to the power supply voltage signal line VDD, the initialization signal line or other lines providing a voltage-stabilizing signal.

[0149] In some embodiments, the overlapped portion of the data signal line DL with the third voltage stabilizing plate pattern Ccs3 serves as the third load plate pattern Cct3 of the compensation capacitor 12. The orthographic projection area of ​​the third voltage stabilizing plate pattern Ccs3 on the substrate is larger than the orthographic projection area of ​​the third load plate pattern Cct3 on the substrate.

[0150] Exemplarily, the area of ​​the positive projection of the third voltage stabilizing plate pattern Ccs3 on the substrate is twice the area of ​​the positive projection of the third load plate pattern Cct3 on the substrate. The third voltage stabilizing plate pattern Ccs3 has a larger area, which is beneficial for processing. The third voltage stabilizing plate pattern Ccs3 has sufficient margin to meet the requirements of the area size of the two plates facing the compensation capacitor 12. At the same time, the position of the third voltage stabilizing plate pattern Ccs3 can be offset within a certain range, which can effectively reduce the difficulty of the process.

[0151] In some examples, the number of pixels in each column of the compensation area is different, the number of compensation capacitors 12 required to be set for each data signal line DL is different, and one compensation capacitor 12 can be set in each non-pixel area NP. That is, the number of non-pixel areas NP required to be set in each column of pixel areas Pa is consistent with the number of compensation capacitors 12 electrically connected to the data signal lines DL passing through the column of pixel areas Pa. The load formed by the compensation capacitors 12 is different according to the size of the compensation capacitors 12. Therefore, in the specific process, the number of compensation capacitors 12 electrically connected to each data signal line is uncertain, and the reference is to meet the consistent or approximately consistent load of each data signal line.

[0152] On the other hand, Fig.23 As shown, some embodiments of the present disclosure provide a display panel 100, comprising an array substrate 10, a light-emitting device layer 20 and a packaging layer 30 as described in any one of the embodiments in the above aspect. The light-emitting device layer 20 is arranged on the side of the source and drain metal layer away from the substrate, and the packaging layer is arranged on the side of the light-emitting device layer away from the substrate.

[0153] The display panels provided by some embodiments of the present disclosure adopt the array substrates of the above embodiments, and have the same effects and functions as the array substrates of the above embodiments, which will not be described in detail here.

[0154] In another aspect, some embodiments of the present disclosure provide a display device 1000, including the display panel 100 of the embodiment in the above another aspect. The display device 1000 may be Figure 1 The watch shown includes a circular display panel 100 .

[0155] The display devices provided in some embodiments of the present disclosure adopt the display panels of the above embodiments and have the same effects and functions as the display panels of the above embodiments, which will not be elaborated here.

[0156] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, comprising a display area, the display area comprising a plurality of pixel areas, the display area being provided with a plurality of pixel driving circuits and a plurality of data signal lines arranged in an array, one pixel driving circuit being provided in each pixel area, one data signal line being electrically connected to a column of the pixel driving circuits, the plurality of data signal lines extending along a column direction and passing through the display area, the display area comprising a compensation area and a non-compensation area, along the column direction, the size of the pixel area located in the compensation area is smaller than the size of the pixel area located in the non-compensation area; the compensation area comprising a non-pixel area, no pixel driving circuit being provided in the non-pixel area; the compensation area being provided with a plurality of compensation devices, the plurality of compensation devices being configured to make the loads of the plurality of data signal lines located in the display area consistent; At least one of the compensation devices is disposed in a non-pixel region of the compensation area; The array substrate comprises: substrate; A first gate layer, disposed on one side of the substrate, the first gate layer comprising at least one voltage-stabilizing plate pattern of the compensation device, the voltage-stabilizing plate pattern being configured to receive a voltage-stabilizing signal; A source-drain metal layer, disposed on a side of the first gate layer away from the substrate, the source-drain metal layer including the plurality of data signal lines; The orthographic projection of a voltage-stabilizing plate pattern of the compensation device on the substrate overlaps with the orthographic projection of one of the data signal lines on the substrate.

2. The array substrate according to claim 1, wherein: At least one pixel region is a compensation pixel region, the compensation pixel region is provided with the voltage stabilizing plate pattern, the voltage stabilizing plate pattern overlaps with the data signal line passing through the compensation pixel region, and the overlapping portion of the two forms the compensation device.

3. The array substrate according to claim 2, wherein: The voltage stabilizing plate pattern includes a first voltage stabilizing plate pattern; The first gate layer also includes an initialization signal line; The first voltage stabilizing plate pattern is electrically connected to the initialization signal line.

4. The array substrate according to claim 3, wherein: The pixel driving circuit includes a first enabling transistor and a second reset transistor; The array substrate further includes: a semiconductor layer, the semiconductor layer comprising a plurality of active patterns, each active pattern being located in one of the pixel regions, the active patterns comprising at least an active layer of the first enabling transistor and an active layer of the second reset transistor; a second gate layer, the second gate layer being disposed between the semiconductor layer and the first gate layer, the second gate layer comprising: a first gate signal line and a second gate signal line, wherein the first gate signal line overlaps with the active layer of the first enable transistor, and the second gate signal line overlaps with the active layer of the second reset transistor; The orthographic projection of the first voltage stabilizing plate pattern on the substrate is located between the orthographic projections of the first gate signal line and the second gate signal line on the substrate.

5. The array substrate according to claim 4, wherein: The width of the portion of the first gate signal line located in the compensation area is smaller than the width of the portion of the first gate signal line located in the non-compensation area; The width of a portion of the second gate signal line located in the compensation area is smaller than the width of a portion of the second gate signal line located in the non-compensation area.

6. The array substrate according to any one of claims 3 to 5, wherein: The portion of the data signal line that overlaps with the first voltage stabilizing plate pattern is used as a first load plate pattern of the compensation device. The orthographic projection area of ​​the first voltage stabilizing plate pattern on the substrate is larger than the orthographic projection area of ​​the first load plate pattern on the substrate.

7. The array substrate according to claim 6, wherein: The voltage stabilizing plate pattern includes a second voltage stabilizing plate pattern; The source-drain metal layer also includes a power supply voltage signal line; The second voltage stabilizing plate pattern is electrically connected to the power supply voltage signal line.

8. The array substrate according to claim 7, wherein: The pixel driving circuit includes a write transistor and a first reset transistor; The array substrate further includes: a semiconductor layer, the semiconductor layer comprising a plurality of active patterns, each active pattern being located in one of the pixel regions, the active patterns comprising at least an active layer of the first reset transistor and an active layer of the write transistor; a second gate layer, the second gate layer being disposed between the semiconductor layer and the first gate layer, the second gate layer comprising: a third gate signal line and a fourth gate signal line, wherein the third gate signal line overlaps with the active layer of the first reset transistor, and the fourth gate signal line overlaps with the active layer of the write transistor; The orthographic projection of the second voltage stabilizing plate pattern on the substrate is located between the orthographic projections of the third gate signal line and the fourth gate signal line on the substrate.

9. The array substrate according to claim 8, wherein: The width of the portion of the third gate signal line located in the compensation area is smaller than the width of the portion of the third gate signal line located in the non-compensation area; A width of a portion of the fourth gate signal line located in the compensation region is smaller than a width of a portion of the fourth gate signal line located in the non-compensation region.

10. The array substrate according to any one of claims 7 to 9, wherein: The portion of the data signal line that overlaps with the second voltage stabilizing plate pattern is used as a second load plate pattern of the compensation device. The orthographic projection area of ​​the second voltage stabilizing plate pattern on the substrate is larger than the orthographic projection area of ​​the second load plate pattern on the substrate.

11. The array substrate according to claim 1, wherein: The array substrate further comprises a peripheral area at least arranged on one side of the display area, the display area is further provided with a plurality of power supply voltage signal lines, and the peripheral area is provided with a power supply voltage bus and a plurality of data signal extension lines; The plurality of power supply voltage signal lines extend to the peripheral area and are electrically connected to the power supply voltage bus; The plurality of data signal lines extend to the peripheral region, each data signal line is electrically connected to one of the data signal extension lines, and at least some of the plurality of data signal extension lines overlap with the positive projection of the power voltage bus on the substrate.

12. The array substrate according to claim 2, wherein: The pixel areas are arranged in an array, one data signal line passes through a column of pixel areas, and in a column of pixel areas in the compensation region, the compensation pixel areas and non-compensation pixel areas other than the compensation pixel areas are alternately arranged.

13. The array substrate according to any one of claims 4 to 5, 8 to 9, wherein: The orthographic projections of the multiple active patterns of the semiconductor layer on the substrate do not overlap with the orthographic projections of the voltage stabilizing plate patterns on the substrate.

14. A display panel, wherein: include: The array substrate according to any one of claims 1 to 13, wherein the array substrate comprises a substrate and a source-drain metal layer; A light emitting device layer is arranged on a side of the source / drain metal layer away from the substrate; The encapsulation layer is arranged on a side of the light emitting device layer away from the substrate.

15. A display device, wherein: The invention comprises the display panel as claimed in claim 14.

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