Semiconductor structure and semiconductor device

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a semiconductor device, the semiconductor structure comprising: a multilayer storage module stacked on the upper surface of the logic chip along a first direction, the first direction being perpendicular to the upper surface of the logic chip; the storage module comprising a plurality of storage chips stacked in a second direction, the second direction being parallel to the upper surface of the logic chip; the storage chip at the top layer having one second wireless communication unit; the storage chip at a non-top layer having two second wireless communication units arranged in the first direction and a wired communication unit connected between the two second wireless communication units; in the first direction, the two second wireless communication units arranged adjacently and located in different storage chips perform wireless communication; and the first wireless communication unit performs wireless communication with the second wireless communication unit in the bottom layer storage chip closest to the first wireless communication unit. The embodiment of the present disclosure can at least improve the capacity density and performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, and specifically relates to a semiconductor structure and a semiconductor device. Background Technology

[0002] To improve the integration of semiconductor structures, more than one memory chip can be placed within the same package. HBM (High Bandwidth Memory) is a new type of memory. Memory chip stacking technology, represented by HBM, extends the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thereby significantly increasing the density of memory chips and achieving large capacity and high bandwidth.

[0003] However, as the number of stacked layers increases, the performance of HBM is affected, meaning that it is difficult to balance the capacity density and performance of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a semiconductor device that can simultaneously improve the capacity density and performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a logic chip having a first wireless communication unit; a multilayer memory module stacked on the upper surface of the logic chip along a first direction perpendicular to the upper surface of the logic chip; the memory module including a plurality of memory chips stacked in a second direction parallel to the upper surface of the logic chip; the top layer of the memory chip having a second wireless communication unit; the non-top layer memory chips having two second wireless communication units arranged in the first direction and a wired communication unit connected between them; in the first direction, two second wireless communication units arranged adjacently and located in different memory chips communicate wirelessly; the first wireless communication unit communicates wirelessly with the second wireless communication unit in the bottom layer memory chip that is closest to it.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor device, wherein the semiconductor device includes: a substrate; a logic chip disposed on the substrate and having a first wireless communication unit; a multilayer memory module stacked on the upper surface of the logic chip along a first direction, the first direction being perpendicular to the upper surface of the logic chip; the memory module including a plurality of memory chips stacked in a second direction, the second direction being parallel to the upper surface of the logic chip; the top layer of the memory chip having a second wireless communication unit; the non-top layer memory chips having two second wireless communication units arranged in the first direction and a wired communication unit connected between them; in the first direction, two second wireless communication units disposed adjacently and located in different memory chips communicate wirelessly; the first wireless communication unit communicates wirelessly with the second wireless communication unit in the bottom layer memory chip that is closest to it.

[0007] The technical solution provided by this disclosure has at least the following advantages: In the first direction, multiple second wireless communication units and wired communication units form a communication path, that is, the communication method between the memory chip and the logic chip combines wireless and wired communication. Wireless communication can eliminate the manufacturing steps of the wired communication units between adjacent memory chips, thereby reducing the process difficulty; wired communication can reduce communication loss. In addition, multiple memory modules are arranged in the first direction, thereby increasing the capacity density of the memory chips. Furthermore, within the same memory module, the stacking direction of multiple memory chips is parallel to the upper surface of the logic chip. Therefore, the distance between the memory chips and the logic chip in the same memory module is the same, which can reduce the difference in communication delay between the same memory module and the logic chip. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0009] Figure 1 A schematic diagram of a semiconductor structure is shown;

[0010] Figures 2-3 Two cross-sectional views of a semiconductor structure provided in an embodiment of this disclosure are shown respectively;

[0011] Figure 4 , Figure 7 , Figure 11 , Figure 13 , Figure 15 The following are bottom views of different storage modules provided in an embodiment of this disclosure; Figure 5 , Figure 6 , Figure 8 , Figure 9 Schematic diagrams of different active surfaces of a memory chip provided in an embodiment of this disclosure are shown respectively;

[0012] Figure 10 , Figure 12 , Figure 14 Partial cross-sectional views of different semiconductor structures provided in an embodiment of this disclosure are shown respectively;

[0013] Figure 16 A schematic diagram of a semiconductor device provided according to another embodiment of this disclosure is shown;

[0014] Figure 17 This illustration shows a structural schematic corresponding to a step in a method for manufacturing a semiconductor structure according to yet another embodiment of the present disclosure. Detailed Implementation

[0015] As is known from the background technology, it is difficult to simultaneously achieve high capacity density and high performance in semiconductor structures. (Reference) Figure 1 Analysis revealed that the main reason is that the arrangement of multiple memory chips 200 is perpendicular to the upper surface of the logic chip 300, and the conductive vias 400 and bonding portions 500 of the multiple memory chips 200 are electrically connected, thus forming a wired communication path. When there are many stacked layers, the communication distance between the topmost and bottommost memory chips 200 and the logic chip 300 differs significantly, resulting in large differences in communication delays between different memory chips 200 and the logic chip 300, thereby affecting the product's operating speed.

[0016] This disclosure provides a semiconductor structure including: a multilayer memory module stacked in a direction perpendicular to the upper surface of a logic chip; the memory module includes multiple memory chips stacked in a direction parallel to the upper surface of the logic chip, i.e., the arrangement direction of the multiple memory chips within the memory module is parallel to the upper surface of the logic chip. Therefore, the memory chips and logic chips within the same memory module are equidistant, reducing the difference in communication latency between the same memory module and the logic chip. Furthermore, multiple memory modules can increase capacity density. Additionally, a second wireless communication unit and a wired communication unit in the first direction can form a communication path. Wired communication can reduce signal loss, while wireless communication eliminates the step of manufacturing a wired communication unit between adjacent memory chips, reducing process complexity. Therefore, the semiconductor structure provided by this disclosure can improve capacity density while maintaining the performance of the semiconductor structure.

[0017] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0018] like Figures 2-15 As shown, one embodiment of this disclosure provides a semiconductor structure, which includes: a logic chip 3 having a first wireless communication unit 31; a multilayer memory module 100 stacked on the upper surface of the logic chip 3 along a first direction X, the first direction X being perpendicular to the upper surface of the logic chip 3; the memory module 100 including a plurality of memory chips 1 stacked in a second direction Y, the second direction Y being parallel to the upper surface of the logic chip 3; the top layer memory chip 1 having a second wireless communication unit 11; the non-top layer memory chips 1 having two second wireless communication units 11 arranged in the first direction X and a wired communication unit 13 connected between them; in the first direction X, two second wireless communication units 11 arranged adjacently and located in different memory chips 1 communicate wirelessly; the first wireless communication unit 31 communicates wirelessly with the second wireless communication unit 11 in the bottom layer memory chip 1 that is closest to it.

[0019] For ease of understanding, the two second wireless communication units 11 of the non-top-level memory chip 1 are defined as the lower communication unit 11b and the upper communication unit 11a, respectively. That is, the first wireless communication unit 31 communicates wirelessly with the lower communication unit 11b within the bottom-level memory chip 1, and then the lower communication unit 11b transmits data to the upper communication unit 11a of the bottom-level memory chip 1 via the wired communication unit 13; the upper communication unit 11a of the bottom-level memory chip 1 communicates wirelessly with the lower communication unit 11b of the next-lowest-level memory chip 1. The memory chips 1 stacked in the first direction X communicate sequentially in this manner. Therefore, the semiconductor structure can combine the advantages of both wireless and wired communication, improving communication quality while eliminating the need for the wired communication unit 13 between adjacent memory chips 1.

[0020] For example, when the bottom-level memory chip 1 is selected, the first wireless communication unit 31 communicates wirelessly with the lower communication unit 11b of the bottom-level memory chip 1. When the top-level memory chip 1 is selected, the first wireless communication unit 31 transmits data to the lower communication unit 11b of the top-level memory chip 1 sequentially through the lower communication unit 11b of the non-top-level memory chip 1, the wired communication unit 13, and the upper communication unit 11a. That is, the lower communication unit 11b of the non-top-level memory chip 1 can be used for its own communication or as a communication relay station for the memory chip 1 located above it; while the wired communication unit 13 and the upper communication unit 11a can only serve as communication relay stations for the memory chip 1 located above them. In other embodiments, the wired communication unit 13 and the upper communication unit 11a are also used for communication with their respective memory chips 1.

[0021] It should be noted that when logic chip 3 performs chip select, it selects one of the storage modules 100 to read and write data. Therefore, the upper and lower layer storage modules 100 will only read and write to the storage chip 1 of the same layer at the same time during operation. Although the overall communication latency of the upper layer storage module 100 is longer than that of the lower layer storage module 100, it does not affect the communication latency of all storage chips 1 within the same layer storage module 100.

[0022] For example, the underlying storage module 100 can be the primary storage module, and the non-underlying storage modules 100 can be secondary storage modules. Since the primary storage module is closest to the logic chip 3, it is beneficial to improve the product's operating speed.

[0023] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0024] The memory chip 1 can be a DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory) chip. The memory chip 1 has a front and a back side facing each other, and a side connecting the front and back sides. The area of ​​the front and back sides is larger than the area of ​​the side side. Adjacent memory chips 1 can be stacked face-to-face, face-to-back, or back-to-back. In some embodiments, the front side of the memory chip 1 can also be understood as the active surface 13; the back side of the front side of the memory chip 1 can also be understood as the non-active surface opposite to the active surface 13.

[0025] refer to Figure 2The multiple storage modules 100 have the same number of storage chips 1, and the storage chips 1 of different storage modules 100 are arranged facing each other in the first direction X. The multi-layer storage modules 100 constitute multiple storage units 10b arranged in the second direction Y, and the storage unit 10b includes multiple storage chips 1 arranged in the first direction X. That is to say, the second wireless communication unit 11 and the wired communication unit 13 within the same storage unit 10b can form a communication path.

[0026] Continue to refer to Figure 2 In the first direction X, the multiple wired communication units 13 within the same storage module 100 have the same length. This facilitates the standardization of the manufacturing process of the multiple wired communication units 13 and improves the consistency of communication latency among the memory chips 1 within the same storage module 100. For example, the wired communication unit 13 can be an internal metal layer, such as aluminum, copper, or silver. The metal layer has low resistance, which helps reduce power consumption.

[0027] Multiple lower communication units 11b within the same storage module 100 are aligned in the second direction Y; multiple upper communication units 11a within the same storage module 100 are aligned in the second direction Y; and the second wireless communication units 11 within the top-level storage module 100 are aligned in the second direction Y. This improves the uniformity of the semiconductor structure and simplifies the manufacturing process. Furthermore, it allows for uniformity in the distance between adjacent second wireless communication units 11, improving the consistency of communication delay.

[0028] In the first direction X, two second wireless communication units 11, which are adjacent to each other and located on different memory chips 1, face each other directly. In other words, for two adjacent memory chips 1 in the first direction X, the lower communication unit 11b of the upper memory chip 1 faces the upper communication unit 11a of the lower memory chip 1. Compared to an oblique arrangement, a direct arrangement is beneficial for reducing the distance between the two adjacent second wireless communication units 11, thereby improving the quality and speed of communication.

[0029] Within the same memory chip 1, two second wireless communication units 11 are directly opposite each other in the first direction X, which helps to reduce the length of the wired communication unit 13 between them and shorten the communication delay.

[0030] The two second wireless communication units 11 within the non-top-level memory chip 1 are located at the upper and lower edges of the memory chip 1, respectively, which helps to reduce the distance between the two second wireless communication units 11 located in different memory chips 1, thereby improving communication quality and speed.

[0031] The second wireless communication unit 11 of the top-layer memory chip 1 is located at the lower edge of the memory chip 1. Compared to being located at the upper edge or the middle of the memory chip 1, being located at the lower edge is advantageous in reducing the distance between the second wireless communication unit 11 of the top-layer memory chip 1 and the second wireless communication unit 11 of the next-top-layer memory chip 1, thereby improving communication quality and speed.

[0032] The first wireless communication unit 31 is located at the edge of the logic chip 3 facing the memory chip 1. Compared to being located in the middle or at the lower edge of the logic chip 3, the first wireless communication unit 31 is located at the upper edge of the logic chip 3, which reduces the distance between it and the second wireless communication unit 11, thereby improving the quality and speed of wireless communication.

[0033] The non-top layer memory chip 1 has solder pads 52 and solder bumps 51, while the top layer memory chip 1 has solder bumps 51. The solder pads 52 are located on the top surface of the memory chip 1, and the solder bumps 51 are located on the bottom surface of the memory chip 1. It should be noted that the aforementioned top surface refers to the top surface of the memory chip 1 connected to the solder pads 52, and the aforementioned bottom surface refers to the bottom surface of the memory chip 1 connected to the solder bumps 51.

[0034] For two adjacent memory chips 1 in the first direction X, the solder bump 51 of the upper memory chip 1 is soldered to the solder pad 52 of the lower memory chip 1, and the solder bump 51 of the bottom memory chip 1 is soldered to the logic chip 3. For example, the upper surface of the logic chip 3 also has solder pads 52, which are soldered to the solder bump 51 of the bottom memory chip 1. A solder layer 53 is also present between the solder pads 52 and the solder bumps 51. That is, the soldering method helps to improve the robustness of the stacked memory modules 100.

[0035] For example, the solder bump 51 can protrude from the bottom surface of the memory chip 1, and the solder pad 52 can protrude from the top surface of the memory chip 1. That is, for two adjacent memory chips 1 in the first direction, the bottom surface of the upper memory chip 1 is spaced apart from the top surface of the lower memory chip 1. In this way, the distance between adjacent memory modules 100 can be appropriately increased, thereby improving the heat dissipation of the memory module 100.

[0036] In the first direction X, the ratio of the height of the solder pad 52 to the height of the memory chip 1 is 1:1250 to 1:1350, for example, 1:1300; the ratio of the height of the solder bump 51 to the height of the memory chip 1 is 1:210 to 1:230, for example, 1:220. When the ratios of the heights of the solder pad 52 and the solder bump 51 to the height of the memory chip 1 are within the above ranges, it is beneficial to improve the soldering strength and to keep the spacing between adjacent memory modules 100 within a reasonable range to facilitate heat dissipation.

[0037] The power supply method of memory chip 1 will be described in detail below.

[0038] It should be noted that, Figure 3 and Figure 2 These are different cross-sections of a semiconductor structure. Figure 3 The conductive via 41 and bonding portion 42 are shown, but the wired communication portion 13 is not shown. (Reference) Figure 3 At least one of the multiple memory chips 1 within the same memory module 100 has a power supply wiring layer 2; all memory chips 1 within at least one memory cell 10b have a power supply wiring layer 2; the power supply wiring layer 2 of the non-top-level memory chip 1 is electrically connected to the solder pad 52 and the solder bump 51; the power supply wiring layer 2 of the top-level memory chip 1 is electrically connected to the solder bump 51; the logic chip 3 has a power supply port 3a, and the solder bump 51 of the bottom-level memory chip 1 is electrically connected to the power supply port 3a.

[0039] In other words, the power supply wiring layer 2, solder pads 52, and solder bumps 51 connected within at least one memory cell 10b can form a power supply path. The solder pads 52 and solder bumps 51 not only connect adjacent memory modules 100 but also serve as a wired power supply structure for the memory chip 1. This wired power supply improves the stability and reliability of the power supply.

[0040] In some embodiments, reference Figure 5 , Figure 6 , Figure 8 , Figure 9 The power supply wiring layer 2 can extend along the active surface 13 of the memory chip 1. That is, the power supply wiring layer 2 is located on the front side of the memory chip 1. Therefore, after the components within the memory chip 1 are manufactured, the power supply wiring layer 2 can be manufactured using existing back-end processes, simplifying the process. Furthermore, the power supply wiring layer 2 can extend only near the upper and lower edges of the memory chip 1, without covering the entire active surface 13 of the memory chip 1. Therefore, the contact area between the power supply wiring layer 2 and the memory chip 1 is small, and the heat from the power supply wiring layer 2 has a smaller impact on the memory chip 1.

[0041] The width of the power supply wiring layer 2 in the second direction Y is smaller than the width of the solder bump 51 in the second direction Y; the width of the power supply wiring layer 2 in the second direction Y is smaller than the width of the solder pad 52 in the second direction Y. That is, the solder bump 51 and solder pad 52 have larger volumes, lower resistance, and are beneficial to improving soldering strength. In addition, it is also beneficial to increase the contact area between the solder bump 51 and solder pad 52 and the power supply wiring layer 2, thereby reducing contact resistance.

[0042] It should be noted that since wireless communication does not occupy space between adjacent storage modules 100, the wired power supply path can be flexibly arranged even if the area of ​​the opposite sides of adjacent storage modules 100 is small.

[0043] refer to Figure 5 , Figure 6 , Figure 8 , Figure 9 Each memory chip 1 has a power supply signal line 12, which is electrically connected to the power supply wiring layer 2. The connection relationship between the power supply signal line 12 and the power supply wiring layer 2 will be described in detail below.

[0044] Each memory chip 1 has multiple power supply signal lines 12. Different power supply signal lines 12 can provide different voltage signals, such as digital signals or analog signals, to the components within the memory chip 1. The power supply signal lines 12 can be ground signal lines 12G or power signal lines 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.

[0045] The power supply routing layer 2 can be a power routing layer 2P, a ground routing layer 2G, or a hybrid routing layer 2PG. That is, the power supply routing layer 2 within a memory chip 1 includes multiple isolated power supply lines 20. Based on the type of power supply lines 20 in each power supply routing layer 2, the power supply routing layer 2 can be divided into the three categories mentioned above. When all power supply lines 20 in the power supply routing layer 2 are power supply lines 20P, this power supply routing layer 2 is called a power supply routing layer 2P; when all power supply lines 20 in the power supply routing layer 2 are ground lines 20G, this power supply routing layer 2 is called a ground routing layer 2G; when the power supply routing layer 2 includes both ground lines 20G and power lines 20P, this power supply routing layer 2 is called a hybrid routing layer 2PG.

[0046] Grounding wiring 20G is electrically connected to grounding signal line 12G, and power wiring 20P is electrically connected to power signal line 12P. It should be noted that the multiple power wirings 20 within power wiring layer 2 are all mutually insulated, thus enabling the power signal lines 12 with different voltage signals to be led out separately.

[0047] If a memory chip 1 has its own power supply wiring layer 2, then at least some of the power supply signal lines 12 of this memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have its own power supply wiring layer 2, then the power supply signal lines 12 of this memory chip 1 can be led out through the power supply wiring layers 2 of other memory chips 1. In other words, this memory chip 1 can establish an electrical connection with other memory chips 1 through conductive vias 41 and bonding portions 42, thereby electrically connecting its own power supply signal lines 12 to the power supply signal lines 12 of other memory chips 1, and further electrically connecting to the power supply wiring layers 2 of other memory chips 1.

[0048] It is noteworthy that within the same storage cell 10b, power supply wiring 20 with the same voltage signal is electrically connected together via solder pads 52 and solder bumps 51, thereby providing this voltage signal to multiple storage chips 1 in the first direction X.

[0049] Multiple memory chips 1 can be stacked using a hybrid bonding method. For example, the surface of memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together by forces such as molecular forces. In addition, the surface of memory chip 1 can also have bonding portions 42, and adjacent bonding portions 42 are bonded together under heating conditions. That is, the dielectric layer 43 is an insulating material, which can play an isolation role; the bonding portion 42 is a conductive material, which can play an electrical connection role. Furthermore, the dielectric layer 43 also exposes the end face of the power supply wiring layer 2 facing or away from the logic chip 3, and covers the sides of the power supply wiring layer 2 except for the end face.

[0050] The following will provide a detailed explanation of the quantitative relationship between memory chip 1 and power supply wiring layer 2.

[0051] Example 1, for reference Figures 2-11 Each memory chip 1 has a power supply wiring layer 2, meaning the number of memory chips 1 is the same as the number of power supply wiring layers 2. Because there are many power supply wiring layers 2, sufficient lead-out locations can be provided for multiple power supply signal lines 12, simplifying the process of leading out the power supply signal lines 12. Furthermore, more power supply wiring layers 2 also help improve power supply stability, thereby improving the performance of the semiconductor structure. In addition, the power supply wiring layers 2 are uniformly arranged within multiple memory chips 1, thus facilitating the standardization of manufacturing processes for different memory chips 1 and reducing production costs.

[0052] In some embodiments, reference Figures 2-9 The storage module 100 includes multiple chipsets 10a, each chipset 10a including two adjacent storage chips 1, which are bonded together. Two power supply wiring layers 2 are located between the two storage chips 1 within the same chipset 10a, and these two power supply wiring layers 2 are respectively located on the surfaces of the two storage chips 1. Each power supply wiring layer 2 is electrically connected to both storage chips 1. That is, the two storage chips 1 of the chipset 10a are bonded face-to-face, i.e., active surfaces facing active surfaces; the two storage chips 1 of the same chipset 10a share the two power supply wiring layers 2 located between them.

[0053] Specifically, refer to Figure 3Each memory chip 1 has conductive vias 41, which are, for example, through-silicon vias (TSVs). Two memory chips 1 in the same chipset 10a are connected by a bonding portion 42, which connects to the conductive vias 41 of the two memory chips 1, thus electrically connecting the two memory chips 1. For example, each memory chip 1 has multiple spaced conductive vias 41, and each conductive via 41 is connected to a corresponding power supply signal line 12 within the memory chip 1. The voltage signals on the power supply signal lines 12 within the same memory chip 1 are different, and correspondingly, the voltage signals on the conductive vias 41 within the same memory chip 1 are also different. In the two memory chips 1 in the same chipset 10a, conductive vias 41 with the same voltage signal are electrically connected through the bonding portion 42, thereby electrically connecting the power supply signal lines 12 with the same voltage signal in the two memory chips 1 together.

[0054] For example, the conductive via 41 includes multiple ground vias 41G and multiple power vias 41P, and the bonding portion 42 includes multiple ground bonding portions 42G and multiple power bonding portions 42P. The ground vias 41G are connected to the ground bonding portions 42G, and the power vias 41P are connected to the power bonding portions 42P.

[0055] The conductive vias 41 of each memory chip 1 can be spaced apart in the third direction Z, which is perpendicular to the upper surface of the logic chip 3. For example, ground vias 41G and power vias 41P are alternately arranged in the third direction Z to reduce electromagnetic interference between adjacent conductive vias 41.

[0056] Figure 4 This is a bottom view of a storage module 100. Figures 5-6 These are schematic diagrams of the active surfaces 13 of the two memory chips 1 of chipset 10a, and... Figures 4-7 Corresponding to the same semiconductor structure. (Reference) Figures 4-7 Chipset 10a includes a first memory chip 1a and a second memory chip 1b. Both memory chips 1a have a first power supply signal line group 121 and a second power supply signal line group 122; the power supply signal lines 12 of both the first and second power supply signal line groups 121 and 122 include a power signal line 12P and a ground signal line 12G. The first power supply signal line group 121 of the two memory chips 1a is led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line group 122 of the two memory chips 1a is led out through the power supply wiring layer 2 of the second memory chip 1b. That is, both power supply wiring layers 2 of the same chipset 10a are hybrid wiring layers 2PG.

[0057] Continue to refer to Figure 4Within the hybrid cabling layer 2PG, grounding cabling 20G and power cabling 20P are alternately arranged in the third direction Z, which helps to reduce electromagnetic interference between adjacent power cabling 20.

[0058] Figure 7 This is a bottom view of a storage module 100. Figures 8-9 These are schematic diagrams of the active surfaces 13 of the two memory chips 1 of chipset 10a, and... Figures 7-9 Corresponding to the same semiconductor structure. (Reference) Figures 7-9 The power supply signal lines 12 of the first power supply signal line group 121 are all power signal lines 12P, and the power supply signal lines 12 of the second power supply signal line group 122 are all ground signal lines 12G. The first power supply signal line group 121 of the two memory chips 1 is led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line group 122 of the two memory chips 1 is led out through the power supply wiring layer 2 of the second memory chip 1a. That is, the two power supply wiring layers 2 of the same chipset 10a are the power wiring layer 2P and the ground wiring layer 2G, respectively. The first power supply signal line group 121 is electrically connected to the power wiring layer 2P, and the second power supply signal line group 122 is electrically connected to the ground wiring layer 2G.

[0059] Thus, based on Figures 4-9 It is known that each memory chip 1 has a first power supply signal line group 121 and a second power supply signal line group 122; both the first power supply signal line group 121 and the second power supply signal line group 122 include multiple power supply signal lines 12; two first power supply signal line groups 121 within the same chipset 10a are electrically connected to a power supply wiring layer 2, and two second power supply signal line groups 122 within the same chipset 10a are electrically connected to another power supply wiring layer 2. That is, the power supply wiring layer 2 is shared by the two power supply wiring layers 2 of the same chipset 10a.

[0060] The advantages of this design are mainly as follows: First, the shared power supply wiring layer 2 is located between the two memory chips 1, which can shorten the distance between the power supply wiring layer 2 and the two memory chips 1, thereby helping to reduce the high power consumption caused by long distances; Second, only the dielectric layer 43 for insulation can be set between adjacent chipsets 10a, thereby reducing the number of bonding parts 42 and simplifying the manufacturing process; Third, the power supply wiring layer 2 is shared by the two memory chips 1, and correspondingly, the number of power supply wiring 20, the number of solder bumps 51 and solder pads 52 are reduced, which helps to provide more space for solder bumps 51 and avoid short circuits; Fourth, only two memory chips 1 in the chipset 10a share the power supply wiring layer 2, that is, the number of memory chips 1 in the chipset 10a is small, which helps to ensure the stability of power supply.

[0061] refer to Figure 4 and Figure 7In the second direction Y, there is a first spacing d1 between two power supply wiring layers 2 within the same chipset 10a; a second spacing d2 between solder bumps 51 connected to different power supply wiring layers 2 within the same chipset 10a; and a third spacing between solder pads 52 connected to different power supply wiring layers 1 within the same chipset 10a. The ratio of the first spacing d1 to the second spacing d2 is 1:1 to 1.2:1. It should be noted that if the second spacing d2 and the third spacing are too large, it may waste space between adjacent memory chips 1; if the second spacing d2 and the third spacing are too small, it may cause incorrect electrical connections between adjacent solder bumps 51 and adjacent solder pads 52. Maintaining the spacing ratio within the above range is beneficial for balancing these two problems. For example, as... Figure 4 and Figure 7 As shown, the first spacing d1 can be the same as the second spacing d2.

[0062] refer to Figures 10-11 , Figure 10 This is a partial cross-sectional view. Figure 11 for Figure 10 The diagram shows a bottom view of the storage module 100. Power supply signal lines 12 within the same storage chip 1 are connected to the power supply wiring layer 2. The power supply wiring layers 2 of different storage chips 1 are independent of each other, and the power supply signal lines 12 of different storage chips 1 are also independent of each other. That is, the power supply signal lines 12 of multiple storage chips 1 do not need to be electrically connected together through conductive vias 41 and bonding portions 42. The power supply signal lines 12 within each storage chip 1 can be led out through the storage chip 1's own power supply wiring layer 2 without borrowing from the power supply wiring layers 2 of other storage chips 1. Since the power supply signal lines 12 of each storage chip 1 can be led out independently, it is beneficial to improve the stability of the power supply. Furthermore, the fabrication steps of the bonding portion 42 and conductive via 41 can be eliminated, thereby reducing production costs.

[0063] Continue to refer to Figure 11 For example, the power supply wiring layer 2 of each memory chip 1 can be a hybrid wiring layer 2PG, with power wiring 20P and ground wiring 20G alternately arranged in the third direction Z to reduce electromagnetic interference. In addition, multiple power supply wiring layers 2 can be formed on the same side of the memory chip 1, thereby unifying the manufacturing process of the power supply wiring layer 2.

[0064] Furthermore, the power supply wiring 20P of multiple memory chips 1 can be arranged in a straight line in the second direction Y, and the ground wiring 20G of multiple memory chips 1 can also be arranged in a straight line in the second direction Y. Alternatively, the power supply wiring 20P and the ground wiring 20G can be alternately arranged in a straight line in the second direction Y. This helps to improve the uniformity of the semiconductor structure and simplifies the manufacturing process.

[0065] Example 2: The number of power supply wiring layers 2 can be greater than the number of memory chips 1. For example, refer to... Figures 12-13 , Figure 12 This is a partial cross-sectional view. Figure 13 for Figure 12 The diagram shows a bottom view of the storage module 100. A power supply wiring layer 2 is provided between two adjacent storage chips 1, and this layer is electrically connected to the storage chips 1 on either side of it. The storage module 100 also has a power supply wiring layer 2 at both ends, which are electrically connected to the storage chips 1 on each end. In other words, except for the two power supply wiring layers 2 at the ends which are not shared by the storage chips 1, the remaining power supply wiring layers 2 in the middle are shared by the storage chips 1 on either side. The storage chips 1 at the beginning and end of the storage module 100 can also be understood as the outermost storage chips 1 on both sides of the storage module 100. The power supply wiring layer 2 located in the middle is connected to the power supply signal lines 12 of the two storage chips 1, which helps to reduce the number of solder bumps 51 and simplifies the manufacturing process. Furthermore, the power supply wiring layers 2 are distributed relatively uniformly within the storage module 100, which further simplifies the manufacturing process.

[0066] like Figure 13 As shown, in some embodiments, the power supply wiring layer 2 includes a power supply wiring layer 2P and a ground wiring layer 2G. The power supply wiring layer 2P includes a plurality of power supply lines 20P, and the ground wiring layer 2G includes a plurality of ground lines 20G. The power supply wiring layer 2P and the ground wiring layer 2G are arranged alternately in the first direction X. In other embodiments, all power supply wiring layers 2 may also be hybrid wiring layers 2PG, and the voltage signals of the power supply signal lines 12 led out from two adjacent hybrid wiring layers 2PG are different.

[0067] Continue to refer to Figures 12-13 The following example illustrates the sharing method of the power supply wiring layer 2. The power supply wiring layer 2P located on the first side of the storage module 100 can be directly connected to the power signal line 12P of the first storage chip 1a. Therefore, the first storage chip 1a may not have a power via 41P and a power bonding portion 42P. The first storage chip 1a and the second storage chip 1b share the ground wiring layer 2G, meaning their ground signal lines 12G are connected together through the ground via 41G and the ground bonding portion 42G, and are led out through the ground wiring layer 2G between them. The second storage chip 1b and the third storage chip 1c share the power supply wiring layer 2P, meaning their power signal lines 12P are connected together through the power via 41P and the power bonding portion 42P, and are led out through the power wiring layer 2P between them. Since the second storage chip 1b and the third storage chip 1c do not share the ground wiring layer 2G, their ground vias 41G and ground bonding portions 42G will not have an electrical connection.

[0068] In other words, if the power supply wiring layer 2 between two adjacent memory chips 1 is a power supply wiring layer 2P, then these two memory chips 1 are electrically connected through a power via 41P and a power bonding portion 42P. Similarly, if the power supply wiring layer 2 between two adjacent memory chips 1 is a ground wiring layer 2G, then these two memory chips 1 are electrically connected through a ground via 41G and a ground bonding portion 42G.

[0069] It is worth noting that since there is one more power supply wiring layer 2 than there are memory chips 1, one of the two power supply wiring layers 2 at the beginning and end does not need to extend along the active surface 13 of the memory chip 1, that is, it can be located on the back side of the memory chip 1. The remaining power supply wiring layers 2 are still located on the active surface 13 of the memory chip 1.

[0070] Example 3: The number of power supply wiring layers 2 can also be less than the number of memory chips 1. For example, refer to... Figures 14-15 , Figure 14 This is a partial cross-sectional view. Figure 15 for Figure 14 The diagram shows a bottom view of the storage module 100. At least two adjacent storage chips 1 are bonded together to form a chipset 10a; a power supply wiring layer 2 is provided between two adjacent chipsets 10a, and the power supply wiring layer 2 is electrically connected to the storage chips 1 of the chipsets 10a on both sides of it; the storage module 100 has a power supply wiring layer 2 at both ends, and is electrically connected to the chipsets 10a at both ends respectively.

[0071] In other words, except for the two power supply wiring layers 2 at the beginning and end that are not shared by chipset 10a, all the power supply wiring layers 2 in the middle position are shared by the chipsets 10a on both sides. One power supply wiring layer 2 in the middle position is connected to the power supply signal lines 12 of the two chipsets 10a. It is worth noting that the fewer the number of power supply wiring layers 2, the fewer the number of solder bumps 51. Therefore, it is beneficial to increase the distance between the solder bumps 51 and the coils in the first wireless communication unit 31 and the second wireless communication unit 11, thereby reducing electromagnetic interference generated by the solder bumps 51 and the coils and avoiding signal loss.

[0072] For example, each chipset 10a has two memory chips 1, and the power supply signal lines 12 with the same voltage signal in the two memory chips 1 are connected together through conductive vias 41 and bonding portions 42.

[0073] Continue to refer to Figures 14-15The following example illustrates the sharing method of power supply wiring layer 2. The first chipset 101 and the second chipset 102 share the ground wiring layer 2G, meaning their ground signal lines 12G are connected together through ground vias 41G and ground bonding portions 42G, and are led out through the ground wiring layer 2G between them. The first chipset 101 and the second chipset 102 do not share the power wiring layer 2P, therefore their power vias 41P and power bonding portions 42P are not electrically connected. The second chipset 102 and the third chipset 103 share the power wiring layer 2P, meaning their power signal lines 12P are connected together through power vias 41P and power bonding portions 42P, and are led out through the power wiring layer 2P between them.

[0074] In some embodiments, reference Figures 2-3 , Figure 10 , Figure 12 , Figure 14 The storage module 100 also has an insulating film 71 on its surface facing the logic chip 3. The insulating film 71 can also be located between adjacent solder bumps 51, thereby isolating the solder bumps 51. Furthermore, the insulating film 71 can be made of a material with good adhesion to fix the solder bumps 51. For example, the insulating film 71 can be a polyimide film. Polyimide films have excellent high and low temperature resistance, electrical insulation, and adhesion.

[0075] In some embodiments, a filler adhesive layer 72 is further provided between the logic chip 3 and the memory chip 1, and the filler adhesive layer 72 covers the solder bumps 51. In addition, the filler adhesive layer 72 may also cover the insulating film 71 and the solder pads 52. The filler adhesive layer 72 can fix the solder bumps 51 and the solder pads 52, thereby ensuring the connection strength between the memory module 100 and the logic chip 3.

[0076] In summary, the embodiments disclosed herein can improve the communication latency differences between different memory chips 1 and logic chips 3 caused by different communication distances. Furthermore, the power supply wiring layers 2 of the multiple memory chips 1 in the first direction X are connected together by solder bumps 51 and pads 52, and are connected to the power supply port of the logic chip 3 through the solder bumps 51 of the underlying memory module 100, thereby achieving wired power supply and improving power supply stability.

[0077] like Figure 16 As shown, another embodiment of this disclosure also provides a semiconductor device, which may include the semiconductor structure provided in the foregoing embodiments. For a detailed description of the semiconductor structure, please refer to the foregoing embodiments.

[0078] The semiconductor device includes: a substrate 8; a logic chip 3 disposed on the substrate 8, having a first wireless communication unit 31; a multilayer memory module 100 stacked on the upper surface of the logic chip 3 along a first direction X, the first direction X being perpendicular to the upper surface of the logic chip 3; the memory module 100 includes a plurality of memory chips 1 stacked in a second direction Y, the second direction Y being parallel to the upper surface of the logic chip 3; the top layer memory chip 1 has a second wireless communication unit 11; the non-top layer memory chips 1 have two second wireless communication units 11 arranged in the first direction X and a wired communication unit 13 connected between them; in the first direction X, two second wireless communication units 11 arranged adjacently and located in different memory chips 1 communicate wirelessly; the first wireless communication unit 13 communicates wirelessly with the second wireless communication unit 11 of the bottom layer memory chip 1 that is closest to it.

[0079] The substrate 8 provides electrical connection, protection, support, heat dissipation, and assembly for the logic chip 3 and the memory module 100. The logic chip 3 can be connected to the substrate 8 via solder balls 81. A power supply can be provided on the substrate 8, and the power supply port 3a of the logic chip 3 is connected to the power supply on the substrate 8 to supply power to the memory chip 1.

[0080] Another embodiment of this disclosure provides a method for manufacturing a semiconductor structure. This manufacturing method can be used to manufacture the semiconductor structure provided in the foregoing embodiments. Detailed descriptions of the semiconductor structure can be found in the foregoing embodiments.

[0081] Specifically, refer to Figure 17 The system provides a memory chip 1, within which a second wireless communication unit 11 and a wired communication unit 13 are fabricated. A power supply wiring layer 2 is formed on the surface of the memory chip 1, thereby leading power supply signal lines 12 to the edge of the memory chip 1. After forming the power supply wiring layer 2, a dielectric layer 43 covering the power supply wiring layer 2 and a bonding portion 42 located within the dielectric layer 43 are formed. By forming the bonding portion 42, multiple memory chips 1 are horizontally stacked and bonded using a hybrid bonding method to form a memory module 100. That is, during the stacking of the memory chips 1, the memory chips 1 are placed horizontally.

[0082] refer to Figure 3 The storage module 100 is rotated 90°, and solder bumps 51 are prepared on the side of the storage module 100. The solder bumps 51 are connected to the power supply wiring layer 2. Then, the storage module 100 is rotated 180°, and solder pads 52 are prepared on the side of the storage module 100. The solder pads are connected to the power supply wiring layer 2. The power supply wiring 2 of the different storage modules 100 are connected together in the first direction X via the solder bumps 51 and solder pads 52.

[0083] A logic chip 3 is provided, which has a power supply port 3a. The logic chip 3 is connected to the underlying storage module 100 via solder bumps 51, with the first direction X perpendicular to the upper surface of the logic chip 3.

[0084] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0085] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A logic chip having a first wireless communication unit; A multi-layer storage module is stacked on the upper surface of the logic chip along a first direction, the first direction being perpendicular to the upper surface of the logic chip; the storage module includes a plurality of storage chips stacked in a second direction, the second direction being parallel to the upper surface of the logic chip; The top-level memory chip has a second wireless communication unit; The non-top-level memory chip has two second wireless communication units arranged in the first direction and a wired communication unit connected between them; In the first direction, two second wireless communication units arranged adjacently and located in different memory chips communicate wirelessly; the first wireless communication unit communicates wirelessly with the second wireless communication unit closest to it in the underlying memory chip, and within the same memory chip, the two second wireless communication units face each other in the first direction.

2. The semiconductor structure according to claim 1, characterized in that, The lengths of the multiple wired communication units within the same storage module are the same.

3. The semiconductor structure according to claim 1, characterized in that, The two second wireless communication sections of the non-top-level memory chip are defined as the lower communication section and the upper communication section, respectively; The plurality of lower communication units within the same storage module are aligned in the second direction; The plurality of upper communication units within the same storage module are aligned in the second direction; The second wireless communication unit within the top-level storage module is aligned in the second direction.

4. The semiconductor structure according to claim 1, characterized in that, In the first direction, two second wireless communication units that are adjacent to each other and located on different memory chips face each other.

5. The semiconductor structure according to claim 1, characterized in that, The two second wireless communication sections within the non-top layer of the memory chip are located at the upper and lower edges of the memory chip, respectively.

6. The semiconductor structure according to claim 1, characterized in that, The second wireless communication unit of the top-layer memory chip is located at the lower edge of the memory chip.

7. The semiconductor structure according to claim 1, characterized in that, The first wireless communication unit is located at the edge of the logic chip facing the memory chip.

8. The semiconductor structure according to claim 1, characterized in that, The non-top layer of the memory chip has solder pads and solder bumps, while the top layer of the memory chip has solder bumps. The solder pads are located on the top surface of the memory chip, and the solder bumps are located on the bottom surface of the memory chip; For two adjacent memory chips in the first direction, the solder bump of the upper memory chip is soldered to the solder pad of the lower memory chip. The solder bumps of the underlying memory chip are soldered to the logic chip.

9. The semiconductor structure according to claim 8, characterized in that, Each of the memory chips has a power supply signal line; at least one of the multiple memory chips in the same memory module has a power supply wiring layer; the power supply signal line is electrically connected to the power supply wiring layer. The multilayer storage modules constitute a plurality of storage cells arranged in the second direction, and the storage cells include a plurality of storage chips arranged in the first direction; At least one of the memory cells has all of the memory chips having the power supply wiring layer; The power supply wiring layer of the non-top layer memory chip is electrically connected to the solder pads and the solder bumps; the power supply wiring layer of the top layer memory chip is electrically connected to the solder bumps. The logic chip has a power supply port, and the solder bumps of the underlying memory chip are electrically connected to the power supply port.

10. The semiconductor structure according to claim 9, characterized in that, The storage module includes multiple chipsets, each chipset including two adjacent storage chips, and the two adjacent storage chips are bonded together. Two power supply wiring layers are provided between two memory chips within the same chipset, and the two power supply wiring layers are respectively located on the surface of the two memory chips; each power supply wiring layer is electrically connected to the two memory chips.

11. The semiconductor structure according to claim 10, characterized in that, Each of the power supply cabling layers includes multiple power supply cabling and multiple grounding cabling; The power supply wiring and the ground wiring of the same power supply wiring layer are arranged alternately in a third direction, which is perpendicular to the first direction and the second direction.

12. The semiconductor structure according to claim 9, characterized in that, At least two adjacent memory chips are bonded together to form a chipset; A power supply wiring layer is provided between two adjacent chipsets, and the power supply wiring layer is electrically connected to the memory chips of the chipsets on both sides of it; The storage module has a power supply wiring layer on both the first and last sides of the second direction arrangement, and is electrically connected to the chipset on both the first and last sides respectively.

13. The semiconductor structure according to claim 9, characterized in that, The width of the power supply wiring layer in the second direction is smaller than the width of the welding bump in the second direction; The width of the power supply wiring layer in the second direction is smaller than the width of the solder pad in the second direction.

14. The semiconductor structure according to claim 9, characterized in that, In the first direction, the ratio of the height of the solder pad to the height of the memory chip is 1:1250 to 1:1350; the ratio of the height of the solder bump to the height of the memory chip is 1:210 to 1:

230.

15. A semiconductor device, characterized in that, include: substrate; A logic chip, disposed on the substrate, has a first wireless communication unit; A multi-layer storage module is stacked on the upper surface of the logic chip along a first direction, the first direction being perpendicular to the upper surface of the logic chip; the storage module includes a plurality of storage chips stacked in a second direction, the second direction being parallel to the upper surface of the logic chip; The top-level memory chip has a second wireless communication unit; The non-top-level memory chip has two second wireless communication units arranged in the first direction and a wired communication unit connected between them; In the first direction, two second wireless communication units arranged adjacently and located in different memory chips communicate wirelessly; the first wireless communication unit communicates wirelessly with the second wireless communication unit closest to it in the underlying memory chip, and within the same memory chip, the two second wireless communication units face each other in the first direction.

Images