Ultra-high speed transmitter
By combining hierarchical serialization, time-interleaved digital-to-analog conversion, and tailless current rudder structure, the stability, power consumption, and signal quality problems of traditional transmitters in ultra-high-speed data transmission are solved, and efficient ultra-high-speed data transmission is achieved.
CN122339489APending Publication Date: 2026-07-03SHANGHAI FORMULA MICROELECTRONICS CO LTD
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Patent Information
- Application Number
- CN202510009209.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2026-07-03
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Figure CN122339489A_ABST
Abstract
This application relates to the field of ultra-high-speed data transmitter circuits in wired communication systems, and discloses an ultra-high-speed transmitter based on a 2:1 multiplexer and time-interleaved DAC architecture. The transmitter includes: a serializer circuit employing a two-stage serialization structure, with the first stage consisting of multiple 8:1 serializers and the second stage consisting of multiple 2:1 multiplexers; a time-interleaved digital-to-analog converter containing multiple DAC subunits employing a tailless current rudder structure; and a clock generation circuit generating clock signals at different rates for controlling the serializer and DAC. This invention achieves ultra-high-speed data transmission of 100Gbps or even 200Gbps and above through a hierarchical serialization and time-interleaved architecture, while effectively reducing system power consumption.
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