Multifunctional integrated interposer and photoelectric collaborative packaging module
By embedding silicon bridges and photonic integrated chips in the dielectric body and using embedded USR protocol processing, the problems of low integration and limited transmission rate in existing optoelectronic co-packaging technologies are solved, realizing high-density, low-loss optoelectronic co-packaging and supporting ultra-high-speed data transmission.
Patent Information
- Application Number
- CN202610612577.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-07
- Publication Date
- 2026-06-05
- Estimated Expiration
- 2046-05-07
AI Technical Summary
Existing optoelectronic co-packaging technologies suffer from low integration of silicon bridges and photonic integrated chips, reliance on external modules for high-speed interface protocol processing, limited transmission rates, and unreasonable multi-chip collaborative layouts. These issues result in long interconnect paths, low integration, severe signal crosstalk and thermal interference, making it difficult to support ultra-high-speed transmission of 224Gbps PAM4 and above.
A multifunctional integrated interposer layer is adopted to embed silicon bridges and photonic integrated chips in the dielectric body in a coplanar manner. Through staggered distribution and rewiring structure, a high degree of integration of high-density, low-loss physical wiring channel circuits and photoelectric conversion functions is achieved. The USR ultra-high-speed interface protocol is embedded in the accelerated computing chip, and the layout of electronic integrated chips and photonic integrated chips is optimized.
It significantly shortens the interconnection path between chips, reduces transmission loss and latency, improves integration and signal integrity, simplifies system structure, supports ultra-high-speed transmission of 224Gbps and above, and reduces power consumption and signal attenuation.