Pin interrupt simulation device for vehicle electronic test

Abstract

The utility model discloses a kind of pin interrupt simulation devices for vehicle-mounted electronic testing, belong to vehicle-mounted electronic testing field, including power module, FPGA module, reference measurement module, load and protection module, control and communication module, measured piece, signal processing module, each module is connected through standardization interface.This utility model realizes the interruption of power line and signal line, plug-in simulation test by modularization processing, FPGA integrated operation, suitable for the reliability test of vehicle-mounted electronic equipment, with super high-speed response, multi-standard dynamic compatibility, programmable flexibility is high, equipment life cycle is long, multi-channel high-precision synchronous test, low-power miniaturization processing and the like advantages.

Description

Technical Field

[0001] This utility model relates to the technical field of automotive electronic testing equipment, specifically to a pin interruption simulation device for simulating power line and signal line interruption and plug-in / plug-out tests, which is suitable for electrical performance testing and meets various automotive standard requirements. Background Technology

[0002] In the research and development and reliability testing of automotive electronic devices, interruption testing of power lines and signal lines is a crucial step in verifying the device's anti-interference capability. Existing traditional interruption testing equipment suffers from the following technical bottlenecks:

[0003] Insufficient switching response speed: It cannot meet the high-speed test requirement of switching time <200ns in the GM3172 standard, which makes it impossible to simulate high-frequency micro-interrupt scenarios;

[0004] Poor compatibility with multiple standards: It is difficult to adapt to different testing standards such as LV124 and ISO16750-2 at the same time, requiring multiple devices to work together, which is costly and inefficient.

[0005] Low waveform adjustment accuracy: The adjustment range of interrupt time and edge characteristics is limited, making it impossible to accurately reproduce complex fault scenarios such as contact failure and relay bounce.

[0006] When testing standards are updated and iterated, the testing equipment needs to be completely replaced, resulting in high equipment costs.

[0007] Insufficient integration: It lacks the ability to test signals and power supplies together, and cannot meet the requirements of multi-channel parallel testing of automotive electronics. Summary of the Invention

[0008] Purpose of the invention

[0009] To address the aforementioned problems, this utility model provides a pin interrupt simulation device for vehicle-mounted electronic testing.

[0010] Technical solution

[0011] Preferably, a pin interrupt simulation device for vehicle-mounted electronic testing includes: a power supply module, an FPGA module, a reference measurement module, a load and protection module, a control and communication module, a signal processing module, and a device under test.

[0012] Preferably, the power module is adapted to 0-80V DC power input, providing ±80V operating voltage for the load and protection module and FPGA module, supporting 12V / 24V / 48V system testing, and the maximum output current is selectable at 50A / 100A.

[0013] Preferably, the FPGA module consists of an external interaction layer, a core control layer, an interface and driver layer, and auxiliary function modules.

[0014] Preferably, the core control layer includes:

[0015] The clock management module (CMT) supports differential clock input and can be multiplied to ≥500MHz via PLL / DCM;

[0016] High-precision timer with timing resolution <1ns, capable of generating interrupt signals of any duration within the range of 1μs to 60s;

[0017] A multi-channel synchronous trigger array enables sub-nanosecond-level synchronization of 16-channel signal interruptions (channel deviation <50ps);

[0018] The state machine control unit parses instructions from the external interaction layer and configures the parameters of each functional unit.

[0019] Preferably, the power switch drive unit includes:

[0020] DC+ / DC- switching drive circuit, using LVDS signal to directly drive external MOSFET / IGBT, switching time <150ns; normally closed switch controller, supports independent configuration of rise / fall time (adjustable from 100ns to 1μs);

[0021] Optocoupler-isolated drive circuits achieve electrical isolation between control signals and power circuits.

[0022] Preferably, the interface and driver layer include:

[0023] DC+ / DC- switching drive circuit, using LVDS signal to directly drive external MOSFET / IGBT, switching time <150ns; normally closed switch controller, supports independent configuration of rise / fall time (adjustable from 100ns to 1μs);

[0024] Optocoupler-isolated drive circuit to achieve electrical isolation between control signals and power circuit;

[0025] 16-channel differential signal processing circuitry, with each channel integrating programmable impedance matching (50Ω / 75Ω / 100Ω optional).

[0026] Preferably, the external interaction layer includes:

[0027] The SPI / I2C communication interface receives configuration commands from the control and communication module and provides feedback on the working status.

[0028] The bus protocol sensing module can identify the frame structure of protocols such as CAN / LIN / SPI and trigger an interrupt at a specific frame bit;

[0029] The reference measurement interface is connected to a 1kΩ / 10Ω resistor of the reference measurement module via a relay switching control circuit.

[0030] Preferably, the auxiliary function module includes:

[0031] The overcurrent detection comparator has its input signal directly connected to the dedicated interrupt pin of the FPGA.

[0032] Emergency power-off trigger, with a total response time of <50ns from overcurrent detection to power-off completion;

[0033] Dual watchdog timers monitor the FPGA's internal logic and the external system clock, respectively.

[0034] ESD protection circuitry is integrated into all input / output interfaces, with an electrostatic protection level of ≥±8kV.

[0035] Preferably, the DC+ and DC- switch drive output terminals are connected in parallel to the positive and negative power supply interfaces of the device under test, and the normally closed switch drive circuit is connected in series in the DC+ circuit and is turned on by default.

[0036] Preferably, the FPGA module receives control signals from the control and communication module (105) through the SPI / I2C interface of the external interaction layer, parses and configures the parameters of each functional unit through the state machine of the core control layer, and simultaneously feeds back the working status to the host computer in real time through a dedicated status feedback interface.

[0037] Preferably, the reference measurement module includes 1kΩ and 10Ω low-inductance reference resistors, used to verify that the switch response time is ≤10μs before testing. The resistors are connected in parallel across the interface of the device under test through a relay switching circuit. During testing, the relay is energized, and the resistors replace the device under test in the circuit. The resistors are made using a non-inductive winding process, with a connecting cable length of <10cm and a parasitic inductance of <1nH, ensuring the accuracy of the reference measurement.

[0038] Preferably, the 16 independent signal line channels in the signal processing module support automatic switching, the interrupt time can be set from 1μs to 60s, the time accuracy reaches ±100ps, and the rise / fall time under a 100Ω load is <200ns.

[0039] Preferably, the load and protection module includes:

[0040] Bleeding resistor (S2): Optional open circuit, 0Ω, 0.1Ω, 1Ω, 100Ω, used for circuit protection and parameter adjustment;

[0041] Short circuit protection: Built-in overcurrent protection circuit to prevent equipment damage during testing.

[0042] Preferably, the control and communication module has a host computer interface (RS-485 / 232, LAN), supports the Modbus protocol, and realizes automated control of the test process. It sends switch on / off commands (TTL level), controls the switch timing through the SPI interface, configures parameters such as interrupt time and channel switching through the I2C interface, controls the switching of the bleeder resistor through the PWM signal, receives overcurrent protection feedback signals, and all signal interfaces are equipped with TVS diodes to prevent electrostatic discharge.

[0043] Beneficial effects

[0044] 1. Ultra-high speed response capability: The FPGA module reduces the switching control delay from the traditional 500ns level to <150ns, meeting the stringent requirement of <200ns in the GM3172 standard, and can simulate high-frequency faults such as relay contact bounce (100μs level).

[0045] 2. Dynamic compatibility with multiple standards: Supports 10+ industry standards such as LV124, ISO16750-2, and LV148 via FPGA firmware upgrades.

[0046] During the LV124 test, the interrupt time was configured to be 50ms and the edge time to be 200ns.

[0047] During ISO16750-2 testing, a high-frequency interrupt sequence with a 100μs interval is generated.

[0048] Programmable flexibility: Supports user-defined interrupt waveforms (such as square waves and sawtooth waves), and enables the implementation of special test scenarios (such as pulse interference simulation of autonomous driving sensors) through Verilog programming.

[0049] No hardware modifications are required during the device's lifecycle to adapt it to new standards via the FPGA module.

[0050] 5. High-precision synchronization test: The synchronization deviation between 16 signal channels is <50ps, which can simulate the extreme working condition of multiple sensors in the vehicle electronic system being disconnected at the same time, and test the fault tolerance capability of the ADAS system.

[0051] 6. Low power consumption and miniaturization: The FPGA uses nanometer technology, which reduces power consumption by 40% compared to the traditional MCU + driver circuit solution. It is integrated into a 19-inch 2U rack, reducing the size by 50%, making it suitable for compact layouts in vehicle-mounted laboratories. Attached Figure Description

[0052] Figure 1 A schematic diagram of a test circuit for a pin interrupt simulation device provided in an embodiment of this disclosure.

[0053] Figure 2 This is a diagram of the internal architecture of the FPGA module (102) provided in an embodiment of the present disclosure.

[0054] In the diagram: 101. Power supply module, 102. FPGA module, 103. Reference measurement module, 104. Load and protection module, 105. Control and communication module, 106. Signal processing module, 107. Device under test. Detailed Implementation

[0055] The embodiments of the present invention will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the present invention.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0057] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0058] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0059] In the research and development and reliability testing of automotive electronic devices, interruption testing of power lines and signal lines is a crucial step in verifying the device's anti-interference capability. Existing technologies, traditional interruption testing equipment suffer from the following technical bottlenecks: 1. Insufficient switching response speed: Unable to meet the high-speed testing requirement of <200ns switching time in the GM3172 standard, resulting in the inability to simulate high-frequency micro-interruption scenarios; 2. Poor multi-standard compatibility: Difficult to simultaneously adapt to different testing standards such as LV124 and ISO16750-2, requiring multiple devices to work together, resulting in high cost and low efficiency; 3. Low waveform adjustment accuracy: Limited adjustment range for interrupt time and edge characteristics, unable to accurately reproduce complex fault scenarios such as contact failures and relay bounce; 4. Requires complete replacement of testing equipment with each update of testing standards, leading to high equipment costs; 5. Insufficient integration: Lacks signal and power supply collaborative testing capabilities, failing to meet the multi-channel parallel testing needs of automotive electronics.

[0060] Example 1

[0061] To address the aforementioned issues, embodiments of this invention provide a pin interrupt simulation device for automotive electronic testing. Through modular processing and FPGA integration, it achieves interrupt and plug-in simulation testing of power lines and signal lines, making it suitable for reliability testing of automotive electronic equipment. It offers advantages such as ultra-high-speed response, dynamic compatibility with multiple standards, high programmability and flexibility, long device lifespan, multi-channel high-precision synchronous testing, and low-power miniaturization.

[0062] To make the objectives, technical solutions, and advantages of this utility model clearer, the following describes specific embodiments and refers to the appendix. Figure 1 , 2 The present invention will be further described in detail below.

[0063] Specifically, such as Figure 1 As shown, the pin interrupt simulation device includes a power supply module (101), an FPGA module (102), a reference measurement module (103), a load and protection module (104), a control and communication module (105), a signal processing module (106), and a device under test (107). Each module is connected through a standardized interface. The FPGA module (102) consists of a core control layer, an interface and driver layer, an external interaction layer, and auxiliary function modules.

[0064] Specifically, the power module (101) is adapted to 0-80V DC power input, providing ±80V operating voltage for the load and protection module (104) and FPGA module (102), supporting 12V / 24V / 48V system testing, with a maximum output current of 50A / 100A selectable, and is connected to the FPGA module (102) via a silicone rubber cable to form a low-inductance main circuit (parasitic inductance <5nH).

[0065] Specifically, such as Figure 2 As shown, the FPGA module (102) consists of a core control layer, an interface and driver layer, an external interaction layer, and auxiliary function modules. The functions and relationships of each layer are as follows:

[0066] Specifically, the core control layer consists of a high-speed timing control unit, a power switch drive unit, a signal processing control unit, a protection logic unit, and a reference measurement interface unit, serving as the "brain" of the FPGA functions: the high-speed timing control unit provides a 500MHz reference clock through a PLL clock generator to achieve a timing resolution of <1ns and outputs synchronization control signals to other units; the power switch drive unit receives the timing control signals and controls the external MOSFET switch through an LVDS drive circuit and an optocoupler isolation unit to achieve high-speed switching of the DC+ / DC- loop within <150ns; the signal processing control unit integrates differential signal conditioning and impedance matching circuits to control the interrupt timing of 16 signal line channels and supports 200ns edge time adjustment;

[0067] The protection logic unit monitors the current in real time through the overcurrent signal acquisition circuit and triggers the emergency power-off drive with a response time of <50ns.

[0068] The reference measurement interface unit drives the relay to switch the reference resistor group, which, together with the load matching adjustment unit, ensures measurement accuracy.

[0069] Specifically, the interface and driver layer is responsible for the "physical connection" between internal signals and external circuits, realizing signal isolation, driving and conditioning: the optocoupler isolation unit realizes the electrical isolation between control signals and power circuits, preventing high voltage interference from entering the FPGA;

[0070] The impedance matching module optimizes the transmission quality of high-speed signals (such as 500MHz clock and LVDS drive signals) and reduces reflection loss; the 16-channel differential drive circuit supports programmable impedance matching (50Ω / 75Ω / 100Ω selectable) to adapt to different test load requirements.

[0071] Specifically, the external interaction layer acts as a "communication bridge" between the FPGA and other modules of the system. It interacts with the control and communication module (105) through the SPI / I2C communication interface and receives instructions such as interrupt time and channel configuration. It has a built-in status register group to store real-time working parameters (such as current switch status, remaining interrupt time, and fault code). When feeding back the status to the host computer, it implements data updates with a cycle of <1ms through a dedicated status feedback interface.

[0072] Specifically, the auxiliary function modules provide a "basic guarantee" for the stable operation of the FPGA: the PLL clock generator provides a 500MHz reference clock for the core control layer, supporting flexible configuration of frequency multiplication / division; the dual watchdog timers monitor the internal logic of the FPGA (to prevent program crashes) on one side and monitor the external system clock on the other side (to ensure timing synchronization); the ESD protection circuit is integrated into all input and output interfaces, meeting the ±8kV electrostatic protection level and adapting to the electromagnetic compatibility requirements of the vehicle testing environment.

[0073] Specifically, the reference measurement module (103) includes 1kΩ and 10Ω low-inductance reference resistors to verify that the switching response time is ≤10μs before testing. The resistors are connected in parallel across the interface of the device under test (107) via a relay switching circuit. During testing, the relay is activated, and the resistors replace the device under test (107) in the circuit. The resistors are made using a non-inductive winding process, with a connecting cable length of <10cm and a parasitic inductance of <1nH, ensuring the accuracy of the reference measurement.

[0074] Specifically, the load and protection module (104) implements circuit protection and parameter adjustment: the discharge resistor can be selected as open circuit, 0Ω, 0.1Ω, 1Ω, or 100Ω, and is connected in parallel to the output of the power module (101) through a multi-channel analog switch to dynamically switch the resistance value; the short circuit protection has a built-in overcurrent protection circuit, and the overcurrent detection chip is connected in series in the main power circuit. When the current is detected to be too high, a high level is output to the control and communication module (105), which triggers the protection logic unit of the FPGA module (102) to disconnect the power supply to avoid damage to the equipment.

[0075] Specifically, the control and communication module (105) serves as the "system hub": it has a host computer interface (RS-485 / 232, LAN), supports the Modbus protocol, and realizes automated control of the test process; it sends switch on / off commands (TTL level) through the SPI interface to control the switch timing (accuracy ±100ps); it configures parameters such as interrupt time and channel switching through the I2C interface (adjustment range 1μs~60s); it receives overcurrent protection feedback signals and links the FPGA module (102) to perform emergency power-off; the signal interface is equipped with TVS diodes to prevent electrostatic discharge (protection level ±8kV).

[0076] It should be noted that the host computer may include devices such as computers and smart mobile terminals. When communicating with the host computer through the control and communication module (105), it can both receive data and / or instructions from the host computer and send data to the host computer.

[0077] Specifically, the signal processing module (106) includes 16 independent signal line channels: it supports automatic switching, the interrupt time can be set from 1μs to 60s, and the time accuracy reaches ±100ps; the rise / fall time under 100Ω load is <200ns, which meets the test requirements of edge characteristics of standards such as GM3172 and LV124; it has a bus protocol awareness function, which can identify the frame structure of protocols such as CAN / LIN / SPI, trigger an interrupt at a specific frame position, and simulate a real communication fault scenario.

[0078] Example 2

[0079] Optionally, the FPGA module architecture can be replaced with an ASIC + logic circuit solution. For cost-sensitive and functionally fixed automotive testing scenarios, the original FPGA layered architecture can be replaced with an ASIC chip + discrete logic circuit solution, as follows: Application-specific integrated circuits (ASICs) are used to implement core timing control, paired with discrete logic chips (such as flip-flops and counters) to complete interface driving, reducing cost and power consumption, making it suitable for mass-production standardized testing equipment. The original core control layer (timing / driving) is replaced with an ASIC chip (customized RTL logic), which can generate 1ns resolution interrupt timing; the interface and driving layer is replaced with 74 series logic chips; the external interaction layer is replaced with a dedicated SPI interface chip; and the auxiliary function modules are replaced with independent watchdog chips to achieve dual watchdog and ESD protection integration.

[0080] Optionally, the ASIC chip is custom-built with the "16-channel synchronous interrupt timing generation" logic, removing the redundant functions of the FPGA, which can reduce costs by 30%; the timing accuracy can still be maintained at 1ns, meeting the <200ns switching time requirements of standards such as GM3172.

[0081] Optionally, in the discrete logic circuit, LVDS to TTL level conversion is implemented using 74 series logic chips, and 50Ω / 75Ω impedance matching is completed with a resistor network; the power switch drive circuit is replaced by a MOSFET gate drive chip instead of the FPGA built-in driver.

[0082] Optionally, the SPI communication protocol is implemented in hardware using a dedicated SPI interface chip for communication and protection, replacing the FPGA soft core and reducing communication latency by 20ns; an independent watchdog chip monitors system reset, and ESD protection is integrated through PCB copper plating and TVS array, resulting in lower cost.

[0083] Therefore, the replaced interrupt simulation device is more suitable for mass production line scenarios of vehicle-mounted test equipment with fixed functions, cost sensitivity, and high reliability requirements.

[0084] Example 3

[0085] Optionally, the load and protection module can be replaced with a solid-state relay. To meet the requirements of high-frequency and long-life testing, the original "MOSFET switch + analog circuit protection" solution can be replaced with a "solid-state relay (SSR) + digital protection" solution.

[0086] Specifically, solid-state relays (without mechanical contacts) are used to extend the lifespan of switches (>10). 8 It features millisecond-level overcurrent protection when paired with a digital signal processor (DSP), making it suitable for high-frequency cyclic testing scenarios.

[0087] Specifically, the power switch driver is replaced with a solid-state relay, which has no contacts and theoretically increases the lifespan by 100 times; the overcurrent protection is replaced with a DSP digital controller, and the bleeder resistor switch is replaced with a digital potentiometer. After the replacement, the overcurrent detection delay is <1ms, and the resistance value is controlled by software from 0Ω to 100Ω.

[0088] Specifically, the solid-state relay supports 50A / 24V DC switching, has an on-resistance of 0.01Ω (close to MOSFET), and a switching time of 150ns (meets standard requirements); the FPGA external interaction layer controls the SSR enable signal, which can effectively improve the switching life by replacing the original MOSFET drive logic.

[0089] Specifically, the DSP digital controller collects the power supply loop current in real time (sampling rate 1MHz). When an overcurrent (>100A) is detected, a shutdown command is sent to the FPGA within 1ms. In conjunction with the FPGA protection logic unit, dual protection of "DSP fast detection + FPGA timing control" is achieved.

[0090] Specifically, the digital potentiometer supports I2C programmable resistance (0Ω~100Ω continuously adjustable), replacing the original multi-channel analog switch; the control and communication module can dynamically adjust the bleed resistor via I2C commands to adapt to different test loads.

[0091] Therefore, the replaced interrupt simulation device is suitable for applications requiring high frequency (>10). 6 Scenarios such as interruption testing and aging testing of vehicle components with long service life (>5 years), such as durability testing of vehicle ECU power modules.

[0092] The FPGA module (102) achieves decoupling of high-speed control and external interaction through a layered design: the core control layer focuses on nanosecond-level timing accuracy (<1ns resolution), and the interface layer ensures signal integrity (impedance matching, optocoupler isolation) and safety (ESD protection), which is suitable for the high reliability requirements of automotive electronic testing.

[0093] The above embodiments are merely exemplary embodiments of this utility model and are not intended to limit this utility model. The scope of protection of this utility model is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to this utility model within its substance and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this utility model.

Claims

1. A pin interrupt simulation device for in-vehicle electronic testing, characterized by, It includes a power supply module (101), an FPGA module (102), a reference measurement module (103), a load and protection module (104), a control and communication module (105), a signal processing module (106), and a device under test (107), wherein: The FPGA module (102) consists of an external interaction layer, a core control layer, an interface and driver layer, and an auxiliary function module; The power module (101) consists of a DC power input interface and a voltage regulation circuit; The reference measurement module (103) consists of a 1kΩ and a 10Ω low inductance resistor; The load and protection module (104) consists of a bleed resistor and a short-circuit protection circuit; The control and communication module (105) consists of an RS-485 / 232 interface, a LAN interface, and a Modbus protocol control unit; The signal processing module (106) consists of 16 independent signal line channels, a switching circuit, and a load resistor.

2. The pin interrupt simulation device for vehicle electronic test according to claim 1, characterized in that, The power module (101) adopts a reverse connection protection terminal, and the DC output terminal is connected to the input terminal of the FPGA module (102) through a cable to form a main power circuit.

3. The pin interrupt simulation device for testing vehicle electronics according to claim 1, wherein, The core control layer of the FPGA module (102) includes: The clock management module (CMT) supports differential clock input and frequency multiplication to ≥500MHz via PLL / DCM; High-precision timer with timing resolution <1ns, capable of generating interrupt signals of any duration within the range of 1μs to 60s; A multi-channel synchronous trigger array enables sub-nanosecond-level synchronization with inter-channel deviation of <50ps for 16-channel signal interruption. The state machine control unit parses instructions from the external interaction layer and configures the parameters of each functional unit.

4. The pin interrupt simulation device for testing vehicle electronics according to claim 1, wherein, The interface and driver layer of the FPGA module (102) includes: DC+ / DC- switching drive circuit, which uses LVDS signal to directly drive external MOSFET / IGBT, with a switching time of <150ns; Normally closed switch controller, supporting rise / fall time range of 100ns~1μs; Optocoupler-isolated drive circuit to achieve electrical isolation between control signals and power circuit; 16-channel differential signal processing circuitry, with each channel integrating programmable impedance matching, with impedance matching options of 50Ω, 75Ω, or 100Ω.

5. The pin interrupt simulation device for testing vehicle electronics according to claim 1, wherein, The external interaction layer of the FPGA module (102) includes: The SPI / I2C communication interface receives configuration commands from the control and communication module (105) and provides feedback on the working status. The bus protocol sensing module can identify the frame structure of CAN / LIN / SPI protocols and trigger an interrupt at a specific frame bit; The reference measurement interface is connected to the 1kΩ / 10Ω resistor of the reference measurement module (103) via a relay switching control circuit.

6. The pin interrupt simulation device for testing vehicle electronics according to claim 1, wherein, The auxiliary function modules of the FPGA module (102) include: The overcurrent detection comparator has its input signal directly connected to the dedicated interrupt pin of the FPGA. Emergency power-off trigger, with a total response time of <50ns from overcurrent detection to power-off completion; Dual watchdog timers monitor the FPGA's internal logic and the external system clock, respectively. ESD protection circuitry is integrated into all input / output interfaces, with an electrostatic protection level of ≥±8kV.

7. The pin interrupt simulation device for vehicle-mounted electronic testing according to claim 1, characterized in that, The DC+ and DC- switch drive output terminals of the FPGA module (102) are connected in parallel to the positive and negative power supply interfaces of the device under test (107), and the normally closed switch drive circuit is connected in series in the DC+ loop and is on by default.

8. The pin interrupt simulation device for vehicle-mounted electronic testing according to claim 1, characterized in that, The FPGA module (102) uses the SPI / I2C control signal of the external interaction layer to parse and configure the parameters of each functional unit through the state machine of the core control layer; at the same time, it uses a dedicated status feedback interface to provide real-time feedback of the working status to the host computer.

9. A pin interrupt simulation device for vehicle-mounted electronic testing according to claim 1, characterized in that, The resistor of the reference measurement module (103) is connected in parallel across the interface of the device under test (107) via a relay switching circuit. During testing, the relay is activated, and the resistor replaces the device under test (107) in the circuit. The resistor uses a non-inductive winding process, with a connecting cable length of <10cm and a parasitic inductance of <1nH, ensuring the accuracy of the reference measurement.

10. A pin interrupt simulation device for vehicle-mounted electronic testing according to claim 1, characterized in that, The discharge resistor of the load and protection module (104) is connected in parallel to the output terminal of the power module (101) through a multi-channel analog switch, and the resistance value can be dynamically switched; the overcurrent detection chip is connected in series in the main power circuit. When the current is detected to be too high, it outputs a high level to the control and communication module (105) to trigger the FPGA module (102) to disconnect the power supply.

11. A pin interrupt simulation device for vehicle-mounted electronic testing according to claim 1, characterized in that, The control and communication module (105) sends switch on / off commands: TTL level, controls the switch timing through the SPI interface; configures the interrupt time and channel switching parameters through the I2C interface; controls the switching of the bleeder resistor through the PWM signal; and receives the overcurrent protection feedback signal.

12. The pin interrupt simulation device for vehicle-mounted electronic testing according to claim 1, characterized in that, The signal interfaces of the control and communication module (105) are all equipped with TVS diodes to prevent electrostatic discharge.

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