Referenceless background calibration method for ultra-high-speed TIADC based on least mean square root

Abstract

This invention provides a reference-free background calibration method for ultra-high-speed TIADCs based on minimum mean square (RMS) calibration. It employs a decimation-calibration-interpolation calibration mode. The original quantized data is decimated using a specific decimation rate to obtain multiple quantization code sets. A step-by-step grouping calibration algorithm is used based on the number of interleaved channels, selecting the first quantization code set for step-by-step calibration. Each step involves grouping the data and using a dual-channel synchronous detection method based on a binary search to search for the clock jitter value of each channel in the grouped quantized data. Other quantization code sets are then compensated using a first-order Taylor approximation in the digital domain based on the clock jitter value of the first quantization code set. Finally, the compensated multiple quantization code sets are re-interpolated to obtain the calibrated result of the original data. This invention eliminates the need for a reference channel, minimizing the RMS of the detected clock jitter value and thus improving compensation accuracy.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design, specifically relating to a background calibration method for a time-domain interleaved ultra-high-speed analog-to-digital converter based on the least mean square root. Background Technology

[0002] In ultra-high-speed ADCs, the time-domain interleaving structure enables M single-channel ADCs with slower but higher quantization speeds to sample and quantize in parallel, thereby increasing the overall ADC speed by a factor of M and relaxing the trade-off between power consumption and speed in single-channel ADC design. Therefore, this structure is widely used in ultra-high-speed ADCs. However, due to device mismatches and parasitic mismatches caused by factors such as manufacturing processes, power supply voltage, and temperature, many non-ideal factors exist between the individual single-channel ADCs, mainly including offset mismatch, gain mismatch, clock jitter, and bandwidth mismatch, which seriously affect the overall performance of the time-domain interleaved ADC.

[0003] To reduce the impact of non-ideal factors on performance, many mismatch calibration algorithms have been proposed. Among them, the error caused by clock jitter is related to both the frequency and amplitude of the input signal, making it difficult to calibrate and a key focus of calibration algorithms. Therefore, a good calibration algorithm needs to be able to quickly and accurately calibrate the clock jitter of large-scale time-domain interleaved ADCs. Summary of the Invention

[0004] To address the aforementioned problems in the existing technology, this invention provides a background calibration method for a time-domain interleaved ultra-high-speed analog-to-digital converter based on the least mean square root. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a reference-free back-end calibration method for ultra-high-speed TIADCs based on least mean square root, comprising:

[0006] Step 1: Obtain the output code of the multi-channel ultra-high-speed TIADC;

[0007] Step 2: Sample the output code of the ultra-high-speed TIADC according to a predetermined decimation rate to obtain multiple quantization code sets;

[0008] Step 3: Perform clock jitter calibration on the first set of quantized codes;

[0009] Step 4: Compensate the remaining quantization code sets based on the clock jitter detection results of the first quantization code set;

[0010] Step 5: Re-interpolate the multiple quantized code sets after compensation to obtain the compensation result of the output code of the ultra-high speed TIADC.

[0011] The present invention has at least one or more of the following beneficial effects:

[0012] 1. The calibration technique of this invention adopts a decimation-calibration-interpolation calibration mode. First, the original ultra-high-speed quantization data is decimated using a decimation rate coprime to the number of interleaved channels to obtain multiple sets of quantization codes to be calibrated. Then, when calibrating multiple sets of quantization codes, a partial detection and overall compensation calibration method is used to improve the detection speed. First, the first decimated set of quantization codes is used for clock jitter calibration. Then, the detected clock jitter values ​​of each channel are used to compensate the other sets of quantization codes in the digital domain. Finally, the compensated sets of multiple quantization codes are re-interpolated to obtain the final calibrated result.

[0013] 2. In the process of partial detection, in order to quickly detect large-scale time-domain interleaved channels, the present invention adopts a stepwise grouping calibration algorithm based on a dual-channel synchronous detection algorithm. During the calibration process, it can not only compensate for the first set of quantized codes extracted, but also minimize the mean square error of clock jitter of all detected channels, thereby improving the compensation accuracy.

[0014] 3. This invention employs a dual-channel synchronous detection algorithm based on the binary search method to detect the clock jitter magnitude between channels within each group in a progressive grouping process. Dual-channel synchronous detection avoids the use of a reference channel and improves detection accuracy. Furthermore, the adjustable detection range expands the applicability of the overall calibration algorithm and facilitates linear compensation of the FIR filter.

[0015] 4. This invention uses linear compensation to solve the problem that the amplitude-frequency response characteristics of the FIR filter at high frequencies are far from the amplitude-frequency characteristics of the ideal differential filter, thereby improving the effective bandwidth when using FIR to calculate derivatives, and thus improving the compensation accuracy when calibrating clock jitter at input high-frequency signals.

[0016] 5. This invention does not use any external or internal reference channels during the calibration process, which not only avoids the hardware overhead of reference channels, but also solves the calibration accuracy problem caused by the selection of reference channels.

[0017] 6. The decimation operation of this invention changes the relationship between the input and the sampling frequency, which expands the spectrum of the decimated data. This solves the problem of extraction failure or non-convergence that occurs when the input signal is near a specific frequency and the autocorrelation function is used to extract the error, thus improving the performance of the calibration algorithm in the Nyquist region.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a block diagram of the large-scale phase domain interleaving calibration algorithm for ultra-high-speed analog-to-digital converters provided by the present invention;

[0020] Figure 2 This is a block diagram of the stepwise grouping calibration algorithm based on dual-channel synchronous detection provided by the present invention;

[0021] Figure 3 This is a block diagram of the dual-channel synchronous clock jitter detection algorithm based on the binary search method provided by the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] Before introducing the present invention, a brief overview of the overall solution of the present invention will be provided.

[0024] This invention employs a decimation-calibration-interpolation working mode. First, all the raw data requiring calibration is decimated at a certain rate, where the decimation rate and the number of channels are coprime. This ensures that the data used for clock jitter calibration includes partial quantization data from each channel. Then, the first quantized code set after decimation is selected for clock jitter calibration, which includes detection and compensation. Based on the detection results, compensation is applied to the other decimated quantized code sets. Finally, the compensated quantized code sets are interpolated at an interpolation rate equal to the decimation rate, thus obtaining the complete result after calibrating the raw data.

[0025] This invention provides a reference-free back-end calibration method for ultra-high-speed TIADCs based on least mean square root, comprising:

[0026] Step 1: Obtain the output code of the multi-channel ultra-high-speed TIADC;

[0027] Step 2: Sample the output code of the ultra-high-speed TIADC according to a predetermined decimation rate to obtain multiple quantization code sets;

[0028] like Figure 1 The diagram shown is a structural block diagram of the proposed time-domain interleaved ultra-high-speed analog-to-digital converter (ADC) background calibration technology applied to a 16-channel ADC. The 16-channel output code D... outAfter a 5x simplification, five new quantization code sets Y1, Y2, Y3, Y4, and Y5 are obtained to be calibrated. The quantization channel order in each quantization code set is shuffled after simplification. When the starting quantization channel is CH1, the quantization channel order in the first quantization code set Y1 is: CH1, CH6, CH11, CH16, CH5, CH10, CH15, CH4, CH9, CH14, CH3, CH8, CH13, CH2, CH7, CH12. Since the simplification rate and the number of channels are coprime, after simplification, partial quantization data from all quantization channels are contained in each quantization code set. Therefore, this invention selects the first quantization code set Y1 for clock jitter calibration. To facilitate subsequent clock jitter calibration, the quantization channel order of the above-mentioned data to be detected is re-marked using the detection channel order of 1ch, 2ch, 3ch...14ch, 15ch, 16ch. Regardless of which quantization code set is used for clock jitter calibration, only the mapping relationship between the detection channels and the quantization channels is changed.

[0029] Step 3: Perform clock jitter calibration on the first quantized code set;

[0030] This invention employs a step-by-step grouping calibration algorithm to perform clock jitter calibration on the first quantization code set in stages. The specific process is as follows:

[0031] A. Determine the number of steps to perform progressive grouping based on the number of channels in the first set of quantized codes;

[0032] B. For step 1, group the quantized codes of the first quantized code set after compensation in step 1 into groups with equal sampling intervals, according to each group of 2 channels. Then, use a dual-channel detection algorithm based on binary search to search for the clock jitter of each channel in the same group to obtain the clock jitter value of step 1. Based on the clock jitter value, perform step 1 compensation on the quantized data in the first quantized code set.

[0033] C, for step H, according to every 2 H Grouping channels into sets, the quantized codes in the first quantized code set are grouped at equal sampling intervals to obtain a set containing 2 channels. H The quantization channels are grouped, and a dual-channel detection algorithm based on binary search is used to search for the clock jitter of each channel in the same group to obtain the clock jitter value in step H. Based on the clock jitter value, the quantization data after compensation in step H-1 is compensated in step H.

[0034] Where H is a positive integer not less than 1;

[0035] D. Repeat the process of C until the last step. Use a dual-channel detection algorithm based on the binary search method to search for the clock jitter of each channel in this group in the last step to obtain the clock jitter value of the last step. Based on the clock jitter value, perform the last step compensation on the quantized data after the compensation in the previous step to obtain the first quantized code set after clock jitter calibration. Sum the clock jitter of each channel searched in each step to obtain the optimal clock jitter vector corresponding to the first quantized code set.

[0036] In the clock jitter calibration process, an FIR differential filter is used to differentiate the quantized codes in all quantized code sets. This invention uses a 12th-order FIR differential filter to calculate the derivative corresponding to the quantized data. In order to improve the amplitude-frequency characteristics of the low-order differential filter at high frequencies and avoid affecting its linear phase-frequency characteristics, this invention uses (21) an FIR filter to differentiate the first quantized code set and uses the first compensation formula to compensate the differentiation result to improve the amplitude-frequency characteristics of the FIR filter, and obtains the compensated differentiation result:

[0037]

[0038] in, Coef represents the uncompensated derivative at the quantization code Y(k). a G is the a-th coefficient in the impulse response of the FIR filter used. d G is the amplitude compensation factor for the FIR filter. The value of the amplitude compensation factor is the ratio of the amplitude-frequency response of the first-order differential filter to that of the 12th-order differential filter at each frequency. d It is a variable that changes with frequency; a represents an integer value, ranging from 0 to 12, and k represents that the quantized data Y(k) in a certain quantization code set is the kth quantization code;

[0039] This invention uses first-order linear compensation to improve the amplitude-frequency response characteristics of the FIR differential filter at high frequencies, thereby increasing the effective bandwidth for calculating the derivative of the filter.

[0040] (22) Applying the derivative of the compensated result to the first-order Taylor approximation compensation formula for clock jitter, we obtain the clock jitter compensation formula:

[0041]

[0042] in, Indicates the quantization code Y in channel i i The uncompensated derivative at (k), t i G represents the detected clock jitter magnitude of channel i, and G is the FIR filter compensation factor G. dThe maximum value of G is chosen to make the compensation of the filter linear. Since the specific input frequency value cannot be obtained from the quantization code during calibration, and to avoid increasing circuit overhead and complexity by using higher-order compensation, this invention selects G as the compensation factor G for the filter. d The maximum value in G is obtained by decomposing the coefficient G to get G = G t ×G d G t ≥1.

[0043] When the input signal is at a high frequency, the clock jitter compensation formula (2) is rewritten as follows:

[0044]

[0045] Due to the filter compensation factor G at different frequencies d is a variable, while G is a fixed value, therefore G t It is also a variable.

[0046] When the input signal is at a low frequency, the characteristics of the differentiating filter do not need to be compensated, so the clock jitter compensation formula (2) is rewritten as follows:

[0047]

[0048] At this point, the compensation factor used for the compensation filter is set to 1, and the compensation coefficient G is directly multiplied by the searched clock jitter value t. i .

[0049] The clock jitter values ​​in clock jitter compensation formulas (3) and (4) need to be multiplied by a coefficient, which will cause the search range of clock jitter to change to varying degrees. However, the dual-channel synchronization detection algorithm based on the bisection method used in this invention can quickly find the appropriate clock jitter detection value when the search range changes.

[0050] (23) For channel i and channel j in each group, adjust the clock jitter t simultaneously. i and t j The size and direction of t make t i =t,t j =-t, and based on the clock jitter compensation formula, the temporary compensation results for the quantized data of channel i and channel j are obtained, expressed as:

[0051]

[0052]

[0053] in, This indicates that channel i is in the quantized data Y iThe derivative at (k) can be obtained using the aforementioned first-order compensated FIR differential filter, Y i (k) represents the quantized data of channel i to be detected. The difference in autocorrelation functions yields the error caused by clock jitter for channels i and j within the same group:

[0054]

[0055] Where ΔT is the deviation of the ideal sampling interval T between the channels to be detected within the same group, Y i (k) represents the quantized data of channel i to be detected within the same group, R x It is the autocorrelation function of the input signal. The difference between the clock jitter of the two channels is detected iteratively using a bisection method, and the value of the autocorrelation function is updated accordingly, ultimately achieving R0. i,j ≈R j,i And error≈0, meaning that the sampling interval between channel i and channel j is equal.

[0056] The specific stepwise grouping calibration process based on dual-channel synchronous detection is as follows: Figure 2 As shown, the first quantization code set Y1 used for calibration is assumed to contain 16 detection channels, so clock jitter calibration requires 4 steps.

[0057] The first step involves dividing the 16 channels into eight groups of two, ensuring that the ideal sampling interval between the two detection channels in each group is equal. For example, detection channels 1 and 9 are grouped together, with channel 1 and channel 9 being the two clock jitter error sources in this group. Similarly, detection channels 2 and 10 are grouped together, with channel 2 and channel 10 being the two clock jitter error sources in this group. Then, a dual-channel detection algorithm based on bisection is used simultaneously to search for clock jitter in each channel within each group and to compensate for the quantized data of each channel. Finally, a set of clock jitter detection values ​​t is obtained. 1st =[t 1ch t 2ch t 3ch …t 15ch t 16ch Furthermore, during the detection process, the corresponding quantitative data is compensated to obtain Y. 1st ;

[0058] The second step is to use Y 1stThe system is divided into four groups of four, ensuring that the ideal sampling interval between the four detection channels in each group is equal. For example, detection channels 1ch, 5ch, 9ch, and 13ch are grouped together. Since the clock jitter error between channels 1 and 9 (and channels 5 and 13) has already been compensated in the previous step, the two clock jitter error sources in this group are the clock jitter errors between 1ch (9ch) and 5ch (13ch). Then, a dual-channel detection algorithm based on binary search is used to search for the clock jitter in each channel of each group and compensate for the quantized data of each channel. Finally, a set of clock jitter detection values ​​t is obtained. 2nd =[t 1ch t 2ch t 3ch …t 15ch t 16ch Furthermore, during the detection process, the corresponding quantitative data is compensated to obtain Y. 2nd ;

[0059] The third step is to use Y 2nd The system is divided into two groups of eight channels each, ensuring that the ideal sampling interval between the eight detection channels in each group is equal. For example, all odd-numbered detection channels (1ch, 3ch, 5ch, 7ch, 9ch, 11ch, 13ch, 15ch) are grouped together. Since the clock jitter error between 1ch, 5ch, 9ch, and 13ch has already been compensated in the previous step, the two clock jitter error sources in this group are the clock jitter error between 1ch and 3ch. Then, a dual-channel detection algorithm based on binary search is used simultaneously to search for the clock jitter of each channel in each group and compensate for the quantized data of each channel. Finally, a set of clock jitter detection values ​​t is obtained. 3rd =[t 1ch t 2ch t 3ch …t 15ch t 16ch Furthermore, during the detection process, the corresponding quantitative data is compensated to obtain Y. 3rd ;

[0060] Step 4, Y 3rd The 16 channels are grouped together. Since the clock jitter errors between all odd-numbered detection channels and between all even-numbered detection channels have already been compensated in the previous step, the actual two clock jitter error sources in this group are the clock jitter errors between 1ch (3ch) and 2ch (4ch). Then, a dual-channel detection algorithm based on binary search is used to search for the clock jitter of each channel in each group and compensate for the quantized data of each channel. Finally, a set of clock jitter detection values ​​t is obtained. 4th =[t 1ch t2ch t 3ch …t 15ch t 16ch Furthermore, during the detection process, the corresponding quantitative data is compensated to obtain Y. 4th .

[0061] Finally, after the compensation in the above four-step group detection, the first quantization code set Y1 used for calibration completes the final clock jitter compensation, resulting in Y. cal_1 =Y 4th Simultaneously, the clock jitter detection values ​​obtained from the four-step group detection are summed to calculate an optimal set of clock jitter detection values ​​t. opt_1 =t 1st +t 2nd +t 3rd +t 4th =[t1′ ch t′ 2ch t′ 3ch …t′ 15ch t′ 16ch ], and at this time t opt_1 The root mean square reaches its minimum.

[0062] like Figure 3 As shown, the steps of the dual-channel detection algorithm based on the binary search method to search for time jitter in each channel include:

[0063] (1) First, determine the reasonable range for subsequent binary search detection through a loop search. First, set the initial range of clock jitter t [t...]. min ,t max ], and satisfy t min <0,t max >0 and |t min |=|t max The condition, and the range of variation, are obtained through simulation. The search count N = 0 and its maximum value N are set. max And obtain t based on the range. mid =0;

[0064] Among them, t in the initial range of change min <0,t max >0 and |t min |=|t max |;

[0065] (2) Determine if the number of loop searches N has met the requirement. The process is as follows: If N > N max If true, then jump back to (1) to reset the initial range of change; if N≤N max Then, according to formulas (5) and (6) respectively, and using t max , t mid and tmin Temporary compensation is applied to each channel in the same group, and three error values ​​are further calculated based on the temporary compensation results using formula (7). max error mid and error min ;where error max =E{Y j,max (k)×[Y i,max (k)-Y i,max (k+1)]}.

[0066] (3)Judge error max ×error min Is >0 true?

[0067] (4) Update the range of clock jitter based on the judgment result. The process is as follows: If error max ×error min If t > 0, then t min =t min / 2,t max =t max / 2, and update the search count to N = N + 1, then jump to (2); if error max ×error min If <0, then further check for error. max ×error mid If < 0 is true, then let t min =t mid And t max =t max And exit the loop search to execute (5) to enter the binary search process; if error max ×error mid If < 0 is not true, then let t max =t min And t min =t mid , and exit the loop search to execute (5) to enter the binary search process;

[0068] (5) The range of variation of clock jitter magnitude t is obtained by the cyclic search of (1)-(4) [t]. min ,t max The range of change satisfies error. max ×error min <0, calculate clock jitter t mid =(t max +t min ) / 2, and set the number of binary search iterations N = 0;

[0069] (6) Based on formulas (5) and (6), and using t respectively max , t mid and t min Temporary compensation is applied to each channel in the same group, and three error values ​​are calculated using formula (7) based on the temporary compensation results. max error mid and error min ;

[0070] (7)Judge error mid ×error min <0, or error mid ×error max Is <0 true?

[0071] (8) Based on the judgment result, narrow down the search range for the clock jitter magnitude t. The process is as follows: If error mid ×error min If < 0 is true, then let t max =t mid If error mid ×error min If < 0 is not true, then let t min =t mid Then update the search count to N = N + 1, and calculate t. mid =(t max +t min ) / 2;

[0072] (9) Determine if the search count requirement is met. The process is as follows: If N≥N max If true, then let the clock jitter magnitude be t = t mid And according to formulas (5) and (6), the quantization data of each channel is compensated using t, and then the binary search process is exited; if N < N max If true, then jump to (6) to continue the binary search process.

[0073] A dual-channel synchronous detection algorithm based on the binary search method is used to detect the clock jitter of the two channels in the above group. First, the preset binary search range and direction are adjusted by cyclic search. Then, the binary search method is used to iteratively detect the clock jitter of the two channels at the same time, so that the clock jitter of the two channels found in the end is equal in magnitude and opposite in sign.

[0074] Step 4: Compensate the remaining quantization code sets based on the calibration results of the first quantization code set;

[0075] It is worth noting that when compensating for the remaining quantization code set, there is no need to repeat the detection process; only the compensation process, i.e., (21) to (22), needs to be performed. The specific steps include:

[0076] Based on the relationship between the decimation rate, the number of interleaving channels, and the order of the quantization code sets, the optimal clock jitter vector corresponding to the first quantization code set is cyclically shifted to the left to obtain the optimal clock jitter vector used to compensate for other quantization code sets; and the other quantization code sets are compensated based on the optimal clock jitter vector used to compensate for other quantization code sets.

[0077] After calibrating the first quantized code set using the stepwise grouping calibration algorithm, the compensated first quantized code set Y is obtained. cal_1 And the optimal clock jitter vector t corresponding to the first quantization code set. opt_1 .like Figure 1 As shown, the extraction process results in a different order of quantization channels in each quantization code set. Therefore, the detected optimal clock jitter vector t opt_1 The compensation formula (2) cannot be directly substituted to correct the quantized data in other sets. However, based on the relationship between the sampling rate, the number of interleaved channels, and the order of these quantized data sets, the detection result t can be used to correct the quantized data. opt_1 The cyclic left shift operation yields the optimal clock jitter vector for compensating other quantization code sets.

[0078] Assuming the cyclic shift length between the optimal clock jitter vectors of adjacent sets is equal to L, the following condition should be satisfied:

[0079] (L×(DEC) mod M ) mod M =1,(0 <L<M) (8)

[0080] in(·) mod M Let M represent the modulo-M operation, where M is the number of interleaving channels and DEC is the decimation rate. Therefore, the optimal clock jitter vector corresponding to the (1±i)th quantized code set after decimation can be derived as follows:

[0081] t opt_(1+i) =t opt_1 ROL(L×(i) mod M ) modM (9)

[0082] Where ROL represents vector t opt_1 Perform a cyclic left shift operation. Substitute the optimal clock jitter value obtained according to formula (9) into the compensation formula to compensate the quantized data in each group, thereby obtaining Y.cal_2 Y cal_3 Y cal_4 , and Y cal_5 .

[0083] Step 5: Re-interpolate the multiple quantized code sets after compensation to obtain the compensation result of the output code of the ultra-high speed TIADC.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0085] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0086] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A reference-free back-end calibration method for an ultra-high-speed TIADC based on least mean square root, characterized in that, include: Step 1: Obtain the output code of the multi-channel ultra-high-speed TIADC; Step 2: Sample the output code of the ultra-high-speed TIADC according to a predetermined decimation rate to obtain multiple quantization code sets; Step 3: Perform clock jitter calibration on the first set of quantized codes; Step 4: Compensate the remaining quantization code sets based on the clock jitter detection results of the first quantization code set; Step 5: Re-interpolate the multiple quantized code sets after compensation to obtain the compensation result of the output code of the ultra-high speed TIADC; Step 3 includes: The clock jitter calibration of the first quantized code set is performed step by step using a progressive grouping calibration algorithm. The stepwise clock jitter calibration of the first quantization code set using the stepwise grouping calibration algorithm includes: A. Determine the number of steps to perform progressive grouping based on the number of channels in the first set of quantized codes; B. For step 1, group the quantized codes of the first quantized code set after compensation in step 1 into groups with equal sampling intervals, according to each group of 2 channels. Then, use a dual-channel detection algorithm based on binary search to search for the clock jitter of each channel in the same group to obtain the clock jitter value of step 1. Based on the clock jitter value, perform step 1 compensation on the quantized data in the first quantized code set. C, for step H, according to every 2 H Grouping channels into sets, the quantized codes in the first quantized code set are grouped at equal sampling intervals to obtain a set containing 2 channels. H The quantization channels are grouped, and a dual-channel detection algorithm based on binary search is used to search for the clock jitter of each channel in the same group to obtain the clock jitter value in step H. Based on the clock jitter value, the quantization data after compensation in step H-1 is compensated in step H. Where H is a positive integer not less than 1; D. Repeat the process of C until the last step. Use a dual-channel detection algorithm based on the binary search method to search for the clock jitter of each channel in this group in the last step to obtain the clock jitter value of the last step. Based on the clock jitter value, perform the last step compensation on the quantized data after the compensation in the previous step to obtain the first quantized code set after clock jitter calibration. Sum the clock jitter of each channel searched in each step to obtain the optimal clock jitter vector corresponding to the first quantized code set. The steps of a dual-channel detection algorithm based on binary search to search for time jitter in each channel within the same group include: (1) Determine the reasonable range of subsequent bisection detection through iterative search. The process is as follows: Set the initial range of clock jitter t. Search count N=0 and its maximum value N max And based on the initial range of change, ; Among them, in the initial range of change , and ; (2) Determine whether the number of loop searches N has met the requirements. The process is as follows: If N > N max If true, then jump back to (1) to reset the initial range of change; if N≤N max Then use respectively , and Temporary compensation is applied to each channel within the same group, and three error values ​​are further calculated based on the results of the temporary compensation. , and ; (3) Judgment Is it valid? (4) Update the range of clock jitter based on the judgment result. The process is as follows: If ,but , And update the search count to N=N+1, then jump to (2); if Then further judgment Is it true? If it is true, then let and , and exit the loop search to execute (5) to enter the binary search process; if If not, then let and , and exit the loop search to execute (5) to enter the binary search process; (5) The range of clock jitter magnitude t is obtained by the cyclic search of (1)-(4). The range of change satisfies Calculate clock jitter And set the number of binary search iterations N=0; (6) Use them separately , and Temporary compensation is performed on each channel in each group, and three error values ​​are calculated based on the temporary compensation results. , and ; (7) Judgment ,or Is it valid? (8) Based on the judgment result, narrow down the search range for the clock jitter magnitude t. The process is as follows: If If established, then... ;if If not, then let Then update the search count to N=N+1, and calculate... ; (9) Determine whether the search count requirement is met. The process is as follows: If N≥N max If true, it will cause the clock jitter to increase. The quantization data of each channel is compensated using t, and then the binary search process is exited; if N < N max If true, then jump to (6) to continue the binary search process.

2. The reference-free back-end calibration method for ultra-high-speed TIADC based on least mean square root as described in claim 1, characterized in that, In (2) use respectively , and Temporary compensation for each channel in the first set of quantized codes includes: (21) The derivative of the first quantized code set is obtained using an FIR filter, and the derivative result is compensated using the first compensation formula to improve the amplitude-frequency characteristics of the FIR filter, resulting in the compensated derivative result: in, Indicates quantization code Uncompensated derivative, It is the a-th coefficient in the impulse response of the FIR filter used. This is the amplitude compensation factor for the FIR filter. The value of the amplitude compensation factor is the ratio of the amplitude-frequency response of the first-order differential filter to that of the 12th-order differential filter at each frequency. It is a variable that changes with frequency; This represents an integer value, ranging from 0 to 12. This represents the quantized data in a certain set of quantized codes. It is the kth quantization code; (22) Applying the result of the compensation to the first-order Taylor approximation compensation formula for clock jitter, we obtain the clock jitter compensation formula: in, Indicates the quantization code Y in channel i i The uncompensated derivative at (k), The detected clock jitter magnitude of channel i. FIR filter compensation factor The maximum value in the middle. This makes the compensation for the filter linear; (23) For channel i and channel j in each group, adjust the clock jitter t simultaneously. i and t j The size and direction of t make t i =t,t j =-t, and based on the clock jitter compensation formula, the temporary compensation results for the quantized data of channel i and channel j are obtained, expressed as: in, This indicates that channel i is in the quantized data Y i The derivative at (k), It is the quantized data of channel i to be detected within the same group.

3. The reference-free back-end calibration method for ultra-high-speed TIADC based on least mean square root as described in claim 1, characterized in that, Step 4 includes: Based on the relationship between the decimation rate, the number of interleaving channels, and the order of the quantization code sets, the optimal clock jitter vector corresponding to the first quantization code set is cyclically shifted to the left to obtain the optimal clock jitter vector used to compensate for other quantization code sets. The other quantization code sets are compensated based on the optimal clock jitter vector used to compensate for the other quantization code sets.

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