Semiconductor device and method of manufacturing the same
By designing the source interconnect metal in a semiconductor device to extend beyond the active region into the passive region, and placing the via in the same source adjacent to the passive region, the performance and reliability issues when connecting the source and via are solved, thereby improving the overall performance and connection reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DYNAX SEMICON
- Filing Date
- 2022-08-09
- Publication Date
- 2026-07-24
AI Technical Summary
In existing technologies, when the source and via are connected by interconnect metal, it is difficult to balance device performance and reliability.
In semiconductor devices, the ends of the source interconnect metal are designed to extend beyond the active region into the passive region, and two vias in the same source are placed adjacent to or extended to the passive region at their edges to increase the distance between the vias, prevent mutual inductance, and improve connection reliability.
This enhances the performance of semiconductor devices and the reliability of the connection between the ground metal and the source through the via, solving the performance problems caused by the misalignment of the source and the via.
Smart Images
Figure CN117637678B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to semiconductor devices and their manufacturing methods. Background Technology
[0002] Gallium nitride semiconductor materials have significant advantages such as large bandgap, high electron saturation drift velocity, high breakdown field strength, and high temperature resistance. Compared with first-generation semiconductor silicon and second-generation semiconductor gallium arsenide, they are more suitable for manufacturing high-temperature, high-voltage, high-frequency, and high-power electronic devices, and have broad application prospects. They have become a hot research topic in the semiconductor industry.
[0003] A common design involves placing the via below the source electrode in the active region, allowing the source electrode in each active region to be directly grounded through the via. This structure reduces the distance from the source electrode to ground in the active region, thereby reducing the grounding resistance. This structural design requires connecting the via and the source electrode metal through interconnecting metal to achieve grounding of the source electrode through the via.
[0004] The question of how to connect the source and via to better balance device performance and reliability is a problem that needs to be solved. Summary of the Invention
[0005] This invention provides a semiconductor device and its manufacturing method to address the issue of better balancing device performance and reliability when the source and via are connected by interconnect metal.
[0006] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising:
[0007] A semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other, the semiconductor substrate including a semiconductor layer adjacent to the first surface, the semiconductor layer including an active region and a passive region, the passive region being disposed around the active region;
[0008] The metal layer located on the second surface;
[0009] Multiple source electrodes are located within the active region, each source electrode including at least two vias. In a first direction, the edges of the at least two vias extend into or adjacent to the passive region. The first direction is the direction of the center line connecting the at least two vias on the same source electrode.
[0010] A source interconnect metal covering the at least two vias and electrically connected to the source electrode, wherein, in a first direction, the end of the source interconnect metal extends beyond the active region to the passive region, and the source electrode is electrically connected to the metal layer of the second surface through the source interconnect metal and the conductive material in the at least two vias to achieve interconnection of multiple sources;
[0011] The active region contains a plurality of drains and a plurality of gates, wherein the drains are interconnected by drain interconnect metal adjacent to the first surface, and the gates are interconnected by gate interconnect metal adjacent to the first surface.
[0012] Optionally, there is a preset distance between the edge of the source interconnect metal and the source edge in the second direction, the preset distance being less than the distance between at least two via edges and the source edge; wherein the second direction is parallel to the substrate and perpendicular to the first direction.
[0013] Optionally, when the via is located in the active region, the positional relationship between the source interconnect metal and the via is: D / 9≤U≤D / 2;
[0014] Wherein, U is the length of the source interconnect metal extending beyond the edge of the via in the first direction, and D is the length of the via itself in the first direction.
[0015] Optionally, when the via is located in the active region and the passive region, the positional relationship between the source interconnect metal and the via is: D / 9≤U≤Z.
[0016] Wherein, U is the length of the source interconnect metal extending beyond the edge of the via in the first direction, D is the length of the via itself in the first direction, and Z is the length of the via located in the passive region in the first direction.
[0017] Optionally, the positional relationship between the source interconnect metal and the active region is: D / 10≤V≤D.
[0018] Wherein, V is the length of the source interconnect metal extending beyond the edge of the active region in the first direction, and D is the length of the via itself in the first direction.
[0019] Optionally, the source interconnect metal is symmetrical at both ends in the first direction.
[0020] Optionally, in the first direction, the portion of the source interconnect metal extending beyond the active region is symmetrical in size.
[0021] Optionally, in the first direction, the portion of the source interconnect metal extending beyond the via is symmetrical in size.
[0022] Optionally, the source interconnect metal extends into the passive region in both the first direction and the second direction.
[0023] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:
[0024] A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface opposite to each other; the semiconductor substrate includes a semiconductor layer adjacent to the first surface, the semiconductor layer including an active region and a passive region, the passive region being disposed around the active region;
[0025] An electrode is formed on one side of the active region of the semiconductor layer. The electrode includes a source, a gate, and a drain. Each source includes at least two vias. In a first direction, the edges of the at least two vias extend into or adjacent to the passive region. The first direction is the direction of the center line connecting the at least two vias on the same source.
[0026] Source interconnect metal is fabricated on one side of the source electrode, and in a first direction, the end of the source interconnect metal extends beyond the active region into the passive region;
[0027] A metal layer is formed on the second surface, and the source electrodes are electrically connected to the metal layer on the second surface through the source electrode interconnecting metal and the conductive material in the at least two vias to achieve interconnection of multiple source electrodes.
[0028] The technical solution of this invention increases the distance between two vias in the same source by setting two vias adjacent to the passive region or extending the edges of the two vias to the passive region, thereby preventing mutual inductance between the two vias in the same source and improving the performance of the semiconductor device. At the same time, setting the end of the source interconnect metal to extend beyond the active region to the passive region solves the problem of the misalignment between the source and the via affecting the performance of the semiconductor device, and also increases the reliability of the connection between the ground metal and the source through the via.
[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in Embodiment 1 of the present invention;
[0032] Figure 2 yes Figure 1 Cross-sectional view along the tangent line A-A';
[0033] Figure 3 This is a schematic diagram illustrating the positional relationship between the source interconnect metal and the via provided in Embodiment 1 of the present invention;
[0034] Figure 4 This is a schematic diagram showing the positional relationship between the source interconnect metal and the via provided in Embodiment 1 of the present invention;
[0035] Figure 5 This is a schematic diagram illustrating the positional relationship between the source interconnect metal and the active region, provided in Embodiment 1 of the present invention.
[0036] Figure 6 This is a schematic diagram illustrating the positional relationship between the source interconnect metal and the active region, provided in Embodiment 1 of the present invention.
[0037] Figure 7 This is a flowchart of a semiconductor device manufacturing method provided in Embodiment 2 of the present invention. Detailed Implementation
[0038] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0040] Example 1
[0041] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in Embodiment 1 of the present invention. Figure 2 yes Figure 1 A cross-sectional view along the tangent line A-A', as shown below. Figure 1 and Figure 2As shown, the semiconductor device 100 includes a semiconductor substrate 110, a plurality of sources 120, a plurality of drains 130, a plurality of gates 140, a metal layer 150, and a source interconnect metal 170. In this embodiment, the semiconductor substrate 110 includes a substrate 111 and a semiconductor layer 112 formed on the substrate 111. The semiconductor layer includes an active region 10 and a passive region 20, wherein the passive region 20 is disposed around the active region 10.
[0042] The semiconductor substrate 110 includes a first surface and a second surface that are opposite to each other. The semiconductor substrate 110 defines a plurality of through holes 162 that penetrate the first surface and the second surface.
[0043] In this embodiment, the metal layer 150 is disposed on the second surface.
[0044] Multiple sources 120 are located within the active region 10. Each source 120 includes at least two vias 160. The source 120 is electrically connected to the metal layer 150 on the second surface through source interconnect metal and conductive material within the at least two vias 160 to achieve interconnection of the multiple sources. In a first direction, the edges of the at least two vias 160 extend into or are located adjacent to the passive region 20. The first direction is the direction of the center line connecting the at least two vias 160 on the same source 120.
[0045] Specifically, please refer to the following: Figure 2 In one embodiment, in the direction perpendicular to the first surface, the via 160 includes a reserved via 161 penetrating the source 120 and a through-hole 162 penetrating the first and second surfaces. An etching barrier layer 163 is disposed in the reserved via 161. The etching barrier layer 163 may be a material with conductive properties and is not in direct contact with the source 120. A conductive material is disposed in the through-hole 162. The etching barrier layer 163 in the reserved via 161 is electrically connected to the metal layer 150 of the second surface through the conductive material in the through-hole 162.
[0046] In one embodiment, in Figure 1 In the first direction X shown, the edges of the two vias 160 extend into or are adjacent to the passive region 20. In this embodiment, the first direction X is the direction of the center line connecting the two vias 160 on the same source electrode 120.
[0047] In one embodiment, such as Figure 1 and Figure 5 As shown, the edges of the two through holes 160 extend into the passive region 20.
[0048] In alternative embodiments, such as Figure 4 As shown, the edges of the two through holes 160 are adjacent to the passive region 20.
[0049] To prevent mutual inductance between two vias in the same source electrode, which would affect the performance of the semiconductor device, a certain distance needs to be maintained between the two vias 160 in the same source electrode 120. In this embodiment, the two vias 160 in the same source electrode 120 are positioned adjacent to the passive region 20, or the edges of the two vias 160 are extended to the passive region 20, thereby increasing the distance between the two vias 160 in the same source electrode 120, preventing mutual inductance between the two vias 160 in the same source electrode 120, and thus improving the performance of the semiconductor device.
[0050] In this embodiment, the etch barrier layer 163 within the reserved via 161 is electrically connected to the source 120 via the source interconnect metal 170. In a first direction, the end of the source interconnect metal 170 extends beyond the active region 10 into the passive region 20. The source 120 is electrically connected to the metal layer 150 on the second surface via the source interconnect metal 170 and the conductive material within at least two vias to achieve interconnection of multiple sources. This solves the problem of the misalignment between the source and the via affecting the performance of the semiconductor device, and also increases the reliability of the connection between the ground metal and the source through the via.
[0051] In an alternative embodiment, an etching barrier layer may not be provided within the reserved through-hole 161. Figure 3 This is a cross-sectional view of another semiconductor device provided in Embodiment 1 of the present invention, as shown below. Figure 3 As shown, the source interconnect metal 170 is directly filled into the reserved via 161. At this time, the source 120 is directly electrically connected to the source interconnect metal 170 in the via 160 and the source interconnect metal 170 covering the source 120. Furthermore, the source 120 is electrically connected to the metal layer 150 of the second surface through the source interconnect metal 170 and the conductive material in at least two vias (the source interconnect metal 170 in the reserved via 161) to achieve interconnection of multiple sources. In the first direction, the end of the source interconnect metal 170 extends beyond the active region 10 into the passive region 20. This can solve the problem of the misalignment between the source and the via affecting the performance of the semiconductor device, and also increases the reliability of the connection between the ground metal and the source through the via.
[0052] In this embodiment, the drains 130 are interconnected via drain interconnect metal 192 adjacent to the first surface, and the gates 140 are interconnected via gate interconnect metal 182 adjacent to the first surface. Specifically, multiple drains 130 and multiple gates 140 are located within the active region 10. The drains 130 are electrically connected to drain interconnect metal 191 within the passive region 20 via drain interconnect 192. The gates 140 are electrically connected to gate interconnect metal 181 within the passive region 20 via gate interconnect 182. An insulating dielectric layer may or may not be provided between the drain interconnect metal 192 and the first surface. An insulating dielectric layer may or may not be provided between the gate interconnect metal 182 and the first surface.
[0053] In one embodiment, the semiconductor substrate 110 may include a substrate layer 111 and an epitaxial layer 112. The substrate layer 111 may be formed of one of the following materials: silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial layer 112 may be formed of one or more of the following materials: gallium nitride, aluminum gallium nitride, indium gallium nitride aluminum nitride, and indium aluminum gallium nitride. In this embodiment, the first surface of the semiconductor substrate 110 may be the side of the epitaxial layer 112 away from the substrate layer 111, and the other side of the semiconductor substrate 110 opposite to or away from the first surface is the second surface of the semiconductor substrate 110. In this embodiment, the epitaxial layer 112 may include a semiconductor layer, wherein the semiconductor layer includes an active region 10 and a passive region 20, and the passive region 20 is disposed around the active region 10. In this embodiment, the active region 10 contains a two-dimensional electron gas, electrons, or holes, which is the working area of the semiconductor device; the passive region 20 has its two-dimensional electron gas, electrons, or holes eliminated or isolated by a mesa etching process, ion implantation process, or oxidation isolation process, and it is not the internal working area of the semiconductor device.
[0054] The semiconductor device provided in Embodiment 1 of the present invention includes a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other, the semiconductor substrate including a semiconductor layer, the semiconductor layer including an active region and a passive region, the passive region being disposed around the active region; a metal layer located on the second surface; a plurality of sources located in the active region, each source including at least two vias, the sources being electrically connected to the metal layer of the second surface through conductive material in the at least two vias to achieve interconnection of the plurality of sources, the edges of the at least two vias extending into or adjacent to the passive region in a first direction, the first direction being the direction of the center line connecting the at least two vias on the same source; a source interconnect metal covering the at least two vias and electrically connected to the source, the ends of the source interconnect metal extending beyond the active region into the passive region in the first direction; a plurality of drains and a plurality of gates located in the active region, the drains being interconnected through drain interconnect metal adjacent to the first surface, and the gates being interconnected through gate interconnect metal adjacent to the first surface. In this embodiment, two vias in the same source are positioned adjacent to the passive region, or the edges of the two vias extend into the passive region, thereby increasing the distance between the two vias in the same source and preventing mutual inductance between the two vias in the same source, thus improving the performance of the semiconductor device. At the same time, the end of the source interconnect metal is set to extend beyond the active region into the passive region, which solves the problem of the misalignment between the source and the via affecting the performance of the semiconductor device, and also increases the reliability of the connection between the ground metal and the source through the via.
[0055] Optional, in Figure 1As shown, there is a preset distance between the edge of the source interconnect metal 170 and the edge of the source 120 in the second direction Y, and this preset distance is smaller than the distance between the edge of the via 160 and the edge of the source 160. That is, the source interconnect metal 170 is located between the edge of the source 120 and the edge of the via 160. The second direction Y is parallel to the substrate and perpendicular to the first direction X. Specifically, the larger the size of the interconnect metal, the greater its resistance. While ensuring the reliability of the connection between the source and the via as much as possible, it is necessary to minimize the size of the source interconnect metal 170. Therefore, placing the source interconnect metal 170 between the edge of the source 120 and the edge of the via 160 in the second direction Y helps to reduce the resistance of the source interconnect metal, thereby improving the performance of the semiconductor device.
[0056] Optional, Figure 4 This is a schematic diagram illustrating the positional relationship between the source interconnect metal and the via provided in Embodiment 1 of the present invention. Figure 4 As shown, when via 160 is located in the active region 10, the positions of the source interconnect metal 170 and via 160 are mainly considered in terms of resistance. Therefore, the positional relationship between the source interconnect metal 170 and via 160 is set as: D / 9≤U≤D / 2. Wherein, U is the length of the source interconnect metal 170 extending beyond the edge of via 160 in the first direction X, and D is the length of via 160 itself in the first direction X.
[0057] Optional, Figure 5 This is a schematic diagram illustrating the positional relationship between the source interconnect metal and the via provided in Embodiment 1 of the present invention. (See diagram below.) Figure 5 As shown, when via 160 is located in the active region 10 and the passive region 20, the positions of the source interconnect metal 170 and via 160 must consider both resistance and connectivity. Therefore, the positional relationship between the source interconnect metal 170 and via 160 is set as: D / 9 ≤ U ≤ Z. For example, when 1 / 3 of via 160 is located in the passive region and the remaining 2 / 3 is located in the active region, the positional relationship between the source interconnect metal 170 and via 160 is D / 9 ≤ U ≤ D / 3.
[0058] Wherein, U is the length of the source interconnect metal 170 extending beyond the edge of the via 160 in the first direction X, D is the length of the via 160 itself in the first direction X, and Z is the length of the via 160 located in the passive region 20 in the first direction X. In this embodiment, after the source interconnect metal 170 extends in the direction opposite to the first direction X, it extends beyond the edge length U of the via 160 on the left side of the source 120, and simultaneously, after the source interconnect metal 170 extends in the first direction X, it also extends beyond the edge length U of the via 160 on the right side of the source 120.
[0059] Optional, Figure 6This is a schematic diagram illustrating the positional relationship between the source interconnect metal and the active region, as provided in Embodiment 1 of the present invention. Figure 6 As shown, the positional relationship between the source interconnect metal 170 and the active region 10 is: D / 10≤V≤D. Where V is the length of the source interconnect metal 170 extending beyond the edge of the active region 10 in the first direction X, and D is the length of the via 160 itself in the first direction X. By establishing the positional relationship between the source interconnect metal and the active region, the problem of device performance being affected by misalignment of the source ohmic metal position and the via position is solved.
[0060] Optionally, the source interconnect metal 170 is symmetrical at both ends in the first direction X.
[0061] Optionally, in the first direction X, the portion of the source interconnect metal 170 extending beyond the active region 10 is symmetrical in size.
[0062] Optionally, in the first direction X, the portion of the source interconnect metal 170 extending beyond the via 160 is symmetrical in size.
[0063] Optionally, the source interconnect metal 170 extends into the passive region 20 in both the first direction X and the second direction Y.
[0064] Example 2
[0065] Figure 7 This is a flowchart illustrating a semiconductor device manufacturing method according to Embodiment 2 of the present invention. This method is used to manufacture the semiconductor device described in the above embodiments. (See also...) Figure 1-2 The method includes:
[0066] S110. A semiconductor substrate 110 is provided, the semiconductor substrate 110 including a first surface and a second surface opposite to each other. The semiconductor substrate 110 includes a semiconductor layer adjacent to the first surface, the semiconductor layer including an active region 10 and a passive region 20, the passive region being disposed around the active region.
[0067] In step S120, an electrode is fabricated on one side of the active region of the semiconductor layer. The electrode includes a source 120, a gate 130, and a drain 140. Each source 120 includes at least two vias 160. In a first direction, the edges of the at least two vias 160 extend into or adjacent to the passive region 10. The first direction is the direction of the center line connecting the at least two vias 160 on the same source. In one embodiment, the source 120 and drain 140 may be ohmic metal electrodes, and the gate 130 may be a Schottky metal contact electrode.
[0068] In one embodiment, reference is also made to Figure 2When fabricating the source electrode 120, a reserved via 161 is formed in the region adjacent to the passive region of the source electrode 120. This reserved via 161 does not contain source ohmic metal. In one embodiment, reserved vias 161 penetrating the source electrode 120 are formed on both sides of the source electrode 120 by etching. An etch barrier layer 163 is formed within the reserved via 161. In this embodiment, the etch barrier layer 163 is located within the reserved via 161 and is approximately smaller than the shape of the reserved via 161. The shape of the etch barrier layer 163 can correspond to the shape of the via 160, or it can be circular, elliptical, square, rounded square, or other shapes. There is a preset interval between the edge of the reserved via 161 and the remaining etch barrier layer 163 within the reserved via 161; that is, the interval between the edge of the reserved via 161 and the remaining etch barrier layer 163 can be an annular groove or a semi-annular groove. In this embodiment, the source 120 is electrically connected to the metal layer 150 of the second surface through the source interconnect metal 170 and the conductive material in at least two vias (the source interconnect metal 170 and the etch barrier layer 163 in the reserved via 161) to realize the interconnection of multiple sources.
[0069] In an alternative embodiment, the etch barrier layer 163 may also fill the reserved via 161. In this case, the source 120 is electrically connected to the metal layer 150 of the second surface through the source interconnect metal 170 and the conductive material in the at least two vias (the etch barrier layer 163 in the reserved via 161) to achieve interconnection of multiple sources.
[0070] In an alternative embodiment, a dielectric layer may be further formed after the source 120 fabrication process is completed to protect the source 120 during other intermediate processes. These dielectric layers are either completely or substantially removed before subsequent step S130 is performed. See also... Figure 1 In one embodiment, there is a preset distance between the edge of the source interconnect metal 170 and the edge of the source 120 in the second direction Y, and the preset distance is less than the distance between the edge of the via 160 and the edge of the source 160. That is, the source interconnect metal 170 is located between the edge of the source 120 and the edge of the via 160. In one embodiment, the part of the dielectric layer that has not been removed can cover the edge 121 of the source 120 to protect the part that is not covered by the source interconnect metal 170.
[0071] S130. A source interconnect metal 170 is fabricated on one side of the source electrode 120. In a first direction, the end of the source interconnect metal extends beyond the active region into the passive region. Specifically, the source interconnect metal 170 can completely cover the etch stop layer 163, and the source electrode 120 and the etch stop layer 163 are interconnected through the source interconnect metal 170. In this embodiment, the source interconnect metal 170 can fill the annular groove or semi-annular groove and cover the source electrode 120, so that the etch stop layer 163 is interconnected through the source interconnect metal 170. Specifically, in the first direction X, the end of the source interconnect metal 170 extends beyond the active region 10 into the passive region 20, where the first direction X is the direction of the center line connecting the two vias 160 on the same source electrode 120. An etch barrier layer 163 is used as a barrier to form a through-hole 162 that penetrates the semiconductor substrate, so as to avoid excessive etching of the source 120 and / or the source interconnect metal 170 when forming the through-hole 16. In this embodiment, the reserved via 161 and the through-hole 162 together define the via 160 included in the source 120 in the first embodiment.
[0072] S140, A metal layer 150 is formed on the second surface, and the source electrode 120 is electrically connected to the metal layer 150 on the second surface through the source electrode interconnecting metal 170 and the conductive material in the at least two vias 160 to realize the interconnection of multiple sources.
[0073] In this embodiment, each source 120 corresponds to two vias 160. The source 120 is electrically connected to the metal layer 150 on the second surface through a source interconnect metal 170, an etch stop layer 163, and conductive material 150 within the via 162, forming an interconnect on the second surface. In a first direction, the edges of the vias 160 of the two sources extend into or adjacent to the passive region 20. In an alternative embodiment, the conductive material 150 and the metal layer 150 within the via 162 can be the same material or different materials. The conductive material 150 and the metal layer 150 within the via 162 can be formed in the same semiconductor process step or formed sequentially using different semiconductor process steps.
[0074] In alternative embodiments, reference is also made to Figure 3Optionally, an etch barrier layer may not be formed within the reserved via 161. The source interconnect metal 170 is directly filled into the reserved via 161. In this case, the source 120 is directly electrically connected to the source interconnect metal 170 within the via 160 and to the source interconnect metal 170 covering the source surface. In the first direction, the end of the source interconnect metal 170 extends beyond the active region 10 into the passive region 20. In this embodiment, the source interconnect metal 170 needs to be thickened to act as a barrier for etching from the second surface to form a through-hole 162 penetrating the semiconductor substrate. The reserved via 161 and the through-hole 162 together define the via 160 included in the source 120 in the first embodiment. In this embodiment, since the etch barrier layer 163 is omitted, each source 120 is electrically connected to the metal layer 150 on the second surface through the interconnect metal layer 170 and the conductive material 150 within the through-hole 162 to form an interconnect on the second surface. In the above embodiment, the metal layer 150 can be a ground metal.
[0075] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0076] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other, the semiconductor substrate including a semiconductor layer adjacent to the first surface, the semiconductor layer including an active region and a passive region, the passive region being disposed around the active region; The metal layer located on the second surface; Multiple source electrodes are located within the active region, each source electrode including at least two vias. In a first direction, the edges of the at least two vias extend into or adjacent to the passive region. The first direction is the direction of the center line connecting the at least two vias on the same source electrode. A source interconnect metal covering the at least two vias and electrically connected to the source electrode extends beyond the active region into the passive region in a first direction; the source electrode is electrically connected to the metal layer of the second surface through the source interconnect metal and the conductive material in the at least two vias to achieve interconnection of multiple sources; The active region contains a plurality of drains and a plurality of gates, wherein the drains are interconnected by drain interconnect metal adjacent to the first surface, and the gates are interconnected by gate interconnect metal adjacent to the first surface. There is a preset distance between the edge of the source interconnect metal and the source edge in the second direction, the preset distance being less than the distance between at least two via edges and the source edge; wherein the second direction is parallel to the semiconductor substrate and perpendicular to the first direction.
2. The semiconductor device according to claim 1, characterized in that, When the at least two vias are located in the active region, the positional relationship between the source interconnect metal and the at least two vias is: D / 9≤U≤D / 2; Wherein, U is the length of the source interconnect metal extending beyond the edges of the at least two vias in the first direction, and D is the length of the at least two vias themselves in the first direction.
3. The semiconductor device according to claim 1, characterized in that, When the at least two vias are located in the active region and the passive region, the positional relationship between the source interconnect metal and the at least two vias is: D / 9≤U≤Z; Wherein, U is the length of the source interconnect metal extending beyond at least two of the edges of the at least two vias in the first direction, D is the length of the at least two vias themselves in the first direction, and Z is the length of the at least two vias located in the passive region in the first direction.
4. The semiconductor device according to claim 1, characterized in that, The positional relationship between the source interconnect metal and the active region is: D / 10≤V≤D; Wherein, V is the length of the source interconnect metal extending beyond the edge of the active region in the first direction, and D is the length of the at least two vias themselves in the first direction.
5. The semiconductor device according to claim 1, characterized in that, The source interconnect metal is symmetrical at both ends in the first direction.
6. The semiconductor device according to claim 1, characterized in that, In the first direction, the portion of the source interconnect metal that extends beyond the active region is symmetrical in size.
7. The semiconductor device according to claim 1, characterized in that, In the first direction, the portion of the source interconnect metal extending beyond the at least two vias is symmetrical in size.
8. The semiconductor device according to claim 1, characterized in that, The source interconnect metal extends into the passive region in both the first and second directions.
9. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface opposite to each other; the semiconductor substrate includes a semiconductor layer adjacent to the first surface, the semiconductor layer including an active region and a passive region, the passive region being disposed around the active region; An electrode is formed on one side of the active region of the semiconductor layer. The electrode includes a source, a gate, and a drain. Each source includes at least two vias. In a first direction, the edges of the at least two vias extend into or adjacent to the passive region. The first direction is the direction of the center line connecting the at least two vias on the same source. In a second direction, there is a preset distance between the edge of the source interconnect metal and the edge of the source. The preset distance is less than the distance between the edges of the at least two vias and the edge of the source. The second direction is parallel to the semiconductor substrate and perpendicular to the first direction. Source interconnect metal is fabricated on one side of the source electrode, and in a first direction, the end of the source interconnect metal extends beyond the active region into the passive region; A metal layer is formed on the second surface, and the source electrodes are electrically connected to the metal layer on the second surface through the source electrode interconnecting metal and the conductive material in the at least two vias to achieve interconnection of multiple source electrodes.