Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device, belonging to the field of display technology. The display substrate includes a base substrate and a plurality of pixel units arranged on the base substrate; the pixel units include a pixel driving circuit; the pixel driving circuit includes at least a first thin film transistor and a second thin film transistor; a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer are sequentially arranged on the base substrate; the first semiconductor layer includes a first active layer of a first thin film transistor; the first active layer includes a first source region, a first drain region, and a first channel region; the first conductive layer includes a first gate of the first thin film transistor; the second conductive layer includes a first transfer electrode, the first transfer electrode being electrically connected to the first source region through a first connecting via; the second semiconductor layer includes a second active layer of a second thin film transistor; the second active layer includes a second source region, a second drain region, and a second channel region; the second source region is electrically connected to the first transfer electrode through a second connecting via.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display device. Background Art

[0002] With the continuous maturity of low-temperature polycrystalline oxide (LTPO) technology, further optimization and development of LTPO backplane technology have been carried out in depth in order to further improve the resolution based on existing technology and break through the current situation where pixel density (Pixels Per Inch, PPI) cannot be increased due to equipment process capabilities.

[0003] Currently, there are many technical solutions that use stacked thin film transistors (TFTs) for design and development, but the biggest problem with using stacked TFT device solutions for production is via lap joints. The design and process of via lap joints directly determine whether the stacked TFT can really greatly improve the PPI level of existing technical capabilities. Usually, in semiconductor devices, the source and drain metals are overlapped downwards through vias to form the TFT device. In principle, such lap joints have a small contact resistance and will not have a significant impact on the conduction or on-state current of the TFT. However, such a design will use multiple drillings in the overall process steps of the stacked device, and drilling is required on almost every layer structure, which has a significant impact on improving PPI and reducing process steps to reduce costs. Then, the electrical connection is achieved by directly overlapping the semiconductor downwards, but during the lap joint process, deeper lap joint holes are formed in some areas, seriously affecting the lap joint yield. Summary of the Invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a base substrate and a plurality of pixel units disposed on the base substrate; the pixel units include a pixel driving circuit; the pixel driving circuit includes at least a first thin film transistor and a second thin film transistor;

[0006] The display substrate comprises a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer sequentially arranged on the base substrate;

[0007] The first semiconductor layer includes a first active layer of the first thin film transistor; the first active layer includes a first source region, a first drain region, and a first channel region sandwiched between the first source region and the first drain region;

[0008] The first conductive layer includes a first gate electrode of the first thin film transistor;

[0009] The second conductive layer includes a first switching electrode, and the first switching electrode is electrically connected to the first source region through a first connecting via;

[0010] The second semiconductor layer includes a second active layer of the second thin film transistor; the second active layer includes a second source region, a second drain region and a second channel region sandwiched between the second source region and the second drain region; the second source region is electrically connected to the first transfer electrode through a second connecting via.

[0011] Wherein, the pixel driving circuit further includes a third thin film transistor and a fourth thin film transistor;

[0012] The first semiconductor layer further includes a third active layer of a third thin film transistor; the third active layer includes a third source region, a third drain region, and a third channel region sandwiched between the third source region and the third drain region;

[0013] The second conductive layer further includes a second switching electrode, and the second switching electrode is electrically connected to the third drain region through a third connecting via;

[0014] The second semiconductor layer also includes a fourth active layer of a fourth thin film transistor; the fourth active layer includes; the fourth active layer includes a fourth source region, a fourth drain region and a fourth channel region sandwiched between the fourth source region and the fourth drain region; the fourth drain region is electrically connected to the second transfer electrode through a fourth connecting via.

[0015] The second drain region is electrically connected to the second transfer electrode through a fifth connecting via.

[0016] The orthographic projections of the third active layer and the fourth active layer on the base substrate at least partially overlap.

[0017] The display substrate further includes a third conductive layer located on a side of the second semiconductor layer facing away from the base substrate; the third conductive layer includes a fourth gate of the fourth thin film transistor and a second gate of the second thin film transistor.

[0018] Wherein, the pixel driving circuit further includes a fifth thin film transistor and a sixth thin film transistor;

[0019] The display substrate further includes a third semiconductor layer located between the first conductive layer and the second conductive layer;

[0020] The first semiconductor layer further includes a sixth active layer of a sixth thin film transistor; the sixth active layer includes a sixth source region, a sixth drain region, and a sixth channel region sandwiched between the sixth source region and the sixth drain region;

[0021] The third semiconductor layer includes a fifth active layer of the fifth thin film transistor; the fifth active layer includes a fifth source region, a fifth drain region and a fifth channel region sandwiched between the fifth source region and the sixth drain region; the fifth drain region is electrically connected to the sixth drain region through a sixth connecting via.

[0022] Wherein, the second conductive layer further includes a fifth gate of a fifth thin film transistor;

[0023] The first conductive layer further includes a sixth gate of a sixth thin film transistor; orthographic projections of the fifth gate and the sixth gate on the base substrate at least partially overlap.

[0024] The second conductive layer further includes a first light-shielding pattern; the orthographic projection of the first light-shielding pattern on the base substrate covers the orthographic projection of the second channel region on the base substrate.

[0025] The first light-shielding pattern and the first switching electrode are connected to form an integrated structure.

[0026] The pixel driving circuit further includes a storage capacitor; the first conductive layer further includes a first plate of the storage capacitor, and the first plate is electrically connected to the third gate of the third thin film transistor.

[0027] In which, the display substrate also includes a fourth conductive layer located between the first conductive layer and the third semiconductor layer; the fourth conductive layer includes a second plate of the storage capacitor and a first power signal terminal; the first power signal terminal is electrically connected to the sixth source region of the sixth thin film transistor through a seventh connecting via.

[0028] The display substrate further includes a fifth conductive layer between the second semiconductor layer and the second conductive layer; the fifth conductive layer includes a data line; and the data line is electrically connected to the fifth source region of the fifth thin film transistor through an eighth connecting via hole.

[0029] The orthographic projections of the seventh connecting via and the eighth connecting via on the base substrate at least partially overlap.

[0030] In which, the pixel unit also includes a light-emitting device; the display substrate also includes a sixth conductive layer located on the side of the second semiconductor layer away from the base substrate, and the sixth conductive layer includes the first electrode of the light-emitting device; the second conductive layer also includes a third transfer electrode; the first electrode is electrically connected to the third transfer electrode through a ninth connecting via; and the third transfer electrode is electrically connected to the first drain region of the first thin film transistor through a tenth connecting via.

[0031] The display substrate further includes a seventh conductive layer located between the second semiconductor layer and the sixth conductive layer; the seventh conductive layer includes an initialization signal line, and the initialization signal line is electrically connected to the fourth source region of the fourth thin film transistor through an eleventh connecting via.

[0032] In a second aspect, an embodiment of the present disclosure provides a display device, comprising any one of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure.

[0034] Figure 2 Schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.

[0035] Figure 3 A schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure.

[0036] Figure 4 A schematic cross-sectional view of another display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0039] Figure 1 is a schematic diagram of an exemplary display substrate according to an embodiment of the present disclosure; Figure 1As shown, the display substrate 100 of the embodiment of the present disclosure includes a base substrate 11. On the base substrate 11, a plurality of pixel units 12 are arranged in the X direction and the Y direction. The pixel unit 12 includes a pixel driving circuit 121 and a light emitting device 122. The pixel driving circuit 121 can drive the light emitting device 122 to emit light.

[0040] It should be noted that a pixel driving circuit 121 can drive the light-emitting device 122 in one pixel unit 12, or can drive the light-emitting devices 122 in multiple pixel units 12 respectively. In this disclosure, one pixel driving circuit 121 driving the light-emitting device 122 in one pixel unit 12 is used as an example for explanation.

[0041] In some examples, the display substrate 100 can be applied to a display panel, such as an active-matrix organic light emitting diode (AMOLED) display panel. The display substrate 100 can be an array substrate, for example, the pixel units 12 can be arranged on the base substrate 11 according to a predetermined array.

[0042] It should be noted that the material of the base substrate 11 can be an organic material, such as plastic, or an inorganic material, such as glass. The light-emitting device 122 can be a mini LED, OLED, or AMOLED, and is configured to emit light under the drive current generated by the pixel driving circuit 121. In this disclosure, the material of the base substrate 11 and the specific type of the light-emitting device 122 are not further limited.

[0043] Figure 2 FIG. 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure. Figure 2 As shown, the pixel driving circuit 121 includes: a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6 and a storage capacitor Cst.

[0044] Furthermore, the first thin-film transistor T1 functions as a first light-emitting control transistor in the pixel driving circuit 121, with its gate connected to the first light-emitting control terminal EM1, its source connected to the first node N1, and its drain connected to the anode of the light-emitting device 122. The second thin-film transistor T2 functions as a compensation transistor in the pixel driving circuit 121, with its gate connected to the first scan signal terminal Gate1, its drain connected to the second node N2, and its source connected to the first node N1. The third thin-film transistor T4 functions as a driving transistor in the pixel driving circuit 121, with its gate connected to the second node, its source connected to the first node N1, and its drain connected to the third node. The fourth thin-film transistor T4 functions as a reset transistor in the pixel driving circuit 121, with its gate connected to the reset signal terminal Reset, its source connected to the initialization signal terminal Vint, and its drain connected to the second node N2. The fifth thin-film transistor T5 functions as a switching transistor in the pixel driving circuit 121. Its gate is connected to the second scan signal terminal Gate2, its source is connected to the data signal terminal Data, and its drain is connected to the third node N3. The sixth thin-film transistor T6 functions as a second emission control transistor in the pixel driving circuit 121. Its gate is connected to the second emission control terminal EM2, its source is connected to the first power signal terminal VDD, and its drain is connected to the third node N3. A storage capacitor Cst has one end connected to the first power signal terminal VDD and the other end connected to the second node N2.

[0045] It should be noted that thin-film transistors can be classified as P-type transistors or N-type transistors. This disclosure uses N-type transistors, such as NMOS transistors, as an example to describe the technical solutions of this disclosure. That is, in the embodiments of this disclosure, the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, and the sixth thin-film transistor T6 are all N-type transistors. However, it should be understood that the thin-film transistors of the embodiments of this disclosure are not limited to N-type transistors. Those skilled in the art may also utilize P-type transistors, such as PMOS transistors, to implement the functions of one or more thin-film transistors in the embodiments of this disclosure, as needed.

[0046] In the embodiment of the present disclosure, the working process of the pixel driving circuit 121 is divided into: a reset phase S1, a data writing phase S2 and a light emitting phase S3.

[0047] In the reset stage S1, a low-level signal is input to the reset signal terminal Reset, and the fourth thin-film transistor T4 is turned on under the control of the low-level signal. The initialization signal (low-level signal) input to the initialization signal terminal Vint is used to reset the second node N2 and the third thin-film transistor T3 respectively, so that the first node N2 and the third thin-film transistor T3 are restored to a lower potential, thereby preventing the high-level data signal input from the previous frame of display from interfering with the second node N2 and the third thin-film transistor T3, thereby affecting the accuracy of the data signal input this time.

[0048] During the data writing phase S2, a low-level signal is input to the second scan signal terminal Gate2. The fifth thin-film transistor T5 is turned on under the control of the low-level signal, writing the data signal to the source of the third thin-film transistor T3. The storage capacitor Cst then stores the data signal. Simultaneously, the second thin-film transistor T2 is turned on under the control of the low-level signal at the first scan signal terminal Gate1, and the third thin-film transistor T3 is turned on under the control of the data signal stored in the storage capacitor Cst. This connects the gate and drain of the third thin-film transistor T3, placing the third thin-film transistor T3 in a self-saturated state. At this point, the data signal and the threshold voltage of the third thin-film transistor T3 are written to the second node N2, compensating for the threshold voltage of the third thin-film transistor T3.

[0049] In the light-emitting stage S3, a low-level signal is input to the first switch control signal terminal EM1 and the second switch control signal terminal EM2, and the first thin-film transistor T1 and the sixth thin-film transistor T6 are turned on under the control of the low-level signal. The third thin-film transistor can convert the voltage of the first power signal terminal VDD into a driving current, so that the light-emitting device 122 between the first power signal terminal VDD and the second power signal terminal VSS forms a current loop, driving the light-emitting device 122 to emit light.

[0050] It should be noted that the pixel driving circuit can be a 7T1C architecture, a 7T2C architecture, a 6T1C architecture, a 6T2C architecture, or a 9T2C architecture, etc. The embodiments of the present disclosure are described using a 6T1C architecture as an example. However, it should be understood that those skilled in the art can change the circuit structure according to actual conditions.

[0051] As users' requirements for display effects continue to increase, improving the PPI of display devices is a problem that needs to be solved in the current display field. While achieving high PPI of display devices, the manufacturing process also needs to be improved. In order to achieve the improvement of the PPI of display devices, some components in the pixel driving circuit adopt a stacked design to reduce the size of the pixel driving circuit, thereby reducing the size of the pixel unit. In a display substrate of a certain area, more pixel units can be set, thereby improving the PPI of the display device. However, in the existing process, most of the component connections of the pixel driving circuit need to be electrically connected through connecting vias, and some connecting vias need to pass through almost all layer structures, resulting in the connecting vias being too deep, thereby affecting the yield; on the other hand, since most of the components in the pixel driving circuit are electrically connected through connecting vias, the manufacturing process and cost are relatively high.

[0052] In view of this, an embodiment of the present disclosure provides a display substrate, which includes a base substrate and a plurality of pixel units arranged on the base substrate. The pixel units include a pixel driving circuit, and the structure of the pixel driving circuit can solve the above-mentioned problems.

[0053] The display substrate of the embodiment of the present disclosure is described below with reference to the accompanying drawings and specific embodiments.

[0054] The embodiment of the present disclosure provides a display substrate, Figure 3 A cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the pixel driving unit 121 includes: a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a storage capacitor Cst, a first power signal terminal VDD, an initialization signal line Vint, and a data line Data. Multiple layer structures are sequentially arranged on the base substrate 11. Each thin-film transistor includes an active layer and a gate. The active layer includes a source region, a drain region, and a channel region between the source and drain regions. The active layer of each thin-film transistor is located in each semiconductor layer of the multiple layer structures on the base substrate, and the gate of each thin-film transistor is located in each conductive layer of the multiple layer structures on the base substrate. The first power signal terminal VDD, the initialization signal line Vint, the data line Data, and the bipolar plates of the storage capacitor Cst are also located in each conductive layer of the multiple layer structures on the base substrate 11. The display substrate also includes a gate insulating layer, an interlayer insulating layer, a buffer layer, and a passivation layer PVX arranged on the base substrate 11.

[0055] In some examples, the display substrate includes a first semiconductor layer 21, a first conductive layer 31, a second conductive layer 32, and a second semiconductor layer 22 sequentially disposed on a base substrate 11. The first semiconductor layer 21 includes a first active layer of a first thin-film transistor T1, the first active layer including a first source region T11, a first drain region T12, and a first channel region sandwiched between the first source region T11 and the first drain region T12. The first conductive layer 31 includes a first gate electrode T13 of the first thin-film transistor T1. The second conductive layer 32 includes a first transfer electrode 51, which is electrically connected to the first source region T11 via a first connection via 1. The second semiconductor layer 22 includes a second active layer of a second thin-film transistor T2, the second active layer including a second source region T21, a second drain region T22, and a second channel region T24 sandwiched between the second source region T21 and the second drain region T22. The second source region T21 is electrically connected to the first transfer electrode 51 via a second connection via 2. The first thin-film transistor T1 and the second thin-film transistor T2 are electrically connected via a first transfer electrode 51 located in the second conductive layer 3232. The source of the first thin-film transistor T1, located in the first source region T11, is electrically connected to the first transfer electrode 51 through a first connection via 1. The source of the second thin-film transistor T2, located in the second source region T21, is electrically connected to the first transfer electrode 51 through a second connection via 2. The first connection via 1 penetrates the first gate T13 insulating layer GI1, the second gate T23 insulating layer GI2, the first buffer layer Buffer1, and the third gate T33 insulating layer GI3 to achieve electrical connection to the first transfer electrode 51. The second connection via 2 penetrates the second buffer layer Buffer2 and the first interlayer insulating layer ILD1 to achieve electrical connection to the first transfer electrode 51. The source of the first thin-film transistor T1 is electrically connected to the first transfer electrode 51 from above, and the source of the second thin-film transistor T2 is electrically connected from below to the first transfer electrode 51.

[0056] It should be understood that during the connection process under the source electrode of the second thin-film transistor T2, no excessively deep connection vias are formed. By using the first transfer electrode 51, two connection vias that penetrate a structure with fewer layers are used instead of the connection via that penetrates a structure with more layers, thereby achieving electrical connection between the first thin-film transistor T1 and the second thin-film transistor T2. The use of the transfer electrode prevents the connection vias from penetrating multiple layers, thereby improving the manufacturing yield of the pixel unit.

[0057] Furthermore, the first gate electrode T13 insulating layer GI1 is disposed on the side of the first semiconductor layer 21 facing away from the substrate 11. The first gate electrode T13 insulating layer GI1 can protect the first semiconductor layer 21. The second gate electrode T23 insulating layer GI2 is disposed on the side of the first conductive layer 31 facing away from the substrate 11. The second gate electrode T23 insulating layer GI2 can protect the first conductive layer 31. The fourth gate electrode T43 insulating layer GI4 is disposed on the side of the second semiconductor layer 22 facing away from the substrate 11. The fourth gate electrode T43 insulating layer GI4 can protect the second semiconductor layer 22. The first interlayer insulating layer ILD1 is disposed on the side of the second conductive layer 32 facing away from the substrate 11. The first interlayer insulating layer ILD1 can protect the second conductive layer 32.

[0058] It should be noted that, in the embodiment of the present disclosure, the materials of the first gate T13 insulating layer GI1 , the second gate T23 insulating layer GI2 , the fourth gate T43 insulating layer GI4 and the first interlayer insulating layer ILD1 are not further limited, as long as the materials can achieve the insulation function.

[0059] In some examples, the pixel driving circuit further includes a third thin-film transistor T3 and a fourth thin-film transistor T4. The first semiconductor layer 21 further includes a third active layer of the third thin-film transistor T3, the third active layer including a third source region, a third drain region, and a third channel region sandwiched between the third source region and the third drain region. The second conductive layer 32 further includes a second transfer electrode 52, the second transfer electrode 52 being electrically connected to the third drain region via a third connection. The second semiconductor layer 22 further includes a fourth active layer of the fourth thin-film transistor T4, the fourth active layer including a fourth source region T41, a fourth drain region T42, and a fourth channel region sandwiched between the fourth source region T41 and the fourth drain region T42, the fourth drain region T42 being electrically connected to the second transfer electrode 52 via a fourth connection via4. The third thin-film transistor T3 and the fourth thin-film transistor T4 are electrically connected via a second transfer electrode 52 located in the second conductive layer 32. The source of the third thin-film transistor T3 in the third source region is electrically connected to the second transfer electrode 52 via a third connection via 3. The drain of the fourth thin-film transistor T4 in the fourth drain region T42 is electrically connected to the second transfer electrode 52 via a fourth connection via 4. The third connection via 3 penetrates the third gate electrode T33 insulating layer GI3, the first buffer layer Buffer1, and the second gate electrode T23 insulating layer GI2. The fourth connection via 4 penetrates the second buffer layer Buffer2 and the first interlayer insulating layer ILD1. With the source of the third thin-film transistor T3 connected to the second transfer electrode 52 from above and the drain of the fourth thin-film transistor T4 connected to the second transfer electrode 52 from below, the source of the third thin-film transistor T3 and the drain of the fourth thin-film transistor T4 are electrically connected.

[0060] It should be understood that during the connection process under the source electrode of the fourth thin-film transistor T4, no excessively deep connection vias are formed. By using the second transfer electrode 52, two connection vias that penetrate a structure with fewer layers are used instead of a connection via that penetrates a structure with more layers, thereby achieving electrical connection between the third thin-film transistor T3 and the fourth thin-film transistor T4. The use of a transfer electrode prevents the connection vias from penetrating multiple layers, thereby improving the manufacturing yield of the pixel unit.

[0061] Furthermore, the orthographic projections of the third active layer of the third thin-film transistor T3 and the fourth active layer of the fourth thin-film transistor T4 on the base substrate 11 at least partially overlap. The display substrate also includes a third conductive layer 33 disposed on the base substrate 11, located on the side of the second semiconductor layer 22 facing away from the base substrate 11. The third conductive layer 33 includes a fourth gate electrode T43 of the fourth thin-film transistor T4 and a second gate electrode T23 of the second thin-film transistor T2. The orthographic projections of the third gate electrode T33 and the fourth gate electrode T43 on the base substrate 11 also at least partially overlap. By stacking thin-film transistors in this manner, the area of ​​the pixel driving circuit is reduced, thereby reducing the area of ​​the pixel unit. This allows more pixel units to be arranged within a given display substrate area, thereby improving the PPI of the display device.

[0062] In some examples, the second drain region T22 of the second thin-film transistor T2 is electrically connected to the second transfer electrode 52 via a fifth connection via via5. The second transfer electrode 52 is also electrically connected to a third connection via via3 and a fourth connection via via4. Through the second transfer platform, the second transfer electrode 52 is connected to the drain of the second thin-film transistor T2 in the second drain region T22, the third gate T33 of the third thin-film transistor T3, and the drain of the fourth thin-film transistor T4 in the fourth drain region T42. The fifth connection via via5 penetrates the second buffer layer Buffer2 and the first interlayer insulating layer ILD1. The second transfer electrode 52 serves as the second node N2 of the aforementioned pixel driving circuit.

[0063] In some examples, the pixel driving circuit further includes a fifth thin-film transistor T5 and a sixth thin-film transistor T6, and the display substrate further includes a third semiconductor layer 23 disposed on the base substrate 11 between the first conductive layer 31 and the second conductive layer 32. The first semiconductor layer 21 further includes a sixth active layer of the sixth thin-film transistor T6, the sixth active layer including a sixth source region T61, a sixth drain region T62, and a sixth channel region sandwiched between the sixth source region T61 and the sixth drain region T62. The third semiconductor layer 23 includes a fifth active layer of the fifth thin-film transistor T5; the fifth active layer includes a fifth source region T51, a fifth drain region T52, and a fifth channel region sandwiched between the fifth source region T51 and the sixth drain region T62. The fifth drain region T52 is electrically connected to the sixth drain region T62 via a sixth connecting via 6. The sixth connecting via 6 penetrates the first buffer layer Buffer1, the second gate electrode T23 insulating layer GI2, and the first gate electrode T13 insulating layer GI1. The second conductive layer 32 further includes a fifth gate electrode T53 of the fifth thin-film transistor T5, and the first conductive layer 31 further includes a sixth gate electrode T63 of the sixth thin-film transistor T6. The orthographic projections of the fifth gate electrode T53 and the sixth gate electrode T63 on the base substrate 11 at least partially overlap. This stacked arrangement of thin-film transistors further reduces the area of ​​the pixel driving circuit, thereby reducing the area of ​​the pixel unit. This allows more pixel units to be arranged within a given display substrate area, thereby improving the PPI of the display device.

[0064] Furthermore, the third gate T33 insulating layer GI3 is disposed on a side of the third semiconductor layer 23 away from the base substrate 11 , and the third gate T33 insulating layer GI3 can protect the third semiconductor layer 23 .

[0065] It should be noted that, in the embodiment of the present disclosure, the material of the insulating layer GI3 of the third gate T33 is not further limited, and the material can achieve the insulation function.

[0066] In some examples, the pixel driving circuit further includes a storage capacitor Cst, and the first conductive layer 31 further includes a first plate Cst1 of the storage capacitor Cst, which is electrically connected to the third gate electrode T33 of the third thin-film transistor T3. The display substrate further includes a fourth conductive layer 34 disposed on the base substrate 11 between the first conductive layer 31 and the third semiconductor layer 23. The fourth conductive layer 34 includes a second plate Cst2 of the storage capacitor Cst and a first power signal terminal VDD. The first power signal terminal VDD is electrically connected to the sixth source region T61 of the sixth thin-film transistor T6 via a seventh connecting via via7. The seventh connecting via7 penetrates the first gate electrode T13 insulating layer GI1 and the second gate electrode T23 insulating layer GI2. During the manufacturing process, the first plate Cst1 of the storage capacitor Cst and the third gate electrode T33 of the third thin-film transistor T3 can be integrally formed, and the first power signal terminal VDD can be provided on the same layer as the first plate Cst1 of the storage capacitor Cst, thereby reducing the manufacturing process.

[0067] In some examples, the display substrate further includes a fifth conductive layer 35 disposed on the base substrate 11 between the second semiconductor layer 22 and the second conductive layer 32, and the fifth conductive layer 35 includes a data line Data. The data line Data is electrically connected to the fifth source region T51 of the fifth thin film transistor T5 through an eighth connection via via8. The eighth connection via8 penetrates the third gate T33 insulating layer GI3 and the first interlayer insulating layer ILD1. The orthographic projections of the seventh connection via via7 and the eighth connection via via8 on the base substrate 11 at least partially overlap. By stacking pixel driving circuit elements in this manner, the area of ​​the pixel driving circuit is further reduced, thereby reducing the area of ​​the pixel unit, so that more pixel units can be arranged on a display substrate of a certain area, thereby improving the PPI of the display device.

[0068] Furthermore, a first buffer layer Buffer1 is provided on the side of the fourth conductive layer 34 away from the base substrate 11, and a second buffer layer Buffer2 is provided on the side of the fifth conductive layer 35 away from the base substrate 11. The first buffer layer Buffer1 and the second buffer layer Buffer2 are typically made of inorganic materials, such as silicon oxide, silicon nitride, etc., to achieve the effect of blocking water, oxygen, and alkaline ions. Therefore, the first buffer layer Buffer1 and the second buffer layer Buffer2 are relatively hard and thick.

[0069] It should be noted that the present disclosure does not further limit the specific materials of the first buffer layer Buffer1 and the second buffer layer Buffer2.

[0070] In some examples, the pixel unit further includes a light-emitting device, and the display substrate further includes a sixth conductive layer 36 disposed on the base substrate 11 on the side of the second semiconductor layer 22 facing away from the base substrate 11. The sixth conductive layer 36 includes a first electrode 61 of the light-emitting device. The second conductive layer 32 further includes a third transfer electrode 53, and the first electrode 61 of the light-emitting device is electrically connected to the third transfer electrode 53 through a ninth connection via 9. The third transfer electrode 53 is electrically connected to the drain electrode of the first thin-film transistor T1 located in the first drain region T12 through a tenth connection via 10. The ninth connection via 9 penetrates the passivation layer PVX, the second interlayer insulating layer ILD2, the fourth gate T43 insulating layer GI4, the second buffer layer Buffer2, and the first interlayer insulating layer ILD1. The tenth connection via 10 penetrates the third gate T33 insulating layer GI3, the first buffer layer Buffer1, the second gate T23 insulating layer GI2, and the first gate T13 insulating layer GI1. It should be understood that when connecting the first electrode 61 of the light-emitting device directly to the drain electrode of the first thin-film transistor T1 located at the bottom in the first drain region T12 through a connecting via, it is necessary to penetrate almost all layers of the structure, resulting in an excessively long via, which affects the yield. By switching on the third transfer platform, two connecting vias that penetrate fewer layers of the structure are used instead of the connecting via that passes through more layers, thereby improving the manufacturing yield of the pixel unit.

[0071] It should be noted that the first transfer electrode 51, the second transfer electrode 52, the third transfer electrode 53, and the first light-shielding metal can be fabricated on the second conductive layer 32 simultaneously with the fifth gate electrode T53 of the fifth thin-film transistor T5. Only one mask is required to form the first transfer electrode 51, the second transfer electrode 52, the third transfer electrode 53, the first light-shielding metal, and the fifth gate electrode T53 of the fifth thin-film transistor T5. This method reduces the number of manufacturing processes and lowers production costs.

[0072] In some examples, the display substrate further includes a seventh conductive layer 37 disposed on the base substrate 11 between the second semiconductor layer 22 and the sixth conductive layer 36. The seventh conductive layer 37 includes an initialization signal line Vint, which is electrically connected to the fourth source region T41 of the fourth thin film transistor T4 through an eleventh connection via 11. The eleventh connection via 11 penetrates the second interlayer insulating layer ILD2 and the fourth gate T43 insulating layer GI4. A passivation layer PVX is disposed on the side of the seventh conductive layer 37 away from the base substrate 11 to protect the seventh conductive layer 37. It should be noted that the material of the passivation layer PVX can be the same as the gate insulating layer and the interlayer insulating layer material, or other insulating materials can be used. In the present disclosure, the passivation layer PVX is not further limited.

[0073] In some examples, the second conductive layer 32 further includes a first light-shielding pattern 54. The orthographic projection of the first light-shielding pattern 54 on the base substrate 11 covers the orthographic projection of the second channel region T24 of the second thin-film transistor T2 on the base substrate 11. The first light-shielding pattern 54 is used to block light reflected from the base substrate 11 to ensure that the second channel region T24 of the second thin-film transistor T2 is not affected by the light, so that the second thin-film transistor T2 can operate normally.

[0074] Further, Figure 4 A cross-sectional schematic diagram of another display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the first light shielding pattern 54 is connected to the first transfer electrode 51 as an integral structure. During production, the first light shielding pattern 54 and the first transfer electrode 51 can be integrally formed to reduce the process flow.

[0075] With respect to the above-mentioned display substrate, the embodiments of the present disclosure provide relevant manufacturing processes for preparing the display substrate.

[0076] S1 . Form a first semiconductor layer 21 on the base substrate 11 .

[0077] Specifically, a semiconductor layer is first deposited on the base substrate 11, and then a photoresist is coated on the side of the semiconductor layer facing away from the base substrate 11 and subjected to processes such as exposure, development, etching, and stripping to obtain a first semiconductor layer 21, that is, a first active layer of the first thin film transistor T1, a third active layer of the third thin film transistor T3, and a sixth active layer of the sixth thin film transistor T6.

[0078] Furthermore, in order to reduce process difficulty, improve work efficiency, and reduce the occupied area of ​​the thin film transistor active layer, the first active layer of the first thin film transistor T1, the third active layer of the third thin film transistor T3, and the sixth active layer of the sixth thin film transistor T6 can be connected into an integrated structure.

[0079] It should be noted that a semiconductor layer is deposited on the base substrate 11 . The semiconductor layer can be deposited on the base substrate 11 by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0080] S2 , forming a first gate T13 insulating layer GI1 on a side of the first semiconductor layer 21 facing away from the substrate 11 .

[0081] Specifically, a first gate T13 insulating layer GI1 is deposited on a side of the first semiconductor layer 21 facing away from the substrate 11 .

[0082] The deposition preparation methods involved in the embodiments of the present disclosure can all adopt the above-mentioned deposition preparation method of the first semiconductor layer 21, and the repeated parts will not be repeated.

[0083] S3 , forming a first conductive layer 31 on a side of the insulating layer GI1 of the first gate electrode T13 facing away from the base substrate 11 .

[0084] Specifically, first, a conductive layer is deposited on the side of the insulating layer GI1 of the first gate electrode T13 facing away from the base substrate 11; then, a photoresist is coated on the side of the conductive layer facing away from the base substrate 11, and exposure, development, etching, stripping and other processes are performed according to pre-set positions to obtain a first conductive layer 31, that is, the first gate electrode T13 of the first thin film transistor T1, the third gate electrode T33 of the third thin film transistor T3, the sixth gate electrode T63 of the sixth thin film transistor T6, and the first plate Cst1 of the storage capacitor Cst are obtained.

[0085] S4 , using the first conductive layer 31 as a mask, doping the first semiconductor layer 21 .

[0086] Exemplarily, the first conductive layer 31 is used as a mask plate to heavily dope the first semiconductor layer 21 with N-type impurities (i.e., phosphorus ions). When phosphorus particles are doped in both the source region and the drain region, the conductivity of the source region and the drain region of the active region in the first thin film transistor T1, the third thin film transistor T3, and the sixth thin film transistor T6 are respectively improved, that is, the conductivity of the source and the drain of the first thin film transistor T1, the third thin film transistor T3, and the sixth thin film transistor T6 are improved.

[0087] S5 , depositing a second gate T23 insulating layer GI2 on the side of the first conductive layer 31 facing away from the base substrate 11 .

[0088] S6. Form a fourth conductive layer 34 on the side of the second gate electrode T23 insulating layer GI2 away from the base substrate 11, thereby forming the first power signal terminal VDD and the second electrode plate Cst2 of the storage capacitor Cst. Form a seventh connecting via hole via7 that penetrates the first gate electrode T13 insulating layer GI1 and the second gate electrode T23 insulating layer GI2 to electrically connect the first power signal terminal VDD to the source electrode of the sixth active layer of the sixth thin-film transistor T6.

[0089] S7 , depositing a first buffer layer Buffer1 on the side of the fourth conductive layer 34 facing away from the base substrate 11 .

[0090] S8. Deposit a third semiconductor layer 23 on the side of the first buffer layer Buffer1 away from the base substrate 11, and make a sixth connecting via hole via6 that penetrates the first buffer layer Buffer1, the second gate T23 insulating layer GI2 and the first gate T13 insulating layer GI1. The drain region of the fifth active layer of the fifth thin film transistor T5 in the third semiconductor layer 23 is electrically connected to the drain of the sixth active layer of the sixth thin film transistor T6 in the first semiconductor layer 21 through the sixth connecting via hole via6.

[0091] S9 , depositing a third gate T33 insulating layer GI3 on ​​a side of the third semiconductor layer 23 facing away from the substrate 11 .

[0092] S10 , depositing a second conductive layer 32 on a side of the insulating layer GI3 of the third gate electrode T33 facing away from the substrate 11 .

[0093] Specifically, a single mask is used to deposit and form the fifth gate electrode T53 of the fifth thin-film transistor T5, the first transfer electrode 51, the second transfer electrode 52, the third transfer electrode 53, and the first light-shielding pattern 54. A third connection via hole via 3 is formed through the third gate electrode T33 insulation layer GI3, the first buffer layer Buffer1, and the second gate electrode T23 insulation layer GI2. A first connection via hole via 1 and a ninth connection via hole via 9 are also formed through the third gate electrode T33 insulation layer GI3, the first buffer layer Buffer1, the second gate electrode T23 insulation layer GI2, and the first gate electrode T13 insulation layer GI1.

[0094] S11 , depositing a first interlayer insulating layer ILD1 on a side of the second conductive layer 32 facing away from the substrate 11 .

[0095] For example, the first interlayer insulating layer ILD1 may include, for example, a silicon compound or a metal oxide.

[0096] S12 , depositing a fifth conductive layer 35 on a side of the first interlayer insulating layer ILD1 facing away from the substrate 11 .

[0097] The fifth conductive layer 35 includes a data line Data, which is electrically connected to the source of the fourth active layer of the fourth thin film transistor T4 through an eighth connection via 8 that penetrates the first interlayer insulating layer ILD1 and the third gate T33 insulating layer GI3.

[0098] S13 , depositing a second buffer layer Buffer2 on a side of the fifth conductive layer 35 facing away from the base substrate 11 .

[0099] The second buffer layer Buffer2 may be a buffer layer made of the same material as the first buffer layer Buffer1; or, it may be a buffer layer made of other materials, which may be set according to actual application scenarios, requirements and experience, and is not specifically limited in the embodiments of the present disclosure.

[0100] S14 , depositing a second semiconductor layer 22 on a side of the second buffer layer Buffer2 facing away from the substrate 11 .

[0101] The second semiconductor layer 22 includes a second active layer of the second thin-film transistor T2 and a fourth active layer of the fourth thin-film transistor T4. The second thin-film transistor T2 is electrically connected to the first transfer electrode 51 and the second transfer electrode 52 via a second connection via 2 and a fifth connection via 5, respectively. The fourth thin-film transistor T4 is electrically connected to the second transfer electrode 52 via a fourth connection via 4. The second connection via 2, the fifth connection via 5, and the fourth connection via 4 extend through the second buffer layer Buffer2 and the first interlayer dielectric layer.

[0102] First, an oxide semiconductor layer is deposited. The second channel region T24 of the second active layer of the second thin-film transistor T2 and the fourth channel region of the fourth active layer of the fourth thin-film transistor T4 are made of indium gallium zinc oxide (IGZO). Then, using the third conductive layer 33 as a mask, the second semiconductor layer 22 is doped to make the source and drain regions of the active layer conductive.

[0103] Exemplarily, the third conductive layer 33 is used as a mask plate to heavily dope the third semiconductor layer 23 with N-type impurities (i.e., phosphorus ions). When phosphorus particles are doped in both the source and drain regions, the conductivity of the source and drain regions of the active regions in the driving transistor T4 and the light-emitting control transistor T5 are respectively improved, that is, the conductivity of the source and drain of the driving transistor T4 and the light-emitting control transistor T5 is improved.

[0104] S15 , depositing a fourth gate T43 insulating layer GI4 on the side of the third conductive layer 33 facing away from the base substrate 11 .

[0105] S16 , depositing a third conductive layer 33 on one side of the insulating layer GI3 of the third gate T33 .

[0106] The third conductive layer 33 includes a second gate electrode T23 of the second thin film transistor T2 and a fourth gate electrode T43 of the fourth thin film transistor T4 .

[0107] S17 , forming a second interlayer insulating layer ILD2 on a side of the third conductive layer 33 facing away from the base substrate 11 .

[0108] S18 , depositing a seventh conductive layer 37 on the side of the second interlayer insulating layer ILD2 facing away from the base substrate 11 .

[0109] The seventh conductive layer 37 includes an initialization signal terminal connected to the source of the fourth active layer of the fourth thin film transistor T4 through an eleventh connection via 11. The eleventh connection via 11 penetrates the second interlayer insulating layer ILD2 and the fourth gate T43 insulating layer GI4.

[0110] S19 , forming a passivation layer PVX on a side of the seventh conductive layer 37 away from the base substrate 11 .

[0111] S20 , forming a sixth conductive layer 36 on a layer of the passivation layer PVX away from the base substrate 11 .

[0112] The sixth conductive layer 36 includes a first electrode 61 of the light emitting element, which is electrically connected to the third transfer electrode 53 of the second conductive layer 32 through the tenth connecting via 10. This further electrically connects the first electrode 61 of the light emitting device to the drain of the first active layer of the first thin film transistor T1.

[0113] In the above-described method for manufacturing a display substrate, a pixel driving circuit for a pixel unit is formed on a base substrate 11, wherein two connection vias that penetrate a structure with fewer layers are used instead of a connection via that penetrates a structure with more layers. Using a transfer electrode, the two connection vias that penetrate the structure with fewer layers are electrically connected to each other, making them equivalent to a single connection via that penetrates a structure with more layers. This prevents the pixel unit yield from being affected by the penetration of multiple layers.

[0114] Here, the specific structure of the display substrate in the method of forming the pixel unit can refer to the structure of the display substrate in the above-mentioned display substrate embodiment, and will not be repeated here.

[0115] In some embodiments, the active layer of the thin film transistor includes a source region, a drain region, and a channel region sandwiched between the source region and the drain region. The source region serves as the source electrode of the thin film transistor, and the drain region serves as the drain electrode of the thin film transistor.

[0116] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display substrates.

[0117] The display substrate described above is used in a display device. By stacking the components of the pixel driver circuit, the area of ​​the pixel driver circuit is reduced, which in turn reduces the area of ​​the pixel units. This allows more pixel units to be installed within a given display area, thereby improving the display device's PPI. Furthermore, while shortening the process flow and reducing process costs, two connecting vias that penetrate fewer layers of the structure replace connecting vias that would otherwise affect the pixel component yield, thereby improving the product quality of the display device.

[0118] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate comprising a base substrate and a plurality of pixel units disposed on the base substrate; the pixel units comprising a pixel driving circuit; the pixel driving circuit comprising at least a first thin film transistor and a second thin film transistor; The display substrate comprises a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer sequentially arranged on the base substrate; The first semiconductor layer includes a first active layer of the first thin film transistor; the first active layer includes a first source region, a first drain region, and a first channel region sandwiched between the first source region and the first drain region; The first conductive layer includes a first gate electrode of the first thin film transistor; The second conductive layer includes a first switching electrode, and the first switching electrode is electrically connected to the first source region through a first connecting via; The second semiconductor layer includes a second active layer of the second thin film transistor; the second active layer includes a second source region, a second drain region, and a second channel region sandwiched between the second source region and the second drain region; the second source region is electrically connected to the first transfer electrode through a second connecting via; in, The pixel driving circuit further includes a third thin film transistor and a fourth thin film transistor; The first semiconductor layer further includes a third active layer of a third thin film transistor; the third active layer includes a third source region, a third drain region, and a third channel region sandwiched between the third source region and the third drain region; The second conductive layer further includes a second switching electrode, and the second switching electrode is electrically connected to the third gate through a third connecting via hole; The second semiconductor layer also includes a fourth active layer of a fourth thin film transistor; the fourth active layer includes; the fourth active layer includes a fourth source region, a fourth drain region and a fourth channel region sandwiched between the fourth source region and the fourth drain region; the fourth drain region is electrically connected to the second transfer electrode through a fourth connecting via.

2. The display substrate according to claim 1, wherein The second drain region is electrically connected to the second transfer electrode through a fifth connection via.

3. The display substrate according to claim 1, wherein The orthographic projections of the third active layer and the fourth active layer on the base substrate at least partially overlap.

4. The display substrate according to claim 3, wherein: The display substrate further includes a third conductive layer located on a side of the second semiconductor layer facing away from the base substrate; the third conductive layer includes a fourth gate of the fourth thin film transistor and a second gate of the second thin film transistor.

5. The display substrate according to claim 1, wherein The pixel driving circuit further includes a fifth thin film transistor and a sixth thin film transistor; The display substrate further includes a third semiconductor layer located between the first conductive layer and the second conductive layer; The first semiconductor layer further includes a sixth active layer of a sixth thin film transistor; the sixth active layer includes a sixth source region, a sixth drain region, and a sixth channel region sandwiched between the sixth source region and the sixth drain region; The third semiconductor layer includes a fifth active layer of the fifth thin film transistor; the fifth active layer includes a fifth source region, a fifth drain region and a fifth channel region sandwiched between the fifth source region and the sixth drain region; the fifth drain region is electrically connected to the sixth drain region through a sixth connecting via. The display substrate according to claim 5 , wherein: The second conductive layer further includes a fifth gate electrode of a fifth thin film transistor; The first conductive layer further includes a sixth gate of a sixth thin film transistor; orthographic projections of the fifth gate and the sixth gate on the base substrate at least partially overlap.

7. The display substrate according to claim 1, wherein: The second conductive layer further includes a first light-shielding pattern; an orthographic projection of the first light-shielding pattern on the base substrate covers an orthographic projection of the second channel region on the base substrate.

8. The display substrate according to claim 7, wherein: The first light-shielding pattern and the first switching electrode are connected to form an integrated structure.

9. The display substrate according to claim 1, wherein: The pixel driving circuit further includes a storage capacitor; the first conductive layer further includes a first plate of the storage capacitor, and the first plate is electrically connected to the third gate of the third thin film transistor.

10. The display substrate according to claim 5, wherein: The display substrate also includes a fourth conductive layer located between the first conductive layer and the third semiconductor layer; the fourth conductive layer includes a second plate of a storage capacitor and a first power signal terminal; the first power signal terminal is electrically connected to the sixth source region of the sixth thin film transistor through a seventh connecting via.

11. The display substrate according to claim 10, wherein: The display substrate further includes a fifth conductive layer between the second semiconductor layer and the second conductive layer; the fifth conductive layer includes a data line; and the data line is electrically connected to the fifth source region of the fifth thin film transistor through an eighth connecting via hole.

12. The display substrate according to claim 11, wherein: The orthographic projections of the seventh connecting via and the eighth connecting via on the base substrate at least partially overlap.

13. The display substrate according to claim 1, wherein The pixel unit further includes a light-emitting device; the display substrate further includes a sixth conductive layer located on a side of the second semiconductor layer facing away from the base substrate, the sixth conductive layer including a first electrode of the light-emitting device; the second conductive layer further includes a third transfer electrode; the first electrode is electrically connected to the third transfer electrode through a ninth connection via; The third switching electrode is electrically connected to the first drain region of the first thin film transistor through a tenth connecting via hole.

14. The display substrate according to claim 13, wherein: The display substrate further includes a seventh conductive layer located between the second semiconductor layer and the sixth conductive layer; the seventh conductive layer includes an initialization signal line, and the initialization signal line is electrically connected to the fourth source region of the fourth thin film transistor through an eleventh connecting via hole.

15. A display device, wherein: The display device comprises the display substrate according to any one of claims 1 to 14.

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