Semiconductor structure and semiconductor structure manufacturing method

Abstract

The disclosed embodiments relate to the semiconductor field, and provide a semiconductor structure and a method for manufacturing the semiconductor structure, wherein the semiconductor structure comprises: a substrate having a power supply port; a storage module located on the substrate; the storage module comprises storage chips stacked along a first direction, the first direction being parallel to the upper surface of the substrate; each of the storage chips has a power supply signal line, at least one of the plurality of storage chips has a power supply wiring layer, the power supply signal line is electrically connected to the power supply wiring layer; the power supply wiring layer comprises a first wiring layer and a second wiring layer connected, the plane where the first wiring layer is located is perpendicular to the upper surface of the substrate; the second wiring layer is located on the surface of the storage chip away from the substrate; a lead connected to the second wiring layer; and a lead frame connected to the lead and the power supply port. The disclosed embodiments can at least improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] To improve the integration of semiconductor structures, more than one memory chip can be placed in the same package structure. HBM (High Bandwidth Memory) is a new type of memory. The memory chip stacking technology represented by HBM expands the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thereby greatly improving the density of memory chips and achieving large capacity and high bandwidth.

[0003] However, as the number of stacked layers increases, the performance of HBM needs to be improved. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the semiconductor structure, which are at least beneficial to improving the performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate, the substrate having a power supply port; a storage module, located on the substrate; the storage module includes storage chips stacked along a first direction, the first direction being parallel to the upper surface of the substrate; each of the storage chips has a power supply signal line, at least one of the multiple storage chips has a power supply wiring layer, the power supply signal line is electrically connected to the power supply wiring layer; the power supply wiring layer includes a first wiring layer and a second wiring layer that are connected, the plane where the first wiring layer is located is perpendicular to the upper surface of the substrate; the second wiring layer is located on the surface of the storage chip away from the substrate; a lead, connected to the second wiring layer; a lead frame, connected to the lead and the power supply port.

[0006] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, the manufacturing method comprising: providing a substrate, the substrate having a power supply port; providing a storage module; the storage module comprising storage chips stacked along a first direction; each of the storage chips having a power supply signal line, at least one of the multiple storage chips having a power supply wiring layer, the power supply signal line being electrically connected to the power supply wiring layer; the power supply wiring layer comprising a first wiring layer and a second wiring layer connected to each other, the plane where the first wiring layer is located being perpendicular to the upper surface of the substrate; the second wiring layer being located on the surface of the storage chip away from the substrate; fixing the storage module on the substrate, and the first direction being parallel to the upper surface of the substrate; providing leads and a lead frame, connecting the leads to the second wiring layer; connecting the lead frame to the leads and the power supply port.

[0007] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the stacking direction of the multiple memory chips is parallel to the substrate, so the communication distances of the multiple memory chips are the same, which is conducive to unifying the communication delay and improving the operating rate. In addition, the power supply wiring layer in the memory chip can lead the power supply signal line out of the memory chip, thereby realizing wired power supply. The stability and reliability of wired power supply are relatively high. In addition, the lead is combined with the lead frame to improve the flexibility of the connection method and the strength of the structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0009] Figure 1 A schematic diagram of a semiconductor structure is shown;

[0010] Figure 2 , Figure 5 Different cross-sectional views of a semiconductor structure provided by an embodiment of the present disclosure are respectively shown;

[0011] Figure 3 , Figure 4 , Figure 6 Schematic diagrams of different active surfaces of a memory chip provided by an embodiment of the present disclosure are respectively shown;

[0012] Figure 7 A top view of a lead frame, leads, and a power supply wiring layer provided by an embodiment of the present disclosure is shown.

[0013] Figure 8-Figure 9A structural schematic diagram corresponding to each step in a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0014] As can be seen from the background technology, the performance of HBM needs to be improved. After analysis, it was found that the main reason is that HBM adopts a parallel stacking method, that is, the front of multiple memory chips 200 is parallel to the upper surface of the substrate 300. In other words, the arrangement direction of multiple memory chips 200 is perpendicular to the upper surface of the substrate 300. When the number of stacked layers is large, the communication distance between the topmost memory chip 200 and the bottommost memory chip 200 and the logic chip 400 is quite different, resulting in a large difference in the communication delay between different memory chips 200 and the logic chip 400, thereby affecting the operating rate of the product. In addition, the power supply method of the semiconductor structure will also affect its performance.

[0015] The disclosed embodiment provides a semiconductor structure, wherein a plurality of memory chips are stacked in a direction parallel to the upper surface of a substrate, that is, the arrangement direction of the plurality of memory chips is parallel to the upper surface of the substrate, and therefore, the communication distances of the plurality of memory chips are the same, which is conducive to unifying the communication delay and improving the operating rate. In addition, the power supply wiring layer in the memory chip can change the layout of the power supply signal line and lead the power supply signal line out of the memory chip, that is, the reliability of power supply can be improved by wired power supply. In addition, the lead makes the connection method between the lead frame and the storage module more flexible, and the lead frame can standardize the layout of the power supply path, thereby ensuring the stability of the power supply.

[0016] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0017] like Figure 2-Figure 7As shown, an embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate 9, the substrate 9 has a power supply port 92; a storage module 100, located on the substrate 9; the storage module 100 includes a plurality of storage chips 1 stacked along a first direction X, and the first direction X is parallel to the upper surface of the substrate 9; each storage chip 1 has a power supply signal line 12, and at least one of the plurality of storage chips 1 has a power supply wiring layer 2, and the power supply signal line 12 is electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 includes a first wiring layer 21 and a second wiring layer 22 connected to each other, and the plane where the first wiring layer 21 is located is perpendicular to the upper surface of the substrate 9; the second wiring layer 22 is located on the surface of the storage chip 1 away from the substrate 9; the lead 74 is connected to the second wiring layer 22; the lead frame 7 is connected to the lead 74 and the power supply port 92.

[0018] Such a design has at least the following effects:

[0019] First, the power supply wiring layer 2 can lead out the power supply signal line 12, so as to facilitate wired power supply to the memory chip 1, thereby improving the power supply stability. Specifically, the surface of the memory chip 1 includes a relative front and back side, and a side connected therebetween, and the area of ​​the front and back side is greater than the area of ​​the side side. The plane where the first wiring layer 21 is located is perpendicular to the upper surface of the substrate 9. In other words, the first wiring layer 21 can be located on the front or back side of the memory chip 1 for connecting the power supply signal line 12. The second wiring layer 22 leads the first wiring layer 21 to the side of the memory chip 1, that is, the second wiring layer 22 can be used as a pad connecting the first wiring layer 21 and the lead 74 to increase the welding area, reduce the welding difficulty, and reduce the contact resistance between the power supply wiring layer 2 and the lead 74.

[0020] Second, the lead 74 and the lead frame 7 can form a wired power supply path between the substrate 9 and the memory chip 1. The lead frame 7 has high strength and is not easily deformed, so that the direction of the wired power supply path can be standardized; the lead 74 is easy to bend, which can improve the flexibility of connecting the lead frame 7 and the power supply wiring layer 2.

[0021] Third, the plurality of memory chips 1 are stacked along the first direction X, that is, the arrangement direction of the plurality of memory chips 1 is parallel to the substrate 9. Thus, the side surface of the memory chip 1 faces the substrate 9, and since the area of ​​the side surface of the memory chip 1 is small, the area of ​​the upper surface of the substrate 9 occupied is small, which is conducive to increasing the number of memory chips 1 stacked.

[0022] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0023] First, it should be noted that the semiconductor structure has a first direction X, a second direction Y and a third direction Z. The first direction X is the stacking direction of the memory chip 1; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the logic chip 3; and the third direction Z is perpendicular to the upper surface of the logic chip 3.

[0024] refer to Figure 2 and Figure 5 , multiple memory chips 1 can be stacked in a hybrid bonding manner. For example, the surface of the memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together by molecular forces and other forces. In addition, the surface of the memory chip 1 can also have a bonding portion 42, and under elevated temperature conditions, adjacent bonding portions 42 are bonded together. In other words, the dielectric layer 43 is an insulating material that can play an isolation role; the bonding portion 42 is a conductive material that can play an electrical connection role. In addition, the dielectric layer 43 also exposes the end face of the first wiring layer 21 facing away from the logic chip 3, and covers the surface of the first wiring layer 21 except the end face.

[0025] The memory chip 1 may be a chip such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random-Access Memory). In some embodiments, the stacking of adjacent memory chips 1 may be front-to-back, which is conducive to unifying the bonding steps of the memory chip 1 and making the production process simpler. In some embodiments, the stacking of adjacent memory chips 1 may also include front-to-front, or back-to-back. In one embodiment, the front of the memory chip 1 may be understood as the active surface 13, and the back may be understood as the non-active surface opposite to the active surface.

[0026] refer to Figure 2-Figure 6 , the first wiring layer 21 can be located on the front side of the memory chip 1, that is, extending along the active surface 13 of the memory chip 1. Therefore, after the components in the memory chip 1 are manufactured, the first wiring layer 21 can be manufactured using the original back-end process, and the process is simpler. In addition, the first wiring layer 21 can extend only at the edge position close to the active surface 13 of the memory chip 1, without covering the entire active surface 13 of the memory chip 1. Therefore, the contact area between the first wiring layer 21 and the memory chip 1 is small, reducing the effect of the heat generated by the first wiring layer 21 on the memory chip 1.

[0027] refer to Figure 2 and Figure 5, the ratio of the width of the second wiring layer 22 in the first direction X to the width of the memory chip 1 in the first direction X is 0.8-2. For example, in the first direction X, the width of the second wiring layer 22 is equal to the width of the memory chip 1. In this way, it can ensure that the lead 74 and the power supply wiring layer 2 have sufficient welding area, and it can also save materials and reduce production costs.

[0028] refer to Figure 3-Figure 4 and Figure 6 Each memory chip 1 has a plurality of power supply signal lines 12, one end of which is led out on the active surface 13 for connecting to the power supply wiring layer 2. Different power supply signal lines 12 can provide different voltage signals, such as digital signals or analog signals, to the components in the memory chip 1. The power supply signal line 12 can be a ground signal line 12G or a power signal line 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.

[0029] Continue to refer Figure 3-Figure 4 and Figure 6 Each power supply wiring layer 2 includes a plurality of power supply wirings 20 arranged at intervals, one power supply wiring 20 is electrically connected to one power supply signal line 12, different power supply signal lines 12 have different voltage signals, and accordingly, different power supply wirings 20 have different voltage signals. The power supply wiring layer 2 includes a ground wiring 20G and a power supply wiring 20P, the ground wiring 20G is electrically connected to the ground signal line 12G correspondingly, and the power supply wiring 20P is electrically connected to the power supply signal line 12P correspondingly.

[0030] If a memory chip 1 has a power supply wiring layer 2, at least part of the power supply signal lines 12 of the memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have a power supply wiring layer 2, the power supply signal lines 12 of the memory chip 1 can be led out through the power supply wiring layers 2 of other memory chips 1. In other words, the memory chip 1 can establish an electrical connection with other memory chips 1 through the conductive through-holes 41 and the bonding parts 42, so as to electrically connect its own power supply signal lines 12 to the power supply signal lines 12 of other memory chips 1, and then electrically connect to the power supply wiring layers 2 of other memory chips 1.

[0031] The position and quantity relationship between the memory chip 1 and the power supply wiring layer 2 will be described in detail below.

[0032] refer to Figure 2 and Figure 5At least one of the memory chips 1 on the outermost sides of the memory module 100 has a power supply wiring layer 2; a conductive through hole 41 is provided in the memory chip 1, and the conductive through hole 41 is electrically connected to the power supply signal line 12; a bonding portion 42 is provided between adjacent memory chips 1, and the bonding portion 42 is connected to the conductive through hole 41; the power supply signal lines 12 of multiple memory chips 1 are electrically connected through the conductive through hole 41 and the bonding portion 42.

[0033] Compared with the case where the power supply wiring layer 2 is located on the memory chip 1 in the middle position within the memory module 100, the case where the power supply wiring layer 2 is located on the memory chip 1 on the outermost side of the memory module 100 is beneficial for reducing the distance between the power supply wiring layer 2 and the lead frame 7, thereby shortening the length of the lead 74 to reduce power consumption and reduce the height of the entire package in the third direction Z.

[0034] In some embodiments, the memory chips 1 on the outermost sides of the memory module 100 have power supply wiring layers 2. There are two groups of lead frames 7, and the two groups of lead frames 7 are respectively close to the outermost memory chips 1 at the front and rear sides, and are connected to the two power supply wiring layers 2 respectively.

[0035] That is, the power supply signal line 12 can be led out from the outermost two sides of the storage module 100. Compared with leading out the power supply signal line 12 from one side of the storage module 100, leading out the power supply signal line 12 from both sides can provide more lead-out positions, which is conducive to reducing the process difficulty and improving the reliability of power supply. In other embodiments, the power supply signal line 12 can also be led out from one side of the storage module 100.

[0036] Specifically, refer to Figure 2-Figure 4 , Figure 3 and Figure 4 They are Figure 2 Schematic diagram of the active surface 13 of the outermost two sides of the memory chip 1. Each memory chip 1 has a first power supply signal line group 121 and a second power supply signal line group 122, each of which includes a plurality of power supply signal lines 12; all first power supply signal line groups 121 are electrically connected to a power supply wiring layer 2; all second power supply signal line groups 122 are electrically connected to another power supply wiring layer 2.

[0037] For example, the memory chips 1 on the outermost sides are respectively the first memory chip 1a and the second memory chip 1b. Figure 2 and Figure 3, the first power supply signal line group 121 of the first memory chip 1a is directly connected to the power supply wiring layer 2 on the surface of the first memory chip 1a, and the first power supply signal line group 121 of the memory chips 1 other than the first memory chip 1a is electrically connected to the first power supply signal group 121 of the first memory chip 1a through the bonding portion 42 and the conductive through hole 41, so that all the first power supply signal line groups 121 can be led out from the power supply wiring layer 2 on the surface of the first memory chip 1a. Similarly, in combination with reference Figure 2 and Figure 4 The second power supply signal line group 122 of the second memory chip 1b is directly connected to the power supply wiring layer 2 on the surface of the second memory chip 1b, and the second power supply signal line group 122 of the memory chip 1 other than the second memory chip 1b is electrically connected to the second power supply signal group 122 of the second memory chip 1b through the bonding portion 42 and the conductive through-hole 41, so that all the second power supply signal line groups 122 can be led out from the power supply wiring layer 2 on the surface of the second memory chip 1b.

[0038] That is, the first signal line group 121 and the second signal line group 122 are respectively led out from both sides of the storage module 100, which is beneficial to provide more sufficient connection positions for the leads 74, thereby increasing the distance between adjacent leads 74 and avoiding erroneous electrical connections.

[0039] refer to Figure 5-Figure 6 , Figure 6 for Figure 5 The schematic diagram of the active surfaces 13 of the memory chips 1 on the outermost sides is shown, and the memory module 100 includes two chipsets 10 arranged in a first direction X, and each chipset 10 includes a plurality of memory chips 1; the power supply signal line 12 of the same chipset 10 is electrically connected to the power supply wiring layer 2 closest to it.

[0040] By way of example, the storage module 100 includes a first chipset 10a and a second chipset 10b, all power supply signal lines 12 of the first storage chip 1a can be directly electrically connected to the power supply wiring layer 2 on the surface of the first storage chip 1a, and the power supply signal lines 12 of other storage chips 1 in the first chipset 10a are electrically connected to the power supply signal lines 12 of the first storage chip 1a through the bonding portion 42 and the conductive through hole 41, so that all power supply signal lines 12 of the first chipset 10a can be led out from the power supply wiring layer 2 on the surface of the first storage chip 1a. Similarly, all power supply signal lines 12 of the second storage chip 1b can be directly electrically connected to the power supply wiring layer 2 on the surface of the second storage chip 1b, and the power supply signal lines 12 of other storage chips 1 in the second chipset 10b are electrically connected to the power supply signal lines 12 of the second storage chip 1b through the bonding portion 42 and the conductive through hole 41, so that all power supply signal lines 12 of the second chipset 10b can be led out from the power supply wiring layer 2 on the surface of the second storage chip 1b. Since the power supply signal lines 12 of the two chipsets 10 are led out separately, it is beneficial to improve the stability and reliability of power supply.

[0041] The lead frame 7 will be described in detail below.

[0042] refer to Figure 2 and Figure 5 The lead frame 7 and the memory module 100 are arranged in the first direction X. That is, the lead frame 7 is arranged opposite to the outermost memory chip 1 of the memory module 100. In this way, the distance between the lead frame 7 and the power supply wiring layer 2 is reduced, so as to shorten the length of the lead 74.

[0043] refer to Figure 7 , Figure 7 7 is a top view of the lead frame 7, the lead wires 74 and the power supply wiring layer 2. Since the power supply wiring layer 2 includes a plurality of power supply wirings 20 spaced apart in the second direction Y, the lead frame 7 accordingly includes a plurality of frame bars 70 spaced apart in the second direction Y, and the connected frame bars 70 and the power supply wirings 20 have the same voltage signal. For example, in the first direction X, the power supply wirings 20 can be arranged one by one opposite to the frame bars 70, so as to facilitate the arrangement of the lead wires 74.

[0044] The frame bar 70 is a power frame bar 70P or a ground frame bar 70G. The power frame bar 70P is electrically connected to the power wiring 20P, and the ground frame bar 70G is electrically connected to the ground wiring 20G. The power frame bar 70P and the ground frame bar 70G are alternately arranged in the second direction Y, that is, the end surface of the power supply wiring 20 away from the substrate 9 can also be alternately arranged in the second direction Y. Since the difference between the power signal and the ground signal is large, the alternating arrangement of the two is conducive to reducing the electromagnetic interference of adjacent frame bars 70.

[0045] refer to Figure 2and Figure 5 The lead frame 7 includes a connected support frame 71 and a main frame 72; the support frame 71 is welded on the upper surface of the substrate 9; the main frame 72 extends in a direction perpendicular to the upper surface of the substrate 9, that is, the main frame 72 extends in the third direction Z; the width of the support frame 71 in the first direction X is greater than the width of the main frame 72 in the first direction X.

[0046] That is, the support frame 71 extends in a direction parallel to the upper surface of the substrate 9, thereby increasing the welding area between the lead frame 7 and the substrate 9 to enhance the firmness of the welding. For example, a welding bump 51 and a solder layer 52 are also provided between the support frame 71 and the substrate 9.

[0047] refer to Figure 2 In some embodiments, the end of the support frame 71 is connected to the end of the main frame 72, that is, a strip of conductive material is bent into two sections to serve as the support frame 71 and the main frame 72 respectively, and the production process is simpler.

[0048] refer to Figure 5 In other embodiments, the orthographic projection of the main frame 72 on the upper surface of the substrate 9 is located at the center of the orthographic projection of the support frame 71 on the upper surface of the substrate 9. In other words, the main frame 72 and the support frame 71 can form an inverted T shape, and the stability of the lead frame 7 is better.

[0049] Continue to refer Figure 2 and Figure 5 The lead frame 7 further includes a welding frame 73, the width of the welding frame 73 in the first direction X is greater than the width of the main frame 72 in the first direction X; the welding frame 73 is welded to the lead 74; and one end of the main frame 72 away from the support frame 71 is connected to the welding frame 73. That is, the welding frame 73 extends in a direction parallel to the upper surface of the substrate 9, thereby facilitating the increase of the welding area between the lead 74 and the lead frame 7, so as to facilitate welding.

[0050] In other embodiments, the lead frame 7 may also include only the main frame 72 without including the welding frame 73 and the support frame 71 , that is, the opposite ends of the main frame 72 are welded to the upper surface of the substrate 9 and the lead 74 respectively.

[0051] It is worth noting that, since the lead frame 7 includes a plurality of frame bars 70 disposed at intervals, in other words, each frame bar 70 may include a main frame 72 , a welding frame 73 and a supporting frame 71 .

[0052] Continue to refer Figure 2 and Figure 5The semiconductor structure further includes: a first sealing layer 81, which surrounds the storage module 100 and exposes the surface of the storage module 100 away from the substrate 9. The first sealing layer 81 can protect the storage module 100 from the influence of the external environment, such as resisting external moisture and solvents, and can also resist thermal shock and mechanical vibration when the semiconductor structure is installed.

[0053] For example, the first sealing layer 81 is in contact with the welding frame 73. In this way, the first sealing layer 81 can support the welding frame 73, thereby improving the stability of the structure; in addition, it is also beneficial to reduce the distance between the welding frame 73 and the storage module 100, thereby reducing the length of the lead 74.

[0054] For example, refer to Figure 2 , the bottom surface of the welding frame 73 may be located on the top surface of the first sealing layer 81. In other embodiments, referring to Figure 5 The first sealing layer 81 has a groove 75 on one side away from the substrate 9, and the welding frame 73 is engaged in the groove 75. For example, the welding frames 73 arranged on two opposite sides in the second direction Y can contact the side walls of the groove 75, and the bottom surface of the welding frame 73 can contact the bottom surface of the groove 75. That is, the first sealing layer 81 can play a role in fixing the welding frame 73 to improve the stability of the lead frame 7.

[0055] refer to Figure 2 and Figure 5 The semiconductor structure further includes a second sealing layer 82, which covers the storage module 100, the lead 74, the lead frame 7, the second wiring layer 22 and the first sealing layer 81. The second sealing layer 82 can improve the protection and isolation effect to ensure the performance of the semiconductor structure.

[0056] In one embodiment, the first sealing layer 81 and the second sealing layer 82 may be made of the same material. For example, the first sealing layer 81 and the second sealing layer 82 may be made of epoxy resin.

[0057] In one embodiment, the materials of the first sealing layer 81 and the second sealing layer 82 may be different. For example, the thermal conductivity of the second sealing layer 82 is higher than that of the first sealing layer 81. Through such a setting, the heat introduced into the second sealing layer 82 through the lead frame 7 can be transferred to the external environment more quickly, thereby reducing the adverse effects of the high temperature environment on the storage module 100.

[0058] refer to Figure 2 and Figure 5 The semiconductor structure also includes: a logic chip 3, located between the upper surface of the substrate 9 and the storage module 100; a first wireless communication unit 31 is included in the logic chip 3; a second wireless communication unit 11 is included in the storage chip 1; and the second wireless communication unit 11 performs wireless communication with the first wireless communication unit 31.

[0059] Since the distances between the multiple memory chips 1 and the logic chip 3 are the same, the delays of the wireless communications between the multiple memory chips 1 and the logic chip 3 remain consistent. In some embodiments, the second wireless communication unit 11 is located on the side of the memory chip 1 facing the logic chip 3. Thus, the distance between the first wireless communication unit 31 and the second wireless communication unit 11 can be reduced, thereby improving the quality of wireless communication.

[0060] It should be noted that if the arrangement direction of multiple memory chips 1 is perpendicular to the upper surface of the logic chip 3, the communication delay between memory chips 1 and logic chip 3 in different layers will be quite different; in addition, as the number of layers increases, the number of through-silicon vias (TSV) used for communication will increase proportionally, thereby sacrificing the wafer area. In the disclosed embodiment, the stacking direction and communication mode of the memory chips 1 are changed, which is beneficial to improving the communication quality and saving the wafer area.

[0061] Continue to refer Figure 2 and Figure 5 , the side of the memory chip 1 is arranged toward the logic chip 3, and the area of ​​the side is small; while the wireless communication method does not need to set up a wired communication part between the memory chip 1 and the logic chip 3, thereby reducing the process difficulty, and providing sufficient space for the connection structure between the memory chip 1 and the logic chip 3 to improve the structural strength of the two. In addition, the lower side of the memory module 100 is used for wireless communication, and the upper side of the memory module 100 is used for laying out the wired power supply path, thereby reducing the electromagnetic interference generated by the current in the wired power supply path to the coil in the wireless communication part and avoiding signal loss.

[0062] In some embodiments, there is also an adhesive layer 6 between the storage module 100 and the logic chip 3. That is, the storage module 100 and the logic chip 3 are connected together by gluing to form a memory core. By way of example, the adhesive layer 6 can be a die attach film (DAF). The bonding process is relatively simple and can save costs. In addition, the adhesive layer 6 can also be doped with metal ions to improve the heat dissipation effect of the storage module 100 and the logic chip 3. In other embodiments, there can be a welding layer (not shown in the figure) between the storage module 100 and the logic chip 3, that is, the storage module 100 and the logic chip 3 are connected together by welding.

[0063] That is to say, by leading the power supply signal line 12 from the top of the storage module 100 , sufficient space can be left under the storage module 100 to connect the logic chip 3 , thereby improving the structural strength.

[0064] Continue to refer Figure 2 and Figure 5 There are also welding bumps 51 and solder layers 52 between the logic chip 3 and the substrate 9, that is, the logic chip 3 is welded on the substrate 9 by flip-chip welding. In this way, the substrate 9 can supply power and exchange signals to the logic chip 3 in a wired manner, and the wired manner has higher reliability.

[0065] To sum up, in the embodiment of the present disclosure, a connection method of lead 74 is adopted at the upper end of the lead frame 7, so that the connection method of lead frame 7 and storage module 100 is more flexible; at the same time, a connection method of welding bump 51 is adopted at the lower end of lead frame 7, so that the connection stability of lead frame 7 and substrate 9 is higher; the two connection methods are matched to make the wired power supply path both flexible and stable.

[0066] like Figure 8-Figure 9 and Figure 2 As shown, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can manufacture the semiconductor structure provided by the above embodiment. For detailed description of the semiconductor structure, please refer to the above embodiment.

[0067] Specifically, refer to Figure 8 , providing a storage module 100; the storage module 100 includes a plurality of storage chips 1 stacked along a first direction X; each storage chip 1 has a power supply signal line 12, at least one of the plurality of storage chips 1 has a power supply wiring layer 2, and the power supply signal line 12 is electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 includes a first wiring layer 21 and a second wiring layer 22 connected to each other, and the plane where the first wiring layer 21 is located is perpendicular to the upper surface of the substrate 9; the second wiring layer 22 is located on the surface of the storage chip 1 away from the substrate 9.

[0068] Specifically, a plurality of memory chips 1 are provided; a first wiring layer 21 is formed on at least one of the plurality of memory chips 1, and after the first wiring layer 21 is formed, the plurality of memory chips 1 are stacked and bonded. For example, the power supply signal line 12 of each layer of memory chip 1 is led out to the top and bottom memory chips 1 through the conductive through hole 41 and the bonding part 42, and then led out to the edge of the memory chip 1 through processing on the power supply wiring layer 2 of the top and bottom memory chips 1. It should be noted that during the bonding process, the memory chip 1 is placed horizontally.

[0069] refer to Fig. 9 , a first molding process is performed on the storage module 100 to form a first sealing layer 81 surrounding the storage module 100, and the first sealing layer 81 also exposes the surface of the storage chip 1 and the first wiring layer 21 away from the substrate 9; after the first molding process, a second wiring layer 22 is formed on the surface of the storage chip 1 away from the substrate 9.

[0070] For example, the storage module 100 is rotated 90° so that each storage chip 1 is perpendicular to the logic chip 3, and the storage chip 1 and the logic chip 3 are fixed by the DAF film; multiple storage modules 100 are reconstructed by a first molding process to form a reconstructed wafer; and a second wiring layer 22 is deposited on the top surface of the reconstructed wafer by a rewiring process to serve as a pad.

[0071] refer to Figure 2 Provide a substrate 9 having a power supply port 92; fix the storage module 100 on the substrate 9, and the first direction X is parallel to the upper surface of the substrate 9. Provide a lead 74 and a lead frame 7, connect the lead 74 to the second wiring layer 22; connect the lead frame 7 to the lead 74 and the power supply port 92.

[0072] Specifically, the reconstructed wafer is diced to form memory chips, each of which includes a storage module 100 and a logic chip 3. The memory chips are soldered to the substrate 9 to which the lead frame 7 has been pre-soldered by flip-chip soldering, and the power supply wiring 20 is connected to the corresponding frame bar 70 through the lead 74 to achieve the connection of the power supply signal between the memory chip 1 and the substrate 9. Thereafter, a second sealing layer 82 covering the storage module 100, the lead 74, the lead frame 7 and other structures is formed by a second molding process.

[0073] It is worth noting that the reason for using two molding processes in succession is that the first molding process can connect multiple storage modules 100 together, so the second wiring layer 22 can be formed on multiple storage modules 100 at the same time later, which is conducive to reducing the process steps. In addition, the volume of a single storage module 100 is small, and the total volume of multiple storage modules 100 connected together becomes larger, the stability is higher, and it is not easy to tip over. In addition, the first sealing layer 81 formed by the first molding process can protect and fix the storage module 100 in the subsequent steps of forming the second wiring layer 22 and flip-chip welding, so as to prevent the storage module 100 from collapsing or being damaged, which is conducive to ensuring the performance of the storage module 100. In addition, the two molding processes in succession can improve the sealing effect. The bottom surface of the substrate 9 can have a solder ball 91, so that the substrate 9 is soldered to the peripheral circuit board.

[0074] In summary, the multi-layer memory chip 1 and the logic chip 3 are stacked vertically to form a memory core, and then the power supply wiring layer 2 is led out to the substrate 9 for packaging through the lead frame 7. The signal communication between the memory chip 1 and the logic chip 3 is realized wirelessly, which can effectively solve the communication difficulties caused by the increase in the number of stacking layers of the memory chip 1 in parallel stacking.

[0075] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0076] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A base plate having a power supply port; A storage module, located on the substrate; The memory module includes a plurality of memory chips stacked along a first direction, the first direction being parallel to an upper surface of the substrate; Each of the memory chips has a power supply signal line, at least one of the plurality of memory chips has a power supply wiring layer, and the power supply signal line is electrically connected to the power supply wiring layer; The power supply wiring layer includes a first wiring layer and a second wiring layer connected to each other, wherein the plane where the first wiring layer is located is perpendicular to the upper surface of the substrate; and the second wiring layer is located on the surface of the memory chip away from the substrate; A lead connected to the second wiring layer; A lead frame connected to the lead and the power supply port; Also included: a logic chip located between the upper surface of the substrate and the storage module; The logic chip has a first wireless communication unit; The memory chip has a second wireless communication unit; The second wireless communication unit performs wireless communication with the first wireless communication unit.

2. The semiconductor structure according to claim 1, characterized in that: The lead frame and the memory module are arranged in the first direction.

3. The semiconductor structure according to claim 2, characterized in that: At least one of the memory chips on the outermost sides of the memory module has the power supply wiring layer; The memory chip has a conductive through hole in it, and the conductive through hole is electrically connected to the power supply signal line; adjacent memory chips have a bonding portion between them, and the bonding portion is connected to the conductive through hole; The power supply signal lines of the plurality of memory chips are electrically connected through the conductive vias and the bonding portions.

4. The semiconductor structure according to claim 3, characterized in that: The memory chips on the outermost sides of the memory module have the power supply wiring layer; There are two groups of lead frames, and the two groups of lead frames are respectively close to the storage chips on the outermost sides and are respectively connected to the two power supply wiring layers.

5. The semiconductor structure according to claim 4, characterized in that: Each of the memory chips has a first power supply signal line group and a second power supply signal line group, wherein the first power supply signal line group and the second power supply signal line group each include a plurality of the power supply signal lines; All of the first power supply signal line groups are electrically connected to one of the power supply wiring layers; and all of the second power supply signal line groups are electrically connected to another of the power supply wiring layers.

6. The semiconductor structure according to claim 4, characterized in that: The storage module includes two chipsets arranged in the first direction, and each of the chipsets includes a plurality of the storage chips; The power supply signal line of the same chipset is electrically connected to the power supply wiring layer closest thereto.

7. The semiconductor structure according to claim 1, characterized in that: The lead frame includes a plurality of frame bars arranged at intervals, wherein the frame bars are power frame bars or ground frame bars; the power frame bars and the ground frame bars are alternately arranged in a second direction, wherein the second direction is parallel to the upper surface of the substrate and perpendicular to the first direction; The power supply wiring layer includes a plurality of power supply wirings and a plurality of ground wirings; the power supply signal line includes a power supply signal line and a ground signal line; The power wiring is electrically connected to the power frame bar and the power signal line; the ground wiring is electrically connected to the ground frame bar and the ground signal line.

8. The semiconductor structure according to claim 1, characterized in that: The lead frame includes a supporting frame and a main frame connected to each other; The support frame is welded on the upper surface of the substrate; The main frame extends in a direction perpendicular to the upper surface of the substrate; The width of the support frame in the first direction is greater than the width of the main frame in the first direction.

9. The semiconductor structure according to claim 8, characterized in that: The lead frame further comprises a welding frame, wherein the width of the welding frame in the first direction is greater than the width of the main frame in the first direction; The welding frame is welded to the lead wire; One end of the main frame away from the supporting frame is connected to the welding frame.

10. The semiconductor structure according to claim 8, characterized in that The orthographic projection of the main frame on the upper surface of the substrate is located at a central position within the orthographic projection of the support frame on the upper surface of the substrate.

11. The semiconductor structure according to claim 9, characterized in that: It also includes: a first sealing layer, the first sealing layer surrounds the storage module and exposes a surface of the storage module away from the substrate; The first sealing layer is in contact with the welding frame.

12. The semiconductor structure according to claim 11, characterized in that: The first sealing layer has a groove on one side away from the substrate, and the welding frame is clamped in the groove.

13. The semiconductor structure according to claim 1, characterized in that There is also an adhesive layer or a welding layer between the storage module and the logic chip.

14. The semiconductor structure according to claim 1, characterized in that A ratio of a width of the second wiring layer in the first direction to a width of the memory chip in the first direction is 0.8-2.

15. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a power supply port; Provide logic chips; Providing a storage module; The memory module includes a plurality of memory chips stacked along a first direction; Each of the memory chips has a power supply signal line, at least one of the plurality of memory chips has a power supply wiring layer, the power supply signal line is electrically connected to the power supply wiring layer; the power supply wiring layer includes a first wiring layer and a second wiring layer connected to each other, the plane where the first wiring layer is located is perpendicular to the upper surface of the substrate; the second wiring layer is located on the surface of the memory chip away from the substrate; Fixing the storage module on the logic chip along a second direction, wherein the second direction is perpendicular to the first direction; Fixing the storage module and the logic chip on the substrate, with the first direction being parallel to the upper surface of the substrate; Provide a lead wire and a lead frame, connect the lead wire to the second wiring layer; and connect the lead frame to the lead wire and the power supply port.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: include: The storage module is provided, comprising: Providing a plurality of the memory chips; forming a first wiring layer on at least one of the plurality of memory chips; After forming the first wiring layer, stacking and bonding a plurality of the memory chips; Before fixing the storage module on the substrate, the method further includes: Performing a first molding process on the memory module to form a first sealing layer surrounding the memory module, wherein the first sealing layer also exposes the surface of the memory chip and the first wiring layer away from the substrate; After the first molding process, the second wiring layer is formed on a surface of the memory chip away from the substrate.

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