Multi-threaded Processor, Data Transmission Method, Electronic Device, and Storage Medium

Abstract

The present invention provides a multi-threaded processor, a data transmission method, an electronic device, and a storage medium. The multi-threaded processor includes an LD / ST unit and multiple execution units (EUs). In the LD / ST unit, an input interface is used to receive transmission instructions from the multiple execution units (EUs) and transmit the SHUFFLE instructions in the transmission instructions to a SHUFFLE unit. The SHUFFLE unit is used to parse the SHUFFLE instructions to obtain the source thread index of the destination thread and determine the data offset of the destination thread in the source thread data based on the source thread index. A Shifter unit shifts the source thread data corresponding to the destination thread to the position of the destination thread based on the data offset to serve as target data. An output interface is used to transmit the target data to the register of the destination thread in the execution unit. The processor, method, device, and medium provided by the present invention greatly save hardware resources.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a multi-thread processor, a data transmission method, an electronic device, and a storage medium. Background Art

[0002] With the rise of large-scale application fields such as GPUs (Graphics Processing Units), GPGPUs (General-Purpose computing on Graphics Processing Units), artificial intelligence, and cluster servers, multi-thread processors need to handle increasingly complex application scenarios, and limited Shared Memory resources become very precious.

[0003] To save the use of Shared Memory resources, the SHUFFLE instruction is proposed. Specifically, in a multi-thread processor, data transmission from a source thread to a destination thread can be directly implemented through the SHUFFLE instruction, thereby achieving the effects of saving Shared Memory resource access and reducing data interaction latency between threads.

[0004] However, a related SHUFFLE unit is usually a basic hardware unit within an EU (Execution Unit). For a SHUFFLE unit within an EU to implement data transmission from a source thread to a destination thread, it requires a large amount of hardware resources (32 32-to-1 muxes). Moreover, for a multi-thread processor with N EUs, where each EU is provided with a SHUFFLE unit, N SHUFFLE units are required, and the setting of N SHUFFLE units will occupy a lot of hardware resources. Summary of the Invention

[0005] The present invention provides a multi-thread processor, a data transmission method, an electronic device, and a storage medium to solve the defect that data transmission between threads based on SHUFFLE in the prior art requires a large amount of hardware resources.

[0006] The present invention provides a multi-thread processor, including:

[0007] an LD / ST unit and a plurality of execution units EU, where the LD / ST unit includes an input interface, a SHUFFLE unit, a Shifter unit, and an output interface;

[0008] The input interface is used to receive transfer instructions from the multiple execution units (EUs) and transfer the SHUFFLE instructions in the transfer instructions to the SHUFFLE unit;

[0009] The SHUFFLE unit is used to parse the SHUFFLE instruction to obtain the source thread index of the destination thread and determine the data offset of the destination thread in the source thread data based on the source thread index;

[0010] The Shifter unit moves the source thread data under the source thread to the position of the destination thread based on the data offset as the target data;

[0011] The output interface is used to transfer the target data to the register of the destination thread in the execution unit.

[0012] According to a multi-threaded processor provided by the present invention, the SHUFFLE unit is specifically used for:

[0013] Obtain the source thread index of each thread in the EU corresponding to the SHUFFLE instruction;

[0014] Based on the source thread index of each thread, determine the data offset corresponding to each destination thread in the source thread data.

[0015] According to a multi-threaded processor provided by the present invention, the SHUFFLE unit is further used for:

[0016] Obtain the exchange mode of each thread in the EU corresponding to the SHUFFLE instruction, where the exchange mode is used to indicate the exchange rule between elements in the destination thread during the SHUFFLE process;

[0017] Based on the exchange mode of each thread, rearrange the elements in each thread.

[0018] According to a multi-threaded processor provided by the present invention, the Shifter unit is specifically used for:

[0019] Based on the data offset, move out the source thread data corresponding to the destination thread from the source data;

[0020] Based on the thread index of the destination thread, move the moved-out source thread data corresponding to the destination thread to the position of the destination thread.

[0021] According to a multi-threaded processor provided by the present invention, the output interface is specifically used for:

[0022] Based on the target EU identifier and the target register address in the SHUFFLE instruction, transfer the target data to the destination register in the target EU.

[0023] A multi-threaded processor provided by the present invention further includes a shared memory unit and a read / write control unit;

[0024] The input interface is further configured to transmit the LD / ST instructions in the transmission instructions to the read / write control unit;

[0025] The read / write control unit is configured to parse the LD / ST instructions to obtain instruction information of the LD / ST instructions, and send the instruction information to the shared memory unit.

[0026] In a multi-threaded processor provided by the present invention, the read / write control unit includes a read control unit and a write control unit;

[0027] The read control unit is configured to parse the LD instructions to obtain read requests of the LD instructions, and send the read requests as the instruction information to the shared memory unit;

[0028] The write control unit is configured to parse the ST instructions to obtain write requests and write data of the ST instructions, and write the write requests and the write data as the instruction information into the shared memory unit.

[0029] The present invention also provides a data transmission method, including:

[0030] Receiving transmission instructions of multiple execution units EU;

[0031] Parsing the SHUFFLE instructions in the transmission instructions to obtain source thread indexes, and determining data offsets of destination threads in the source thread data based on the source thread indexes;

[0032] Based on the data offsets, moving the source thread data corresponding to the destination thread to the position of the destination thread as target data;

[0033] Transmitting the target data to the registers of the destination threads in the execution units.

[0034] The present invention also provides an electronic device, including a memory and the multi-threaded processor as described above; a computer program that can run on the multi-threaded processor is stored in the memory;

[0035] Or, including a multi-threaded processor, a memory is provided inside the multi-threaded processor, a computer program for implementing internal data transmission of the multi-threaded processor is stored in the memory, and when the computer program is executed by the multi-threaded processor, the data transmission method as described above is implemented.

[0036] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a multi-threaded processor, the data transmission method described above is implemented.

[0037] A multi-threaded processor, a data transmission method, an electronic device, and a storage medium provided by the present invention are implemented by arranging a SHUFFLE unit in an LD / ST unit shared by multiple EUs. The SHUFFLE unit cooperates with the original Shifter unit in the LD / ST unit to execute, realizing the data transmission function from the source thread to the destination thread. And since multiple EUs can share one LD / ST unit, and only one SHUFFLE unit needs to be arranged in one LD / ST unit, there is no need to separately arrange SHUFFLE units for each EU, greatly saving hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 is a schematic flowchart of data transmission through LD / ST in the related art;

[0040] Figure 2 is a schematic hardware structure diagram of the SHUFFLE unit in the related art;

[0041] Figure 3 is a schematic structure diagram of the SHUFFLE unit of the multi-threaded processor in the related art;

[0042] Figure 4 is a schematic structure diagram of the multi-threaded processor provided by the present invention;

[0043] Figure 5 is a schematic thread mapping diagram provided by the present invention;

[0044] Figure 6 is a schematic SHUFFLE principle diagram provided by the present invention;

[0045] Figure 7 is a schematic cross-EU transmission diagram provided by the present invention;

[0046] Figure 8 is one of the schematic structure diagrams of the electronic device provided by the present invention;

[0047] Figure 9 is one of the schematic flowcharts of the data transmission method provided by the present invention;

[0048] Figure 10 It is the second flow schematic diagram of the data transmission method provided by the present invention;

[0049] Figure 11 It is the second structural schematic diagram of the electronic device provided by the present invention. Detailed implementation manners

[0050] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0051] In a multi-threaded processor, different threads often need to access each other's data. To achieve this goal, the traditional method is to use LD / ST (Load / Store) instructions for data transmission between registers and memories.

[0052] Specifically, the source thread within the same warp will first store the data in the shared memory, and then the destination thread will load the data at the same address from the shared memory and return it to its own register. In this way, data transmission between different threads within the same warp can be achieved.

[0053] Furthermore, Figure 1 is the flow schematic diagram of data transmission through LD / ST in the related art. As Figure 1 shown, through the cooperation of LD / ST and the shared memory Shared Memory, data transmission and sharing within the EU, as well as data transmission and sharing between EUs, can be achieved.

[0054] Although data transmission between threads within the same warp can be achieved through LD / ST instructions, the execution of LD / ST occupies a lot of shared memory resources, and the data transmission delay between threads is also relatively large.

[0055] Based on the above problems, the SHUFFLE instruction is proposed.

[0056] The SHUFFLE instruction is mainly used to transfer data between different threads within the same warp. In hardware, each thread within a warp has its own lane, and each lane is equipped with a TLR (Thread Local Register). Therefore, the data interaction between lanes is actually a data transfer within or between TLRs.

[0057] Figure 2 is a schematic diagram of the hardware structure of the SHUFFLE unit in the related art, as Figure 2 shown. Within the same EU, a warp contains multiple lanes. As an example, a warp can contain 32 lanes, or it can be more than 32 lanes. Here, taking 32 lanes as an example, the data of each destination lane may come from any one of the 32 source lanes. Therefore, for each destination lane, a 32-to-1 multiplexer (MUX) is required. In this way, at least 32 32-to-1 MUXs are needed for 32 destination lanes. Figure 2 In, lane0, lane1, and lane31 in the destination lane come from lane0, lane0, and lane31 respectively. Figure 2 In, dem represents data element.

[0058] Figure 3 is a schematic diagram of the structure of the SHUFFLE unit of a multi-threaded processor in the related art, as Figure 3 shown. For a multi-threaded processor, N EUs (N >= 1 and N is an integer) can work in parallel in its hardware structure. There is a SHUFFLE unit in each EU. Therefore, at least N × 32 32-to-1 MUXs are required. When the number N of EUs is large, the hardware resource overhead of the SHUFFLE unit is huge.

[0059] Combined with Figure 2 and Figure 3 it can be seen that in the related art, when the SHUFFLE unit in an EU implements data transfer, it needs to occupy a large amount of hardware resources, specifically 32 32-to-1 MUXs. For a multi-threaded processor with N EUs, there is a SHUFFLE unit in each EU, and N EUs require N SHUFFLE units, which will occupy more hardware resources and the SHUFFLE units between different EUs cannot be shared.

[0060] In view of the above problems, an embodiment of the present invention provides a multi-threaded processor. Figure 4 It is a schematic structural diagram of the multi-threaded processor provided by the present invention. As Figure 4 shown, the multi-threaded processor includes:

[0061] An LD / ST unit 10 and multiple execution units EU20. The LD / ST unit 10 includes an input interface 11, a SHUFFLE unit 12, a Shifter unit 13, and an output interface 14;

[0062] The input interface 11 is used to receive transfer instructions from the multiple execution units EU20 and transmit the SHUFFLE instructions in the transfer instructions to the SHUFFLE unit 12;

[0063] The SHUFFLE unit 12 is used to parse the SHUFFLE instructions to obtain source thread indexes and determine the data offset of the destination thread in the source thread data based on the source thread indexes;

[0064] The Shifter unit 13 moves the source thread data corresponding to the destination thread to the position of the destination thread based on the data offset as target data;

[0065] The output interface 14 is used to transmit the target data to the register of the destination thread in the execution unit.

[0066] Here, in the multi-threaded processor, the LD / ST unit 10 is both an LD / ST instruction execution unit and can also be called an LD / ST unit. Different from the LD / ST unit for executing LD / ST instructions in the related art, the LD / ST unit 10 in the embodiment of the present invention can not only execute LD / ST instructions but also execute SHUFFLE instructions.

[0067] Furthermore, the LD / ST unit 10 in the embodiment of the present invention not only includes the common input interface 11, Shifter unit 13, and output interface 14, but also includes a SHUFFLE unit 12. That is, by adding a SHUFFLE unit 12 in the hardware of the LD / ST, the shifter logic in the LD / ST unit 10 is reused to implement data transfer from the source thread to the destination thread without the need to additionally set up hardware logics MUX and Buffer.

[0068] Specifically, each execution unit EU20 in the multi-threaded processor can send transfer instructions to the LD / ST unit 10. The transfer instructions here are instructions for data transfer between threads, which can specifically be SHUFFLE instructions or LD / ST instructions.

[0069] The transfer instructions sent by the execution unit EU20 are concentrated at the input interface 11 of the LD / ST unit 10. The input interface 11 here can specifically be Arb. The input interface selects a transfer instruction of an execution unit EU20 from the transfer instructions sent by multiple execution units EU20 and transfers it backward in units of the transfer instructions that can be received. When transferring here, the unit that receives and executes at the back end can be determined based on the type of the transfer instruction. Specifically, when the transfer instruction is a SHUFFLE instruction, the SHUFFLE instruction is sent to the SHUFFLE unit 12 built into the LD / ST unit 10.

[0070] The SHUFFLE unit 12, that is, the SHUFFLE unit, can support any mapping from the source lane to the destination lane. After receiving the SHUFFLE instruction distributed by the input interface 11, the SHUFFLE unit 12 can obtain the index of the source lane of the data to be transferred, that is, the source lane index, by parsing the SHUFFLE instruction. The index here is used to reflect the absolute position of the thread in a warp. After that, the data offset byte offset of the destination lane in the source lane data can be determined based on the source lane index. The data offset can represent the source lane data corresponding to the destination lane, that is, the offset of the target data to be transferred in the source lane data. Here, the unit of byteoffset can be byte.

[0071] It can be understood that before the mapping, the source lane index can be pre-configured for each thread to facilitate determining the data offset required during data migration. And it should be noted that the data offset byte offset output by the SHUFFLE unit 12 is the same as the data offset required for the Shifter unit in the LD / ST unit in the related technology to perform a shift. Thus, without changing the Shifter unit, the SHUFFLE unit 12 can be adapted to the Shifter unit 13, so as to implement SHUFFLE-based data transfer in the hardware of LD / ST.

[0072] The Shifter unit 13 can receive the data offset output by the SHUFFLE unit 12, and determine the source lane data corresponding to the destination lane that needs to be migrated, that is, the target data, from the source lane data based on the data offset, and then migrate the target data to the position of the destination lane. Specifically, the target data can be filled into the position corresponding to the destination lane.

[0073] After the Shifter unit 13 finishes execution, the target data can be transmitted to the register of the destination thread in the EU20 through the output interface 14. Specifically, it can be transmitted to the TLR address of the destination thread in the EU20. It can be understood that here, the output interface 14 can transmit the target data to the register of a certain destination thread in the EU20, or can also transmit the target data to the registers of multiple destination threads in the EU20. The embodiments of the present invention do not make specific limitations on this.

[0074] In the multi-threaded processor provided by the embodiments of the present invention, the SHUFFLE unit is implemented in the LD / ST unit shared by multiple EUs. The SHUFFLE unit cooperates with the original Shifter unit in the LD / ST unit to execute, realizing the data transmission function from the source thread to the destination thread. And because multiple EUs can share one LD / ST unit, and only one SHUFFLE unit needs to be set in one LD / ST unit, there is no need to set SHUFFLE units for each EU respectively, greatly saving hardware resources.

[0075] Based on the above embodiments, the SHUFFLE unit is specifically used for:

[0076] Obtain the source thread index of each thread in the EU corresponding to the SHUFFLE instruction;

[0077] Based on the source thread index of each thread, determine the data offset corresponding to each destination thread in the source thread data.

[0078] Specifically, the source thread index can be pre-configured for each thread in the EU. Taking an EU with 32 lanes as an example, the source thread index source lane index can be configured for each of the 32 lanes respectively.

[0079] On this basis, the SHUFFLE unit can respectively determine the data offset of the source thread data at the source thread corresponding to each destination thread indicated by the SHUFFLE instruction according to the pre-configured source thread index.

[0080] It can be understood that in the embodiments of the present invention, for one EU, each thread in the EU is configured with its own source thread index. Thus, each destination thread can correspond to its own source thread index, and the source thread index of each thread can be flexibly configured by software, thereby ensuring the flexibility of the application of the SHUFFLE unit.

[0081] For example, Figure 5 is the thread mapping schematic diagram provided by the present invention. As Figure 5As shown, a warp includes 32 thread lanes, and each destination thread lane may originate from any one of the 32 source thread indices (0 to 31).

[0082] In addition, in the related art, the SHUFFLE between thread lanes is performed at the granularity of the entire lane, and it is impossible to perform a finer-grained SHUFFLE on the elements within a lane, and it is impossible to complete the swap between multiple elements within a lane. To address this problem, based on any of the above embodiments, the SHUFFLE unit is further configured to:

[0083] Obtain the exchange mode of each thread in the EU corresponding to the SHUFFLE instruction, where the exchange mode is used to indicate the exchange rule between the elements within the destination thread during the SHUFFLE process;

[0084] Rearrange the elements in each thread based on the exchange mode of each thread.

[0085] Specifically, an exchange mode swap_mode can be pre-configured for each thread in the EU. Here, the exchange mode swap_mode is used to specify the swap rule between the elements within the thread lane during the SHUFFLE process.

[0086] Taking a 32-bit lane as an example, the swap rules between the elements within the lane are shown in Table 1. In this example, for 8-bit elements, any swap of 4 elements within a 32-bit lane can be achieved (a total of 24 kinds); for 16-bit elements, the swap of 2 elements within a 32-bit lane can be achieved (a total of 2 kinds).

[0087] Table 1. Example of exchange rules

[0088]

[0089]

[0090] It can be understood that in Table 1, the "swap_mode" column represents the rule identifier of the swap rule, the "8-bit demindestination lane (LSB->MSB)" column represents the arrangement of 4 elements "dem" within a thread when the element "element" in the destination thread is 8-bit; the "16-bit dem in destination lane (LSB->MSB)" column represents the arrangement of 2 elements "dem" within a thread when the element "element" in the destination thread is 16-bit. LSB (Least Significant Bit) represents the "dem" in the lower byte within the thread, and MSB (Most Significant Bit) represents the "dem" in the higher byte within the thread. Reserved is a reserved item.

[0091] After determining the swap mode of each thread, the elements within each thread can be rearranged based on the swap rule indicated by the swap mode of each thread. After the rearrangement is completed, the swap between the elements within the thread is achieved.

[0092] The method provided by the embodiments of the present invention realizes arbitrary swapping between elements within a thread during the SHUFFLE process by setting a swap mode for each thread, thereby realizing data transmission at the element granularity.

[0093] Based on any of the above embodiments, the Shifter unit is specifically used for:

[0094] Based on the data offset, shift out the source thread data corresponding to the destination thread from the source data;

[0095] Based on the destination thread index, move the shifted source thread data corresponding to the destination thread to the position of the destination thread.

[0096] Specifically, after obtaining the data offset output by the SHUFFLE unit, the Shifter unit can, according to the data offset, find the source thread data corresponding to the destination thread from the source data according to the shifter logic of the destination thread, that is, the target data. After locating the source thread data corresponding to the destination thread, the source thread data corresponding to the destination thread can be shifted out from the source data, and then, according to the index of the destination thread, that is, the destination thread index, the previously shifted source thread data corresponding to the destination thread can be moved to the position of the destination thread, thereby realizing the offset of the target data.

[0097] It can be understood that in the Shifter unit, the movement of the source thread data corresponding to each target thread can be parallel. For example, when a warp includes 32 thread lanes, 32 thread lanes can be used as target threads for parallel shifting, so as to complete the SHUFFLE operation of 32 lanes.

[0098] For example, Figure 6 is a schematic diagram of the SHUFFLE principle provided by the present invention. As Figure 6 shown, for the SHUFFLE unit, the source thread index when each thread is used as a target thread can be obtained. For example, the source thread index source laneindex of lane0 is 1, the source thread index source lane index of lane1 is 0, and the source thread index source laneindex of lane2 is 6.

[0099] Based on the corresponding relationship between each source thread index and the data offset, the data offset when each thread is used as a target thread can be determined. Thus, the data offset byte offset of lane0 is 4, the data offset byte offset of lane1 is 0, and the data offset byte offset of lane2 is 24.

[0100] Subsequently, for the Shifter unit, based on the data offset of each thread, the source thread data to be moved to the target thread corresponding to each target thread can be obtained from the source data Source data. For example, for lane0, the data offset byte offset is 4, the target data for lane0 (i.e., the data of source thread lane1) can be obtained starting from 4B of the source data Source data, and based on the thread index of the target thread, i.e., the index 0 of lane0, the source thread data corresponding to the target thread is moved to lane0.

[0101] Based on any of the above embodiments, the output interface is specifically used for:

[0102] Based on the target EU identifier and the target register address in the SHUFFLE instruction, the target data is transmitted to the target register in the target EU.

[0103] Specifically, the multi-threaded processor provided by the embodiments of the present invention can not only implement data transmission between different threads within the same EU, but also implement data transmission between different EUs. That is, in the embodiments of the present invention, the data transmission from the source thread to the target thread can be cross-EU.

[0104] To achieve cross-EU data transmission, when the output interface transmits the target data to the destination thread in the EU, it is necessary to determine the EU and TLR address to be delivered according to the target EU identifier EU_ID and the target register address TLR_ADDR in the SHUFFLE instruction, so as to achieve data sharing between EUs based on the SHUFFLE instruction.

[0105] Figure 7 is the schematic diagram of cross-EU transmission provided by the present invention. As Figure 7 shown, the SHUFFLE instruction can carry the EU identifier and register address of the source thread and the destination thread, thereby realizing cross-EU data transmission through the LD / ST unit. For example, Figure 7 in it, the data of EU0 is sent to EU4, and the data of EU2 is sent to EU3.

[0106] Based on any of the above embodiments, the multi-threaded processor further includes a shared memory unit and a read-write control unit;

[0107] The input interface is further configured to transmit the LD / ST instruction in the transmission instruction to the read-write control unit;

[0108] The read-write control unit is configured to parse the LD / ST instruction to obtain the instruction information of the LD / ST instruction, and send the instruction information to the shared memory unit.

[0109] Specifically, when the input interface transmits an instruction backward, it can determine the unit that receives and executes at the backend based on the type of the transmission instruction. Specifically, when the transmission instruction is a SHUFFLE instruction, the SHUFFLE instruction is sent to the SHUFFLE unit built in the LD / ST unit, and when the transmission instruction is an LD / ST instruction, it is transmitted to the read-write control unit.

[0110] Here, the read-write control unit is the processing unit of the LD / ST instruction. After receiving the LD / ST instruction, the read-write control unit can parse the LD / ST instruction to obtain the instruction information of the LD / ST instruction. The instruction information here can include corresponding read and write requests, such as a read request read request, or a write request write request and the information to be written write data. After obtaining the instruction information of the above LD / ST instruction, the read-write control unit can send the instruction information to the shared memory unit shared memory, thereby realizing data reading and writing.

[0111] Based on any of the above embodiments, the read-write control unit includes a read control unit and a write control unit;

[0112] The read control unit is used to parse the LD instruction, obtain the read request of the LD instruction, and send the read request as the instruction information to the shared memory unit;

[0113] The write control unit is used to parse the ST instruction, obtain the write request and write data of the ST instruction, and write the write request and the write data as the instruction information to the shared memory unit.

[0114] Specifically, the read-write control unit may include a read control unit read control and a write control unit writecontrol.

[0115] Among them, the read control unit read control is used to parse the LD instruction, thereby obtaining the read request read request, and sending the read request to the shared memory unit. Taking 32 lanes as a warp as an example, the read control unit read control can send the read requests of 32 lanes to the shared memory unit.

[0116] The write control unit write control is used to parse the ST instruction, thereby obtaining the write request write request and the information to be written write data, and sending the write request and write data to the shared memory unit. Taking 32 lanes as a warp as an example, the write control unit write control can send the write requests and write data of 32 lanes to the shared memory unit.

[0117] Figure 8 One of the schematic diagrams of the physical structure of an electronic device is exemplified, as Figure 8 shown, the electronic device may include: a multi-threaded processor 810, a communication interface (Communications Interface) 820, a memory (memory) 830, and a communication bus 840. Among them, the multi-threaded processor 810, the communication interface 820, and the memory 830 complete mutual communication through the communication bus 840. The multi-threaded processor 810 can call the logical instructions in the memory 830 to implement the corresponding method. It should be noted that the method implemented by the multi-threaded processor 810 by calling the logical instructions in the memory 830 depends on the specific logical instructions stored in the memory 830. When the multi-threaded processor 810 executes the logical instructions in the memory 830, for the part that needs to perform data transmission in the logical instructions, it is implemented by the SHUFFLE unit and the Shifter unit in the multi-threaded processor 810.

[0118] In addition, when the logical instructions in the above-mentioned memory 830 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0119] Based on any of the above embodiments, Figure 9 is one of the schematic flowcharts of the data transmission method provided by the present invention. As Figure 9 shown, this method is a method for implementing data transmission between threads that can be executed in the multi-threaded processor provided in the above embodiments. This method includes:

[0120] Step 910, receiving transmission instructions from multiple execution units EU;

[0121] Step 920, parsing the SHUFFLE instruction in the transmission instruction to obtain the source thread index, and determining the data offset of the destination thread in the source thread data based on the source thread index;

[0122] Step 930, based on the data offset, moving the source thread data corresponding to the destination thread to the position of the destination thread as the target data;

[0123] Step 940, transmitting the target data to the register of the destination thread in the execution unit.

[0124] Specifically, each execution unit EU can separately send a transmission instruction to the LD / ST unit. The transmission instruction here is an instruction for data transmission between threads, which can specifically be a SHUFFLE instruction or an LD / ST instruction.

[0125] After receiving the transmission instruction, taking the received transmission instruction as a unit, select the transmission instruction of one execution unit EU from the transmission instructions sent by multiple execution units EU and transmit it backward. Specifically, when the transmission instruction is a SHUFFLE instruction, the SHUFFLE instruction can be sent to the SHUFFLE unit built in the LD / ST unit.

[0126] The SHUFFLE instruction can be parsed by the SHUFFLE unit to obtain the index of the source thread to be transmitted, that is, the source thread index (source lane index). The index here is used to reflect the absolute position of the thread in a warp. After that, the data offset (byte offset) of the source thread data corresponding to the destination thread can be determined based on the source thread index. The data offset can represent the source thread data corresponding to the destination thread, that is, the offset of the target data to be transmitted in the source thread data. Here, the unit of byte offset can be byte.

[0127] It can be understood that before mapping, the source thread index can be pre-configured for each thread to facilitate the determination of the data offset required during data migration. And it should be noted that the data offset (byte offset) output by the SHUFFLE unit is the same as the data offset required for the Shifter unit in the LD / ST unit in the related art to perform a shift. Thus, without changing the Shifter unit, the SHUFFLE unit can be adapted to the Shifter unit, so as to implement SHUFFLE-based data transmission in the hardware of LD / ST.

[0128] Subsequently, through the Shifter unit, the source thread data corresponding to the destination thread to be migrated, that is, the target data, can be determined from the source thread data based on the data offset, and then the target data is migrated to the position of the destination thread. Specifically, the target data can be filled into the corresponding position of the destination thread.

[0129] Finally, the target data can be transmitted to the register of the destination thread in the EU, specifically, it can be transmitted to the TLR address of the destination thread in the EU. It can be understood that the output interface here can transmit the target data to the register of a certain destination thread in the EU, or it can also transmit the target data to the registers of multiple destination threads in the EU. The embodiments of the present invention do not make specific limitations on this. The data transmission method provided by the embodiments of the present invention realizes the data transmission function from the source thread to the destination thread. And since multiple EUs can share one LD / ST unit, and only one SHUFFLE unit needs to be set in one LD / ST unit, there is no need to set SHUFFLE units for each EU respectively, which greatly saves hardware resources.

[0130] Based on any of the above embodiments, Figure 10 is the second flowchart of the data transmission method provided by the present invention. As Figure 10 shown, the data transmission method may include the following steps:

[0131] ① The LD / ST unit receives instructions from N EUs and selects an instruction from one EU for processing. According to different instruction types, LD / ST instructions can be sent to the read / write control unit respectively, and SHUFFLE instructions can be sent to the SHUFFLE unit.

[0132] ② For ST instructions, the write control unit sends the write data and write requests of 32 lanes to the shared memory unit. For LD instructions, the read control unit only needs to send the read requests of 32 lanes to the shared memory unit.

[0133] ③ The shared memory unit writes the stored data into the SRAM (ST instruction) or reads data from the SRAM (LD instruction).

[0134] ④ The SHUFFLE unit parses the source thread indices of 32 lanes from the SHUFFLE instruction.

[0135] ⑤ The SHUFFLE unit calculates the data offsets of 32 lanes in the destination data according to the source thread indices of 32 lanes.

[0136] ⑥ The Shifter unit shifts the data of each lane (from LD return data or source data of SHUFFLE) according to the LD instruction or the data offsets of 32 lanes calculated by the SHUFFLE unit, and fills it into the corresponding lane position of the destination data of 32 lanes.

[0137] ⑦ The data composed of 32 shifted lanes can be sent to the corresponding TLR address of the corresponding EU according to the corresponding EU_ID and TLR_ADDR.

[0138] The data transmission method provided by the embodiment of the present invention is implemented by setting a SHUFFLE unit in the LD / ST unit shared by multiple EUs. The SHUFFLE unit cooperates with the original Shifter unit in the LD / ST unit to implement the data transmission function from the source thread to the destination thread. And since multiple EUs can share one LD / ST unit, and only one SHUFFLE unit needs to be set in one LD / ST unit, there is no need to set SHUFFLE units for each EU separately, which greatly saves hardware resources.

[0139] Based on any of the above embodiments, Figure 11 This is the second schematic structural diagram of the electronic device provided by the present invention. As Figure 11 shown, the electronic device includes a multi-threaded processor 1100. A memory 1110 is provided inside the multi-threaded processor 1100. A computer program for implementing data transmission inside the multi-threaded processor 1100 is stored in the memory 1110. When the computer program is executed by the multi-threaded processor 1100, the data transmission method is implemented. The data transmission method includes:

[0140] Receiving transmission instructions from multiple execution units EU;

[0141] Parsing the SHUFFLE instruction in the transmission instruction to obtain the source thread index, and determining the data offset of the destination thread in the source thread data based on the source thread index;

[0142] Based on the data offset, moving the source thread data corresponding to the destination thread to the position of the destination thread as the target data;

[0143] Transmitting the target data to the register of the destination thread in the execution unit.

[0144] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the data transmission method provided by the above methods. The method includes:

[0145] Receiving transmission instructions from multiple execution units EU;

[0146] Parsing the SHUFFLE instruction in the transmission instruction to obtain the source thread index, and determining the data offset of the destination thread in the source thread data based on the source thread index;

[0147] Based on the data offset, moving the source thread data corresponding to the destination thread to the position of the destination thread as the target data;

[0148] Transfer the target data to the register of the destination thread in the execution unit.

[0149] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a data transfer method provided by the above-mentioned various methods. The method includes:

[0150] Receive transfer instructions of multiple execution units EU;

[0151] Parse the SHUFFLE instruction in the transfer instruction to obtain the source thread index, and determine the data offset of the destination thread in the source thread data based on the source thread index;

[0152] Based on the data offset, move the source thread data corresponding to the destination thread to the position of the destination thread as the target data;

[0153] Transfer the target data to the register of the destination thread in the execution unit.

[0154] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0155] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution essentially or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-threaded processor, characterized in that, Including: An LD / ST unit and multiple execution units EU, where the LD / ST unit includes an input interface, a SHUFFLE unit, a Shifter unit, and an output interface; The input interface is used to receive transfer instructions from the multiple execution units EU and transfer the SHUFFLE instructions in the transfer instructions to the SHUFFLE unit; The SHUFFLE unit is used to parse the SHUFFLE instructions to obtain the source thread index of the destination thread and determine the data offset of the destination thread in the source thread data based on the source thread index; The Shifter unit moves the source thread data corresponding to the destination thread to the position of the destination thread based on the data offset as the target data, and the data offset output by the SHUFFLE unit is consistent with the data offset required for the Shifter unit to perform a shift; The output interface is used to transfer the target data to the register of the destination thread in the execution unit.

2. The multi-threaded processor according to claim 1, characterized in that, Specifically, the SHUFFLE unit is used to: Obtain the source thread index of each thread in the EU corresponding to the SHUFFLE instruction; Based on the source thread index of each thread, determine the data offset corresponding to each destination thread in the source thread data.

3. The multi-threaded processor according to claim 1, characterized in that, The SHUFFLE unit is further used to: Obtain the exchange mode of each thread in the EU corresponding to the SHUFFLE instruction, where the exchange mode is used to indicate the exchange rule between elements within the destination thread during the SHUFFLE process; Rearrange the elements in each thread based on the exchange mode of each thread.

4. The multi-threaded processor according to claim 1, wherein Specifically, the Shifter unit is used to: Shift out the source thread data corresponding to the destination thread from the source data based on the data offset; Based on the destination thread index, move the shifted source thread data corresponding to the destination thread to the position of the destination thread.

5. The multi-threaded processor according to claim 1, characterized in that, Specifically, the output interface is used to: Based on the target EU identifier and the target register address in the SHUFFLE instruction, transfer the target data to the target register in the target EU.

6. The multi-threaded processor according to any one of claims 1 to 5, characterized in that It further includes a shared memory unit and a read / write control unit; The input interface is further used to transfer the LD / ST instructions in the transfer instructions to the read / write control unit; The read / write control unit is used to parse the LD / ST instructions to obtain the instruction information of the LD / ST instructions and send the instruction information to the shared memory unit.

7. The multi-threaded processor according to claim 6, wherein The read / write control unit includes a read control unit and a write control unit; The read control unit is used to parse the LD instructions to obtain the read requests of the LD instructions and send the read requests as the instruction information to the shared memory unit; The write control unit is used to parse the ST instructions to obtain the write requests and write data of the ST instructions and write the write requests and the write data as the instruction information to the shared memory unit.

8. A data transmission method, characterized in that, The method is applied to a multi-threaded processor as described in any one of claims 1 to 7, and the method includes: Receiving transfer instructions from multiple execution units EU; Parse the SHUFFLE instruction in the transmission instruction to obtain the source thread index, and determine the data offset of the destination thread in the source thread data based on the source thread index; Based on the data offset, move the source thread data corresponding to the destination thread to the position of the destination thread as the target data; Transmit the target data to the register of the destination thread in the execution unit.

9. An electronic device, characterized in that, Comprising a memory, a multi-threaded processor as claimed in any one of claims 1 to 7; a computer program capable of running on the multi-threaded processor is stored in the memory; Alternatively, comprising a multi-threaded processor, a memory is provided inside the multi-threaded processor, and a computer program for implementing data transmission inside the multi-threaded processor is stored in the memory. When the computer program is executed by the multi-threaded processor, the data transmission method as claimed in claim 8 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the multi-threaded processor, the data transmission method as claimed in claim 8 is implemented.

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