PCB trace design detection method and device, terminal equipment and storage medium

Abstract

Embodiments of the present application disclose a PCB wiring design detection method, device, equipment and storage medium, the method receives a detection operation, the detection operation is used to indicate detecting the abnormal wiring in the PCB layout; in response to the detection operation, the target wiring parameter and the actual wiring parameter are acquired, the target wiring parameter is the wiring parameter of the first wiring in the target network layer which is stored in advance, and the actual wiring parameter is the actual wiring parameter of the first wiring in the target network layer; the first wiring is the wiring in the PCB layout; according to the target wiring parameter and the actual wiring parameter, whether the first wiring is an abnormal wiring is determined; if it is determined that the first wiring is an abnormal wiring, the information of the first wiring is displayed. The present scheme realizes bidirectional matching of the design impedance and the actual wiring parameter of each wiring, avoiding missing the wiring which does not meet the design impedance or the design wiring parameter.

Description

PCB trace design testing methods, devices, terminal equipment and storage media Technical Field

[0001] The embodiments of the present invention relate to the field of PCB design technology, and in particular to PCB trace design and inspection methods, devices, terminal equipment and storage media. Background Technology

[0002] PCB (Printed Circuit Board) design is based on circuit schematics to realize the functions required by the circuit designer. The characteristic impedance of the traces on the PCB is a crucial indicator in circuit design, especially in high-frequency circuit PCB design. It is essential to consider whether the characteristic impedance of the traces matches the characteristic impedance required by the components or signals. During PCB design, the impedance of the traces on the board must be controlled to minimize signal reflections, other electromagnetic interference, and signal incompleteness, ensuring the stability of the PCB in actual use. The basic requirement for impedance control is that the impedance in the PCB traces is equal to the impedance inside the output terminal; this requirement is called "impedance matching." Impedance is closely related to the routing method. Therefore, to meet the basic impedance requirements of the final product, the impedance matching of the traces must be controlled during the design phase.

[0003] In existing PCB designs, impedance control of traces is achieved by pre-setting impedance rules. The DRC (Design Rules Checking) function built into the PCB design software will detect areas that do not meet the impedance design and report DRC detection anomalies. Designers can use DRC detection anomalies to check problematic traces.

[0004] When the inventors used existing methods to manage the impedance of traces, they found that the method of calculating impedance by simulation may miss the detection of design impedance or design line width and spacing for some traces. Summary of the Invention

[0005] This invention provides a PCB trace design inspection method, apparatus, terminal equipment, and storage medium to solve the technical problem that existing control measures for certain traces may have omissions in the detection of design impedance or design line width and spacing.

[0006] In a first aspect, embodiments of the present invention provide a PCB trace design inspection method, including:

[0007] Receive detection operations, which are used to indicate abnormal traces in the PCB layout;

[0008] In response to the detection operation, the target routing parameters and actual routing parameters are obtained. The target routing parameters are the pre-stored routing parameters of the first routing in the target network layer, and the actual routing parameters are the actual routing parameters of the first routing in the target network layer. The first routing is the routing in the PCB layout.

[0009] Based on the target routing parameters and the actual routing parameters, determine whether the first routing is an abnormal routing;

[0010] If the first trace is determined to be an abnormal trace, the information of the first trace will be displayed.

[0011] Secondly, embodiments of the present invention also provide a PCB trace design inspection device, comprising:

[0012] An operation receiving unit is used to receive detection operations, which are used to indicate abnormal traces in the PCB layout.

[0013] The parameter acquisition unit is used to acquire target routing parameters and actual routing parameters in response to the detection operation. The target routing parameters are the pre-stored routing parameters of the first routing in the target network layer, and the actual routing parameters are the actual routing parameters of the first routing in the target network layer. The first routing is the routing in the PCB layout.

[0014] The routing determination unit is used to determine whether the first routing is an abnormal routing based on the target routing parameters and the actual routing parameters.

[0015] An error display unit is used to display information about the first trace if it is determined to be an error trace.

[0016] Thirdly, embodiments of the present invention also provide a terminal device, including:

[0017] One or more processors;

[0018] Memory, used to store one or more computer programs;

[0019] When one or more computer programs are executed by one or more processors, the terminal device implements the PCB trace design inspection method as described in the first aspect.

[0020] Fourthly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the PCB trace design detection method as described in the first aspect.

[0021] The aforementioned PCB trace design inspection method, apparatus, terminal device, and storage medium receive inspection operations, which are used to indicate abnormal traces in the PCB layout. In response to the inspection operations, target trace parameters and actual trace parameters are acquired. The target trace parameters are pre-stored trace parameters of a first trace in the target network layer, and the actual trace parameters are the actual trace parameters of the first trace in the target network layer. The first trace is a trace in the PCB layout. Based on the target trace parameters and actual trace parameters, it is determined whether the first trace is an abnormal trace. If the first trace is determined to be an abnormal trace, its information is displayed. By configuring the PCB traces with a reference and setting target trace parameters corresponding to different impedances, when controlling the impedance of the PCB layout, the design impedance and actual trace parameters of each trace are first acquired. Based on the design impedance, the actual trace parameters are matched with the target trace parameters corresponding to each impedance in the reference configuration, thereby achieving bidirectional matching of the design impedance and actual trace parameters for each trace, avoiding the omission of traces that do not meet the design impedance or design trace parameters. Attached Figure Description

[0022] Figure 1 is a flowchart of a PCB trace design inspection method provided by an embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of the trace detection operation provided in an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the initial display parameters and subsequent display parameters in a PCB trace design detection method provided by an embodiment of the present invention;

[0025] Figure 4 is a structural schematic diagram of a PCB trace design testing device provided in an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present invention. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and not for limiting the invention. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention and not the entire structure.

[0028] It should be noted that, due to space limitations, this application specification does not exhaustively list all possible implementation methods. Those skilled in the art should be able to conceive after reading this application specification that, as long as the technical features do not contradict each other, any combination of technical features can constitute an optional implementation method.

[0029] The embodiments are described in detail below.

[0030] Figure 1 is a flowchart of a PCB trace design inspection method provided by an embodiment of the present invention. This PCB trace design inspection method is used in a terminal device. As shown in the figure, the PCB trace design inspection method includes:

[0031] Step S101: Receive detection operation, which is used to indicate the detection of abnormal traces in the PCB layout.

[0032] In PCB design, controlling trace impedance primarily involves setting impedance rules. These rules constrain the impedance, width, and spacing of traces. After the PCB design is complete, the system's built-in DRC (Diagnosis Related Conformance) function evaluates the impedance and trace width / spacing based on the trace design parameters. If a trace is detected that does not meet the impedance design requirements, the system outputs a detection result to remind the designer to optimize the corresponding trace. However, the specific evaluation process of the DRC function involves calculating the impedance using simulation software and comparing it with the target impedance, or comparing the trace width and spacing. Different simulation software uses different methods to calculate impedance, and even if the calculated impedance matches the target impedance, it does not guarantee that the trace width meets the target impedance's design requirements. Furthermore, in actual trace width and spacing detection, generally only the minimum value is controlled, not the maximum value. Also, signal lines running in a neck pattern within the specified area rules may meet the design requirements and will not display an DRC, but they can actually be optimized according to normal impedance design prompts. Furthermore, the impedance of differential signal coupling capacitors may be inconsistent before and after (e.g., 85 ohms on one end and a short 50-ohm single-wire connection on the other). If the uncoupled length meets design requirements after model assignment, DRC will not be reported. Other issues, such as multiplexed circuit modules, may also go undetected by the software's built-in DRC function due to differences in impedance, trace width, or trace spacing before and after replication. This makes it difficult for designers to control signals that do not meet impedance design requirements. Overall, existing impedance-based DRC detection may miss some traces due to design impedance or design trace width / spacing issues.

[0033] This solution proposes a novel trace inspection strategy. Before inspection, a baseline configuration for traces on the PCB layout is set, defining the target trace parameters for the first trace. The PCB layout can have multiple network layers, and the target trace parameters may differ for different target network layers. The baseline configuration process can involve receiving a configuration operation; this operation instructs the configuration of the impedance corresponding to the first trace in the target network layer as the target trace parameters; and it associates and stores the impedance and its corresponding target trace parameters. In the baseline configuration, the type of the first trace is distinguished by its impedance magnitude; each impedance corresponds to a set of target trace parameters, and each impedance and its corresponding target trace parameters are associated and recorded. The first trace added during the PCB design process corresponds to a design with impedance and trace parameters. The design of the impedance and trace parameters should meet a certain design requirement, namely, satisfying the impedance and corresponding target trace parameters recorded in the baseline configuration. During the PCB design process, the design can be performed according to the designer's habits. After the design is completed or during the design process, the designed content can be inspected using this solution to identify first traces that do not meet the corresponding target trace parameters in the actual design. In the specific configuration process, for each impedance, the target routing parameters include target trace width and target trace spacing. Correspondingly, the actual routing parameters obtained from the PCB layout during subsequent testing include actual trace width and actual trace spacing. The trace width refers to the width of a trace perpendicular to the connection direction, and the trace spacing refers to the distance between two adjacent traces. Of course, the target routing parameters must at least include the target trace width of the first trace, and correspondingly, the actual routing parameters must at least include the actual trace width of the first trace.

[0034] It should be noted that each impedance and its corresponding target routing parameters do not necessarily mean that there is a separate file to record them. They can be recorded in a single file with the baseline configuration as the unit. That is, a single file records multiple impedances and their corresponding target routing parameters in different target network layers.

[0035] The designed PCB layout is used as the PCB layout to be inspected. Based on the displayed PCB layout, inspection operations are received. Specifically, receiving inspection operations can be triggered by a control set in the menu bar of the design software, or by a shortcut key corresponding to trace inspection. Alternatively, it can be done by opening a dedicated trace inspection window through an operation in the menu bar, and then receiving inspection operations within that window. The inspection control window 10 shown in Figure 2 is an example of a dedicated trace inspection window. Receiving a trigger operation on the trace identification control 11 corresponding to "Confirm" in the inspection control window 10 initiates the trace inspection process.

[0036] Step S102: In response to the detection operation, obtain the target routing parameters and the actual routing parameters.

[0037] Upon receiving the detection operation, as the start of trace detection, the traces in the PCB layout and their corresponding design impedances (i.e., the actual impedance of the trace in the PCB layout after design) and actual trace parameters are identified. The PCB layout used to implement this solution may include multiple network layers. Traces are assigned names and corresponding design impedances during design; this information can be directly read. Traces have clear location information in the PCB layout, and the actual trace parameters can be obtained based on this location information. The target trace parameters are the pre-stored trace parameters of the first trace in the target network layer, and the actual trace parameters are the actual trace parameters of the first trace in the target network layer; the first trace is the trace in the PCB layout.

[0038] In the baseline configuration, each baseline configuration includes an impedance and a corresponding target routing parameter. For each identified routing trace, the corresponding target routing parameter is determined based on the target network layer where its design impedance is located. Of course, there may be cases where the target routing parameter corresponding to one or more design impedances is not initially configured, meaning the corresponding target routing parameter cannot be obtained in step S102. In this case, such routing traces can be directly treated as abnormal routing traces, or a prompt can be output indicating that some routing traces have not had their corresponding target routing parameters confirmed. Based on the interruption confirmation operation or continued confirmation operation received based on the prompt, the corresponding interruption detection and addition of target routing parameters can be performed, or the prompt can be ignored and subsequent steps can continue. Specifically, the acquisition process can be based on an impedance matching process, that is, from the baseline configuration, the impedance in the corresponding target network layer that is the same as the design impedance is confirmed, and the routing parameter corresponding to that impedance is used as the target routing parameter corresponding to that design impedance.

[0039] In the specific process of trace inspection, the triggering process can be further refined to achieve precise control over the trace inspection process and accurate viewing of trace data.

[0040] As an optional implementation, the detection operation can be a combined operation, where each sub-operation corresponds to a processing step in the detection process. For example, in the detection control window 10 shown in Figure 2, when a trigger operation is received for the trace identification control 11 corresponding to "Confirm," the traces in the target network layer of the PCB layout, as well as the corresponding design impedance and actual trace parameters, are identified. Subsequently, when a trigger operation is received for the trace detection control 13 corresponding to "Detect," it is a parameter detection operation, which triggers the process of determining whether the first trace is an abnormal trace.

[0041] Step S103: Determine whether the first trace is an abnormal trace based on the target trace parameters and the actual trace parameters.

[0042] For each trace, if the actual trace parameters are the same as the corresponding target trace parameters, the actual trace parameters are considered a match; otherwise, they are considered a mismatch. For example, if the actual trace width is 5 mil and the target trace width is 5 mil, the actual trace parameters match. However, if the actual trace width is 5.5 mil or 4.5 mil and the target trace width is 5 mil, the actual trace parameters do not match, and the trace can be identified as an abnormal trace. It should be noted that a mismatch in actual trace parameters may not necessarily indicate that the trace design is unqualified; it only indicates that the actual trace parameters are inconsistent with the saved target trace parameters. This inconsistency may actually stem from redundant design in the actual trace parameters. Through this comparison method, all traces can be tested based on impedance and target trace parameters, allowing designers to further judge traces that exceed or fall below the target trace parameters, ensuring accurate judgment of the actual trace parameters for all traces.

[0043] Besides determining abnormal routing based on whether the actual routing parameters are the same as the target routing parameters, abnormal routing can also be determined by the deviation range between the actual and target routing parameters. That is, the difference between the target and actual routing parameters is determined. If the difference is within a preset range, the first routing is determined not to be abnormal; if the difference is not within the preset range, the first routing is determined to be abnormal. The preset range is determined based on the specific product and the design requirements of the first routing. For example, the preset range may be a positive and negative range centered on the target routing parameters, or a negative range with the target routing parameters as the lower limit.

[0044] Step S104: If the first trace is determined to be an abnormal trace, the information of the first trace is displayed.

[0045] Information on the first trace identified as abnormal can be displayed in detail after the inspection is completed. Specifically, the display shows the first trace's characterization information and abnormal information in the form of a trace list. The characterization information identifies which specific trace on the PCB layout is the abnormal first trace, while the abnormal information indicates the abnormal state. The characterization information can include at least one of location and name information; either one is sufficient to identify the abnormal trace. The abnormal information can include actual trace information and target trace information, allowing the user to confirm the abnormal state of the first trace.

[0046] During the specific testing process, the initial information of the first identified abnormal trace may not be displayed. Instead, the number of abnormal first traces can be displayed to allow the designer to confirm the general situation of the trace testing. The number includes the absolute number of abnormal first traces and may also include the proportion of abnormal first traces among all traces. The designer can then determine the subsequent processing strategy based on the quantity information. The display of quantity information can be shown in Figure 2. The box after "Mismatch Quantity" is used to fill in the quantity information for display.

[0047] Based on displaying the number of the first abnormal traces, you can then examine the content of the first abnormal traces through specific operations.

[0048] Based on the detection control window 10 shown in Figure 2, when a trigger operation is received on the information viewing control 12 corresponding to "View", the information viewing operation is confirmed to have been received. In response to the information viewing operation, a wiring list pops up to display the characterization information and abnormal information of the first abnormal wiring. The specific characterization information and abnormal information are the same as in the previous implementation method of directly popping up the wiring list.

[0049] As shown in Figure 3, the detailed information of the first trace for each anomaly is displayed in the form of a trace list 20. The trace list 20 displays the detailed information of the first trace for each anomaly in a row-column structure. In this structure, the first row is the header 21. Each cell in the header 21 identifies the information attribute of the corresponding record in that column. For example, "Impedance Type" indicates the design impedance of the trace, which is also the configured impedance; "Target Linewidth" indicates the target linewidth in the target trace parameters; "Trace Name" indicates the name configured by the designer for the trace. The name information reflects the core information of a trace's design goal (e.g., connecting two components or transmitting certain information). The designer can quickly review the initial design concept for the trace through the name information; "Actual Linewidth" indicates the actual linewidth obtained during the testing process; and "Trace Location" indicates the location information of the trace, generally recorded in the form of location coordinates. Starting from the second line, each line is a trace information record 22 for the first trace of an anomaly. The trace information record 22 contains specific information corresponding to the information attributes identified in the header 21 of each cell. For example, the first trace information record 22 indicates that the design impedance (configuration impedance) of the first trace of the anomaly is 40 ohms, the target line width is 5.5mil, the name information is "M_B_ACT_N", the actual line width is 5mil, and the location information is (3248.35 3548.41).

[0050] When displaying the routing list, different display attributes can be used based on the anomaly type of the first abnormal routing trace. For example, the first routing trace with actual parameters greater than the target routing parameters is displayed with a background of one color or pattern; the first routing trace with actual parameters less than the target routing parameters is displayed with a background of another color or pattern. Designers can quickly identify the corresponding optimization strategy for the first routing trace based on the anomaly type. For example, for the first routing trace with actual parameters greater than the target routing parameters, the current actual routing parameters can be maintained, or the actual routing parameters can be appropriately reduced; for the first routing trace with actual parameters less than the target routing parameters, there is a high probability that the actual routing parameters need to be increased, i.e., increasing the trace width or trace spacing. In addition, if the design impedance of the routing trace does not have a corresponding configured impedance in the baseline configuration, it is also considered an abnormal first routing trace. In this case, the designer needs to directly check in the routing list whether the actual routing parameters of this first routing trace meet the design requirements, or add the corresponding baseline configuration and re-execute this solution for testing.

[0051] For the first trace shown in the trace list, you can check it in detail through step S1051, or you can confirm through steps S1061 and S1062 that the actual trace parameters of the first trace are normal and do not need to be adjusted or optimized.

[0052] Step S1051: Receive the operation to view any information in the routing list, and highlight the corresponding first routing in the PCB layout.

[0053] If a double-click operation is received on a routing information record in the routing list, or a right-click viewing operation is received, or a trigger operation is received in the pop-up viewing control after selecting a routing information record, then the routing viewing operation is confirmed to have been received. The first routing corresponding to the name or location information in the routing information corresponding to the routing viewing operation is the first routing to be viewed.

[0054] In response to the trace inspection operation, the location of the first trace to be inspected is retrieved from the trace list. This location is then highlighted on the PCB layout. Highlighting can be achieved through methods such as highlighting, zooming in, changing the background color, changing the trace color, or adding annotations. After highlighting the first trace, adjustments can be made to its design based on the inspection results. For example, if the actual trace parameters are too large, they can be appropriately reduced; if they are too small, they can be appropriately increased. After adjustment, a trace inspection can be performed again, re-executing the process to confirm whether the first trace is abnormal based on its actual parameters and the corresponding target trace parameters.

[0055] In addition, while highlighting the corresponding first trace, the trace list can be displayed at the top of the PCB layout. After the designer completes the adjustment of a first trace on the PCB layout, he can directly continue to step S1061 in the trace list to quickly enter the viewing and adjustment process of the next first trace, avoiding switching back and forth between the PCB layout and the trace list.

[0056] Step S1061: Receive abnormal deletion operation, the abnormal deletion operation corresponds to at least one target information in the routing list.

[0057] If a right-click confirmation operation is received for a routing information record in the routing list, or if a trigger operation is received in the pop-up confirmation control after selecting at least one routing information record, then the abnormal deletion operation is confirmed. The relevant routing information record is the target information corresponding to the abnormal deletion operation, and the at least one target information corresponding to the abnormal deletion operation is the target information to be deleted.

[0058] Step S1062: In response to the abnormal deletion operation, delete the target information from the routing list.

[0059] The deletion of target information in the routing list is used to confirm that the actual routing parameters of the first trace corresponding to that target information meet the design requirements and do not require changes to its design content in the PCB layout. In practice, the design impedance and actual routing parameters of the deleted first trace can be temporarily recorded. During subsequent testing, if the design impedance and actual routing parameters of these first traces remain unchanged, they will not be identified as abnormal first traces. This reduces repetitive processing in subsequent testing, simplifies the number of routing information records in the routing list, and allows for a more focused display of abnormal first traces.

[0060] Based on the implementation methods shown in Figures 2 and 3, the detection of PCB traces is achieved through the detection control window 10 in the operation interface shown in Figure 2, which receives the operation and displays the overall statistics. In the operation interface shown in Figure 3, the trace list 20 is used to present information on the first abnormal trace and to select it. It should be understood that the above is only an exemplary information presentation and interaction method. As mentioned above, in actual implementation, after identifying the first abnormal trace, the quantity and information of the first abnormal trace can be displayed simultaneously, and the reception of the detection operation and the display of information on the first abnormal trace can be completed in the same window. For example, based on Figure 2, the trace identification control 11 corresponding to "Confirm" and the information viewing control 12 corresponding to "View" can be omitted, and only the trace detection control 13 corresponding to "Detect" and the detection end control 14 corresponding to "End" can be set. Based on this control setup, after detecting a trace detection operation applied to the trace detection control 13, the detailed information corresponding to the first trace identified as abnormal is directly displayed in the same window as a trace list. That is, the trace list 20 shown in Figure 3 does not need to be displayed in a separate window, but rather in the detection control window 10 shown in Figure 2, displayed together with the relevant controls of the detection operation. Based on this design, after adjusting the abnormal first trace, a one-click re-detection and display of the abnormal first trace is possible. The labels and layout of the controls in Figures 2 and 3 are merely illustrative examples within the overall design of this solution and do not imply that they must be used in this way. Other labels and layouts used to implement the overall design of this solution do not deviate from the design scope of this solution.

[0061] It should also be noted that the step numbering in this solution is for descriptive convenience only and does not imply that the implementation process must necessarily follow all the step numbers in sequence. For example, after step S104, the designer may need to check the status of the first trace of a certain abnormality in the PCB layout, in which case step S105 should be executed; or after step S104, the designer may confirm that the actual trace parameters of the first trace of a certain abnormality meet the design requirements and need to delete the abnormality, in which case steps S1061 and S1062 should be executed.

[0062] The above method, during the PCB design process, receives a detection operation to indicate abnormal traces in the PCB layout. In response to the detection operation, it acquires target trace parameters and actual trace parameters. The target trace parameters are pre-stored trace parameters of a first trace in the target network layer, and the actual trace parameters are the actual trace parameters of the first trace in the target network layer. The first trace is the trace in the PCB layout. Based on the target trace parameters and actual trace parameters, it determines whether the first trace is an abnormal trace. If the first trace is determined to be an abnormal trace, its information is displayed. By configuring the PCB traces with a reference and setting target trace parameters corresponding to different impedances, when controlling the impedance of the PCB layout, it first acquires the design impedance and actual trace parameters of each trace, and matches the actual trace parameters with the reference trace parameters corresponding to each design impedance in the reference configuration. This achieves bidirectional matching of the design impedance and actual trace parameters for each trace, avoiding the omission of traces that do not meet the design impedance or design trace width / spacing requirements. Overall, this solution performs trace inspection based on a baseline configuration, enabling bidirectional matching of the design impedance and actual trace parameters for each trace. With a fixed design impedance, it identifies target traces whose actual trace parameters do not match the baseline trace parameters. Designers can quickly confirm whether the target traces meet the design requirements and optimize accordingly, achieving accurate and comprehensive trace inspection.

[0063] Figure 4 is a schematic diagram of a PCB trace design inspection device provided in an embodiment of the present invention. Referring to Figure 4, the PCB trace design inspection device is used in a terminal device and includes an operation receiving unit 210, a parameter acquisition unit 220, a trace determination unit 230, and an anomaly display unit 240.

[0064] The system includes: an operation receiving unit 210 for receiving a detection operation, which indicates the detection of abnormal traces in the PCB layout; a parameter acquisition unit 220 for acquiring target trace parameters and actual trace parameters in response to the detection operation, wherein the target trace parameters are pre-stored trace parameters of the first trace in the target network layer, and the actual trace parameters are the actual trace parameters of the first trace in the target network layer; the first trace is a trace in the PCB layout; a trace determination unit 230 for determining whether the first trace is an abnormal trace based on the target trace parameters and the actual trace parameters; and an abnormality display unit 240 for displaying information about the first trace if it is determined to be an abnormal trace.

[0065] Based on the above embodiments, the PCB trace design inspection device further includes:

[0066] Receive configuration operation; the configuration operation is used to instruct the target trace parameters in the target network layer to configure the impedance corresponding to the first trace.

[0067] Associate the storage impedance with the corresponding target trace parameters.

[0068] Based on the above embodiments, the routing determination unit 230 includes:

[0069] The difference determination module is used to determine the difference between the target routing parameters and the actual routing parameters;

[0070] The first determining module is used to determine that the first trace is not an abnormal trace if the difference is within a preset range.

[0071] The second determination module is used to determine that the first trace is an abnormal trace if the difference is not within a preset range.

[0072] Based on the above embodiments, the anomaly display unit 240 includes:

[0073] The exception list display module is used to pop up a list of the first trace and display its characterization information and exception information if the first trace is determined to be an exception trace.

[0074] Based on the above embodiments, the PCB trace design inspection device further includes:

[0075] The abnormal routing inspection unit is used to receive the operation of viewing any information in the routing list and highlight the corresponding first routing in the PCB layout.

[0076] Based on the above embodiments, the PCB trace design inspection device further includes:

[0077] The second operation receiving unit is used to receive abnormal deletion operations, which correspond to at least one target information in the routing list.

[0078] The abnormal information deletion unit is used to delete the target information from the wiring list in response to an abnormal deletion operation.

[0079] Based on the above embodiments, the characterization information includes at least one of location information and name information.

[0080] Based on the above embodiments, the abnormal information includes actual routing information and target routing information.

[0081] Based on the above embodiments, the target routing parameters include the target line width of the first routing, and the actual routing parameters include the actual line width of the first routing.

[0082] or,

[0083] The target routing parameters include the target line width and target line spacing of the first routing line, and the actual routing parameters include the actual line width and actual line spacing of the first routing line.

[0084] The PCB trace design inspection device provided in this embodiment of the invention is included in the terminal device and can be used to execute any of the PCB trace design inspection methods provided in the above embodiments, and has corresponding functions and beneficial effects.

[0085] It is worth noting that in the embodiments of the PCB trace design testing device described above, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0086] Figure 5 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present invention. As shown in Figure 5, the terminal device includes a processor 310, a memory 320, an input device 330, an output device 340, and a communication device 350. The number of processors 310 in the terminal device can be one or more; Figure 5 shows an example of one processor 310. The processor 310, memory 320, input device 330, output device 340, and communication device 350 in the terminal device can be connected via a bus or other means; Figure 5 shows an example of connection via a bus.

[0087] The memory 320, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the PCB trace design inspection method in this embodiment of the invention (e.g., the operation receiving unit 210, parameter acquisition unit 220, trace determination unit 230, and abnormal display unit 240 in the PCB trace design inspection device). The processor 310 executes various functional applications and data processing of the terminal device by running the software programs, instructions, and modules stored in the memory 320, thereby realizing the aforementioned PCB trace design inspection method.

[0088] The memory 320 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 320 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 320 may further include memory remotely located relative to the processor 310, which can be connected to the terminal device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0089] Input device 330 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the terminal device. Output device 340 may include display devices such as a display screen.

[0090] The aforementioned terminal equipment includes a PCB trace design inspection device, which can be used to perform any PCB trace design inspection method and has corresponding functions and beneficial effects.

[0091] This invention also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program performs the relevant operations in the PCB trace design and inspection method provided in any embodiment of this application, and has corresponding functions and beneficial effects.

[0092] Those skilled in the art will understand that embodiments of this application may be provided as methods, systems, or computer program products.

[0093] Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams. These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0094] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory. Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0095] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0096] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0097] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for inspecting PCB trace design, characterized in that, include: Receive a detection operation, the detection operation being used to indicate the detection of abnormal traces in the PCB layout; In response to the detection operation, target routing parameters and actual routing parameters are obtained. The target routing parameters are the pre-stored routing parameters of the first routing in the target network layer, and the actual routing parameters are the actual routing parameters of the first routing in the target network layer. The first routing is the routing in the PCB layout. Determine the difference between the target routing parameters and the actual routing parameters; If the difference is within a preset range, the first trace is determined not to be an abnormal trace; if the difference is not within the preset range, the first trace is determined to be an abnormal trace; if the first trace is determined to be an abnormal trace, a trace list is popped up to display the characterization information and abnormal information of the first trace; a configuration operation is received; the configuration operation is used to instruct the configuration of the target trace parameters of the impedance corresponding to the first trace in the target network layer; the impedance and the corresponding target trace parameters are associated and stored.

2. The PCB trace design inspection method according to claim 1, characterized in that, If the first trace is determined to be an abnormal trace, after popping up a trace list to display the characterization information and abnormal information of the first trace, the process includes: receiving a trace viewing operation for any piece of information in the trace list, and highlighting the corresponding first trace in the PCB layout.

3. The PCB trace design inspection method according to claim 1, characterized in that, If the first trace is determined to be an abnormal trace, after popping up a trace list to display the characterization information and abnormal information of the first trace, the process includes: receiving an abnormal deletion operation, the abnormal deletion operation corresponding to at least one target information in the trace list; and in response to the abnormal deletion operation, deleting the target information from the trace list.

4. The PCB trace design inspection method according to claim 1, characterized in that, The representation information includes at least one of location information and name information.

5. The PCB trace design inspection method according to claim 1, characterized in that, The abnormal information includes actual routing information and target routing information.

6. The PCB trace design inspection method according to claim 1, characterized in that, The target routing parameters include the target line width of the first routing, and the actual routing parameters include the actual line width of the first routing; or, the target routing parameters include the target line width and target line spacing of the first routing, and the actual routing parameters include the actual line width and actual line spacing of the first routing.

7. A PCB trace design inspection device, characterized in that, include: An operation receiving unit is used to receive a detection operation, which is used to indicate the detection of abnormal traces in the PCB layout. The parameter acquisition unit is used to acquire target routing parameters and actual routing parameters in response to the detection operation. The target routing parameters are the routing parameters of the first routing in the target network layer that are pre-stored, and the actual routing parameters are the actual routing parameters of the first routing in the target network layer. The first routing is the routing in the PCB layout. The routing determination unit is used to determine whether the first routing is an abnormal routing based on the target routing parameters and the actual routing parameters; the abnormal display unit is used to display the information of the first routing if it is determined that the first routing is an abnormal routing; the configuration storage unit is used to receive a configuration operation; the configuration operation is used to instruct the configuration of the target routing parameters of the impedance corresponding to the first routing in the target network layer. The system associates storage impedance with corresponding target routing parameters. The routing determination unit includes: a difference determination module for determining the difference between the target routing parameters and the actual routing parameters; a first determination module for determining that the first routing is not an abnormal routing if the difference is within a preset range; and a second determination module for determining that the first routing is an abnormal routing if the difference is not within the preset range. The abnormal display unit includes: an abnormal list display module for displaying the characterization information and abnormal information of the first routing if it is determined that the first routing is an abnormal routing.

8. A terminal device, characterized in that, include: One or more processors; Memory, used to store one or more computer programs; When the one or more computer programs are executed by the one or more processors, the terminal device implements the PCB trace design inspection method as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the PCB trace design inspection method as described in any one of claims 1-6.

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