A method for growing a passivation layer and an insulated gate bipolar transistor wafer

Abstract

The embodiment of the present application provides a growth method of a passivation layer and an insulated gate bipolar transistor wafer. Ultraviolet rays are projected on the wafer surface provided with a front metal layer based on a passivation layer design; photosensitive polyimide is printed on the wafer surface where the ultraviolet rays are projected; and the photosensitive polyimide is cured and formed under the ultraviolet ray projection to form a passivation layer meeting the passivation layer design. The passivation layer can be accurately configured at the required position on the wafer surface according to the chip design requirement, and the thickness is controllable, so that the prepared passivation layer has high uniformity, and the etching process can be omitted to avoid the adverse effects of the etching process on the wafer surface.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for growing a passivation layer and an insulated gate bipolar transistor wafer. Background Technology

[0002] In existing technologies, the fabrication of Insulated Gate Bipolar Transistor (IGBT) wafers involves growing and forming a passivation layer on the wafer surface. Generally, the passivation layer is obtained by spin-coating a thermosetting polyimide onto the wafer surface, followed by etching. However, the passivation layer obtained using this method is thinner at the center and thicker at the edges, making it difficult to achieve a highly uniform passivation layer, which negatively impacts the performance of the IGBT wafer. Summary of the Invention

[0003] The present invention provides a method for growing a passivation layer and an insulated gate bipolar transistor wafer to solve the problem of uneven passivation layer on insulated gate bipolar transistor wafers.

[0004] This invention discloses a method for growing a passivation layer, the method comprising:

[0005] Ultraviolet light is projected onto the surface of a wafer with a front-side metal layer based on a passivation layer design.

[0006] Photosensitive polyimide is printed onto the wafer surface where ultraviolet light is projected.

[0007] The photosensitive polyimide is cured and molded under ultraviolet light to form a passivation layer that meets the design requirements.

[0008] Optionally, the step of designing the projection of ultraviolet light on the wafer surface with a passivation layer based on the front metal layer includes:

[0009] Ultraviolet light is projected layer by layer and / or point by point on the surface of a wafer with a front metal layer based on a passivation layer design.

[0010] The step of curing the photosensitive polyimide under ultraviolet light to form a passivation layer that meets the passivation layer design includes:

[0011] The photosensitive polyimide is cured layer by layer and / or point by point under ultraviolet light to form a passivation layer that meets the design requirements.

[0012] Optionally, the step of curing the photosensitive polyimide layer by layer and / or point by point under ultraviolet light to form a passivation layer that meets the passivation layer design includes:

[0013] Based on the area of ​​the wafer, the target molding method corresponding to the photosensitive polyimide curing is determined to be layer-by-layer and / or point-by-point curing.

[0014] Using the aforementioned target molding method, the photosensitive polyimide is cured and molded under ultraviolet light to form a passivation layer that meets the design requirements.

[0015] Optionally, the photosensitive polyimide is prepared in the following manner:

[0016] Polyamic acid was synthesized using dianhydride and diamine to obtain a polyamic acid solution;

[0017] The polyamic acid solution is thermally imidized in air to obtain a thermosetting polyimide solution;

[0018] A resin with photosensitive functional groups is added to the thermosetting polyimide solution to obtain a polyimide resin solution with photocurable properties.

[0019] The solvent in the photocurable polyimide resin solution is removed to obtain photosensitive polyimide powder.

[0020] Optionally, the resin having photosensitive functional groups includes epoxy acrylates having unsaturated double bonds or epoxy functional groups.

[0021] Optionally, the wafer with the front metal layer is prepared by the following method:

[0022] The first groove surface is formed on the surface of the first wafer by etching with deposited tungsten metal.

[0023] A wafer with a front-side metal layer is formed by depositing aluminum on the first groove surface.

[0024] Optionally, the first wafer is prepared using the following method:

[0025] A hard mask is formed on the front surface of the second wafer;

[0026] The trenches are etched and then gate oxidation is performed.

[0027] Polycrystalline silicon is deposited on the surface of the trench to form a trench gate;

[0028] The first ion is injected to form a P-trap, and the second ion is injected to form an N+ region;

[0029] Depositing undoped silicon glass and borosilicate glass to form a dielectric layer;

[0030] A third wafer is obtained by drilling holes between the trenches;

[0031] A Ti / TiN layer is deposited on the front surface of the third wafer to obtain the first wafer.

[0032] Optionally, the second wafer is prepared using the following method:

[0033] The pre-defined N-type substrate is oxidized to form a silicon oxide layer;

[0034] Etching is performed on the surface of the silicon oxide layer, and boron ions are implanted into the etched area to form a p+ region;

[0035] Etching forms the active region and the field oxide region, resulting in a second wafer.

[0036] Optionally, the method further includes:

[0037] The wafer thickness is reduced on the back side of the wafer where the front metal layer is provided by a grinding process.

[0038] A third ion is implanted on the back side of the wafer with the front metal layer to form a P+ region, and then laser annealing is performed.

[0039] A back metal layer is deposited on the back side of the wafer on which the front metal layer is provided.

[0040] This invention also provides an insulated gate bipolar transistor wafer, wherein the passivation layer of the insulated gate bipolar transistor wafer is prepared using the method described in this invention.

[0041] The embodiments of the present invention have the following advantages:

[0042] By using ultraviolet light projection, photosensitive polyimide is printed onto the wafer surface where ultraviolet light is projected. The photosensitive polyimide is cured and formed under ultraviolet light projection to form a passivation layer that meets the design requirements. The passivation layer can be precisely configured at the required position on the wafer surface according to the chip design requirements, and the thickness is controllable. This results in a high uniformity of the prepared passivation layer and eliminates the need for etching, thus avoiding the adverse effects that etching may have on the wafer surface. Attached Figure Description

[0043] Figure 1 This is a flowchart of the steps of a passivation layer growth method provided in an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of an insulated gate bipolar transistor wafer fabrication process provided in an embodiment of the present invention. Detailed Implementation

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Reference Figure 1The diagram illustrates a flowchart of a passivation layer growth method provided in an embodiment of the present invention, which may specifically include the following steps:

[0047] Step 101: Project ultraviolet light onto the wafer surface with the front metal layer based on the passivation layer design;

[0048] Specifically, during wafer fabrication, the wafer can be patterned according to chip requirements, and through a series of etching, deposition, and other processes, the arrangement of various functions in the final wafer can meet the chip design requirements. Therefore, embodiments of the present invention can design the passivation layer pattern, and based on the passivation layer design requirements, ultraviolet light is projected onto the wafer surface where the passivation layer needs to be grown, where a front-side metal layer is located, so that the passivation layer can be subsequently deposited at the corresponding location based on the ultraviolet light.

[0049] Generally, a passivation layer can be placed on the wafer surface where the front metal layer is not masked, to flatten the wafer surface and protect the front metal layer. Therefore, the passivation layer can typically be designed to cover uneven areas on the wafer's front surface and the area around the front metal layer.

[0050] In practice, to further protect the front surface of the wafer, a SiN layer can be deposited on the front surface of the wafer using a sputtering process before the passivation layer is deployed. This further strengthens the passivation layer of the wafer and also provides a certain buffer protection.

[0051] Step 102: Print photosensitive polyimide onto the wafer surface where ultraviolet light is projected;

[0052] In this embodiment of the invention, photosensitive polyimide can be printed onto the wafer surface at a location where ultraviolet light is projected, thereby deploying the photosensitive polyimide onto the wafer surface at the location where a passivation layer needs to be grown.

[0053] Step 103: The photosensitive polyimide is cured and molded under ultraviolet light to form a passivation layer that meets the design requirements of the passivation layer.

[0054] In this embodiment of the invention, the photosensitive polyimide is sensitive to ultraviolet light. Under ultraviolet light projection, the photosensitive polyimide can be cured and molded. The irradiation position of the ultraviolet light can be gradually varied according to actual needs, and the photosensitive polyimide can be deployed at the corresponding positions to form the corresponding passivation layer according to the design. In this way, the growth position and thickness of the passivation layer are highly controllable, and the formed passivation layer can have good flatness. At the same time, since no etching process is required, the adverse effects on the wafer surface can be appropriately reduced.

[0055] Optionally, the step of designing the projection of ultraviolet light on the wafer surface with a passivation layer based on the front metal layer includes:

[0056] S11, UV light is projected layer by layer and / or point by point on the wafer surface with a front metal layer based on a passivation layer design.

[0057] In this embodiment of the invention, the passivation layer can be regarded as a three-dimensional structure. In order to improve the growth accuracy of the passivation layer, the passivation layer can be divided into multiple layers or multiple points based on the passivation layer design. Ultraviolet light is projected layer by layer and / or point by point on the wafer surface with the front metal layer so that the passivation layer can be formed layer by layer and / or point by point, which can greatly improve the accuracy of the passivation layer.

[0058] The step of curing the photosensitive polyimide under ultraviolet light to form a passivation layer that meets the passivation layer design includes:

[0059] S21, the photosensitive polyimide is cured layer by layer and / or point by point under ultraviolet light to form a passivation layer that meets the design requirements of the passivation layer.

[0060] Specifically, when ultraviolet light is projected layer by layer and / or point by point, a suitable amount of photosensitive polyimide can be applied at the ultraviolet projection location. The photosensitive polyimide is cured and formed under ultraviolet light irradiation, thereby forming a passivation layer at the current layer and / or current point. As the ultraviolet projection location changes, the photosensitive polyimide continues to be applied at the corresponding location, thereby curing and forming the passivation layer with high precision under ultraviolet light projection layer by layer and / or point by point.

[0061] Optionally, the step of curing the photosensitive polyimide layer by layer and / or point by point under ultraviolet light to form a passivation layer that meets the passivation layer design includes:

[0062] S31, based on the area of ​​the wafer, determine that the target molding method corresponding to the photosensitive polyimide curing is layer-by-layer and / or point-by-point curing.

[0063] In one embodiment of the present invention, the curing process employs layer-by-layer and / or point-by-point curing, which can be determined based on the wafer area. When the wafer area is relatively large, the growth rate required for the passivation layer can be relatively low. In this case, only a layer-by-layer curing process can be used. In this case, the layer-by-layer arrangement of photosensitive polyimide can be more efficient than point-by-point arrangement, while maintaining good precision.

[0064] When the wafer area is small, a passivation layer needs to be grown with high precision to avoid adverse effects on other front surfaces such as the front metal layer. In this case, a point-by-point deployment method can be used to deploy the passivation layer to maintain high precision.

[0065] Depending on the actual needs, both layer-by-layer curing and point-by-point curing can be used simultaneously to complete the deployment of the passivation layer. For example, each layer of ultraviolet projection can be further divided into multiple areas. If the entire area needs to be covered with the passivation layer, then layer-by-layer curing can be used to quickly cover the entire area. However, if there are areas that need to be avoided, such as the front metal layer, then the deployment of the passivation layer needs to maintain a high speed. In this case, point-by-point curing can be used to precisely deploy the passivation layer to the location that meets the design requirements of the passivation layer.

[0066] Therefore, a suitable molding method can be selected based on the wafer area, which can be used as the target molding method for photosensitive polyimide curing, so as to appropriately increase the passivation layer generation speed and maintain a good progress.

[0067] S32, using the target molding method, the photosensitive polyimide is cured and molded under ultraviolet light to form a passivation layer that meets the design requirements of the passivation layer.

[0068] After determining the target molding method, ultraviolet light can be projected onto the wafer surface in a corresponding manner, and photosensitive polyimide can be deployed at the ultraviolet light projection point, cured and molded to form a passivation layer that meets the passivation layer design.

[0069] In one embodiment of the present invention, the photosensitive polyimide is prepared in the following manner:

[0070] S41, polyamic acid is synthesized using dianhydride and diamine to obtain a polyamic acid solution;

[0071] In practical applications, polyimides are primarily synthesized from dianhydrides and diamines. Compared to monomers of many other heterocyclic polymers, such as polybenzimidazole, polybenzoxazole, polybenzothiazole, polyquinoxaline, and polyquinoline, these two monomers have a wider range of raw material sources and are easier to synthesize. Polyimides can be obtained by first undergoing low-temperature polycondensation of dianhydrides and diamines in polar solvents, such as DMF (dimethylformamide), DMAc (dimethylacetamide), NMP (N-methyl-2-pyrrolidone), or THF (tetrahydrofuran) / methanol mixtures, to obtain soluble polyamic acid.

[0072] S42, the polyamic acid solution is thermally imidized in air to obtain a thermosetting polyimide solution;

[0073] In practice, after the polyamic acid solution is formed into a film or spun, it is heated to about 300°C to dehydrate and then converted into polyimide through thermal imidization to obtain a thermosetting polyimide solution.

[0074] Alternatively, acetic anhydride and tertiary amine catalysts can be added to polyamic acid to perform chemical dehydration and cyclization, yielding polyimide solutions or powders. Dianone and diamine can also undergo heating and polycondensation in high-boiling solvents, such as phenolic solvents, to obtain polyimide in one step. Furthermore, polyimide can be obtained by reacting a tetrabasic acid diester with a diamine; alternatively, polyamic acid can be first converted to polyisoimide, and then heated to polyimide.

[0075] S43, a resin having photosensitive functional groups is added to the thermosetting polyimide solution to obtain a polyimide resin solution with photocurable properties.

[0076] Subsequently, a resin with photosensitive functional groups can be added to the thermosetting polyimide solution. The thermosetting polyimide can undergo a cross-linking reaction with the resin with photosensitive functional groups, thereby forming a polyimide resin solution with photocurable properties.

[0077] S44, remove the solvent from the photocurable polyimide resin solution to obtain photosensitive polyimide powder.

[0078] Subsequently, the solvent in the photocurable polyimide resin solution can be removed by evaporating the solvent or adding an anti-solvent, to obtain a photocurable polyimide resin in the photocurable polyimide resin solution. The photocurable polyimide resin can then be dispersed to obtain photosensitive polyimide powder.

[0079] Optionally, the resin with photosensitive functional groups includes epoxy acrylates having unsaturated double bonds or epoxy functional groups, the functional groups of which can have light sensitivity and responsiveness, so that the polyimide crosslinked with the epoxy acrylates having unsaturated double bonds or epoxy functional groups can generate photosensitivity, making it applicable to the generation of passivation layers.

[0080] In one embodiment of the present invention, the wafer with the front metal layer is prepared by the following method:

[0081] S51, a first groove surface is formed on the surface of the first wafer by etching with deposited tungsten metal;

[0082] Specifically, tungsten metal possesses a high melting point, high density, and excellent electron mobility, making it commonly used in microelectronic devices for fabricating electrodes, wires, and contact materials. By depositing tungsten metal on a wafer surface, a metal layer with good conductivity can be formed, and the shape and size of the groove surface can be precisely controlled. Simultaneously, it can form an interface layer, improving the adhesion and compatibility between the wafer and other materials. Furthermore, it can protect the substrate to some extent during the etching process, preventing further damage. Therefore, a first groove surface can be formed on the surface of a first wafer by depositing tungsten metal and etching, facilitating the subsequent deployment of a front-side metal layer and improving its robustness.

[0083] S52, a wafer with a front metal layer is formed on the first groove surface by depositing aluminum.

[0084] Specifically, aluminum can be deposited on a surface where tungsten metal has already been deposited. Aluminum can be used as a conductor on the wafer surface, and it can be firmly set on the wafer surface through tungsten metal, thereby forming a front metal layer and obtaining a wafer with a front metal layer.

[0085] Optionally, the first wafer is prepared using the following method:

[0086] S53, forming a hard mask on the front surface of the second wafer;

[0087] In a specific implementation, before etching the wafer surface, a hard mask can be formed on the front surface of a second wafer to protect other functional layers previously formed on the wafer surface. This hard mask can be silicon nitride, silicon oxide, etc., and this invention does not limit its application to these materials.

[0088] S54, etching to form trenches and performing gate oxidation treatment;

[0089] In this embodiment of the invention, to maintain a uniform carrier concentration distribution and reduce on-state losses without affecting tail current and turn-off losses, a trench gate structure can be deployed in the wafer. The main difference from a conventional planar gate structure is that when the IGBT is turned on, the inversion channel of the P-type emitter region is vertical rather than lateral, meaning that the JFET (Junction Field Effect Transistor) effect does not exist. Due to the injection of a large number of electrons, the conductivity modulation efficiency near the emitter region is very high.

[0090] Therefore, the front surface of the second wafer can be etched first to form trenches, and then gate oxidation can be performed to form an insulating layer, separating the gate lines and the substrate.

[0091] S55, depositing polysilicon on the surface of the trench to form a trench gate;

[0092] Subsequently, after the gate oxidation process is completed, a trench gate can be formed by depositing polysilicon on the trench surface. Polysilicon has good electrical conductivity and can be used as electrodes, wires, and interconnect structures. By depositing polysilicon on the trench surface, a material layer with good electrical conductivity can be formed for the connection and signal transmission of electronic devices.

[0093] S56, the first ion is injected to form a P-trap, and the second ion is injected to form an N+ region;

[0094] Specifically, a P-well can be formed by implanting a first ion at the corresponding location according to the chip design requirements. The first ion can be a P-type dopant such as boron.

[0095] Specifically, by forming a P-well, a P-type region can be formed on an N-type substrate, achieving electrical isolation between N-type and P-type transistors. Simultaneously, the electric field distribution of the transistor can be adjusted, thereby improving transistor performance and reliability. It can reduce the capacitance effect of the PN junction, and improve the switching speed and noise immunity of the transistor.

[0096] Subsequently, a second ion can be implanted above the P-well to form an N+ region. The second ion can be an N-type dopant such as phosphorus. The N+ region is typically used to form source, drain, and contact electrode regions to provide a low-resistance current path.

[0097] S57, deposit undoped silicon glass and borosilicate glass to form a dielectric layer;

[0098] Subsequently, undoped silicon glass and borosilicate glass can be deposited to form a dielectric layer. The main function of the dielectric layer is to isolate the charge between the gate and the main electrode, preventing current from flowing directly through. By providing electrical isolation, it ensures that the gate signal does not directly affect the main electrode, thereby enabling control of the IGBT. In this embodiment of the invention, undoped silicon glass (NSG) and borosilicate glass (BPSG) can be used as the dielectric layer. Specifically, the deposition of undoped silicon glass and borosilicate glass can be achieved through techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PECVD).

[0099] S58, A hole is made between the trenches to obtain a third wafer;

[0100] In this embodiment of the invention, to enhance electric field control and reduce charge accumulation, holes can be made between the trenches to provide more channels, making it easier for charge to flow and reducing charge accumulation. Specifically, at least one hole can be made through both undoped silicon glass and borosilicate glass to obtain a third wafer.

[0101] S59, deposit a Ti / TiN layer on the front surface of the third wafer to obtain the first wafer.

[0102] In a practical implementation, a Ti / TiN layer can be further deposited on the front surface of the third wafer to further improve the surface hardness of the wafer, thus obtaining the first wafer.

[0103] In one embodiment of the present invention, the second wafer is prepared by the following method:

[0104] S61, oxidize the preset N-type substrate to form a silicon oxide layer;

[0105] First, the pre-defined N-type substrate can be oxidized to form a silicon oxide layer. The silicon oxide layer provides electrical isolation, isolating the N-type substrate from other electrodes or layers and preventing unintended current flow.

[0106] S62 involves etching the surface of a silicon oxide layer and implanting boron ions into the etched area to form a p+ region.

[0107] Subsequently, etching can be performed on the surface of the silicon oxide layer, and boron ions can be implanted into the etched area to form a p+ region, thereby forming an electrical channel.

[0108] S63, etching to form the active region and the field oxide region, to obtain the second wafer.

[0109] Subsequently, further etching can be performed to form the active region and the field oxide region. The active region is the active area in the transistor used to control the flow of current. By etching to form the active region, the channel length and width of the transistor can be defined, thereby controlling the current flow characteristics. The field oxide region is an insulating layer in the transistor used to isolate the gate and the active region. It can prevent current leakage between the gate and the active region and provide electric field control.

[0110] Optionally, the method further includes:

[0111] S71, the wafer thickness is reduced on the back side of the wafer on which the front metal layer is provided by a grinding process;

[0112] First, the wafer thickness can be reduced through grinding processes according to the actual required wafer thickness, so that the wafer can meet the subsequent process requirements.

[0113] S72, a third ion is implanted on the back side of the wafer on which the front metal layer is provided to form a P+ region, and laser annealing is performed.

[0114] Subsequently, a third ion can be implanted on the back side of the wafer with the front metal layer to form a P+ region. The third ion can be a P-type dopant such as boron. Then, laser annealing is used to quickly repair the damage to the wafer caused by the implanted ions.

[0115] S73, a back metal layer is deposited on the back side of the wafer on which the front metal layer is provided.

[0116] Subsequently, a back metal layer can be deposited on the back side of the wafer with the front metal layer to form a back electrode.

[0117] This invention also provides an insulated gate bipolar transistor wafer, wherein the passivation layer of the insulated gate bipolar transistor wafer is prepared by the method described in this invention, and will not be described in detail here.

[0118] By using ultraviolet light projection, photosensitive polyimide is printed onto the wafer surface where ultraviolet light is projected. The photosensitive polyimide is cured and formed under ultraviolet light projection to form a passivation layer that meets the design requirements. The passivation layer can be precisely configured at the required position on the wafer surface according to the chip design requirements, and the thickness is controllable. This results in a high uniformity of the prepared passivation layer and eliminates the need for etching, thus avoiding the adverse effects that etching may have on the wafer surface.

[0119] refer to Figure 2 This paper illustrates a wafer fabrication process for an insulated gate bipolar transistor according to an embodiment of the present invention. The process specifically includes the following steps:

[0120] Step 1: Perform substrate oxidation (INT Oxide) on the surface of an N-type silicon substrate using a high-temperature thermal diffusion process.

[0121] A pre-defined N-type substrate can be oxidized to form a silicon oxide layer. The silicon oxide layer can provide electrical isolation, separating the N-type substrate from other electrodes or layers and preventing unintended current flow.

[0122] The second step is to coat the oxidized substrate surface with photoresist (PR), and then perform exposure, development, and etching using a ring mask. The areas where the oxide layer is etched away are then implanted with a high dose of boron to form P+ regions, thereby creating electrical channels.

[0123] Step 3: Etching to form field oxidation and active area.

[0124] Further etching can be performed to form the active region and the field oxide region. The active region is the active area in the transistor used to control the flow of current. By etching to form the active region, the channel length and width of the transistor can be defined, thereby controlling the current flow characteristics. The field oxide region is an insulating layer in the transistor used to isolate the gate and the active region. It can prevent current leakage between the gate and the active region and provide electric field control.

[0125] Step 4: Hard mask deposition

[0126] Before etching the wafer surface, a hard mask can be formed on the front surface of a second wafer to protect other functional layers previously formed on the wafer surface. This hard mask can be silicon nitride, silicon oxide, etc., and this invention does not limit its application.

[0127] Step 4: Trench silicon etching and gate oxide

[0128] To maintain a uniform carrier concentration distribution and reduce on-state losses without affecting tail current and turn-off losses, trench gate structures can be deployed in the wafer. The main difference from ordinary planar gate structures is that when the IGBT is turned on, the inversion channel of the P-type emitter region is vertical rather than lateral, meaning there is no JFET effect. Due to the injection of a large number of electrons, the conductivity modulation efficiency near the emitter region is very high. Therefore, the front surface of the second wafer can be etched first to form trenches, followed by gate oxidation to form an insulating layer, isolating the gate lines and substrate.

[0129] Step 5: Polysilicon deposition to form the gate poly and etching.

[0130] After gate oxidation, a trench gate can be formed by depositing polysilicon on the trench surface. Polysilicon has excellent electrical conductivity and can be used as electrodes, wires, and interconnect structures. By depositing polysilicon on the trench surface, a material layer with good electrical conductivity can be formed for the connection and signal transmission of electronic devices.

[0131] Step 6: P-well injection and N+ injection

[0132] According to chip design requirements, a first ion is implanted at the corresponding location to form a P-well. The first ion can be a P-type dopant such as boron. By forming the P-well, a P-type region can be formed on the N-type substrate, achieving electrical isolation between N-type and P-type transistors. Subsequently, a second ion can be implanted above the P-well to form an N+ region. The second ion can be an N-type dopant such as phosphorus. The N+ region is typically used to form source, drain, and contact electrodes to provide a low-resistance current path.

[0133] Step 7: Deposition of undoped silicon glass (NSG) and borosilicate glass (BPSG) to form the dielectric layer (ILD).

[0134] Undoped silicon glass and borosilicate glass (BPSG) are further deposited to form a dielectric layer. The main function of the dielectric layer is to isolate the charge between the gate and the master electrode, preventing direct current flow. By providing electrical isolation, it ensures that the gate signal does not directly affect the master electrode, thereby enabling control of the IGBT. In this embodiment of the invention, undoped silicon glass (NSG) and borosilicate glass (BPSG) can be used as the dielectric layer.

[0135] Step 8: Contact etching. An opening is created between the two trenches, with one hole passing through the undoped silicon glass (NSG) and borosilicate glass (BPSG).

[0136] To enhance electric field control and reduce charge accumulation, vias can be created between the trenches to provide more channels, facilitating charge flow and reducing charge accumulation. Specifically, at least one via can be created through both undoped silicon glass and borosilicate glass to obtain a third wafer.

[0137] Step 9: Ti / TiN layer deposition and rapid annealing

[0138] A Ti / TiN layer can be further deposited on the front surface of the third wafer to further improve the surface hardness of the wafer.

[0139] Step 10: Metal deposition. First, perform tungsten (W) deposition etching, then perform front-side alpha (AL) deposition.

[0140] A first groove is formed on the surface of the first wafer by etching tungsten metal deposition to facilitate the subsequent deployment of a front-side metal layer and improve its adhesion. Subsequently, aluminum can be deposited on the surface where tungsten metal has been deposited. Aluminum can be used as a conductor on the wafer surface, and it can be firmly set on the wafer surface by tungsten metal, thereby forming a front-side metal layer, resulting in a wafer with a front-side metal layer.

[0141] Step 11: Passivation layer growth. First, a SiN layer is deposited on the surface of the aluminum metal layer using a sputtering process. Then, the computer-controlled ultraviolet light is used to form a projection or a movable laser point to solidify the photosensitive polyimide point by point or layer by layer according to the chip design requirements, ultimately forming a passivation layer of the required thickness.

[0142] Step 12: Backside thinning. After the frontside processes are completed normally, the wafer is flipped over, and the wafer thickness is reduced through a grinding process.

[0143] The wafer thickness can be reduced through grinding processes to meet the actual requirements of the desired wafer thickness, thus ensuring that the wafer meets subsequent process requirements.

[0144] Step 13: Backside P+ Injection and Laser Annealing

[0145] A third ion can be implanted on the back side of a wafer with a front-side metal layer to form a P+ region. The third ion can be a P-type dopant such as boron. Subsequently, laser annealing can quickly repair the damage to the wafer caused by the implanted ions.

[0146] Step 14: Backside Metal Deposition

[0147] A back metal layer can be deposited on the back side of a wafer with a front metal layer to form a back electrode.

[0148] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0149] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0150] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0151] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for growing a passivation layer, characterized in that, The method includes: Ultraviolet light is projected onto the surface of a wafer with a front-side metal layer based on a passivation layer design. Photosensitive polyimide is printed onto the wafer surface where ultraviolet light is projected. The photosensitive polyimide is cured and molded under ultraviolet light to form a passivation layer that meets the design requirements.

2. The method according to claim 1, characterized in that, The step of designing ultraviolet radiation projection based on a passivation layer on the surface of a wafer with a front metal layer includes: Ultraviolet light is projected layer by layer and / or point by point on the surface of a wafer with a front metal layer based on a passivation layer design. The step of curing the photosensitive polyimide under ultraviolet light to form a passivation layer that meets the passivation layer design includes: The photosensitive polyimide is cured layer by layer and / or point by point under ultraviolet light to form a passivation layer that meets the design requirements.

3. The method according to claim 2, characterized in that, The step of curing the photosensitive polyimide layer by layer and / or point by point under ultraviolet light to form a passivation layer that meets the design requirements includes: Based on the area of ​​the wafer, the target molding method corresponding to the photosensitive polyimide curing is determined to be layer-by-layer and / or point-by-point curing. Using the aforementioned target molding method, the photosensitive polyimide is cured and molded under ultraviolet light to form a passivation layer that meets the design requirements.

4. The method according to claim 1, characterized in that, The photosensitive polyimide was prepared in the following manner: Polyamic acid was synthesized using dianhydride and diamine to obtain a polyamic acid solution; The polyamic acid solution is thermally imidized in air to obtain a thermosetting polyimide solution; A resin with photosensitive functional groups is added to the thermosetting polyimide solution to obtain a polyimide resin solution with photocurable properties. The solvent in the photocurable polyimide resin solution is removed to obtain photosensitive polyimide powder.

5. The method according to claim 3, characterized in that, The resin having photosensitive functional groups includes epoxy acrylates having unsaturated double bonds or epoxy functional groups.

6. The method according to claim 1, characterized in that, The wafer with the front-side metal layer is prepared using the following method: The first groove surface is formed on the surface of the first wafer by etching with deposited tungsten metal. A wafer with a front-side metal layer is formed by depositing aluminum on the first groove surface.

7. The method according to claim 6, characterized in that, The first wafer was prepared using the following method: A hard mask is formed on the front surface of the second wafer; The trenches are etched and then gate oxidation is performed. Polycrystalline silicon is deposited on the surface of the trench to form a trench gate; The first ion is injected to form a P-trap, and the second ion is injected to form an N+ region; Depositing undoped silicon glass and borosilicate glass to form a dielectric layer; A third wafer is obtained by drilling holes between the trenches; A Ti / TiN layer is deposited on the front surface of the third wafer to obtain the first wafer.

8. The method according to claim 1, characterized in that, The second wafer was prepared using the following method: The pre-defined N-type substrate is oxidized to form a silicon oxide layer; Etching is performed on the surface of the silicon oxide layer, and boron ions are implanted into the etched area to form a p+ region; Etching forms the active region and the field oxide region, resulting in a second wafer.

9. The method according to claim 1, characterized in that, The method further includes: The wafer thickness is reduced on the back side of the wafer where the front metal layer is provided by a grinding process. A third ion is implanted on the back side of the wafer with the front metal layer to form a P+ region, and then laser annealing is performed. A back metal layer is deposited on the back side of the wafer on which the front metal layer is provided.

10. An insulated gate bipolar transistor wafer, characterized in that, The passivation layer of the insulated gate bipolar transistor wafer is prepared by the method described in any one of claims 1-9.

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