Gate oxide integrity test method and apparatus, and wat test apparatus

Abstract

A method and apparatus for testing the integrity of a gate oxide layer, and a WAT ​​testing apparatus. The method is used to test the gate oxide layer integrity in a first exposure area of ​​a first wafer; the method includes: acquiring failure mode data information of the GOI test bond in the first exposure area; the failure mode data information includes: information on a first current value corresponding to the gate end solder area of ​​the GOI test bond at a first voltage value; and information on a second current value corresponding to the gate end solder area of ​​the GOI test bond at a second voltage value; the first voltage value is the operating voltage value of the GOI test bond, and the second voltage value is 2.3 times the operating voltage value; applying the voltage value or current value in the failure mode data information to the gate end solder area of ​​the GOI test bond to perform gate oxide layer integrity testing on the first exposure area. Using the above method, the time required for GOI testing can be shortened.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a method and apparatus for testing gate oxide integrity (GOI) and a WAT ​​testing apparatus. Background Technology

[0002] In the manufacturing process of semiconductor devices, in order to monitor the manufacturing process and ensure the reliability of semiconductor devices, the common practice is to form test keys in the devices for testing some key parameters.

[0003] In CMOS processes, the gate oxide layer is a crucial component of the device structure. Ideally, it should be an ideal dielectric layer, free from defects that affect its insulating properties. However, factors during manufacturing, such as ion diffusion and trapped charge, can negatively impact the quality of the gate oxide layer. Failure of the gate oxide layer can lead to the overall failure of the device.

[0004] GOI testing is a process for verifying the quality of the gate oxide layer. If the GOI test fails, GOI failure analysis is required to identify the cause of the failure. This allows for process improvements and ultimately, increases in product yield.

[0005] Existing GOI testing methods are time-consuming and inefficient. Summary of the Invention

[0006] The problem this invention aims to solve is: how to shorten the time required for GOI testing.

[0007] To address the aforementioned problems, this invention provides a method for testing the integrity of a gate oxide layer, used to test the gate oxide layer integrity in a first exposure area of ​​a first wafer. The method includes: acquiring failure mode data information of a GOI test bond in the first exposure area; the failure mode data information includes: information on a first current value corresponding to the gate terminal solder area of ​​the GOI test bond when the voltage is a first voltage value; and information on a second current value corresponding to the gate terminal solder area of ​​the GOI test bond when the voltage is a second voltage value; the first voltage value is the operating voltage value of the GOI test bond, and the second voltage value is 2.3 times the operating voltage value; applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test bond to perform a gate oxide layer integrity test on the first exposure area.

[0008] Optionally, applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes:

[0009] A first voltage value is applied to the gate terminal soldering area of ​​the GOI test key, and the current value of the gate terminal soldering area of ​​the GOI test key is detected to be greater than the first current value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure.

[0010] A second voltage value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the second current value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

[0011] Optionally, applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes:

[0012] A first current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is less than the first voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure.

[0013] A second current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is greater than the second voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

[0014] Optionally, applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes:

[0015] A first current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is less than the first voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure.

[0016] A second voltage value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the second current value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

[0017] Optionally, applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes:

[0018] A first voltage value is applied to the gate terminal soldering area of ​​the GOI test key, and the current value of the gate terminal soldering area of ​​the GOI test key is detected to be greater than the first current value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure.

[0019] A second current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is greater than the second voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

[0020] Optionally, during the WAT test of the first wafer, the integrity test of the gate oxide layer in the first exposure area can be completed using WAT test resources.

[0021] Optionally, after performing the WAT test on the first wafer, the integrity test of the gate oxide layer in the first exposure area can be completed using the WAT test resources.

[0022] Optionally, the step of utilizing WAT testing resources to complete the gate oxide layer integrity test in the first exposure area includes:

[0023] The source and drain solder areas of the GOI test bond are left suspended, while the substrate solder area is grounded. The gate oxide integrity test is then performed at the gate solder area of ​​the GOI test bond.

[0024] Optionally, the GOI test bond includes six device structures. When performing gate oxide integrity testing on the first exposure area, gate oxide integrity testing is performed on each device structure in the GOI test bond.

[0025] This invention also provides a gate oxide layer integrity testing apparatus, the apparatus comprising: an acquisition unit adapted to acquire failure mode data information of a GOI test bond in a first exposure area; the failure mode data information including: information on a first current value corresponding to the gate end solder area of ​​the GOI test bond when the voltage is a first voltage value; and information on a second current value corresponding to the gate end solder area of ​​the GOI test bond when the voltage is a second voltage value; the first voltage value is the operating voltage value of the GOI test bond, and the second voltage value is 2.3 times the operating voltage value; and a testing unit adapted to apply the voltage value or current value in the failure mode data information to the gate end solder area of ​​the GOI test bond to perform a gate oxide layer integrity test on the first exposure area.

[0026] This invention also provides a WAT ​​testing apparatus, which includes the aforementioned gate oxide integrity testing apparatus.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0028] By applying the solution of this invention, failure mode data information of the GOI test bond in the first exposure area is obtained, and then the voltage or current value in the failure mode data information is applied to the gate end solder area of ​​the GOI test bond to perform gate oxide layer integrity testing on the first exposure area. Compared with the existing GOI testing method, it is not necessary to continuously increase the voltage of the gate end solder area in the GOI test bond in a certain step to draw a plot. Only a fixed voltage or current value needs to be applied to the gate end solder area of ​​the GOI test bond to complete the gate oxide layer integrity test. This can greatly shorten the testing time required for gate oxide layer integrity testing, reduce the testing resources occupied, improve testing efficiency, and meet the monitoring needs of mass production and the gate oxide layer integrity testing needs in the event of an emergency. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the plot chart corresponding to the wafer where the test bond with an operating voltage of 3.3V is located;

[0030] Figure 2 This is a flowchart of a method for testing the integrity of a gate oxide layer according to an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram showing the change of current value in the gate soldering area of ​​each exposure field zone of a wafer operating at 5V as a function of voltage.

[0032] Figure 4 This is a schematic diagram of a gate oxide layer integrity testing device according to an embodiment of the present invention. Detailed Implementation

[0033] In wafer manufacturing, photolithography is a crucial process. It involves transferring a pattern from a photomask to photoresist, and then onto the wafer, thus completing the photolithography process. A single exposure is insufficient to pattern the entire wafer area; therefore, multiple exposures are required to form the pattern across the entire wafer. The area exposed in one exposure is called a shot, and a single wafer can contain dozens or even hundreds of shot areas.

[0034] An exposure zone typically covers an area comprising multiple chip regions arranged in an array, with dicing ridges separating adjacent chip regions. Test keys can be formed on these dicing ridges. Therefore, an exposure zone includes multiple test keys. Test keys are not actual device structures, but they are formed in the same manufacturing process as the devices in the chip regions. By measuring and testing these test keys, the process and performance of the devices in the chip regions can be monitored and controlled. After the wafer completes its chip fabrication process, subsequent processes such as dicing and packaging are performed.

[0035] In practical applications, the test key used for GOI testing within an exposure area is called the GOI test key. The GOI test key can be a portion of the device structure of a dedicated test key for wafer reliability testing. The GOI test key can include six device structures composed of transistors. To enable the connection between the transistors and external components, the GOI test key is equipped with corresponding pads for connecting the transistors to their respective ends, including drain pads, gate pads, and source pads.

[0036] Current GOI testing methods involve applying a voltage to the gate solder joint of a device structure used for GOI testing using a probe, and continuously increasing the voltage in increments, a process known as GOI VRAMP testing. While applying the voltage to the gate solder joint, the current within the gate solder joint is detected to determine if the output current density in the gate solder joint is greater than or equal to the breakdown current. If the output current density in the gate solder joint is greater than or equal to the breakdown current, the corresponding gate solder joint voltage is output. For each exposure area of ​​a wafer, a corresponding gate solder joint voltage is output, resulting in a plot for the entire wafer. This plot is then used to determine if any failure has occurred in each exposure area of ​​the wafer.

[0037] In this field, GOI failure modes include two types: one is Mode A, which is a failure mode in which the gate solder area current is greater than the breakdown current when the gate solder area voltage is the operating voltage; the other is Mode B, which is a failure mode in which the gate solder area current is greater than the breakdown current when the gate solder area voltage is 2.3 times the operating voltage.

[0038] The plot for a single wafer is a curve showing how the cumulative failure rate of all exposure areas in the wafer changes as the voltage applied to the gate bonding area increases. Figure 1 This is a plot chart corresponding to the wafer where the test bond is located, operating at a voltage of 3.3V. From Figure 1It can be seen that when a voltage of 7.59V (i.e., 2.3*3.3V) is applied to the gate solder area of ​​each exposure zone, the voltage of most exposure zones on the wafer is basically the same. Only two exposure zones in section 11 have voltages different from the other exposure zones. At this time, when judging whether a failure has occurred in each exposure zone of the wafer based on the plot, the exposure zone where the gate solder area voltage is greater than the working voltage but less than 2.3 times the working voltage can be directly identified (i.e., Figure 1 The two exposure areas in section 11 were identified as having experienced GOI failure.

[0039] The above-described scheme, which uses plot charts to determine whether failures have occurred in each exposure area of ​​a wafer, completes GOI testing for the entire wafer. However, this method is time-consuming, resource-intensive (e.g., testing equipment), and inefficient. In practical applications, it can only be used to test a small number of wafers with a limited sample size. When production lines encounter reliability issues requiring long-term monitoring of a large number of mass-produced wafers, the above scheme cannot meet the required test coverage and time demands. For example, testing 80 exposure areas per wafer would take approximately 180 minutes to complete the GOI testing for all 80 areas, which is time-consuming.

[0040] To address this issue, this invention provides a method for testing the integrity of the gate oxide layer. Using this method, failure mode data information of the GOI test bond in the first exposure area is first obtained. Then, voltage or current values ​​from the failure mode data information are applied to the gate solder area of ​​the GOI test bond to perform gate oxide layer integrity testing on the first exposure area. The entire gate oxide layer integrity testing process can be completed simply by applying a specific voltage or current value to the gate solder area of ​​the GOI test bond. There is no need to continuously increase the voltage of the gate solder area in the GOI test bond in a certain step, nor is it necessary to draw a plot. This significantly shortens the testing time required for gate oxide layer integrity testing, reduces the testing resources required, and improves testing efficiency.

[0041] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] This invention provides a method for testing the integrity of a gate oxide layer. Using this method, the integrity of the gate oxide layer in a first exposure field region of a first wafer can be tested.

[0043] In this embodiment, the first wafer can be any one of the wafers requiring gate oxide integrity testing, and the first exposure area can be any one of the exposure areas in the first wafer requiring gate oxide integrity testing. This embodiment describes gate oxide integrity testing performed on a first exposure area in a first wafer. Those skilled in the art can, based on the description in this embodiment, implement gate oxide integrity testing on any wafer requiring gate oxide integrity testing.

[0044] Specifically, refer to Figure 2 The method may include the following steps:

[0045] Step 21: Obtain the failure mode data information of the GOI test key in the first exposure area.

[0046] In specific implementation, the failure mode data information refers to the critical voltage and critical current values ​​of the first wafer under two failure modes. Specifically, the failure mode data information may include: voltage and current values ​​corresponding to the failure of the first exposure field area GOI. Specifically, the failure mode data information includes: information on the first current value corresponding to the gate solder area of ​​the GOI test bond when the voltage is a first voltage value; and information on the second current value corresponding to the gate solder area of ​​the GOI test bond when the voltage is a second voltage value; the first voltage value is the operating voltage value of the GOI test bond, and the second voltage value is 2.3 times the operating voltage value.

[0047] In other words, the failure mode data information includes four values ​​and two corresponding relationships: a first voltage value, a second voltage value, a first current value, and a second current value. The first voltage value corresponds to the first current value, representing the critical voltage and critical current values ​​for the first wafer when it is in failure mode A. The second voltage value corresponds to the second current value, representing the critical voltage and critical current values ​​for the first wafer when it is in failure mode B.

[0048] In practice, the current value in the failure mode data information can be obtained by performing GOI testing on a specific exposure area of ​​other wafers in the same batch or on a first wafer. The specific GOI testing method is not limited; for example, existing GOI testing methods can be used to obtain the critical voltage or current values ​​corresponding to different failure modes.

[0049] For example, for a wafer operating at 5V, it is possible to obtain in advance... Figure 3 The curves 31 showing the change of current value with voltage in the gate soldering area of ​​each exposure field of the wafer are shown. From this, the first current value and the second current value can be obtained. Then, the first current value and the second current value are used to perform GOI test on other wafers in the same batch.

[0050] Reference Figure 3 When a 5V operating voltage is applied to the gate solder area, the corresponding first current value is approximately 5E-11A. When a 2.3*5V operating voltage is applied to the gate solder area, the corresponding first current value is approximately 1E-5A. The first and second current values ​​are then used to perform GOI testing on the first wafer.

[0051] It should be noted that in actual implementation, the first current value and the second current value may be different when different devices are used. The curve of the current value of the gate welding area in the exposure area under test changing with the voltage should be adjusted and corrected in real time.

[0052] Step 22: Apply the voltage or current value from the failure mode data information to the gate end soldering area of ​​the GOI test key to perform gate oxide layer integrity test on the first exposure area.

[0053] In one embodiment of the present invention, a first voltage value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the first current value. Based on the detection result, it may be determined whether the first exposure area is a mode A failure. A second voltage value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the second current value. Based on the detection result, it may be determined whether the first exposure area is a mode B failure.

[0054] Specifically, the gate oxide integrity testing device has a probe through which a first voltage value can be applied to the gate terminal solder area of ​​the GOI test bond, while simultaneously detecting the current value at the gate terminal solder area of ​​the GOI test bond. If the current value at the gate terminal solder area of ​​the GOI test bond is greater than the first current value, it indicates that the GOI test bond gate terminal has been broken down, and Mode A failure has occurred in the exposure field area where the GOI test bond is located. If the current value at the gate terminal solder area of ​​the GOI test bond is less than or equal to the first current value, it indicates that the GOI test bond gate terminal has not been broken down, and Mode A failure has not occurred in the exposure field area where the GOI test bond is located.

[0055] When a second voltage value is applied to the gate solder area of ​​the GOI test key using a probe, the current value of the GOI test key gate solder area is simultaneously detected. If the current value of the GOI test key gate solder area is greater than the second current value, it indicates that the GOI test key gate has broken down, and Mode B failure has occurred in the exposure field area where the GOI test key is located. If the current value of the GOI test key gate solder area is less than or equal to the second current value, it indicates that the GOI test key gate has not broken down, and Mode B failure has not occurred in the exposure field area where the GOI test key is located.

[0056] In another embodiment of the present invention, a first current value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the voltage value of the gate end soldering area of ​​the GOI test key is less than the first voltage value. Based on the detection result, it may be determined whether the first exposure area is a mode A failure. A second current value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the voltage value of the gate end soldering area of ​​the GOI test key is greater than the second voltage value. Based on the detection result, it may be determined whether the first exposure area is a mode B failure.

[0057] Specifically, a first current value is applied to the gate soldering area of ​​the GOI test key using a probe, while simultaneously detecting the voltage value of the GOI test key gate soldering area. If the voltage value of the GOI test key gate soldering area is less than the first voltage value, it indicates that the GOI test key gate has broken down, and Mode A failure has occurred in the exposure field area where the GOI test key is located. If the voltage value of the GOI test key gate soldering area is greater than or equal to the first voltage value, it indicates that the GOI test key gate has not broken down, and Mode A failure has not occurred in the exposure field area where the GOI test key is located.

[0058] A second current value is applied to the gate solder area of ​​the GOI test key using a probe, while the voltage value of the GOI test key gate solder area is simultaneously detected. If the voltage value of the GOI test key gate solder area is less than the second voltage value, it indicates that the GOI test key gate is broken down, and Mode B failure occurs in the exposure area where the GOI test key is located. If the voltage value of the GOI test key gate solder area is greater than or equal to the second voltage value, it indicates that the GOI test key gate is not broken down, and Mode B failure does not occur in the exposure area where the GOI test key is located.

[0059] In another embodiment of the present invention, a first current value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the voltage value of the gate end soldering area of ​​the GOI test key is less than the first voltage value. Based on the detection result, it may be determined whether the first exposure area is a mode A failure. A second voltage value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the second current value. Based on the detection result, it may be determined whether the first exposure area is a mode B failure.

[0060] Specifically, while applying a first current value to the gate solder area of ​​the GOI test key using a probe, the voltage value of the GOI test key gate solder area is detected. If the voltage value of the GOI test key gate solder area is less than the first voltage value, it indicates that the GOI test key gate is broken down, and Mode A failure occurs in the exposure area where the GOI test key is located. If the voltage value of the GOI test key gate solder area is greater than or equal to the first voltage value, it indicates that the GOI test key gate is not broken down, and Mode A failure does not occur in the exposure area where the GOI test key is located.

[0061] When a second voltage value is applied to the gate solder area of ​​the GOI test key using a probe, the current value of the GOI test key gate solder area is simultaneously detected. If the current value of the GOI test key gate solder area is greater than the second current value, it indicates that the GOI test key gate has broken down, and Mode B failure has occurred in the exposure field area where the GOI test key is located. If the current value of the GOI test key gate solder area is less than or equal to the second current value, it indicates that the GOI test key gate has not broken down, and Mode B failure has not occurred in the exposure field area where the GOI test key is located.

[0062] In another embodiment of the present invention, a first voltage value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the first current value. Based on the detection result, it may be determined whether the first exposure area is a mode A failure. A second current value may be applied to the gate end soldering area of ​​the GOI test key, and it may be detected whether the voltage value of the gate end soldering area of ​​the GOI test key is greater than the second voltage value. Based on the detection result, it may be determined whether the first exposure area is a mode B failure.

[0063] Specifically, a first voltage value is applied to the gate soldering area of ​​the GOI test key using this probe, while simultaneously detecting the current value at the gate soldering area. If the current value at the gate soldering area is greater than the first current value, it indicates that the GOI test key gate has broken down, and Mode A failure has occurred in the exposure area where the GOI test key is located. If the current value at the gate soldering area is less than or equal to the first current value, it indicates that the GOI test key gate has not broken down, and Mode A failure has not occurred in the exposure area where the GOI test key is located.

[0064] A second current value is applied to the gate solder area of ​​the GOI test key using a probe, while the voltage value of the GOI test key gate solder area is simultaneously detected. If the voltage value of the GOI test key gate solder area is less than the second voltage value, it indicates that the GOI test key gate is broken down, and Mode B failure occurs in the exposure area where the GOI test key is located. If the voltage value of the GOI test key gate solder area is greater than or equal to the second voltage value, it indicates that the GOI test key gate is not broken down, and Mode B failure does not occur in the exposure area where the GOI test key is located.

[0065] It should be noted that the first current value and the second current value are themselves critical values. When the current value of the gate end soldering area of ​​the GOI test key is equal to the first current value or the second current value, it can be determined that the exposure field area has failed. Alternatively, when the current value of the gate end soldering area of ​​the GOI test key is equal to the first current value or the second current value, it can be determined that the exposure field area has not failed. Whether to determine whether the exposure field area has failed can be set by those skilled in the art according to the actual situation, and no restrictions are imposed here.

[0066] Similarly, the first voltage value and the second voltage value are also critical values. When the current value of the gate end soldering area of ​​the GOI test key is equal to the first current value or the second current value, it can be determined that the exposure field area has failed. Alternatively, when the current value of the gate end soldering area of ​​the GOI test key is equal to the first current value or the second current value, it can be determined that the exposure field area has not failed. Whether to determine whether the exposure field area has failed can be set by those skilled in the art according to the actual situation, and no restrictions are imposed here.

[0067] In practice, the GOI test key includes six device structures. When performing gate oxide integrity testing on the first exposure area, the gate oxide integrity test needs to be performed on each device structure in the GOI test key separately. If any device structure experiences GOI failure, the first exposure area is considered to have experienced GOI failure.

[0068] In practical applications, wafers typically need to undergo an acceptance test (WAT) after they are manufactured.

[0069] WAT testing is used to ensure that if errors occur in the early stages of wafer production that cause the die to malfunction, WAT testing can detect these errors in advance, thus saving costs. WAT testing can also infer the functionality of components in nearby dies. In short, WAT testing is a mandatory test for every wafer.

[0070] In practical implementation, to further conserve testing resources and improve testing efficiency, the gate oxide integrity test can be made compatible with existing WAT testing. Any platform capable of WAT testing can be used to complete the gate oxide integrity test. In this way, the results of the gate oxide integrity test can be obtained quickly through the WAT testing method, thereby identifying problematic wafers with gate oxide integrity failures among mass-produced wafers.

[0071] In practical implementation, the area covered by the first exposure field can be multiple rows of chip areas. In this case, the test keys in the first exposure field are the test keys between adjacent chip areas in the same row. Alternatively, the area covered by the first exposure field can be multiple columns of chip areas. In this case, the test keys in the first exposure field are the test keys between adjacent chip areas in the same column. Based on the arrangement of the test keys in the first exposure field, the gate oxide layer integrity test of the first exposure field can be completed using WAT test resources during or after the WAT test of the first wafer.

[0072] For example, when the test bonds in the first exposure area are arranged in rows, this is the same as the arrangement of the test bonds after the WAT test. In this case, the gate oxide integrity test of the first exposure area can be completed during the WAT test of the first wafer. When the test bonds in the first exposure area are arranged in columns, this is different from the arrangement of the test bonds after the WAT test. In this case, the gate oxide integrity test of the first exposure area can be completed after the WAT test of the first wafer.

[0073] Whether the gate oxide integrity test of the first exposure area is completed during or after the WAT test, and regardless of whether an exposure area map of the first exposure area is obtained, the two-end testing method can be used to test the gate oxide integrity of the first exposure area using WAT test resources. The two-end testing method involves leaving the source and drain solder areas of the GOI test bond suspended, while grounding the substrate solder area, and performing the gate oxide integrity test at the gate solder area of ​​the GOI test bond.

[0074] To utilize Figure 3 Taking the GOI test on the first wafer as an example after determining the first and second current values ​​using curve 31, when performing gate oxide layer integrity testing on an exposure area of ​​the first wafer using WAT testing resources, the source and drain bonding areas of the GOI test bond can be left floating, while the substrate bonding area is grounded. Two voltages are applied to the gate bonding area: one at the operating voltage of 5V and the other at 2.3 times the operating voltage, i.e., 2.3 * 5V = 11.5V. After each voltage application, the current value Ig of the gate bonding area is read.

[0075] When a 5V voltage is applied to the gate solder area, if the current value Ig in the gate solder area is greater than 5E-11A, it indicates that GOI mode A failure has occurred in the first exposure field region. When an 11.5V voltage is applied to the gate solder area, if the current value Ig in the gate solder area is greater than 1E-5A, it indicates that GOI mode B failure has occurred in the first exposure field region. The GOI test results for the first wafer can then be obtained, such as... Figure 3 As shown. In Figure 3 In the exposure area 32, GOI mode A failure occurred; in the exposure area 33, GOI mode B failure occurred; and no GOI failure occurred in the other exposure areas.

[0076] Using the above method to test the gate oxide layer integrity of wafers, taking testing 80 exposure areas per wafer as an example, the total testing time to complete the testing of GOI test bonds in 80 exposure areas is approximately 5 minutes, which is time-consuming. Compared with existing GOI testing methods, the testing time is reduced by 97.2%.

[0077] By adopting the solution of the present invention, the time required for GOI testing is greatly shortened and the testing resources are less. In the event of a sudden event or when it is necessary to identify whether GOI is invalid on a large number of mass-produced wafers, the testing time can be greatly shortened, the testing burden can be reduced, the wafer fabrication efficiency and the machine utilization efficiency can be improved, thereby reducing production costs and optimizing the overall quality monitoring system of the factory.

[0078] To enable those skilled in the art to better understand and implement the present invention, the apparatus corresponding to the above method is described in detail below.

[0079] Reference Figure 4 This invention also provides a testing device 40 for the integrity of a gate oxide layer, which may include: an acquisition unit 41 and a testing unit 42. Wherein:

[0080] The acquisition unit 41 is adapted to acquire failure mode data information of the GOI test key in the first exposure area; the failure mode data information includes: information on the first current value corresponding to the gate end solder area of ​​the GOI test key when the voltage is a first voltage value; and information on the second current value corresponding to the gate end solder area of ​​the GOI test key when the voltage is a second voltage value; the first voltage value is the operating voltage value of the GOI test key, and the second voltage value is 2.3 times the operating voltage value;

[0081] The test unit 42 is adapted to apply the voltage or current value in the failure mode data information to the gate end solder area of ​​the GOI test key to perform gate oxide layer integrity test on the first exposure area.

[0082] This invention also provides a WAT ​​testing device, which may include the gate oxide integrity testing device 40 described above.

[0083] The acquisition unit 41 and the testing unit 42 can be implemented with reference to the above description of steps 21 and 22, and will not be repeated here.

[0084] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for testing the integrity of a gate oxide layer, used to test the integrity of the gate oxide layer in a first exposure field region of a first wafer, characterized in that, include: Obtain failure mode data information of the GOI test key in the first exposure area; The failure mode data information includes: information on the first current value corresponding to the gate solder area of ​​the GOI test key when the voltage is a first voltage value; and information on the second current value corresponding to the gate solder area of ​​the GOI test key when the voltage is a second voltage value; the first voltage value is the operating voltage value of the GOI test key, and the second voltage value is 2.3 times the operating voltage value; The voltage or current value from the failure mode data information is applied to the gate end solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area.

2. The method for testing the integrity of the gate oxide layer as described in claim 1, characterized in that, Applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes: A first voltage value is applied to the gate terminal soldering area of ​​the GOI test key, and the current value of the gate terminal soldering area of ​​the GOI test key is detected to be greater than the first current value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure. A second voltage value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the second current value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

3. The method for testing the integrity of the gate oxide layer as described in claim 1, characterized in that, Applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes: A first current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is less than the first voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure. A second current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is greater than the second voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

4. The method for testing the integrity of the gate oxide layer as described in claim 1, characterized in that, Applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes: A first current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is less than the first voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure. A second voltage value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the current value of the gate end soldering area of ​​the GOI test key is greater than the second current value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

5. The method for testing the integrity of the gate oxide layer as described in claim 1, characterized in that, Applying the voltage or current value from the failure mode data information to the gate terminal solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area includes: A first voltage value is applied to the gate terminal soldering area of ​​the GOI test key, and the current value of the gate terminal soldering area of ​​the GOI test key is detected to be greater than the first current value. Based on the detection result, it is determined whether the first exposure field area is a mode A failure. A second current value is applied to the gate end soldering area of ​​the GOI test key, and it is detected whether the voltage value of the gate end soldering area of ​​the GOI test key is greater than the second voltage value. Based on the detection result, it is determined whether the first exposure field area is a mode B failure.

6. The method for testing the integrity of the gate oxide layer as described in claim 1, characterized in that, During the WAT test on the first wafer, the integrity test of the gate oxide layer in the first exposure area is completed using WAT test resources.

7. The method for testing the integrity of the gate oxide layer as described in claim 1, characterized in that, After performing the WAT test on the first wafer, the integrity test of the gate oxide layer in the first exposure area is completed using the WAT test resources.

8. The method for testing the integrity of the gate oxide layer as described in claim 6 or 7, characterized in that, The process of utilizing WAT testing resources to complete the gate oxide layer integrity test in the first exposure area includes: The source and drain solder areas of the GOI test bond are left suspended, while the substrate solder area is grounded. The gate oxide integrity test is then performed at the gate solder area of ​​the GOI test bond.

9. The method for testing the integrity of the gate oxide layer as described in claim 1, characterized in that, The GOI test bond includes six device structures. When performing gate oxide integrity testing on the first exposure area, gate oxide integrity testing is performed on each device structure in the GOI test bond.

10. A testing apparatus for the integrity of a gate oxide layer, characterized in that, include: The acquisition unit is adapted to acquire failure mode data information of the GOI test key in the first exposure area; The failure mode data information includes: information on the first current value corresponding to the gate solder area of ​​the GOI test key when the voltage is a first voltage value; and information on the second current value corresponding to the gate solder area of ​​the GOI test key when the voltage is a second voltage value; the first voltage value is the operating voltage value of the GOI test key, and the second voltage value is 2.3 times the operating voltage value; The test unit is adapted to apply the voltage or current value from the failure mode data information to the gate end solder area of ​​the GOI test key to perform gate oxide layer integrity testing on the first exposure area.

11. A WAT testing apparatus, comprising the gate oxide integrity testing apparatus of claim 10.

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