Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate, a first buffer structure, a second buffer structure and a conductive structure, the substrate comprising a first surface and a second surface opposite to each other; the first buffer structure is located in the substrate and extends along a first direction, the first direction being a direction from the first surface to the second surface; the second buffer structure is located on a part of the sidewall of the first buffer structure and extends along a second direction, the second direction intersecting with the first direction; the conductive structure is located in the first buffer structure and extends along the first direction. The semiconductor structure provided by the present disclosure improves the stress release capability and improves the problem of stress concentration in the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the development of semiconductors, Moore's Law is reaching its limit. 2.5D and 3D integration technologies have gradually become effective means to continue Moore's Law and improve the performance and functional density of electronic systems. TSV (Through Silicon Via) conductive vias are widely used in 2.5D and 3D integration technologies. The TSV process forms metal pillars in the wafer and is equipped with metal bumps to achieve direct three-dimensional interconnection between wafers (chips) or between chips and substrates, which can make up for the limitations of two-dimensional wiring of traditional semiconductor chips. Compared with traditional stacking technologies such as bonding technology, this interconnection method has the advantages of high stacking density in the three-dimensional direction and small external dimensions after packaging, thereby greatly improving the speed of the chip and reducing power consumption. Therefore, TSV technology has been widely regarded as the fourth generation of packaging technology after bonding, tape bonding and flip chip, and will gradually become the mainstream technology in the field of high-density packaging.

[0003] However, the TSV front-end interconnection process in the existing process has the following disadvantages: in the current isotropic dry etching process of TSV, a convex part will appear at the edge of the TSV hole. When the insulating layer, seed layer and metal filling are made, a multi-layer structure "stress concentration" area will be formed, which makes it easy to delaminate or crack between the insulating layer and the substrate, seriously affecting the quality and reliability of TSV. The current process and structure cannot eliminate the influence of the stress concentration area.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor structure and a method for forming the semiconductor structure, wherein the semiconductor structure has improved stress release capability and improves the problem of stress concentration in the semiconductor structure.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of an embodiment of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising:

[0008] A substrate including a first surface and a second surface opposite to each other;

[0009] A first buffer structure is located in the substrate and extends along a first direction, where the first direction is a direction from the first surface to the second surface;

[0010] a second buffer structure, located on a portion of the sidewall of the first buffer structure and extending along a second direction, wherein the second direction intersects the first direction; and

[0011] The conductive structure is located in the first buffer structure and extends along the first direction.

[0012] In an exemplary embodiment of the present disclosure, the second buffer structure is located on an end of the first buffer structure close to the first surface.

[0013] In an exemplary embodiment of the present disclosure, the second buffer structure is an annular protrusion in the circumferential direction of the first buffer structure.

[0014] In an exemplary embodiment of the present disclosure, the semiconductor structure includes a plurality of second buffer structures, and the plurality of second buffer structures are uniformly distributed in the first direction.

[0015] In an exemplary embodiment of the present disclosure, the width of the second buffer structure in the first direction first gradually increases and then gradually decreases along the second direction.

[0016] In an exemplary embodiment of the present disclosure, the first buffer structure and the second buffer structure are an integrated structure.

[0017] In an exemplary embodiment of the present disclosure, the first buffer structure and the second buffer structure are made of different materials.

[0018] In an exemplary embodiment of the present disclosure, a protrusion is provided on a side wall of the first buffer structure, the protrusion has a first surface and a second surface, the first surface and the second surface intersect, and the second buffer structure extends along the second direction on the first surface.

[0019] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

[0020] A blocking structure is located on the first surface of the protrusion.

[0021] In an exemplary embodiment of the present disclosure, the blocking structure is located on both sides of the second buffer structure.

[0022] In an exemplary embodiment of the present disclosure, the blocking structure is annular in a circumferential direction of the first buffer structure.

[0023] In an exemplary embodiment of the present disclosure, two ends of the conductive structure are exposed from the first surface and the second surface respectively.

[0024] According to another aspect of an embodiment of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0025] Providing a substrate, the substrate comprising a first side and a second side opposite to each other;

[0026] forming a first recessed portion on the first surface of the substrate along a first direction, wherein the first direction is a direction from the first surface to the second surface;

[0027] forming a second recessed portion on a side wall of the first recessed portion along a second direction, wherein the second direction intersects the first direction;

[0028] forming a second buffer structure in the second recessed portion, and forming a first buffer structure in the first recessed portion;

[0029] A conductive structure is formed in the first buffer structure, and the conductive structure extends in the first direction.

[0030] In an exemplary embodiment of the present disclosure, a second recessed portion is formed on a side wall of the first recessed portion along a second direction, comprising:

[0031] forming a blocking structure on a portion of the sidewall of the first recessed portion;

[0032] Part of the sidewall of the first recess is etched using the blocking structure as a mask to form a second recess.

[0033] In an exemplary embodiment of the present disclosure, a blocking structure is formed on a portion of the sidewall of the first recessed portion, comprising:

[0034] Ion doping is performed on a portion of the sidewall of the first recessed portion, and the ion doped region forms a blocking structure.

[0035] In an exemplary embodiment of the present disclosure, a plurality of blocking structures are formed on a portion of the sidewalls of the first recessed portion, and the sidewalls of the first recessed portion between two adjacent blocking structures are laterally etched along the second direction to form the second recessed portion.

[0036] In an exemplary embodiment of the present disclosure, the second recessed portion is filled with a second buffer material to form a second buffer structure; and the first recessed portion is filled with a first buffer material to form the first buffer structure.

[0037] In an exemplary embodiment of the present disclosure, the first buffer structure is etched along the first direction to form a first buffer structure having a first trench, and the conductive structure is formed in the first trench.

[0038] In an exemplary embodiment of the present disclosure, after forming the first buffer structure and before forming the conductive structure, the forming method further includes:

[0039] Filling a barrier material in the first trench to form a barrier initial layer;

[0040] The barrier initial layer is etched along the first direction to form a barrier layer having a second groove; and the conductive structure is formed in the second groove.

[0041] In an exemplary embodiment of the present disclosure, the first buffer structure and the second buffer structure are made of the same material; the first buffer structure is formed in the first recessed portion, and the second buffer structure is formed in the second recessed portion through a same filling process.

[0042] In an exemplary embodiment of the present disclosure, a conductive structure is formed in the first buffer structure;

[0043] forming a conductive initial structure in the first buffer structure;

[0044] Chemical mechanical polishing is performed on the second surface to form a conductive structure with two ends exposed from the first surface and the second surface respectively.

[0045] In the semiconductor structure provided by the present disclosure, the first buffer structure in the contact structure covers the side wall of the conductive structure and can serve as a stress buffer layer to release the stress concentration area of ​​the TSV; the second buffer structure is located on the outside of the first buffer structure and can further release the stress of the TSV, thereby alleviating the problem of stress concentration in the TSV in the semiconductor structure.

[0046] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0048] Figure 1 A schematic diagram of a semiconductor structure provided for an embodiment of the present disclosure;

[0049] Figure 2 A flow chart of a method for forming a semiconductor structure provided for one embodiment of the present disclosure;

[0050] Figure 3-Figure 14 A diagram of a process for forming a semiconductor structure provided for one embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concept of the example embodiments to those skilled in the art.

[0052] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0053] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. The terms "one", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusion, and mean that there may be additional components in addition to the listed components, etc.; the terms "first", "second", etc. are used only as labels and are not quantitative restrictions on their objects.

[0054] After TSV is fabricated, during the wafer back thinning process, the stress at the bottom of the TSV is the greatest, forming a stress concentration area, which makes it easy for the bottom of the TSV to be delaminated or cracked, seriously affecting the quality and reliability of the TSV.

[0055] In view of the above technical problems, the embodiments of the present disclosure first provide a semiconductor structure, such as Figure 1 As shown, the semiconductor structure includes: a substrate 100, a first buffer structure 210, a second buffer structure 220 and a conductive structure 400, wherein the first buffer structure 210, the second buffer structure 220 and the conductive structure 400 form a contact structure.

[0056] The substrate 100 includes a first surface 101 and a second surface 102 facing each other. The first surface 101 is provided with a first recessed portion 110 extending along a first direction Y. The first buffer structure 210 is located in the substrate 100 and extends along the first direction Y. The first direction Y is a direction from the first surface 101 to the second surface 102. The second buffer structure 220 is located on a partial side wall of the first buffer structure 210 and extends along a second direction X. The second direction X intersects with the first direction Y. The conductive structure 400 is located in the first buffer structure 210 and extends along the first direction Y.

[0057] In the semiconductor structure provided by the present disclosure, the first buffer structure 210 in the contact structure covers the side wall of the conductive structure 400 and can serve as a stress buffer layer to release the stress concentration area of ​​the TSV; the second buffer structure 220 is located on the outside of the first buffer structure 210 and can further release the stress of the TSV, thereby alleviating the problem of stress concentration in the TSV in the semiconductor structure.

[0058] Specifically, Figure 4-Figure 8 As shown, a first recessed portion 110 is provided on the first surface 101 of the substrate 100, and a second recessed portion 140 extending along the second direction X is provided on the sidewall of the first recessed portion 110, and the second recessed portion 140 is located at one end of the first recessed portion 110 close to the first surface 101. The second buffer structure 220 is located in the second recessed portion 140 and connected to the second buffer structure 220; Figure 8 As shown, a third recessed portion 210 is provided on one side of the first buffer structure 210 away from the inner wall, as shown in FIG. Fig.12 As shown, the conductive structure 400 is located in the third recessed portion 210. The second direction X is a direction pointing to the periphery of the sidewall in the circumferential direction of the first buffer structure 210, and the plane angle between the second direction X and the first direction Y can be a right angle or an acute angle.

[0059] For example, the substrate 100 may be a wafer, and the wafer has a first surface 101 and a second surface 102 opposite to each other. The material of the wafer may be, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or a combination thereof, and the wafer may also be a multilayer structure composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeO), etc.; the wafer may also include an epitaxial layer for forming a drift region of a split-gate trench power device. Taking an N-type MOSFET device as an example, the doping type of the wafer and the epitaxial layer are both N-type.

[0060] In addition, the material of the substrate 100 can be formed of other inorganic materials or organic materials. The inorganic material can be, for example, a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material of various metals or their alloys such as stainless steel, aluminum, nickel, etc. The organic material can be, for example, polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. The material of the substrate 100 can also be a flexible material. For example, polyimide (PI).

[0061] In one embodiment of the present disclosure, Figure 1 As shown, the first recessed portion 110 does not penetrate the wafer in the thickness direction of the wafer.

[0062] Among them, a first recessed portion 110 extending toward the second surface 102 can be formed on the first surface 101 of the wafer by the Bosch process. The Bosch process realizes etching and sidewall passivation by alternately switching etching gas and passivation gas, wherein the etching gas is SF6 and the passivation gas is C4F8. C4F8 can form a fluorinated carbon polymer in plasma, which is deposited on the silicon surface to prevent the reaction between fluoride ions and silicon; etching and passivation are switched every 5s to 10s, and the silicon surface that has just been etched is passivated after a short period of isotropic etching. Due to the physical sputtering bombardment of ions in the depth direction, the passivation film can be retained, so that the next cycle of etching will not cause lateral etching. Through this periodic "etching-passivation-etching", etching is only carried out along the depth direction, thereby meeting the requirements of deeper TSV.

[0063] In the Bosch process, due to the mutual conversion between etching and passivation, and each etching step is isotropic, the Bosch process will cause the following Figure 3 The scalloping effect of the etched sidewall surface is shown, that is, a plurality of spaced protrusion structures 120 are formed on the sidewall of the first recessed portion 110 in the depth direction. The cross section of the formed protrusion structure 120 is a fan-shaped structure (scallop).

[0064] In one embodiment of the present disclosure, Figure 8As shown, since a plurality of spaced-apart protrusion structures 120 are formed on the sidewall of the first recessed portion 110 in the depth direction, after the first buffer structure 210 is formed in the first recessed portion 110, a protrusion 2110 is provided on the sidewall of the first buffer structure 210, and the protrusion 2110 has a first surface 2111 and a second surface 2112, and the first surface 2111 and the second surface 2112 intersect each other, and the second buffer structure 220 extends along the second direction X on the first surface 2111.

[0065] Among them, the shape of the protrusion 2110 matches the shape of the recessed portion formed between the multiple protrusion structures 120 on the side wall of the first recessed portion 110, and the cross-section of the protrusion 2110 in the first direction Y is triangular or circular, or other irregular shapes, etc.; the shapes and sizes of the multiple protrusions 2110 may be the same or different, and the present disclosure does not impose any restrictions on this.

[0066] In one embodiment of the present disclosure, the semiconductor structure further includes a blocking structure 130. Figure 1 As shown, the blocking structure 130 is located on the second surface 2112 of the protrusion 2110 , covers a portion of the sidewall of the first buffer layer 210 , and the blocking structure 130 is disposed adjacent to the second buffer structure 220 .

[0067] Specifically, Figure 4 As shown, after the first recessed portion 110 is formed on the substrate 100, ion doping can be added to the protruding structure 120 at the opening end of the first recessed portion 110, thereby changing the etching property of the upper layer of the protruding structure 120 toward the first surface 101, so that the modified surface portion of the protruding structure 120 forms a blocking structure 130, that is, the formed blocking structure 130 is the ion implantation region of the protruding structure 120.

[0068] The blocking structure 130 formed by particle doping has a different selective etching ratio from the substrate 100. Since the blocking structure 130 has a different selective etching ratio from the substrate 100, the blocking structure 130 may be used as a mask to etch a portion of the sidewall of the first recessed portion 110. Figure 5 As shown, a second recessed portion 140 recessed along the second direction X into the side wall of the first recessed portion 110 is formed.

[0069] Of course, a mask layer can also be directly formed on the surface of the protruding structure 120 by deposition or other processes, and the mask layer serves as the blocking structure 130. Part of the sidewall of the first recessed portion is etched through the mask layer to form a second recessed portion 140 recessed along the second direction X into the sidewall of the first recessed portion 110.

[0070] In one embodiment of the present disclosure, after the second recessed portion 140 is formed on the sidewall of the first recessed portion 100, the second buffer structure 220 can be disposed in the second recessed portion 140 through a filling process. By filling the second buffer structure 220 in the second recessed portion 140, the second buffer structure 220 completely occupies the second recessed portion 140, thereby avoiding a gap between the second buffer structure 220 and the substrate 100, thereby further providing the effect of releasing stress of the buffer structure and improving the product yield of the semiconductor structure.

[0071] Among them, Figure 1 As shown, the width of the second buffer structure 220 in the first direction Y first gradually increases and then gradually decreases along the second direction X. For example, the cross-section of the second buffer structure 220 in the plane where the first direction Y and the second direction X are located is elliptical; of course, it can also be circular or irregular, etc., and the present disclosure does not limit this.

[0072] For example, Figure 1 As shown, multiple second buffer structures 220 are provided. For example, two, three or more second buffer structures 220 are provided; of course, only one second buffer structure 220 may be provided, and the present disclosure does not limit this. By providing multiple second buffer structures 220, the stress release of the buffer structure can be further improved, and stress concentration in the contact structure can be further avoided; however, providing a large number of second buffer structures 220 will increase the process difficulty, increase the manufacturing cost of the semiconductor structure, and reduce the manufacturing efficiency.

[0073] Among them, when the first recessed portion 110 is formed on the substrate 100 by TVS, the formed protruding structure 120 is annular on the side wall of the first recessed portion 110, and then the blocking structure 130 formed by ion doping is also annular. In the first direction Y, the blocking structure 130 is located on both sides of the second buffer structure 220, and then the second recessed portion 140 formed by the blocking structure 130 as a mask is also annular, so that the second buffer structure 220 filled in the second recessed portion 140 is also annular. The second buffer structure 220 is annular, and stress can be released through the second buffer structure 220 in the circumferential direction of the contact structure, and the stress release is more uniform, thereby further reducing the problem of stress concentration in the contact structure.

[0074] In one embodiment of the present disclosure, Figure 1As shown, the multiple second buffer structures 220 are evenly distributed in the first direction Y, that is, the gaps between the connected second buffer structures 220 are the same size. By making the multiple second buffer structures 220 evenly distributed in the first direction Y, the uniformity of stress release can be improved in the first direction Y, thereby further improving the effect of stress release on the contact structure. Of course, some of the multiple second buffer structures 220 can be evenly distributed in the first direction Y, and some can be unevenly distributed in the first direction Y; or, all of the multiple second buffer structures 220 can be unevenly distributed in the first direction Y, and the present disclosure does not limit this.

[0075] In one embodiment of the present disclosure, the plurality of second buffer structures 220 are symmetrically distributed. By making the plurality of second buffer structures 220 symmetrically distributed, the uniformity of stress release can be improved, thereby further improving the effect of stress release on the contact structure. Of course, the plurality of second buffer structures 220 can also be partially symmetrically distributed and partially asymmetrically distributed; or, the plurality of second buffer structures 220 can be all asymmetrically distributed, and the present disclosure does not limit this.

[0076] Specifically, Figure 1 As shown, the plurality of second buffer structures 220 are located on one end of the side wall of the first buffer structure 210 close to the first surface 101 in the first direction Y. Locating the plurality of second buffer structures 220 on one end of the side wall of the first buffer structure 210 in the first direction Y can largely alleviate the stress concentration of the contact structure at the end, thereby ensuring the stress release effect of the contact structure at the end.

[0077] Of course, the present disclosure does not limit the fact that multiple second buffer structures 220 are located on one end of the side wall of the first buffer structure 210 close to the second surface 102 in the first direction Y, or multiple second buffer structures 220 are evenly located on the side wall of the first buffer structure 210 in the first direction Y, or multiple second buffer structures 220 are arbitrarily distributed on the side wall of the first buffer structure 210 in the first direction Y. By locating the second buffer structure 220 on the outside of the first buffer structure 210, the stress of the TSV can be further released, thereby alleviating the problem of stress concentration in the TSV in the semiconductor structure.

[0078] The material of the first buffer structure 210 is oxide, such as silicon oxide, silicon oxynitride, and silicon nitride; the material of the second buffer structure 220 is oxide, such as silicon oxide, silicon oxynitride, and silicon nitride.

[0079] Among them, the materials of the first buffer structure 210 and the second buffer structure 220 can be the same or different. The same materials of the first buffer structure 210 and the second buffer structure 220 can reduce the manufacturing cost of the semiconductor structure. The first buffer structure 210 and the second buffer structure 220 can be an integrated structure, which improves the structural stability of the first buffer structure 210 and the second buffer structure 220.

[0080] Specifically, Figure 1 As shown, the contact structure further includes a barrier layer 310. The barrier layer 310 is located between the conductive structure 400 and the first buffer structure 210. The material of the barrier layer 310 may be, for example, tantalum (Ta), titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), neodymium (Nd), or a combination of the above materials and compounds thereof.

[0081] The material of the conductive structure 400 may be, for example, metal, conductive metal oxide, conductive polymer, conductive composite material or a combination thereof. The metal may be platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese or a combination thereof; the conductive metal oxide may be InO2, SnO2, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO) or a combination thereof; the conductive polymer may be polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene) / polystyrene sulfonic acid (PEDOT / PSS) or a combination thereof; the conductive composite material may be a conductive composite material dispersed with carbon black, graphite powder, metal particles, etc.

[0082] The semiconductor structure may include multiple contact structures, which may be distributed in an array on the substrate, and the multiple contact structures may be completely identical or partially identical and partially different. The number of the multiple contact structures and the specific distribution method on the substrate may be set as required, and the present disclosure does not limit this.

[0083] In one embodiment of the present disclosure, Fig.14 As shown, the first recessed portion 110 penetrates the substrate 100 in the first direction Y. Fig.13As shown, the semiconductor structure can be thinned from the second surface 102 of the substrate as needed, for example, by mechanical chemical polishing (CMP) to achieve BVR (Backside Via Reveal), forming a first recessed portion 110 that penetrates the substrate 100, so that the two ends of the conductive structure 400 are exposed from the first surface 101 and the second surface 102, respectively. During the thinning process, the first surface 101 is located at the bottom, and since the second buffer structure 220 is located at one end of the first recessed portion 110 close to the first surface 101, the stress of the end of the TSV close to the first surface 101 can be further released, thereby alleviating the problem of stress concentration at the end of the TSV close to the first surface 101 in the semiconductor structure during the thinning process.

[0084] The embodiments of the present disclosure also provide a method for forming a semiconductor structure, such as Figure 2 As shown, the forming method includes:

[0085] Step S100, providing a substrate, wherein the substrate comprises a first surface and a second surface opposite to each other;

[0086] Step S200, forming a first recessed portion extending along a first direction on the first surface of the substrate, wherein the first direction is from the first surface to the second surface;

[0087] Step S300, forming a second recessed portion on a side wall of the first recessed portion along a second direction, wherein the second direction intersects the first direction;

[0088] Step S400, forming a second buffer structure in the second recessed portion, and forming a first buffer structure in the first recessed portion;

[0089] Step S500: forming a conductive structure in the first buffer structure, wherein the conductive structure extends in a first direction.

[0090] The present invention provides a method for forming a semiconductor structure, which forms a first recessed portion extending toward a second surface on a first surface of a substrate, and then forms a second recessed portion formed along a second direction on a portion of a side wall of the first recessed portion; forms a first buffer structure in the first recessed portion, forms a second buffer structure in the second recessed portion, and finally forms a conductive structure in the first buffer structure. After the conductive structure is formed, the first buffer structure and the second buffer structure can be used as stress buffer layers, thereby releasing stress and alleviating the problem of stress concentration in the semiconductor structure.

[0091] Next, each step in the method for forming a semiconductor structure provided by the present disclosure will be described in detail.

[0092] In step S100 , a substrate is provided, wherein the substrate includes a first surface and a second surface opposite to each other.

[0093] Specifically, Figure 3 As shown, a substrate 100 is provided. The substrate 100 may be, for example, a wafer. The wafer includes a first surface 101 and a second surface 102 opposite to each other. The material of the wafer may be: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or a combination thereof. The wafer may also be a multilayer structure composed of these semiconductor materials, or may be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeO). The wafer may also include an epitaxial layer for forming a drift region of a split-gate trench power device. Taking an N-type MOSFET device as an example, the doping types of the wafer and the epitaxial layer are both N-type.

[0094] In addition, the material of the substrate can be formed of other inorganic materials or organic materials. The inorganic material can be, for example, a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, or various metals or their alloys. The organic material can be, for example, polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. The material of the substrate 100 can also be a flexible material. For example, polyimide (PI).

[0095] In step S200 , a first recessed portion extending along a first direction is formed on a first surface of the substrate, where the first direction is from the first surface to the second surface.

[0096] In one embodiment of the present disclosure, Figure 3 As shown, the first recessed portion 110 does not penetrate the substrate 100 in the thickness direction of the substrate 100 .

[0097] Among them, a first recessed portion 110 extending toward the second surface 102 can be formed on the first surface 101 of the wafer by the Bosch process. The Bosch process realizes etching and sidewall passivation by alternately switching etching gas and passivation gas, wherein the etching gas is SF6 and the passivation gas is C4F8. C4F8 can form a fluorinated carbon polymer in plasma, which is deposited on the silicon surface to prevent the reaction between fluoride ions and silicon; etching and passivation are switched every 5s to 10s, and the silicon surface that has just been etched is passivated after a short period of isotropic etching. Due to the physical sputtering bombardment of ions in the depth direction, the passivation film can be retained, so that the next cycle of etching will not cause lateral etching. Through this periodic "etching-passivation-etching", etching is only carried out along the depth direction, thereby meeting the requirements of deeper TSV.

[0098] In the Bosch process, due to the mutual conversion between etching and passivation, and each etching step is isotropic, the Bosch process will cause the following Figure 3 The scalloping effect of the etched sidewall surface is shown, that is, a plurality of spaced protrusion structures 120 are formed on the sidewall of the first recessed portion 110 in the depth direction. The cross section of the formed protrusion structure 120 is a fan-shaped structure (scallop).

[0099] For example, a mask structure may be first formed on the first surface 101 of the substrate, wherein an opening is formed on the mask structure, and the substrate is etched for the first time through the opening to form a groove, for example, using etching gas SF6, and then a passivation layer is formed in the formed groove using passivation gas C4F8 to protect the sidewalls of the groove; then, the bottom of the groove is etched and passivated for the second time through the opening; after the groove is formed by the second etching process, a protruding structure 120 is formed at the connection with the groove formed by the first etching process; the above steps are repeated to achieve alternating protection of the sidewalls of the groove and etching, until a first recessed portion penetrating the wafer is formed; and a number of protruding structures 120 corresponding to the number of etching processes are formed on the sidewalls of the first recessed portion.

[0100] A plurality of first recesses 110 may be formed on the semiconductor structure, and the plurality of first recesses 110 may be distributed in an array on the substrate 100. The number of the plurality of first recesses 110 and the specific distribution on the substrate 100 may be set as required, and the present disclosure does not limit this.

[0101] In step S300 , a second recessed portion is formed on a sidewall of the first recessed portion along a second direction, where the second direction intersects the first direction.

[0102] Specifically, Figure 3 As shown in FIG. 1 , the protruding structure 120 on the first recessed portion formed by TSV has a fan-shaped cross-section. Figure 4 As shown, after the first recessed portion 110 is formed on the substrate 100, an additional ion doping can be performed to dope the protruding structure 120 at an open end of the first recessed portion 110, thereby changing the etching property of the upper layer of the protruding structure 120 toward the first surface 101, so that the modified surface portion of the protruding structure 120 forms a blocking structure 130, and the blocking structure 130 formed by particle doping has a different selective etching ratio from that of the substrate 100.

[0103] Among them, by changing the energy and angle of ion implantation, the properties of the upper layer on the surface of the protruding structure 120 can be changed, and ion doping of the protruding structure 120 in the target area of ​​the first recessed portion can be achieved, that is, the formed blocking structure 130 is the ion implantation area of ​​the protruding structure 120.

[0104] Of course, a mask layer may be directly formed on the surface of the protruding structure 120 by deposition or other processes, and the mask layer serves as the blocking structure 130 , and the selective etching ratio between the mask layer and the substrate 100 only needs to meet the etching requirements.

[0105] Specifically, Figure 5 As shown, after the first recessed portion 110 is formed on the substrate 100 by TSV, due to the different selective etching ratios between the blocking structure 130 formed by particle doping and the substrate 100, a portion of the sidewall of the first recessed portion 110 is etched using the blocking structure 130 as a mask to form a second recessed portion 140. The second recessed portion 140 extends along a second direction X, and the second direction X intersects with the first direction Y.

[0106] In one embodiment of the present disclosure, Figure 5 As shown, when the first recessed portion 110 does not penetrate the substrate 100 in the thickness direction of the substrate 100 , the second recessed portion 140 is located at one end close to the opening of the first recessed portion 110 .

[0107] Wherein, the blocking structure 130 includes a plurality of blocking structures 130, and the sidewall of the first recessed portion 110 between two adjacent blocking structures 130 is lateral etched. Wherein, the formed plurality of second buffer structures 220 are located on the sidewall of the first buffer structure 210 near one end of the first surface 101 in the first direction Y. For example, in the first direction Y, the depth of the region where the second recessed portion 140 is formed in the first recessed portion 110 is not greater than one-third of the depth of the first recessed portion 110; those skilled in the art should be aware that setting a large number of second recessed portions 140 will increase the difficulty of the process, increase the manufacturing cost of the semiconductor structure and reduce the manufacturing efficiency. The present disclosure sets the depth of the region where the second recessed portion 140 is formed in the first recessed portion 110 to be no more than one-third of the depth of the first recessed portion 110, which can avoid increasing the manufacturing cost of the semiconductor structure and reducing the manufacturing efficiency while ensuring sufficient stress release effect; of course, the depth of the region where the second recessed portion 140 is formed in the first recessed portion 110 can also be greater than one-third of the depth of the first recessed portion 110, and the present disclosure does not limit this.

[0108] Of course, the multiple second buffer structures 220 formed are located on one end of the side wall of the first buffer structure 210 close to the second surface 102 in the first direction Y, or the multiple second buffer structures 220 are evenly located on the side wall of the first buffer structure 210 in the first direction Y, or the multiple second buffer structures 220 are arbitrarily distributed on the side wall of the first buffer structure 210 in the first direction Y. The present disclosure does not impose any restrictions on this. By locating the second buffer structure 220 on the outside of the first buffer structure 210, the stress of the TSV can be further released, thereby alleviating the problem of stress concentration in the TSV in the semiconductor structure.

[0109] Among them, the protruding structure 120 formed in the first recessed portion 110 by the Bosch process is annular, the blocking structure 130 formed on the protruding structure 120 is also annular, and the second recessed portion 140 formed by two adjacent blocking structures 130 is also annular. Of course, the blocking structure 130 can also be an arc-shaped non-closed structure, and the second recessed portion 140 formed by two adjacent blocking structures 130 also matches the corresponding arc-shaped non-closed structure. The present disclosure does not limit the specific shape of the blocking structure.

[0110] In step S400 , a second buffer structure is formed in the second recessed portion, and a first buffer structure is formed in the first recessed portion.

[0111] In one embodiment of the present disclosure, the first buffer structure 210 and the second buffer structure 220 are made of different materials. When the first buffer structure 210 and the second buffer structure 220 are made of different materials, the second buffer structure is formed by filling in the first recessed portion 110, and then a mask structure with an opening is formed on the first surface 101 of the substrate 100, and the second buffer structure in the first recessed portion 110 is etched by the mask structure to remove the second buffer structure outside the second recessed portion 140, thereby forming the second buffer structure 220 in the second recessed portion 140; then the first buffer structure 210 is formed by filling in the first recessed portion 110, and then a mask structure with an opening is formed on the first surface 101 of the substrate 100, and the first buffer structure 210 in the first recessed portion 110 is etched along the first direction Y by the mask structure, thereby forming the first buffer structure 210 having the third recessed portion 230 on the side away from the inner wall thereof in the second recessed portion 140.

[0112] In another embodiment of the present disclosure, the first buffer structure 210 and the second buffer structure 220 are made of the same material. Figure 6 As shown, when the first buffer structure 210 and the second buffer structure 220 are made of the same material, the first recessed portion 110 and the second recessed portion 140 are simultaneously filled with the buffer material to form the initial buffer structure 200 through the same filling process, and the initial buffer structure 200 located in the second recessed portion 140 forms the second buffer structure 220. Figure 7 As shown, a mask structure 510 having an opening is formed on the first surface 101 of the substrate 100, as shown in FIG. Figure 8 As shown, the buffer initial structure 200 in the first recess 110 is etched along the first direction Y through the mask structure 510 , so as to form a first buffer structure 210 having a third recess 230 on a side away from the inner wall of the second recess 140 .

[0113] By using the first buffer structure 210 and the second buffer structure 220 of the same material, the deposition and mask etching processes can be reduced once, thereby reducing the manufacturing cost of the semiconductor structure. In addition, the first buffer structure 210 and the second buffer structure 220 of the same material can be formed into an integrated structure, further improving the structural stability of the first buffer structure 210 and the second buffer structure 220, thereby improving the stress release effect of the first buffer structure 210 and the second buffer structure 220.

[0114] The material of the first buffer structure 210 is oxide, such as at least one of silicon oxide, silicon oxynitride, and silicon nitride; the material of the second buffer structure 220 is oxide, such as at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0115] In one embodiment of the present disclosure, Figure 3 As shown, the sidewall of the first recessed portion 110 is formed with a plurality of protruding structures 120 spaced apart in the depth direction, as shown in FIG. Figure 8 As shown, after the first buffer structure 210 is formed in the first recessed portion 110, a protrusion 2110 is provided on the side wall of the first buffer structure 210. The protrusion 2110 has a first surface 2111 and a second surface 2112. The first surface 2111 and the second surface 2112 intersect, and the second buffer structure 220 extends along the second direction X on the first surface 2111.

[0116] Among them, the shape of the protrusion 2110 matches the shape of the recessed portion formed between the multiple protrusion structures 120 on the side wall of the first recessed portion 110, and the cross-section of the protrusion 2110 in the first direction Y is triangular or circular, or other irregular shapes, etc.; the shapes and sizes of the multiple protrusions 2110 may be the same or different, and the present disclosure does not impose any restrictions on this.

[0117] In step S500 , a conductive structure is formed in the first buffer structure, where the conductive structure extends in a first direction.

[0118] Specifically, Fig. 9 As shown, a conductive material is filled in the third recess 230 to form a conductive structure 400 . The first buffer structure 210 exists between the formed conductive structure 400 and the sidewall of the first recess 110 and the second buffer structure 220 .

[0119] In one embodiment of the present disclosure, Fig. 9 As shown, after forming the first buffer structure 210 and before forming the conductive structure 400, the forming method further includes: filling the third recessed portion 230 with a barrier material to form a barrier initial layer 300; Fig.10 As shown, a mask structure 520 having a second opening is formed above the blocking initial layer 300; Fig.11 As shown, the barrier initial layer 300 is etched along the first direction Y through the second opening to form a barrier layer 310 having a fourth recessed portion 320; Fig.12 As shown, a conductive material is filled in the fourth recess 320 to form a conductive initial structure.

[0120] Specifically, after the semiconductor structure is formed, when the first recessed portion 110 does not penetrate the substrate 100, as shown in FIG. Fig.13 As shown, the first surface 101 of the substrate 100 can be disposed on the base 600, and the semiconductor structure can be thinned from the second surface 102 of the substrate 100 as needed, for example, by mechanical chemical polishing (CMP) to achieve BVR (Backside Via Reveal). Fig.14 As shown, a first recessed portion is formed through the substrate 100 , so that two ends of the conductive initial structure are exposed from the first surface 101 and the second surface 102 , respectively, to form a conductive structure 400 .

[0121] The present disclosure provides a method for forming a semiconductor structure, which forms a blocking structure 1301 on a portion of the side walls of a first recessed portion 110 on a substrate 100, and etches a portion of the side walls of the first recessed portion 110 using the blocking structure 130 as a mask to form a second recessed portion 140; forms a first buffer structure 210 in the first recessed portion 110, forms a second buffer structure 220 in the second recessed portion 140, and finally forms a conductive structure 400 in the first buffer structure 210. After the conductive structure 400 is formed, the first buffer structure 210 and the second buffer structure 220 can be used as a stress buffer layer, so that when the semiconductor structure is thinned from the second surface 102 of the substrate 100, the stress can be released through the second buffer structure 220, thereby eliminating the influence of stress concentration, alleviating the problem of stress concentration in the semiconductor structure, and improving the product yield.

[0122] It should be noted that the flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor do they have to be executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0123] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0124] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate including a first surface and a second surface opposite to each other; A first buffer structure is located in the substrate and extends along a first direction, wherein the first direction is a direction from the first surface to the second surface; a second buffer structure is located on a portion of a sidewall of the first buffer structure and extends along a second direction, wherein the second direction intersects the first direction; as well as A conductive structure, located in the first buffer structure and extending along the first direction; A convex portion is provided on a side wall of the first buffer structure, the convex portion has a first surface and a second surface, the first surface and the second surface intersect, and the second buffer structure extends along the second direction on the first surface; and A blocking structure is located on the first surface of the protrusion.

2. The semiconductor structure according to claim 1, characterized in that: The second buffer structure is located on an end of the first buffer structure close to the first surface.

3. The semiconductor structure according to claim 1, characterized in that: The second buffer structure is an annular protrusion in the circumferential direction of the first buffer structure.

4. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure includes a plurality of second buffer structures, and the plurality of second buffer structures are uniformly distributed in the first direction.

5. The semiconductor structure according to claim 1, characterized in that: The width of the second buffer structure in the first direction first gradually increases and then gradually decreases along the second direction.

6. The semiconductor structure according to claim 1, characterized in that The first buffer structure and the second buffer structure are an integrated structure.

7. The semiconductor structure according to claim 1, characterized in that: The first buffer structure and the second buffer structure are made of different materials.

8. The semiconductor structure according to claim 1, characterized in that: The blocking structure is located at two sides of the second buffer structure.

9. The semiconductor structure according to claim 1, characterized in that: The blocking structure is annular in a circumferential direction of the first buffer structure.

10. The semiconductor structure according to claim 1, wherein: Two ends of the conductive structure are exposed from the first surface and the second surface respectively.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first side and a second side opposite to each other; forming a first recessed portion on the first surface of the substrate along a first direction, wherein the first direction is a direction from the first surface to the second surface; forming a blocking structure on a portion of the sidewall of the first recessed portion; Using the blocking structure as a mask, etching a portion of the sidewall of the first recessed portion to form a second recessed portion on the sidewall of the first recessed portion along a second direction, wherein the second direction intersects the first direction; forming a second buffer structure in the second recessed portion, and forming a first buffer structure in the first recessed portion; A conductive structure is formed in the first buffer structure, and the conductive structure extends in the first direction.

12. The forming method according to claim 11, characterized in that: A blocking structure is formed on a portion of the sidewall of the first recessed portion, comprising: Ion doping is performed on a portion of the sidewall of the first recessed portion, and the ion doped region forms a blocking structure.

13. The forming method according to claim 11, characterized in that: A plurality of blocking structures are formed on a portion of the sidewalls of the first recessed portion, and the sidewalls of the first recessed portion between two adjacent blocking structures are laterally etched along the second direction to form the second recessed portion.

14. The forming method according to claim 11, characterized in that: The second recessed portion is filled with a second buffer material to form a second buffer structure; and the first recessed portion is filled with a first buffer material to form the first buffer structure.

15. The forming method according to claim 14, characterized in that: The first buffer structure is etched along the first direction to form a first buffer structure having a first trench, and the conductive structure is formed in the first trench.

16. The forming method according to claim 15, characterized in that: After forming the first buffer structure and before forming the conductive structure, the forming method further includes: Filling a barrier material in the first trench to form a barrier initial layer; The barrier initial layer is etched along the first direction to form a barrier layer having a second groove; and the conductive structure is formed in the second groove.

17. The method according to claim 11, characterized in that The first buffer structure and the second buffer structure are made of the same material; the first buffer structure is formed in the first recessed portion, and the second buffer structure is formed in the second recessed portion through a same filling process.

18. The method according to claim 11, characterized in that forming a conductive structure in the first buffer structure; forming a conductive initial structure in the first buffer structure; Chemical mechanical polishing is performed on the second surface to form a conductive structure with two ends exposed from the first surface and the second surface respectively.

Images