True time delay line based on misaligned symmetric artificial surface plasmon structure

Abstract

The application discloses a true time delay line based on a misaligned symmetric artificial surface plasmon structure and belongs to the field of novel microwave devices, comprising a metal ground, a dielectric substrate arranged above and below the metal ground, a true time delay line structure arranged on the dielectric substrate above the metal ground, the true time delay line structure comprising an artificial surface plasmon waveguide periodically arranged by a plurality of misaligned symmetric artificial surface plasmon unit structures loaded with varactor diodes, a microstrip line for feeding the artificial surface plasmon waveguide, and a varactor diode bias circuit composed of a metal patch and the microstrip line. The true time delay line based on the misaligned symmetric artificial surface plasmon structure has the characteristics of approximately constant time delay value in a wideband range, real-time regulation of the time delay value through the varactor diode, low insertion loss and easy processing, and has a wide application prospect in a wideband phased array system.

Description

Technical Field

[0001] This invention relates to the field of novel microwave device technology, and in particular to a true time delay line based on a misaligned symmetric artificial surface plasmon structure. Background Technology

[0002] With increasingly stringent requirements for radar performance, broadband phased array radar has become a research hotspot in various countries. Compared to narrowband phased array radar, broadband phased array radar offers significant advantages in target classification and identification, improved resolution in multi-target scenarios, enhanced radar measurement accuracy, target attribute determination, target event measurement, improved radar survivability and anti-jamming capabilities, multipath signal suppression, enhanced clutter suppression, and the integration of electronic systems. Traditionally, phase shifters provide phase difference between adjacent antenna elements in a phased array. However, in broadband phased array systems, using phase shifters for scanning causes the array's radiation characteristics to deviate significantly from ideal conditions. This results in beam skew, where different frequency components point in different directions, and aperture crossing, where signals at both ends of the array cannot be superimposed due to envelope misalignment. Using true delay lines for delay control instead of phase shifters can solve the beam skew and aperture crossing problems, thus enabling broadband phased arrays. Common adjustable true delay lines include switching lines and distributed load lines. True delay lines with switching characteristics require high-performance SPNT (single-pole N-throw) switches and a large area. Distributed load lines have limited operating bandwidth and can only achieve approximately constant delay values ​​within a narrow frequency band. Both types mostly use microstrip line structures, but microstrip lines exhibit significant dispersion effects at higher frequencies, resulting in large fluctuations in delay values ​​within the operating frequency band. Summary of the Invention

[0003] This invention provides a true delay line based on a misaligned symmetric artificial surface plasmon structure, which solves the problems of existing true delay lines, such as difficulty in achieving continuous adjustment, narrow operating bandwidth, and large fluctuations in delay value at high operating frequencies, and realizes a true delay line with continuously adjustable broadband delay value.

[0004] This invention provides a true time delay line based on a misaligned symmetric artificial surface plasmon structure, comprising:

[0005] metal ground;

[0006] Dielectric substrate disposed above and below the metal ground;

[0007] A true delay line structure is disposed above the dielectric substrate above the metal ground. The true delay line structure includes an artificial surface plasmon waveguide and a varactor diode bias circuit, which are periodically arranged from multiple staggered symmetrical artificial surface plasmon units with loaded varactor diodes.

[0008] The artificial surface plasmon waveguide, formed by the periodic arrangement of multiple loaded varactor diodes in the staggered symmetrical artificial surface plasmon unit structure, is connected to microstrip lines at both ends for feeding the artificial surface plasmon waveguide.

[0009] The varactor diode bias circuit is connected to the center of the artificial surface plasmon waveguide via a microstrip line to prevent high-frequency leakage caused by power supply from entering the artificial surface plasmon waveguide;

[0010] The misaligned symmetrical artificial surface plasmon waveguide with a varactor diode is a misaligned double-toothed unit. The upper and lower teeth are respectively located at one-quarter and three-quarters of the period of the central metal conductor in each unit. Each tooth has a slit. At the slit, one end of the varactor diode is welded to the central metal conductor, and the other end is welded to a metal rack. The metal rack has a metal through-hole, which is connected to the metal ground. By applying a DC voltage to the central metal conductor and the metal ground, the capacitance value of the varactor diode is changed, thereby controlling the dispersion of the artificial surface plasmon waveguide and achieving continuous control of the time delay value.

[0011] In one embodiment of the present invention, the varactor diode bias circuit is composed of a metal patch and a microstrip line, and the metal patch and the metal ground form an equivalent forming capacitor.

[0012] In one embodiment of the present invention, the thickness of the dielectric substrate above the metal ground is 0.127 mm, and the thickness of the dielectric substrate below it is 0.508 mm.

[0013] In one embodiment of the present invention, the radius of the metal through hole is 0.2 mm.

[0014] The true time delay line based on the misaligned symmetric artificial surface plasmon structure in this embodiment of the invention can achieve approximately constant time delay over a wide bandwidth. By adjusting the bias voltage of the varactor diode in the misaligned symmetric artificial surface plasmon unit structure with the varactor diode loaded, the time delay value can be continuously adjusted.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0017] Figure 1 This is a side view of a true time delay line structure based on a misaligned symmetric artificial surface plasmon structure according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a misaligned symmetric artificial surface plasmon unit structure provided in an embodiment of the present invention;

[0019] Figure 3 A structural diagram of a true time delay line comprising eight misaligned symmetric artificial surface plasmon units provided in an embodiment of the present invention;

[0020] Figure 4 Schematic diagrams of symmetrical artificial surface plasmon unit structures and misaligned symmetrical artificial surface plasmon unit structures provided in embodiments of the present invention;

[0021] Figure 5 A comparison of the dispersion curve simulation results of the symmetrical artificial surface plasmon unit structure and the misaligned symmetrical artificial surface plasmon unit structure provided in the embodiments of the present invention;

[0022] Figure 6 A schematic diagram of the dispersion curve simulation results of the misaligned symmetrical artificial surface plasmon unit of the varactor diode when the capacitance value of the varactor diode is changed, according to an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of the simulation results of the port reflection coefficient of a true delay line provided according to an embodiment of the present invention;

[0024] Figure 8 This is a schematic diagram of the insertion loss simulation results of a true delay line provided according to an embodiment of the present invention;

[0025] Figure 9 This is a schematic diagram illustrating the simulation results of the isolation between the true delay line transmission port and the DC feed port according to an embodiment of the present invention.

[0026] Figure 10 This is a schematic diagram of the simulation results of true delay line delay control provided in an embodiment of the present invention. Detailed Implementation

[0027] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0028] To address the problems in related technologies, artificial surface plasmon structures were introduced. By designing the configuration of the unit structure and changing various parameters of the unit structure, the dispersion relation of the artificial surface plasmon modes can be controlled, achieving approximately invariant time delay values ​​and continuous control of time delay values ​​over a wide bandwidth.

[0029] Combination Figure 1 , Figure 2 and Figure 3 As shown, the true time delay line based on the misaligned symmetric artificial surface plasmon structure includes:

[0030] metal ground 1;

[0031] Dielectric substrates 2 and 4 are disposed above and below the metal ground;

[0032] A true time delay line structure is provided above the dielectric substrate 2 above the metal ground. The true time delay line structure includes an artificial surface plasmon waveguide 5 formed by a periodic arrangement of multiple staggered symmetrical artificial surface plasmon unit structures 3 loaded with varactor diodes and a varactor diode bias circuit 7.

[0033] The artificial surface plasmon waveguide 5, formed by a periodic arrangement of multiple loaded varactor diodes in a staggered symmetrical artificial surface plasmon unit structure, is connected to microstrip lines 6 at both ends for feeding the artificial surface plasmon waveguide.

[0034] The varactor diode bias circuit 7 is connected to the center of the artificial surface plasmon waveguide 5 via a microstrip line to prevent high-frequency leakage caused by power supply from entering the artificial surface plasmon waveguide.

[0035] The misaligned symmetrical artificial surface plasmon waveguide with a varactor diode is a misaligned double-toothed unit. The upper and lower teeth are respectively located at the quarter-cycle and three-quarter-cycle of the central metal conductor in each unit. Each tooth has a slit. At the slit, one end of the varactor diode is welded to the central metal conductor, and the other end is welded to a metal rack. The metal rack has a metal through-hole, which is connected to the metal ground. By applying a DC voltage to the central metal conductor and the metal ground, the capacitance value of the varactor diode is changed, thereby controlling the dispersion of the artificial surface plasmon waveguide and realizing continuous control of the time delay value.

[0036] It is understandable that one end of the varactor diode is soldered to the central metal conductor strip, and the other end is soldered to a metal rack structure. The rack structure is connected to the metal ground plane on the bottom of the dielectric substrate through metal vias. Therefore, applying a DC voltage to the metal conductor strip and the metal ground plane is sufficient to apply a voltage across the varactor diode. When the DC voltage applied across the varactor diode is different, the varactor diode will exhibit different capacitance values, which is determined by the characteristics of the varactor diode itself. As the capacitance value changes continuously, the proposed time delay line structure will also exhibit different time delay characteristics. Therefore, by changing the voltage, the time delay value of the designed time delay line can be changed, achieving real-time dynamic control of the time delay value.

[0037] like Figure 4As shown, traditional artificial surface plasmon unit structures typically use symmetrical structures, such as... Figure 4 As shown in (a). However, simulations revealed that, under the same parameters, Figure 4 Compared to the misaligned symmetric structure shown in (b) Figure 4 The symmetrical structure shown in (a) has a straighter dispersion curve, as... Figure 5 As shown.

[0038] In one embodiment of the present invention, the varactor diode bias circuit is composed of a metal patch and a microstrip line, and the metal patch and a metal ground form an equivalent capacitor.

[0039] The true time delay line based on a misaligned symmetric artificial surface plasmon structure implemented in this invention includes a metal ground 1, a dielectric substrate 2 above the metal ground, and a dielectric substrate 4 below the metal ground 1. Above the dielectric substrate 2 is... Figure 3 The true delay line structure is shown. (Example) Figure 3 As shown, the true delay line includes an artificial surface plasmon waveguide 5 (8 units in the figure) periodically arranged from multiple staggered symmetrical artificial surface plasmon polariton units with loaded varactor diodes, a microstrip structure feeding the artificial surface plasmon waveguide, and a varactor diode bias circuit 7. The metal patch in the varactor diode bias circuit 7 and the metal ground are equivalent to a capacitor, effectively preventing high-frequency leakage caused by the feed into the artificial surface plasmon waveguide, allowing the delay line to operate normally and avoiding performance degradation caused by the parasitic effect of lumped capacitance at high frequencies. For practical ease of feeding, a portion of the dielectric substrate 4 is removed below the feed port, allowing the metal ground to be soldered to the pins of the SMA connector, making the metal ground equipotential with the device casing. The total area of ​​the true delay line is 210.9 × 100 mm. 2 .

[0040] like Figure 1 and Figure 2 As shown, above the metal ground 1 is a 0.127mm thick Rogers RT5880 dielectric substrate 2; because the dielectric substrate 2 is too thin in this design, a 0.508mm thick Rogers RO4003C dielectric substrate 4 is added below the metal ground 1; above the dielectric substrate 2 is a misaligned symmetrical artificial surface plasmon resonance (ASPR) cell structure 3 with a varactor diode loaded. The misaligned symmetrical ASPR cell structure 3 is as follows... Figure 2 As shown, the upper and lower teeth of the staggered double-sided tooth unit are located at one-quarter and three-quarters of the unit's cycle, respectively. Each tooth has a slot, and a varactor diode is welded into the slot. To facilitate power supply to the varactor diode, a via with a radius of 0.2 mm is added to each metal tooth. Where p = 1.5 mm, w1 = 1.6 mm, w2 = 0.6 mm, h = 1 mm, h... c=0.2mm. For example... Figure 6 As shown, the dispersion curve of the unit cell structure was successfully controlled by changing the capacitance value of the varactor diode.

[0041] like Figure 7 The simulation results of the 1-port return loss of this invention are shown. It can be seen that S11 is less than -10dB within the range of 8GHz to 10GHz. Figure 8 The simulation results of the insertion loss of the present invention are shown. It can be seen that the insertion loss is less than 2dB in the range of 8GHz to 10GHz, and the loss is small. Figure 9 The figure shows the simulated value of the isolation between the DC power supply port and the true delay line transmission port of the present invention, which is greater than 36dB. Figure 10 The figure shows the simulation results of the true delay line when the capacitance value of the varactor diode is changed. Within the 8GHz to 10GHz range, the delay value remains approximately constant without changing the capacitance value, exhibiting good broadband characteristics and delay invariance. Furthermore, changing the capacitance value allows for continuous control of the delay value. It can be seen that this true delay line achieves good performance despite its relatively small size.

[0042] The true delay line based on the misaligned symmetric artificial surface plasmon structure proposed in this embodiment of the invention has the characteristics of approximately constant delay value over a wide range, real-time adjustment of delay value through varactor diode, low insertion loss, and easy processing, and has broad application prospects in broadband phased array systems.

[0043] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A true time delay line based on a misaligned symmetric artificial surface plasmon structure, characterized in that, include: metal ground; Dielectric substrate disposed above and below the metal ground; A true delay line structure is disposed above the dielectric substrate above the metal ground. The true delay line structure includes an artificial surface plasmon waveguide and a varactor diode bias circuit, which are periodically arranged from multiple staggered symmetrical artificial surface plasmon units with loaded varactor diodes. The artificial surface plasmon waveguide, formed by the periodic arrangement of multiple loaded varactor diodes in the staggered symmetrical artificial surface plasmon unit structure, is connected to microstrip lines at both ends for feeding the artificial surface plasmon waveguide. The varactor diode bias circuit is connected to the center of the artificial surface plasmon waveguide via a microstrip line to prevent high-frequency leakage caused by power supply from entering the artificial surface plasmon waveguide; The misaligned symmetrical artificial surface plasmon waveguide with a varactor diode is a misaligned double-toothed unit. The upper and lower teeth are respectively located at one-quarter and three-quarters of the period of the central metal conductor in each unit. Each tooth has a slit. At the slit, one end of the varactor diode is welded to the central metal conductor, and the other end is welded to a metal rack. The metal rack has a metal through-hole, which is connected to the metal ground. By applying a DC voltage to the central metal conductor and the metal ground, the capacitance value of the varactor diode is changed, thereby controlling the dispersion of the artificial surface plasmon waveguide and achieving continuous control of the time delay value.

2. The true time delay line based on the misaligned symmetric artificial surface plasmon structure according to claim 1, characterized in that, The varactor diode bias circuit is composed of a metal patch and a microstrip line, and the metal patch and the metal ground form an equivalent capacitor.

3. The true time delay line based on the misaligned symmetric artificial surface plasmon structure according to claim 1, characterized in that, The thickness of the dielectric substrate above the metal ground is 0.127 mm, and the thickness of the dielectric substrate below it is 0.508 mm.

4. The true time delay line based on the misaligned symmetric artificial surface plasmon structure according to claim 1, characterized in that, The radius of the metal through hole is 0.2 mm.

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