Feedback circuit for charge pump

Abstract

The application discloses a feedback circuit of charge pump, comprising voltage detection circuit, comparator, counter and clock generation circuit. The voltage detection circuit comprises capacitor voltage dividing circuit and resistance voltage dividing circuit; the capacitor voltage dividing circuit is used to detect voltage to reduce DC power consumption in standby mode. The output end of capacitor voltage dividing circuit is connected to the first input end of comparator, the second input end of comparator is connected to reference voltage. The output end of comparator outputs first enable signal. The first enable signal forms second enable signal, the clock generation circuit adjusts the clock signal output to charge pump and the first output voltage under the control of second enable signal; the counter is used to count the number of first enable signal generated by comparator in standby mode, and is used to start resistance voltage dividing circuit to correct the deviation of capacitor voltage dividing circuit. The application can reduce standby consumption, and can also correct the detection deviation of capacitor voltage dividing circuit in combination with resistance voltage dividing circuit.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a feedback circuit for a charge pump. Background Technology

[0002] In integrated circuits, charge pumps are often used to provide internal circuits with voltages higher than the power supply voltage. For example, high voltages are required for erase and program operations in flash memory.

[0003] To stabilize the output voltage, a charge pump requires a feedback circuit for control. This feedback circuit uses a voltage detection circuit to monitor the charge pump's output voltage. This voltage detection circuit typically employs a resistor divider circuit, utilizing the voltage division created by the resistors to detect the output voltage. The divided voltage is then compared to a reference voltage. The comparison result reveals the deviation between the output voltage and the target voltage, allowing for output voltage adjustment. Specifically, an enable signal is output from a comparator. This enable signal is input to a clock generation circuit, controlling the clock signal output by that circuit. When the clock signal is input to the charge pump, the capacitors in the pump charge, causing the output voltage to rise. Without a clock signal, the charge pump stops operating, the capacitors do not charge, and the output voltage gradually decreases due to leakage current in the capacitors. Therefore, by controlling the clock signal output by the clock generation circuit using the enable signal, the output signal can be regulated.

[0004] In the feedback circuit of the existing charge pump, the resistor divider circuit will still divide the voltage to maintain the output voltage when the charge pump is in standby mode. However, the resistor series in the resistor divider circuit will form a leakage path between the output voltage and ground, resulting in a large leakage current and thus a large power consumption. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a feedback circuit for a charge pump that can reduce the DC current consumption of the detection circuit, thereby reducing standby power consumption; and can also correct detection deviations.

[0006] To solve the above-mentioned technical problems, the feedback circuit of the charge pump provided by the present invention includes: a voltage detection circuit, a comparator, a counter, and a clock generation circuit.

[0007] The voltage detection circuit includes a capacitor voltage divider circuit and a resistor voltage divider circuit. The input terminal of the capacitor voltage divider circuit is connected to the output terminal of the charge pump, and the output terminal of the capacitor voltage divider circuit forms the first voltage division of the first output voltage of the charge pump.

[0008] When the charge pump is in standby mode, the voltage detection circuit detects the first output voltage through the capacitor voltage divider circuit, and reduces the DC power consumption of the voltage detection circuit by utilizing the characteristic that the capacitor voltage divider circuit has no DC current.

[0009] The output of the capacitor voltage divider circuit is connected to the first input of the comparator, and the second input of the comparator is connected to the reference voltage.

[0010] The comparator outputs a first enable signal.

[0011] The first enable signal generates a second enable signal, which is connected to the enable terminal of the clock generation circuit. Under the control of the second enable signal, the clock generation circuit adjusts the clock signal output to the charge pump and thereby adjusts the first output voltage. When the first voltage division is less than the reference voltage, the first enable signal is valid, the second enable signal is valid, the clock generation circuit outputs the clock signal to the charge pump, thereby making the charge pump work and raising the first output voltage. When the first voltage division is greater than or equal to the reference voltage, the first enable signal is invalid, the second enable signal is invalid, the clock generation circuit stops outputting the clock signal to the charge pump, thereby making the charge pump stop working.

[0012] The input terminal of the counter is connected to the first enable signal, and the output terminal outputs the first count.

[0013] The counter is used to count the effective level pulses of the first enable signal and form the first count; when the first count is greater than or equal to a first set value, the resistor voltage divider circuit is activated and the detection deviation of the capacitor voltage divider circuit is corrected.

[0014] A further improvement is that the input terminal of the resistor voltage divider circuit is connected to the output terminal of the charge pump, and the output terminal of the resistor voltage divider circuit forms a second voltage division of the first output voltage.

[0015] The enable terminal of the resistor divider circuit is connected to a third enable signal.

[0016] The output terminal of the resistor voltage divider circuit is connected to the output terminal of the capacitor voltage divider circuit through a first switching circuit.

[0017] The enable terminal of the first switching circuit is connected to the fourth enable signal.

[0018] When the charge pump is in normal working condition, both the third enable signal and the fourth enable signal are valid. The voltage detection circuit uses the resistor divider circuit to detect the first output voltage, and the resistor divider circuit charges the capacitor divider circuit.

[0019] When the charge pump is in standby mode:

[0020] When the first count is greater than or equal to the first set value, the third enable signal is valid, the resistor voltage divider circuit starts and outputs the second voltage divider, the fourth enable signal is valid, the first switch circuit is enabled and thus connects the output terminal of the resistor voltage divider circuit and the output terminal of the capacitor voltage divider circuit, thereby realizing the correction of the capacitor voltage divider circuit.

[0021] When the first count is less than the first set value, the fourth enable signal is invalid, the first switch circuit is disabled, and the output terminals of the resistor voltage divider circuit and the capacitor voltage divider circuit are not connected. The third enable signal is invalid, the resistor voltage divider circuit is disabled, and the output of the second voltage divider circuit stops.

[0022] A further improvement is that the first set value is set according to the control requirements for the detection deviation.

[0023] A further improvement is that the effective level of the fourth enable signal is a delayed level of the effective level of the third enable signal, and the first delay time between the effective level of the fourth enable signal and the effective level of the third enable signal is greater than or equal to the establishment time of the second voltage output by the resistor divider circuit.

[0024] A further improvement is that the feedback circuit also includes a control circuit, wherein a first input terminal of the control circuit is connected to the first enable signal and a second input terminal is connected to the first counter.

[0025] The first output terminal of the control circuit outputs the second enable signal, and the second enable signal is generated based on the first enable signal.

[0026] The second output terminal of the control circuit outputs the third enable signal, and the third output terminal of the control circuit outputs the fourth enable signal. The third enable signal is formed based on the first count, and the fourth enable signal is formed based on the third enable signal.

[0027] A further improvement is that the first enable terminal of the control circuit is connected to a fifth enable signal. When the fifth enable signal is invalid, the control circuit stops working and the charge pump stops working; when the fifth enable signal is valid, the control circuit works.

[0028] A further improvement is that the second control terminal of the control circuit is connected to the standby signal, and the control terminal of the counter is connected to the standby signal.

[0029] When the standby signal is invalid, the charge pump is in normal working condition and the counter is not working.

[0030] When the standby signal is valid, the charge pump is in standby mode. When standby starts, both the third enable signal and the fourth enable signal are invalid. The first output voltage is detected by the capacitor voltage divider circuit. The counter works and controls the levels of the third enable signal and the fourth enable signal according to the first count output by the counter.

[0031] A further improvement is that the invalid level of the standby signal is low and the valid level is high.

[0032] A further improvement is that the effective level of the third enable signal is high, and the effective level of the fourth enable signal is high.

[0033] A further improvement is that the effective level of the fifth enable signal is high.

[0034] A further improvement is that the effective level of the first enable signal is high, and the effective level of the second enable signal is also high.

[0035] This invention employs a capacitor voltage divider circuit in the voltage detection circuit. In standby mode, the capacitor voltage divider circuit is used to realize voltage detection. Since no DC flows through the capacitor voltage divider circuit, the DC power consumption of the detection circuit can be reduced, thereby reducing standby power consumption.

[0036] The present invention can also set a resistor voltage divider circuit in the voltage detection circuit. During normal operation, the resistor voltage divider circuit is used for voltage division. During standby, the resistor voltage divider circuit can correct the detection deviation of the capacitor voltage divider circuit. Attached Figure Description

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0038] Figure 1 This is a circuit structure diagram of the feedback circuit of the charge pump according to an embodiment of the present invention. Detailed Implementation

[0039] like Figure 1 The diagram shown is a circuit structure diagram of the feedback circuit of the charge pump according to an embodiment of the present invention. The feedback circuit of the charge pump according to an embodiment of the present invention includes: a voltage detection circuit, a comparator 103, a counter 107 and a clock generation circuit 104.

[0040] The voltage detection circuit includes a capacitor voltage divider circuit 102 and a resistor voltage divider circuit 105.

[0041] The input terminal of the capacitor voltage divider circuit 102 is connected to the output terminal of the charge pump 101, and the output terminal of the capacitor voltage divider circuit 102 forms the first voltage division of the first output voltage VPP output by the charge pump 101.

[0042] When the charge pump 101 is in standby mode, the voltage detection circuit detects the first output voltage VPP through the capacitor voltage divider circuit 102, and reduces the DC power consumption of the voltage detection circuit by utilizing the DC-free characteristic of the capacitor voltage divider circuit 102.

[0043] The output of the capacitor voltage divider circuit 102 is connected to the first input of the comparator 103, and the second input of the comparator 103 is connected to the reference voltage VREF.

[0044] The comparator 103 outputs a first enable signal EN.

[0045] The first enable signal EN forms a second enable signal PCLKEN, which is connected to the enable terminal of the clock generation circuit 104. Under the control of the second enable signal PCLKEN, the clock generation circuit 104 adjusts the clock signal output to the charge pump 101 and thereby adjusts the first output voltage VPP. When the first voltage division is less than the reference voltage VREF, the first enable signal EN and the second enable signal PCLKEN are valid. The clock generation circuit 104 outputs the clock signal to the charge pump 101, thereby making the charge pump 101 work and raising the first output voltage VPP. When the first voltage division is greater than or equal to the reference voltage VREF, the first enable signal EN and the second enable signal PCLKEN are invalid. The clock generation circuit 104 stops outputting the clock signal to the charge pump 101, thereby making the charge pump 101 stop working.

[0046] The input terminal of the counter 107 is connected to the first enable signal EN, and the output terminal outputs the first count.

[0047] The counter 107 is used to count the effective level pulses of the first enable signal EN and form the first count; the first count is used to detect the detection deviation. When the first count is greater than or equal to a first set value, the resistor voltage divider circuit 105 is activated and corrects the detection deviation of the capacitor voltage divider circuit 102. The first set value is set according to the control requirements of the detection deviation, that is, determined according to the actual situation. The input terminal of the resistor voltage divider circuit 105 is connected to the output terminal of the charge pump 101, and the output terminal of the resistor voltage divider circuit 105 forms the second voltage divider of the first output voltage VPP.

[0048] The enable terminal of the resistor divider circuit 105 is connected to the third enable signal RESEN.

[0049] The output terminal of the resistor voltage divider circuit 105 is connected to the output terminal of the capacitor voltage divider circuit 102 through the first switching circuit 106.

[0050] The enable terminal of the first switching circuit 106 is connected to the fourth enable signal RESEND.

[0051] When the charge pump 101 is in normal working condition, both the third enable signal RESEN and the fourth enable signal RESEND are valid. The voltage detection circuit uses the resistor voltage divider circuit 105 to detect the first output voltage VPP. The resistor voltage divider circuit 105 charges the capacitor voltage divider circuit 102.

[0052] When the charge pump 101 is in standby mode:

[0053] Leakage in the capacitor voltage divider circuit 102 will cause a detection deviation in the capacitor voltage divider circuit 102. The detection deviation is the difference between the actual value of the first output voltage VPP and the detection value obtained by the first voltage divider conversion. If the detection deviation is too large, the actual output first output voltage VPP will be inaccurate.

[0054] In this embodiment of the invention, since the detection deviation is determined based on the first count, the third enable signal RESEN and the fourth enable signal RESEND are set according to the first count. When the first count is greater than or equal to the first set value, the third enable signal RESEN is valid, the resistor voltage divider circuit 105 is enabled and outputs the second voltage divider, the fourth enable signal RESEND is valid, the first switch circuit 106 is enabled and thus connects the output terminal of the resistor voltage divider circuit 105 to the output terminal of the capacitor voltage divider circuit 102, thereby realizing the correction of the capacitor voltage divider circuit 102.

[0055] In this embodiment of the invention, the effective level of the fourth enable signal RESEND is the delayed level of the effective level of the third enable signal RESEN, and the first delay time between the effective level of the fourth enable signal RESEND and the effective level of the third enable signal RESEN is greater than or equal to the establishment time of the second voltage output by the resistor voltage divider circuit 105.

[0056] When the first count is less than the first set value, the fourth enable signal RESEND is invalid, the first switch circuit 106 is disabled, and the output terminal of the resistor voltage divider circuit 105 and the output terminal of the capacitor voltage divider circuit 102 are not connected. The third enable signal RESEN is invalid, the resistor voltage divider circuit 105 is disabled, and the second voltage divider is stopped from outputting.

[0057] In this embodiment of the invention, the feedback circuit further includes a control circuit 108, wherein the first input terminal of the control circuit 108 is connected to the first enable signal EN and the second input terminal is connected to the first counter.

[0058] The first output terminal of the control circuit 108 outputs the second enable signal PCLKEN, and the second enable signal PCLKEN is formed based on the first enable signal EN.

[0059] The second output terminal of the control circuit 108 outputs the third enable signal RESEN, and the third output terminal of the control circuit 108 outputs the fourth enable signal RESEND. The third enable signal RESEN is formed based on the first count, and the fourth enable signal RESEND is formed based on the third enable signal RESEN.

[0060] The first enable terminal of the control circuit 108 is connected to the fifth enable signal PUMPEN. When the fifth enable signal PUMPEN is invalid, the control circuit 108 stops working and the charge pump 101 stops working; when the fifth enable signal PUMPEN is valid, the control circuit 108 works.

[0061] The second control terminal of the control circuit 108 is connected to the standby signal STB, and the control terminal of the counter 107 is connected to the standby signal STB.

[0062] When the standby signal STB is invalid, the charge pump 101 is in normal working condition and the counter 107 is not working.

[0063] When the standby signal STB is valid, the charge pump 101 is in standby mode. When standby starts, the third enable signal RESEN and the fourth enable signal RESEND are both invalid. The first output voltage VPP is detected by the capacitor voltage divider circuit 102. The counter 107 is working, and the level of the third enable signal RESEN and the fourth enable signal RESEND is controlled according to the first count output by the counter 107.

[0064] In some embodiments, the invalid level of the standby signal STB is a low level and the valid level is a high level.

[0065] The effective level of the first enable signal EN is high, and the effective level of the second enable signal PCLKEN is high.

[0066] The effective level of the third enable signal RESEN is high, and the effective level of the fourth enable signal RESEND is high.

[0067] The effective level of the fifth enable signal PUMPEN is high.

[0068] In this embodiment of the invention, a capacitor voltage divider circuit 102 is used in the voltage detection circuit. In standby mode, the capacitor voltage divider circuit 102 is used to realize voltage detection. Since no DC flows through the capacitor voltage divider circuit 102, the DC power consumption of the detection circuit can be reduced, thereby reducing standby power consumption.

[0069] In this embodiment of the invention, a resistor voltage divider circuit 105 can be set in the voltage detection circuit. During normal operation, the resistor voltage divider circuit 105 is used to divide the voltage, so that the first output voltage can be accurately controlled. In standby mode, the resistor voltage divider circuit 105 can correct the detection deviation of the capacitor voltage divider circuit 102.

[0070] In this embodiment of the invention, voltage detection is performed using a capacitor voltage divider circuit 102, which reduces the DC current consumption of the detection circuit and thus reduces standby power consumption. Simultaneously, a counter 107 is used to activate the resistor voltage divider circuit 105 after the charge pump 101 has been enabled a certain number of times, correcting the detection deviation caused by leakage current in the capacitor voltage divider circuit 102.

[0071] The workflow of the feedback circuit of the charge pump in this embodiment of the invention includes:

[0072] 1. When PUMPEN = 0, charge pump 101 is in the off state.

[0073] 2. During normal operation (STB=0), RESEN=1, RESEND=1. The first output voltage VPP of the charge pump 101 is detected by the resistor voltage divider circuit 105, and the capacitor voltage divider circuit 102 is charged to initialize the voltage. When VPP is less than the target voltage, the clock generation circuit 104 outputs a clock signal, and the charge pump 101 circuit operates to raise the first output voltage VPP. When the first output voltage VPP is greater than the target voltage, the clock generation circuit 104 is turned off, thereby stopping the charge pump 101 from operating.

[0074] 3. After entering standby mode (STB=1), signals RESEN and RESEND are set low sequentially. At this time, the first output voltage VPP is detected by the capacitor voltage divider circuit 102.

[0075] 3.1. Similarly, when the first output voltage VPP is less than the target voltage, the clock generation circuit 104 outputs a clock signal, and the charge pump 101 circuit operates to raise the first output voltage VPP; when the first output voltage VPP is greater than the target voltage, the clock generation circuit 104 is turned off, thereby causing the charge pump 101 to stop working.

[0076] 3.2. Counter 107 is used to count the number of times the first enable signal EN output by comparator 103 is set high during standby. When the count reaches a certain number of times (which can be any number, determined according to the influence of leakage current on capacitor voltage divider circuit 102), control circuit 108 turns on resistor voltage divider circuit 105. After waiting for a certain period of time (for resistor voltage divider circuit 105 to be established), switch circuit 106 is turned on to correct capacitor voltage divider circuit 102 and eliminate the detection deviation of capacitor voltage divider circuit 102 caused by leakage current.

[0077] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A feedback circuit for a charge pump, characterized in that, include: Voltage detection circuit, comparator, counter and clock generation circuit; The voltage detection circuit includes a capacitor voltage divider circuit and a resistor voltage divider circuit. The input terminal of the capacitor voltage divider circuit is connected to the output terminal of the charge pump, and the output terminal of the capacitor voltage divider circuit forms the first voltage division of the first output voltage of the charge pump. When the charge pump is in standby mode, the voltage detection circuit detects the first output voltage through the capacitor voltage divider circuit, and reduces the DC power consumption of the voltage detection circuit by utilizing the characteristic that the capacitor voltage divider circuit has no DC current. The output of the capacitor voltage divider circuit is connected to the first input of the comparator, and the second input of the comparator is connected to the reference voltage. The comparator outputs a first enable signal. The first enable signal generates a second enable signal, which is connected to the enable terminal of the clock generation circuit. Under the control of the second enable signal, the clock generation circuit adjusts the clock signal output to the charge pump and thereby adjusts the first output voltage. When the first voltage division is less than the reference voltage, the first enable signal is valid, the second enable signal is valid, the clock generation circuit outputs the clock signal to the charge pump, thereby making the charge pump work and raising the first output voltage. When the first voltage divider is greater than or equal to the reference voltage, the first enable signal is invalid, the second enable signal is invalid, the clock generation circuit stops outputting the clock signal to the charge pump and thus the charge pump stops working; The input terminal of the counter is connected to the first enable signal, and the output terminal outputs the first count. The counter is used to count the effective level pulses of the first enable signal and form the first count; when the first count is greater than or equal to a first set value, the resistor voltage divider circuit is activated and the detection deviation of the capacitor voltage divider circuit is corrected. The input terminal of the resistor voltage divider circuit is connected to the output terminal of the charge pump, and the output terminal of the resistor voltage divider circuit forms the second voltage division of the first output voltage. The enable terminal of the resistor voltage divider circuit is connected to a third enable signal; The output terminal of the resistor voltage divider circuit is connected to the output terminal of the capacitor voltage divider circuit through a first switching circuit. The enable terminal of the first switching circuit is connected to the fourth enable signal; When the charge pump is in normal working condition, both the third enable signal and the fourth enable signal are valid. The voltage detection circuit uses the resistor voltage divider circuit to detect the first output voltage, and the resistor voltage divider circuit charges the capacitor voltage divider circuit. When the charge pump is in standby mode: When the first count is greater than or equal to the first set value, the third enable signal is valid, the resistor voltage divider circuit starts and outputs the second voltage divider, the fourth enable signal is valid, the first switch circuit is enabled and thus connects the output terminal of the resistor voltage divider circuit and the output terminal of the capacitor voltage divider circuit, thereby realizing the correction of the capacitor voltage divider circuit. When the first count is less than the first set value, the fourth enable signal is invalid, the first switch circuit is disabled, and the output terminals of the resistor voltage divider circuit and the capacitor voltage divider circuit are not connected. The third enable signal is invalid, the resistor voltage divider circuit is disabled, and the output of the second voltage divider circuit stops.

2. The feedback circuit of the charge pump as described in claim 1, characterized in that: The first setting value is set according to the control requirements for the detection deviation.

3. The feedback circuit of the charge pump as described in claim 2, characterized in that: The effective level of the fourth enable signal is a delayed level of the effective level of the third enable signal, and the first delay time between the effective level of the fourth enable signal and the effective level of the third enable signal is greater than or equal to the establishment time of the second voltage output by the resistor divider circuit.

4. The feedback circuit of the charge pump as described in claim 3, characterized in that: The feedback circuit further includes a control circuit, wherein a first input terminal of the control circuit is connected to the first enable signal and a second input terminal is connected to the first counter. The first output terminal of the control circuit outputs the second enable signal, and the second enable signal is generated based on the first enable signal; The second output terminal of the control circuit outputs the third enable signal, and the third output terminal of the control circuit outputs the fourth enable signal. The third enable signal is formed based on the first count, and the fourth enable signal is formed based on the third enable signal.

5. The feedback circuit of the charge pump as described in claim 4, characterized in that: The first enable terminal of the control circuit is connected to the fifth enable signal. When the fifth enable signal is invalid, the control circuit stops working and the charge pump stops working; when the fifth enable signal is valid, the control circuit works.

6. The feedback circuit of the charge pump as described in claim 5, characterized in that: The second control terminal of the control circuit is connected to the standby signal, and the control terminal of the counter is connected to the standby signal; When the standby signal is invalid, the charge pump is in normal working condition and the counter is not working. When the standby signal is valid, the charge pump is in standby mode. When standby starts, both the third enable signal and the fourth enable signal are invalid. The first output voltage is detected by the capacitor voltage divider circuit. The counter works and controls the levels of the third enable signal and the fourth enable signal according to the first count output by the counter.

7. The feedback circuit of the charge pump as described in claim 6, characterized in that: The invalid level of the standby signal is low, and the valid level is high.

8. The feedback circuit of the charge pump as described in claim 1, characterized in that: The effective level of the third enable signal is high, and the effective level of the fourth enable signal is high.

9. The feedback circuit of the charge pump as described in claim 5, characterized in that: The effective level of the fifth enable signal is high.

10. The feedback circuit of the charge pump as described in claim 1, characterized in that: The effective level of the first enable signal is high, and the effective level of the second enable signal is high.

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