Display device, display apparatus, and driving method

Abstract

The application discloses a display device, a display apparatus and a driving method. The display device comprises a display panel and a backlight module. The display panel comprises a plurality of pixels arranged in an array, a plurality of pixels arranged along a first direction form a pixel row, a plurality of pixels arranged along a second direction form a pixel column, and the first direction intersects the second direction. When the display panel displays one frame of image, the working process comprises a refreshing stage and a backlight lighting stage. The refreshing stage comprises a first stage and a second stage executed in sequence. In the first stage, a pre-charge data signal is written to the pixel, the voltage corresponding to the pre-charge data signal is a first voltage, and the gray scale corresponding to the first voltage is greater than 0. In the second stage, an image data signal is written to the pixel. In the backlight lighting stage, the backlight module is controlled to be turned on. In the application, the length of the backlight lighting stage in one frame of image can be increased, which is beneficial to improving the display effect and improving the ghosting.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device, display equipment and driving method. BACKGROUND

[0002] With the continuous development of display technology, display panels have been widely used in people's production and life. Especially liquid crystal display panels can be used in smart phones, smart watches and VR displays.

[0003] However, the existing liquid crystal display panel still has some technical problems to be solved due to the response time of liquid crystal. For example, high-frequency display ghosting and other problems affect the display effect of the display panel. SUMMARY

[0004] The present application provides a display device, display equipment and driving method to improve the display effect.

[0005] According to an aspect of the present application, a display device is provided, comprising a display panel and a backlight module;

[0006] The display panel comprises a plurality of pixels arranged in an array, a plurality of pixels arranged along a first direction form a pixel row, a plurality of pixels arranged along a second direction form a pixel column, and the first direction intersects the second direction;

[0007] When the display panel displays 1 frame of image, the working process thereof comprises a refresh stage and a backlight lighting stage;

[0008] The refresh stage comprises a first stage and a second stage executed in sequence; in the first stage, a pre-charge data signal is written to the pixels, the voltage corresponding to the pre-charge data signal is a first voltage, and the gray scale corresponding to the first voltage is greater than 0; in the second stage, an image data signal is written to the pixels;

[0009] In the backlight lighting stage, the backlight module is turned on.

[0010] According to another aspect of the present application, a display equipment is provided, comprising the aforementioned display device.

[0011] According to another aspect of the present application, a driving method of a display device is provided, the display device comprising a display panel and a backlight module; the display panel comprises a plurality of pixels arranged in an array, a plurality of pixels arranged along a first direction form a pixel row, a plurality of pixels arranged along a second direction form a pixel column, and the first direction intersects the second direction; when the display panel displays 1 frame of image, the working process thereof comprises a refresh stage and a backlight lighting stage; the refresh stage comprises a first stage and a second stage executed in sequence;

[0012] The driving method comprises:

[0013] In the first stage, a pre-charge data signal is written to the pixel, the voltage corresponding to the pre-charge data signal being a first voltage, the gray scale corresponding to the first voltage being greater than 0;

[0014] In the second stage, an image data signal is written to the pixel;

[0015] In the backlight lighting stage, the backlight module is controlled to be turned on.

[0016] In the present application, when the display panel displays one frame of image, the working process thereof comprises a refresh stage and a backlight lighting stage; the refresh stage comprises sequentially executed first and second stages; in the first stage, a pre-charge data signal is written to the pixel, the voltage corresponding to the pre-charge data signal being a first voltage, the gray scale corresponding to the first voltage being greater than 0; in the second stage, an image data signal is written to the pixel; in the backlight lighting stage, the backlight module is controlled to be turned on. In the present application, the pixel is pre-charged in the first stage, and the image data signal is written to the pixel in the second stage, so that after the image data signal is written to the pixel, the liquid crystal response of the pixel is switched from a specific gray scale greater than 0 and corresponding to the pre-charge data signal to a gray scale corresponding to the image data signal, compared with the liquid crystal response being switched from an initial gray scale equal to 0 to a gray scale corresponding to the image data signal, the liquid crystal response time of the pixel can be shortened, and thus the time length of the refresh stage in one frame of image is shortened, thereby the time length of the backlight lighting stage is increased, which is beneficial to improving the display effect and reducing the ghosting.

[0017] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a schematic diagram of a display device provided by an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of a display panel provided by an embodiment of the present application;

[0021] Figure 3is a schematic diagram of a display device driving timing provided by an embodiment of the present application;

[0022] Figure 4 is Figure 3 is a schematic diagram of a first stage of a display device in the middle;

[0023] Figure 5 is Figure 3 is a schematic diagram of a second stage of a display device in the middle;

[0024] Figure 6 is a schematic diagram of another display device driving timing;

[0025] Figure 7 is a schematic diagram of another display device driving timing provided by an embodiment of the present application;

[0026] Figure 8 is a schematic diagram of another display device driving timing provided by an embodiment of the present application;

[0027] Figure 9 is a schematic diagram of another display device provided by an embodiment of the present application;

[0028] Figure 10 is a schematic diagram of another display device provided by an embodiment of the present application;

[0029] Figure 11 is a schematic diagram of another display device provided by an embodiment of the present application;

[0030] Figure 12 is a schematic diagram of another display device driving timing provided by an embodiment of the present application;

[0031] Figure 13 is a schematic diagram of another display device provided by an embodiment of the present application;

[0032] Figure 14 is Figure 13 is a schematic diagram of a display device driving timing in the middle;

[0033] Figure 15 is a schematic diagram of a display device provided by an embodiment of the present application;

[0034] Figure 16 is a schematic diagram of a display device driving method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work should belong to the protection scope of the present application.

[0036] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a list of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0037] Figure 1 is a schematic view of a display device provided by an embodiment of the present application, Figure 2 is a schematic view of a display panel provided by an embodiment of the present application. As Figure 1 and Figure 2 shown, the display device comprises a backlight module 110 and a display panel 120; the display panel 120 comprises a plurality of pixels 121 arranged in an array, a plurality of pixels 121 arranged along a first direction F1 form a pixel row 122, a plurality of pixels 121 arranged along a second direction F2 form a pixel column 123, the first direction F1 and the second direction F2 intersect; when the display panel 120 displays one frame of image, the working process thereof comprises a refresh stage and a backlight lighting stage; the refresh stage comprises a first stage and a second stage executed in sequence; in the first stage, a pre-charge data signal is written to the pixel 121, the voltage corresponding to the pre-charge data signal is a first voltage, and the gray scale corresponding to the first voltage is greater than 0; in the second stage, an image data signal is written to the pixel 121; in the backlight lighting stage, the backlight module 110 is controlled to be turned on.

[0038] In this embodiment, the display device includes a backlight module 110 and a display panel 120. The display panel 120 includes a light-emitting surface and a backlight surface. The side of the display panel 120 displaying the image is defined as the light-emitting surface, and the backlight surface is defined relative to the light-emitting surface. Specifically, the side of the display panel 120 facing away from the light-emitting surface is defined as the backlight surface. Optionally, the backlight mode of the display device can be direct-lit backlight, with the backlight module 110 facing the backlight surface of the display panel 120, but this is not a limitation. In other embodiments, the backlight mode of the display device can also be edge-lit backlight.

[0039] Display panel 120 is a liquid crystal display panel, and backlight module 110 provides backlight for display panel 120. Specifically, the light emitted by backlight module 110 is projected onto the backlight surface of display panel 120. The light source of backlight module 110 can be a light-emitting diode (LED) light source, but is not limited thereto. Any backlight module suitable for display devices falls within the protection scope of this invention.

[0040] The display panel 120 includes a plurality of pixels 121 arranged in an array. The plurality of pixels 121 arranged along a first direction F1 form a pixel row 122, and the plurality of pixels 121 arranged along a second direction F2 form a pixel column 123. The first direction F1 and the second direction F2 intersect. Specifically, the display panel 120 includes a plurality of pixel rows 122 arranged along the F2 direction and a plurality of pixel columns 123 arranged along the F1 direction. Optionally, the F1 direction may be perpendicular to the F2 direction, but this is not a limitation. In other embodiments, the angle between the F1 direction and the F2 direction may not be a multiple of 90°.

[0041] Figure 3 This is a schematic diagram of a display device driving timing provided in an embodiment of the present invention. Figure 3 As shown, when the display panel 120 displays one frame of image, the operation of one frame of image includes a refresh phase T10 and a backlight illumination phase T20. In the refresh phase T10, data signals are written to the pixels 121, and the backlight module 110 is turned off. In the backlight illumination phase T20, the backlight module 110 is turned on to provide backlight to the display panel 120, and no data signals are written to the pixels 121. The refresh phase T10 includes a first phase T11 and a second phase T12 executed sequentially. In the first phase T11, a pre-charge data signal is written to the pixels 121. The voltage corresponding to the pre-charge data signal is a first voltage, and the grayscale corresponding to the first voltage is greater than 0. In the second phase T12, an image data signal is written to the pixels 121. Here, the grayscale corresponding to the first voltage is greater than 0, but based on product requirements, relevant personnel can reasonably design the voltage value of the first voltage, for example, the voltage value of the first voltage may be greater than 0 or less than 0.

[0042] Figure 4 is Figure 3 a schematic diagram of a first stage of the display device as shown in Figure 4 As shown in FIG. 1, for the display panel 120, the first stage T11 is a pre-charge stage, and the same pre-charge data signal can be optionally written to each pixel 121 simultaneously. Specifically, a specific gray scale (for example, 127) greater than 0 is preset, and a voltage value corresponding to the specific gray scale 127 can be determined based on a mapping table of gray scale and voltage, which is defined as the pre-charge data signal Vc. When the display panel 120 displays 1 frame of image, the same pre-charge data signal Vc is written to each pixel 121 simultaneously in the first stage T11, so as to realize pixel pre-charge. In other embodiments, the pre-charge data signal can be optionally written to at least one pixel row in the first stage.

[0043] Figure 5 is Figure 3 a schematic diagram of a second stage of the display device as shown in Figure 5As shown, after the pixel pre-charge phase, i.e. the first phase T11, the second phase T12 is entered. In the second phase T12, corresponding image data signals are written to the pixels 121 based on 1 frame of image displayed by the display panel 120. Taking the first row of pixels 121 as an example, the pixels 121 in the first row are sequentially labeled as P11, P12, P13, P14, P15, … along the F1 direction, the image data signal corresponding to the pixel P11 is V11, the image data signal corresponding to the pixel P12 is V12, the image data signal corresponding to the pixel P13 is V13, the image data signal corresponding to the pixel P14 is V14, the image data signal corresponding to the pixel P15 is V15, and so on. Given that the data signal corresponding to each pixel 121 in the first phase T11 is Vc, then in the second phase T12, the image data signal write for the first row of pixels 121 is performed, in which the pixel P11 is charged from Vc to V11, the pixel P12 is charged from Vc to V12, the pixel P13 is charged from Vc to V13, the pixel P14 is charged from Vc to V14, the pixel P15 is charged from Vc to V15, and so on. Sequentially, the image data signal write for the second row of pixels 121 is performed, in which the pixel P21 is charged from Vc to the corresponding image data signal V21, the pixel P22 is charged from Vc to the corresponding image data signal V22, the pixel P23 is charged from Vc to the corresponding image data signal V23, the pixel P24 is charged from Vc to the corresponding image data signal V24, the pixel P25 is charged from Vc to the corresponding image data signal V25, and so on. As described above, in the second phase T12, the image data signal write for each row of pixels 122 in the display panel 120 is performed according to the scanning mode, so as to write the corresponding image data signal to each pixel 121. It is obvious that in the second phase T12, for any one pixel 121, it is charged from Vc to the corresponding image data signal, and the voltage corresponding to the pre-charge data signal Vc is the first voltage, the gray scale corresponding to the first voltage is greater than 0, so in the refresh phase T10, the pixel 121 pre-charged from the initial gray scale greater than 0 is switched to the gray scale corresponding to the image data signal.

[0044] Specifically, the display panel 120 is a liquid crystal display panel. After the pixel 121 is written with the data signal, the liquid crystal needs a certain response time. In order to avoid seeing a trailing shadow in high brushing, the backlight module is only turned on to light up the backlight after the display panel completes scanning and the whole liquid crystal response is completed, so as to avoid the process of picture refreshing and improve the display effect. If the backlight lighting time in 1 frame of image is too short, the brightness of the display device will be reduced; if the backlight lighting time is prolonged, the working time of 1 frame of image will be increased, so that the refreshing frequency is reduced, and the corresponding backlight on-off frequency is reduced, and the backlight flicker will be seen. The display device provided in the embodiment can improve the backlight lighting time without increasing the length of the working time of 1 frame of image, which is beneficial to high-frequency display and can also improve the display effect. The liquid crystal response time is the corresponding time of gray scale switching.

[0045] Figure 6 is another schematic diagram of the driving time sequence of the display device. As shown in Figure 6 , the working process time length of 1 frame of image of the display device is equal to the working process time length of 1 frame of image of the display panel 120 as shown in Figure 3 . As shown in Figure 6 , when the display device displays 1 frame of image (1 frame), the working process of 1 frame of image thereof includes a refreshing stage T30 and a backlight lighting stage T40. Unlike Figure 3 , the refreshing stage T30 in Figure 6 does not include a first stage (a pre-charging stage), but directly writes the image data signal to the pixel after entering the refreshing stage T30, and the backlight module is closed and not lighted up. After entering the backlight lighting stage T40, the backlight module is turned on to provide backlight for the display panel, and no image data signal is written to the pixel. The refreshing stage T30 includes a charging stage T31; in the charging stage T31, the image data signal is written to the pixel. The interval stage T32 between the charging stage T31 and the backlight lighting stage T40 in the refreshing stage T30 can be understood as the liquid crystal response time of the last row of pixels of the display panel. In the charging stage T31, for any one pixel, it is directly charged to the corresponding image data signal; and after the image data signal is written to the pixel, the liquid crystal needs a certain response time. Specifically, the liquid crystal response is from the initial gray scale equal to 0 to the gray scale corresponding to the image data signal, and the liquid crystal response time of the pixel is relatively long. Based on this, the time of the refreshing stage in 1 frame of image is relatively long, which leads to a relatively short opening time of the backlight lighting stage, and affects the display effect.

[0046] In the embodiment, in the refreshing stage T10, for any one pixel 121, the image data signal is written after pre-charging, and then the liquid crystal response is from a specific gray scale greater than 0 (for example, the gray scale 127 corresponding to Vc) to the gray scale corresponding to the image data signal after the pre-charging data signal Vc is charged to the corresponding image data signal.Figure 6 Compared with the liquid crystal response starting from the initial gray level equal to 0 to the gray level corresponding to the image data signal, the embodiment can shorten the liquid crystal response time of the pixel 121, and further shorten the liquid crystal response time of a row of pixels 121, thereby shortening the time length of the refresh stage in 1 frame of image, increasing the time length of the backlight lighting stage, and being beneficial to improving the display effect, wherein T10 < T30, and T20 > T40. The interval stage T13 between the second stage T12 in the refresh stage T10 and the backlight lighting stage T20 can be understood as the liquid crystal response time of the last row of pixels 121 of the display panel 120.

[0047] In the present application, when the display panel displays 1 frame of image, the working process thereof includes a refresh stage and a backlight lighting stage; the refresh stage includes sequentially executed first and second stages; in the first stage, a pre-charge data signal is written to the pixel, the voltage corresponding to the pre-charge data signal is a first voltage, and the gray level corresponding to the first voltage is greater than 0; in the second stage, an image data signal is written to the pixel; and in the backlight lighting stage, the backlight module is controlled to be turned on. In the present application, the pixel is pre-charged in the first stage, and the image data signal is written to the pixel in the second stage, so that after the image data signal is written to the pixel, the liquid crystal response of the pixel starts from a specific gray level greater than 0 and corresponding to the pre-charge data signal to switch to the gray level corresponding to the image data signal. Compared with the liquid crystal response starting from the initial gray level equal to 0 to the gray level corresponding to the image data signal, the liquid crystal response time of the pixel can be shortened, and further the time length of the refresh stage in 1 frame of image can be shortened, thereby increasing the time length of the backlight lighting stage, being beneficial to improving the display effect, and improving the ghosting.

[0048] Optionally, at least part of the pixel rows simultaneously execute the first stage. In the present embodiment, in the first stage, a pre-charge data signal is written to i rows of pixels in the display panel, i is greater than 1, and the i rows of pixels can be adjacent i rows of pixels or can not be adjacent. In other embodiments, in the first stage, a pre-charge data signal is written to at least one row of pixels in the display panel; or, as shown in the first stage T11, a pre-charge data signal is written to each pixel in the display panel. Figure 3

[0049] Figure 7 is another schematic diagram of a display device driving time sequence provided by an embodiment of the present application. As shown in Figure 7 ​As shown, optionally in the first stage T11, pre-charge data signals are written into the first row of pixels L(1) to the i-th row of pixels L(i) in the display panel. Based on this, after entering the second stage T12 of the refresh stage T10, any one of the first row of pixels L(1) to the i-th row of pixels L(i), the pixel is charged from the pre-charge data signal to the corresponding image data signal, and the liquid crystal response of the pixel is switched from a specific gray scale (corresponding to the pre-charge data signal) greater than 0 to the gray scale corresponding to the image data signal. Therefore, the liquid crystal response time of any one of the first row of pixels L(1) to the i-th row of pixels L(i) can be shortened, and the time length of the refresh stage in 1 frame of image is further shortened, the time length of the backlight lighting stage is increased, and the display effect is improved.

[0050] Optionally, there are two adjacent pixel rows in the display panel, and the end time of the second stage of one of the pixel rows is earlier than or equal to the start time of the first stage of the other pixel row.

[0051] In this embodiment, the refresh stage of the display panel can include a plurality of refresh sub-stages, and each refresh sub-stage includes a first stage and a second stage executed in sequence. For two adjacent refresh sub-stages, the last pixel row of the former refresh sub-stage is adjacent to the first pixel row of the latter refresh sub-stage, and the end time of the second stage of the last pixel row of the former refresh sub-stage is earlier than or equal to the start time of the first stage of the first pixel row of the latter refresh sub-stage. The problem of writing pre-charge data signals of the latter refresh sub-stage into the pixel rows corresponding to the former refresh sub-stage can be prevented, and the display effect is improved.

[0052] Figure 8 is another schematic diagram of a display device driving timing provided by an embodiment of the present application. As shown in the figure, Figure 8 As shown, when the display panel displays 1 frame of image, the working process of the 1 frame of image includes a refresh stage T10 and a backlight lighting stage T20. In the refresh stage T10, data signals are written into pixels, and the backlight module is turned off. In the backlight lighting stage T20, the backlight module is turned on, and no data signals are written into the pixels. The refresh stage T10 includes a first refresh sub-stage T10a and a second refresh sub-stage T10b executed in sequence; but is not limited to this, in other embodiments, the refresh stage can also include a plurality of refresh sub-stages.

[0053] Firstly, the first refresh sub-stage T10a is executed, and the first refresh sub-stage T10a comprises a first stage T11a and a second stage T12a. In the first stage T11a, a pre-charge data signal is written into the first row of pixels L(1) to the i-th row of pixels L(i), and the voltage corresponding to the pre-charge data signal is the first voltage, and the gray scale corresponding to the first voltage is greater than 0. In the second stage T12a, the corresponding image data signal is written into each pixel in the first row of pixels L(1); sequentially, the corresponding image data signal is written into each pixel in the second row of pixels; and in turn, the corresponding image data signal is written into each pixel in the i-th row of pixels L(i). Then, for any one of the first row of pixels L(1) to the i-th row of pixels L(i), after the corresponding image data signal is written, the liquid crystal response is switched from a specific gray scale (corresponding to the pre-charge data signal) greater than 0 to the gray scale corresponding to the image data signal, and the liquid crystal response time of the first row of pixels L(1) to the i-th row of pixels L(i) can be shortened.

[0054] In turn, the second refresh sub-stage T10b is executed, and the second refresh sub-stage T10b comprises a first stage T11b and a second stage T12b. In the first stage T11b, a pre-charge data signal is written into the (i+1)-th row of pixels L(i+1) to the n-th row of pixels L(n), and the voltage corresponding to the pre-charge data signal is the first voltage, and the gray scale corresponding to the first voltage is greater than 0. The pre-charge data signal can be the same as or different from the pre-charge data signal corresponding to the first stage T11a. In the second stage T12b, the corresponding image data signal is written into each pixel in the (i+1)-th row of pixels L(i+1); sequentially, the corresponding image data signal is written into each pixel in the (i+2)-th row of pixels; and in turn, the corresponding image data signal is written into each pixel in the last row of pixels. Then, for any one of the (i+1)-th row of pixels L(i+1) to the n-th row of pixels L(n), after the corresponding image data signal is written, the liquid crystal response is switched from a specific gray scale (corresponding to the pre-charge data signal) greater than 0 to the gray scale corresponding to the image data signal, and the liquid crystal response time of the (i+1)-th row of pixels L(i+1) to the n-th row of pixels L(n) can be shortened. The n-th row of pixels L(n) can be the last row of pixels in the display panel, but is not limited thereto.

[0055] In this embodiment, the liquid crystal response time of the pixels can be reduced by pre-charging at least two rows of pixels. Based on this, the duration of the refresh stage in one frame of image can be shortened, and the duration of the backlight lighting stage can be increased, which is beneficial to improve the display effect. It should be noted that when the number of pixel rows in the first stage of the refresh stage of one frame of image changes, the proportion of the refresh stage in one frame of image can also change.

[0056] Optionally, Vt=(Vmax+Vmin) / 2, wherein Vt is the absolute value of the first voltage, Vmax is the maximum value of the absolute value of the voltage corresponding to the data signal of the 1-frame image, and Vmin is the minimum value of the absolute value of the voltage corresponding to the data signal of the 1-frame image.

[0057] In this embodiment, for a 1-frame image of the display panel, the display device can obtain the image data signal of each pixel in the frame image, and further can obtain the absolute value of the voltage corresponding to the image data signal of each pixel. Based on this, for the 1-frame image, the display device can obtain the maximum value and the minimum value of the absolute value of the voltage corresponding to the image data signal in the 1-frame image, Vmax is equal to the maximum value of the absolute value of the voltage corresponding to the image data signal in the 1-frame image, and Vmin is equal to the minimum value of the absolute value of the voltage corresponding to the image data signal in the 1-frame image. The display device calculates the average value of Vmax and Vmin, the absolute value Vt of the first voltage is equal to the average value (Vmax+Vmin) / 2, and the absolute value of the first voltage corresponding to the pre-charge data signal is Vt.

[0058] It can be understood that the specific values of Vmax and Vmin of different frame images can be different, and the specific values of the absolute value Vt of the first voltage of the corresponding different frame images are different. Of course, the display device can also preset a fixed absolute value Vt of the first voltage, and the first stage of different frame images writes the same pre-charge data signal.

[0059] Optionally, the absolute value of the first voltage is equal to the average value of the absolute value of the voltage corresponding to the data signal of the 1-frame image.

[0060] In this embodiment, for a 1-frame image of the display panel, the display device can obtain the image data signal of each pixel in the frame image, and further can obtain the absolute value of the voltage corresponding to the image data signal of each pixel. Based on this, for the 1-frame image, the display device can obtain the maximum value and the minimum value of the absolute value of the voltage corresponding to the image data signal in the 1-frame image, Vmax is equal to the maximum value of the absolute value of the voltage corresponding to the image data signal in the 1-frame image, and Vmin is equal to the minimum value of the absolute value of the voltage corresponding to the image data signal in the 1-frame image. The display device calculates the average value of Vmax and Vmin, the absolute value Vt of the first voltage is equal to the average value (Vmax+Vmin) / 2, and the absolute value of the first voltage corresponding to the pre-charge data signal is Vt.

[0061] It can be understood that the specific values of Vmax and Vmin of different frame images can be different, and the specific values of the absolute value Vt of the first voltage of the corresponding different frame images are different. Of course, the display device can also preset a fixed absolute value Vt of the first voltage, and the first stage of different frame images writes the same pre-charge data signal.

[0062] Optionally, Gt≈(Gmax+Gmin) / 2; wherein, Gt is the gray scale corresponding to the first voltage, Gmax is the maximum gray scale value allowed to be displayed by the pixel, and Gmin is the minimum gray scale value allowed to be displayed by the pixel. For each pixel in the display device, different brightness levels can be shown by controlling the voltage of the pixel, and the gray scale represents the level of different brightness from the darkest to the brightest. The more levels of different brightness from the darkest to the brightest, the more delicate the picture effect can be presented.

[0063] For example, for an 8-bit display device, any one pixel has 256 brightness levels, which are 256 gray scales, from 0 gray scale to 255 gray scale. The maximum gray scale value Gmax allowed to be displayed by the pixel is 255, and the minimum gray scale value Gmin allowed to be displayed by the pixel is 0. The display device calculates the average value of Gmax and Gmin, and the gray scale Gt corresponding to the first voltage is approximately equal to the average value (Gmax+Gmin) / 2. The pre-charge data signal is the first voltage. Specifically, Gt can be 127 or 128. Based on the corresponding relationship between the data voltage and the gray scale, the voltage corresponding to the gray scale Gt is determined as the first voltage.

[0064] For example, for a 10-bit display device, any one pixel has 1024 brightness levels, which are 1024 gray scales, from 0 gray scale to 1023 gray scale. The maximum gray scale value Gmax allowed to be displayed by the pixel is 1023, and the minimum gray scale value Gmin allowed to be displayed by the pixel is 0. The display device calculates the average value of Gmax and Gmin, and the gray scale Gt corresponding to the first voltage is approximately equal to the average value (Gmax+Gmin) / 2. Specifically, Gt can be 511 or 512. Based on the corresponding relationship between the data voltage and the gray scale, the voltage corresponding to the gray scale Gt is determined as the first voltage.

[0065] In other embodiments, Gmax can also be the maximum grayscale value allowed to be displayed by a pixel in one frame of an image, and Gmin can be the minimum grayscale value allowed to be displayed by a pixel in one frame of an image. For one frame of an image on a display panel, the display device can obtain the grayscale value corresponding to the image data signal of each pixel in that frame of the image, and thus obtain the maximum and minimum grayscale values ​​corresponding to the image data signal in one frame of the image. Gmax is equal to the maximum grayscale value corresponding to the image data signal in one frame of the image, and Gmin is equal to the minimum grayscale value corresponding to the image data signal in one frame of the image. The display device calculates the average value of Gmax and Gmin, and the grayscale value Gt corresponding to the first voltage is approximately equal to this average value (Gmax + Gmin) / 2. It is understood that the specific values ​​of Gmax and Gmin may be different for different frames of the image, and the specific values ​​of the first voltage may be different for different frames of the image.

[0066] The grayscale value corresponding to the first voltage can be denoted as Gt, where Gt is equal to the average grayscale value displayed by each pixel in one frame of the image. For one frame of the display panel, the display device can obtain the grayscale value corresponding to the image data signal of each pixel in that frame, and then calculate the average grayscale value based on the grayscale values ​​of each pixel in the frame. The grayscale value Gt corresponding to the first voltage is this average grayscale value. It can be understood that the grayscale values ​​of each pixel in different frames of the image may be different, and the specific value of the first voltage in different frames of the image will be different.

[0067] The gray level corresponding to the first voltage can be selected as the first gray level; the total number of gray levels that a pixel is allowed to display is M, and the M gray levels include one first gray level and (M-1) second gray levels; ta≤tb; where ta is the sum of the time from the first gray level to each gray level, and tb is the sum of the time from the second gray level to each gray level.

[0068] Taking an 8-bit display device as an example, the total number of gray levels that a pixel can display is M = 256, which range from gray level 0 to gray level 255. Before leaving the factory, testing is performed, controlling the pixel to display gray level 1, and testing the time t for the transition from gray level 1 to gray level 0. 1 / 0 The time t for transitioning from grayscale 1 to grayscale 2 1 / 2 The time t for transitioning from grayscale 1 to grayscale 3 1 / 3 And so on, the time t for transitioning from grayscale 1 to grayscale 255. 1 / 255 Calculate t 1 / 0 +t 1 / 2 +t 1 / 3 +…+t 1 / 255 This sum is defined as the total time taken to transition from grayscale 1 to each of the subsequent grayscale levels. Sequentially, pixels are displayed as grayscale 2, and the time t taken to transition from grayscale 2 to grayscale 0 is measured. 2 / 0 The time t for transitioning from grayscale 2 to grayscale 12 / 1 the time length t of 2 gray scale to 3 gray scale 2 / 3 and so on, the time length t of 2 gray scale to 255 gray scale 2 / 255 calculate t 2 / 0 t 2 / 1 t 2 / 3 t 2 / 255 The sum value is determined as the sum of the time of 2 gray scale to each gray scale. In turn, the pixel is displayed as 255 gray scale, and the sum of the time of 255 gray scale to each gray scale is tested. The gray scale corresponding to the minimum value of the sum of the time is determined as the first gray scale, and the first gray scale is stored in the display device. It can be understood that the time of A gray scale to B gray scale is the corresponding liquid crystal response time. Table 1 below is the liquid crystal response time of one gray scale value to each gray scale in an 8-bit display device, wherein the data other than the gray scale value is the time length, and the unit is ms.

[0069] Table 1

[0070] Grey scale 0 31 63 95 127 159 191 223 255 0 23.4 23.4 24.8 24.2 22.3 19.4 15.4 7.1 31 9.2 21.8 23.0 23.6 22.2 19.2 15.2 6.9 63 9.4 16.0 23.9 23.8 22.0 19.2 15.3 7.0 95 9.5 15.1 19.6 21.9 21.0 18.5 15.1 7.0 127 9.7 14.2 18.4 21.1 19.9 17.8 14.3 6.8 159 10.0 13.7 17.4 20.0 20.3 17.9 14.3 6.6 191 10.4 13.7 17.0 19.3 19.8 18.9 14.6 6.5 223 10.9 13.9 17.0 19.1 19.9 19.0 17.0 6.4 255 12.0 14.8 17.7 19.8 20.6 20.1 19.0 15.7

[0071] From the results of Table 1 actually measured, the following trends can be found:

[0072] 1) Within 0-127 gray scales, the liquid crystal response time is longer when driving from low gray scale to high gray scale; for example, the time length of G0 (0 gray scale) to G63 (63 gray scale) is 23.4 ms, and the time length of G63 to G0 is 9.4 ms.

[0073] 2) Within 127-255 gray scales, the liquid crystal response speed difference is small when driving from low gray scale to high gray scale or driving from high gray scale to low gray scale; for example, the time length of G127 to G223 is 14.3 ms, and the time length of G223 to G127 is 19.9 ms.

[0074] It is found through testing that the sum of the time of 127 gray scale to each gray scale is less than the sum of the time of any other gray scale to each gray scale, so 127 gray scale can be determined as the first gray scale, and the voltage corresponding to 127 gray scale is determined as the first voltage. In practical applications, when the display panel displays one frame of image, the display device writes the pre-charge data signal to the pixel in the first stage based on the pre-set pre-charge data signal. Considering the effect of the barrel effect, the time of backlight lighting is the longest liquid crystal response time, so pre-charging the data signal corresponding to 127 gray scale to the pixel can reduce the liquid crystal response time as a whole, thereby lengthening the backlight lighting time.

[0075] The gray scale corresponding to the optional first voltage is a third gray scale; one frame of image includes different N gray scales, N is greater than 1, the N gray scales include one third gray scale and (N-1) fourth gray scales; tc≤td; wherein, tc is the sum of the time from the third gray scale to each gray scale in one frame of image, td is the sum of the time from the fourth gray scale to each gray scale in one frame of image.

[0076] Before factory, test to establish the mapping table of gray scale and time (such as table 1). Taking 8bit display device as an example, the total number of gray scales allowed to be displayed by the pixel is M=256, and the 256 gray scales are 0 gray scale to 255 gray scale. Before factory, test, control the pixel to display 1 gray scale, test the time t 1 / 0 from 1 gray scale to 0 gray scale 1 / 2 from 1 gray scale to 2 gray scale 1 / 3 from 1 gray scale to 3 gray scale 1 / 255 , and so on, the time t C1 from 1 gray scale to 255 gray scale C2 Record each time and gray scale transition relationship. In order, the pixel displays 2 gray scale, tests the time from 2 gray scale to each gray scale, and records each time and gray scale transition relationship. In order, the pixel displays 255 gray scale, tests the time from 255 gray scale to each gray scale, and records each time and gray scale transition relationship. Thus, the mapping table of gray scale and time similar to table 1 is established.

[0077] In actual application, for the 1 frame image of the display panel, the display device can obtain the gray scale value corresponding to the image data signal of each pixel in the frame image, there may be multiple pixels with the same gray scale value in the 1 frame image, and then the gray scale value of the multiple pixels is counted as one. Taking 8bit display device as an example, the total number of gray scales included in 1 frame image N may be equal to 256, or N may be less than 256. The N gray scales in 1 frame image are arranged in ascending order as G C1 , G C2 , G C3 , G C4 , …, G CN , and the third gray scale is determined in combination with the mapping table of gray scale and time. Specifically, for G C1 , the time from G C1 to G C2 , the time from G C1 to G C3 , the time from G C1 to G C4 , …, the time from G C1 to G CN is extracted from the mapping table of gray scale and time, and the sum of the (N-1) times is calculated. The sum value is determined as G C1The sum of the time of transition to (N-1) gray scales. In sequence, for G C2 The gray scale corresponding to the minimum value of the sum of the time of transition to (N-1) gray scales is determined as the third gray scale. C2 The time of transition to G C1 The time of transition to G C2 The time of transition to G C3 The time of transition to G C2 The time of transition to G C4 The time of transition to G C2 The time of transition to G CN The sum of the time of transition to (N-1) gray scales. In sequence, for G C2 The gray scale corresponding to the minimum value of the sum of the time of transition to (N-1) gray scales is determined as the third gray scale. CN The gray scale corresponding to the minimum value of the sum of the time of transition to (N-1) gray scales is determined as the third gray scale. CN The sum of the time of transition to (N-1) gray scales. The gray scale corresponding to the minimum value of the sum of the time of transition to (N-1) gray scales is determined as the third gray scale.

[0078] For example, for 1 frame of image, it is found that the sum of the time of transition to other (N-1) gray scales of 91 gray scale is less than the sum of the time of transition to each gray scale of other any gray scale, then 91 gray scale is determined as the third gray scale of the frame of image, and the voltage corresponding to 91 gray scale is determined as the voltage corresponding to the pre-charge data signal. Based on this, when the display panel displays the frame of image, the display device writes the voltage corresponding to 91 gray scale to the pixel in the first stage. Pre-charging the data signal to the pixel can reduce the liquid crystal response time of 1 frame of image as a whole, thereby prolonging the backlight lighting time of the frame of image. It can be understood that the third gray scale of different frames of image can be different.

[0079] Figure 9 is another schematic diagram of a display device provided by an embodiment of the present application, as shown in Figure 9 The optional display device further includes a plurality of scan lines SL, a gate drive circuit 210, a first switch unit 220, a first power supply line VG1, and a first switch control line CKA. The gate drive circuit 210 is electrically connected to the plurality of scan lines SL, and one scan line SL is electrically connected to one pixel row in correspondence. The input end of the first switch unit 220 is electrically connected to the first power supply line VG1, the output end of the first switch unit 220 is electrically connected to the scan line SL, and the control end of the first switch unit 220 is electrically connected to the first switch control line CKA. The refresh stage includes: in the first stage, the first switch control line CKA controls the first switch unit 220 to be turned on, and the first power supply signal provided by the first power supply line VG1 is transmitted to the scan line SL through the first switch unit 220; in the second stage, the first switch control line CKA controls the first switch unit 220 to be turned off.

[0080] In this embodiment, the display device includes a plurality of scan lines SL and a gate driving circuit 210. The scan lines SL extend along the F1 direction, and the plurality of scan lines SL are arranged along the F2 direction and sequentially labeled as SL1, SL2, SL3, SL4, …, one scan line SL is electrically connected to one pixel row, and the plurality of pixels 121 in the pixel row are arranged along the F1 direction. The gate driving circuit 210 is electrically connected to the plurality of scan lines SL, and the gate driving circuit 210 provides a scan signal to the plurality of scan lines SL. For example, the gate driving circuit 210 provides an effective scan signal to the scan line SL1 to turn on the first row of pixels 121, and a data signal can be written to the pixels 121; sequentially, the gate driving circuit 210 provides an effective scan signal to the scan line SL2 to turn on the second row of pixels 121, and a data signal can be written to the pixels 121; and so on.

[0081] The display device includes a plurality of first switch units 220, a first power supply line VG1, and a first switch control line CKA. One first switch unit 220 is electrically connected to one scan line SL. For any one first switch unit 220, the input end of the first switch unit 220 is electrically connected to the first power supply line VG1, the output end of the first switch unit 220 is electrically connected to the corresponding scan line SL, and the control end of the first switch unit 220 is electrically connected to the first switch control line CKA. The control ends of the first switch units 220 in the optional display panel are electrically connected to the same first switch control line CKA. Optionally, the first switch unit 220 is an N-type transistor, and the first switch control line CKA provides a high-level signal to control the corresponding first switch units 220 to be turned on at the same time; the first switch control line CKA provides a low-level signal to control the corresponding first switch units 220 to be turned off at the same time. In other embodiments, the first switch unit can also be a P-type transistor.

[0082] In other embodiments, the first switch units in the optional display panel are divided into at least two groups, which are suitable for Figure 8 The driving timing of the display device is shown. Figure 10 is another schematic diagram of a display device provided by an embodiment of the present application, which is different from Figure 9 in that, Figure 10 In the display panel in the embodiment, the display panel includes two first switch control lines CKA1 and CKA2, the first switch control line CKA1 is connected to the control ends of the plurality of first switch units 220, and the first switch control line CKA2 is connected to the control ends of the other plurality of first switch units 220. In combination with Figure 8 and Figure 10As shown, the refresh phase of the display panel can include two refresh sub-phases; in the first phase T11a of the refresh sub-phase T10a, the first switch control line CKA1 provides a valid signal to control the corresponding first switch units 220 to be turned on simultaneously; in the first phase T11b of the refresh sub-phase T10b, the first switch control line CKA2 provides a valid signal to control the corresponding first switch units 220 to be turned on simultaneously.

[0083] like Figure 9 As shown, the optional display device also includes multiple data lines DL, multiple data source lines SIL, a gating drive circuit 230, multiple second switch units 240, multiple clock control lines CKB, a second power supply line VG2, and a second switch control line CKC; one data line DL is electrically connected to one pixel column; the gating drive circuit 230 includes multiple output terminals electrically connected to the multiple data lines DL, multiple input terminals electrically connected to the multiple data source lines SIL, and multiple control terminals electrically connected to the multiple second switch units 240. The gating drive circuit 230 is used to transmit the data signal of the data source line SIL to the data line DL based on the control of the output signal of the second switch unit 240; the second switch unit 240 includes a first input terminal, a second input terminal, a total output terminal, and a total control terminal. The first input terminal is electrically connected to the second power supply line VG2, and the second input terminal is electrically connected to the clock control line CKC. The clock control line CKB is electrically connected to the control terminal of the gating drive circuit 230, and the control terminal is electrically connected to the second switch control line CKC. The refresh phase includes: in the first phase, the signal provided by the second switch control line CKC controls the transmission path between the first input terminal and the total output terminal of the second switch unit 240 to be connected, and the second power signal provided by the second power line VG2 is transmitted to the control terminal of the gating drive circuit 230 through the second switch unit 240, so that the transmission path between the input terminal and the output terminal of the gating drive circuit 230 is connected, and the data source line SIL provides a precharge data signal; in the second phase, the signal provided by the second switch control line CKC controls the transmission path between the second input terminal and the total output terminal of the second switch unit 240 to be connected, and the clock signal provided by the clock control line CKB is transmitted to the control terminal of the gating drive circuit 230 through the second switch unit 240, and the data source line SIL provides an image data signal.

[0084] In this embodiment, the display device includes a plurality of data lines DL, a plurality of data source lines SIL and a gate drive circuit 230. One data line DL is electrically connected to one pixel column, and one pixel column includes a plurality of pixels 121 arranged along the F2 direction. A plurality of output terminals of the gate drive circuit 230 are electrically connected to the plurality of data lines DL one by one, and a plurality of input terminals of the gate drive circuit 230 are electrically connected to the plurality of data source lines SIL one by one. The plurality of data source lines SIL are arranged along the F2 direction and are sequentially marked as SIL(1), SIL(2), … The gate drive circuit 230 is configured to selectively output signals of the data source lines SIL to the data lines DL.

[0085] The display device includes a plurality of second switch units 240, a plurality of clock control lines CKB, a second power line VG2 and a second switch control line CKC. A row of pixels 121 in the optional display panel includes a red pixel R, a green pixel G and a blue pixel B. The display device can include three clock control lines CKB1, CKB2 and CKB3. The clock control line CKB1 provides an effective clock signal that can be used to drive the red pixel R to work. The clock control line CKB2 provides an effective clock signal that can be used to drive the green pixel G to work. The clock control line CKB3 provides an effective clock signal that can be used to drive the blue pixel B to work. Correspondingly, the display device includes three second switch units 240a, 240b and 240c. The gate drive circuit 230 includes three control terminals CT1, CT2 and CT3 electrically connected to the three second switch units 240 one by one. The total output terminal of the second switch unit 240a is connected to the first control terminal CT1 of the gate drive circuit 230. The total output terminal of the second switch unit 240b is connected to the second control terminal CT2 of the gate drive circuit 230. The total output terminal of the second switch unit 240c is connected to the third control terminal CT3 of the gate drive circuit 230. The gate drive circuit 230 is configured to transmit data signals of the data source lines SIL to the data lines DL based on the control of the second switch unit 240.

[0086] The first input end of each second switch unit 240 is electrically connected to the second power supply line VG2. The second input end of the second switch unit 240 is electrically connected to the clock control line CKB. Specifically, the second input end of the second switch unit 240a is electrically connected to the clock control line CKB1, the second input end of the second switch unit 240b is electrically connected to the clock control line CKB2, and the second input end of the second switch unit 240c is electrically connected to the clock control line CKB3. The global control end of each second switch unit 240 is electrically connected to the second switch control line CKC. The second switch control line CKC is used to control the transmission path between the first input end and the global output end of each second switch unit 240 to be turned on at the same time, and the transmission path between the second input end and the global output end of each second switch unit 240 to be turned off at the same time; or the second switch control line CKC is used to control the transmission path between the first input end and the global output end of each second switch unit 240 to be turned off at the same time, and the transmission path between the second input end and the global output end of each second switch unit 240 to be turned on at the same time.

[0087] In combination Figure 3 and Figure 9 As shown in FIG. 1, when the display panel displays 1 frame of image, the refresh stage T10 includes the first stage T11 and the second stage T12.

[0088] In the first stage T11, the first switch control line CKA provides an effective signal to control each first switch unit 220 to be turned on at the same time, and the first power supply signal provided by the first power supply line VG1 is transmitted to each scanning line SL through each first switch unit 220 at the same time. The first power supply signal provided by the first power supply line VG1 can turn on the pixel 121, that is, each pixel 121 is turned on at the same time. At the same time, the signal provided by the second switch control line CKC controls the transmission path between the first input end and the global output end of the second switch unit 240 to be turned on, and the second power supply signal provided by the second power supply line VG2 is transmitted to the control end CT of the gate drive circuit 230 through the second switch unit 240, so that the transmission path between the input end and the output end of the gate drive circuit 230 is turned on. Then, the pre-charge data signal provided by the data source line SIL is transmitted to each data line DL, and the pre-charge data signal is written to the pixel 121.

[0089] In the second stage T12, the first switch control line CKA controls the first switch unit 220 to be off, and the gate drive circuit 210 provides the scanning signal to the plurality of scanning lines SL, so that the pixel rows can be driven to be turned on in the row-by-row scanning mode. Taking the first row of pixels 121 as an example, the gate drive circuit 210 provides the effective scanning signal to the scanning line SL1 to turn on the first row of pixels 121. At the same time, the signal provided by the second switch control line CKC controls the transmission path between the second input end of the second switch unit 240 and the total output end to be turned on, so that the clock signal provided by the clock control line CKB1 is transmitted to the control end CT1 of the gate drive circuit 230 through the second switch unit 240a, the clock signal provided by the clock control line CKB2 is transmitted to the control end CT2 of the gate drive circuit 230 through the second switch unit 240b, and the clock signal provided by the clock control line CKB3 is transmitted to the control end CT3 of the gate drive circuit 230 through the second switch unit 240c. The gate drive circuit 230 transmits the image data signal provided by the data source line SIL to the corresponding data line DL based on the clock signals provided by the clock control lines CKB1, CKB2 and CKB3, so as to write the image data signal to the first row of pixels 121.

[0090] Figure 11 is a schematic diagram of still another display device provided by an embodiment of the present application, as shown in Figure 11 The optional second switch unit 240 includes a first switch device M1 and a second switch device M2, the second switch control line CKC includes a first sub-switch control line CKC1 and a second sub-switch control line CKC2, the control end of the first switch device M1 is electrically connected to the first sub-switch control line CKC1, and the input end of the first switch device M1 is electrically connected to the second power supply line VG2; the control end of the second switch device M2 is electrically connected to the second sub-switch control line CKC2, and the input end of the second switch device M2 is electrically connected to the corresponding clock control line CKB; the output end of the first switch device M1 and the output end of the second switch device M2 are both electrically connected to the total output end of the second switch unit 240; the refresh stage includes: in the first stage, the signal provided by the first sub-switch control line CKC1 controls the first switch device M1 to be turned on, the signal provided by the second sub-switch control line CKC2 controls the second switch device M2 to be turned off, and the second power supply signal provided by the second power supply line VG2 is transmitted to the control end CT of the gate drive circuit 230 through the first switch device M1; in the second stage, the signal provided by the first sub-switch control line CKC1 controls the first switch device M1 to be turned off, the signal provided by the second sub-switch control line CKC2 controls the second switch device M2 to be turned on, and the clock signal provided by the clock control line CKB is transmitted to the control end CT of the gate drive circuit 230 through the second switch device M2.

[0091] In the embodiment, the first switch device M1 and the second switch device M2 can be N-type transistors. The first sub-switch control line CKC1 is connected to the control end of the first switch device M1, and thus the first sub-switch control line CKC1 provides a high-level signal to simultaneously turn on the first switch devices M1, and provides a low-level signal to simultaneously turn off the first switch devices M1. The second sub-switch control line CKC2 is connected to the control end of the second switch device M2, and thus the second sub-switch control line CKC2 provides a high-level signal to simultaneously turn on the second switch devices M2, and provides a low-level signal to simultaneously turn off the second switch devices M2. The input end of the first switch device M1 is electrically connected to the second power supply line VG2. The input end of the second switch device M2 is electrically connected to the corresponding clock control line CKB.

[0092] In combination Figure 3 and Figure 11 As shown in FIG. 11, in the first stage T11, the signal provided by the first sub-switch control line CKC1 controls the first switch device M1 to turn on, and the signal provided by the second sub-switch control line CKC2 controls the second switch device M2 to turn off, and thus the second power supply signal provided by the second power supply line VG2 is transmitted to the control end CT of the gate drive circuit 230 through the first switch device M1, so that the transmission path between the input end and the output end of the gate drive circuit 230 is turned on, and the pre-charge data signal provided by the data source line SIL is transmitted to each data line DL to write the pixel 121.

[0093] In the second stage T12, the signal provided by the first sub-switch control line CKC1 controls the first switch device M1 to turn off, and the signal provided by the second sub-switch control line CKC2 controls the second switch device M2 to turn on, and the clock signal provided by the clock control line CKB is transmitted to the control end CT of the gate drive circuit 230 through the second switch device M2, and the gate drive circuit 230 transmits the image data signal provided by the data source line SIL to the corresponding data line DL based on the clock signals provided by the clock control lines CKB1, CKB2 and CKB3, to write the image data signal to the turned-on pixel 121.

[0094] In other embodiments, the first switch device and the second switch device can also be P-type transistors. Alternatively, refer to Figure 9The first switch device M1 and the second switch device M2 can also be different types of transistors, where the first switch device M1 can be a P-type transistor and the second switch device M2 can be an N-type transistor, and the control terminal of the first switch device M1 and the control terminal of the second switch device M2 are connected to the same second switch control line CKC, and the second switch control line CKC provides a high-level signal to turn off the first switch device M1 and turn on the second switch device M2, and the second switch control line CKC provides a low-level signal to turn on the first switch device M1 and turn off the second switch device M2.

[0095] The first power supply line VG1 and the second power supply line VG2 can be electrically connected to the same power supply signal terminal. If the high-level signal transmitted by the scan line SL can control the pixel 121 to turn on, and the high-level signal provided by the second switch unit 240 can control the transmission path between the input terminal and the output terminal of the gate drive circuit 230 to be conductive, then the first power supply line VG1 and the second power supply line VG2 are electrically connected to the same power supply signal terminal, and the power supply signal terminal provides a high-level signal. Similarly, if the low-level signal transmitted by the scan line SL can control the pixel 121 to turn on, and the low-level signal provided by the second switch unit 240 can control the transmission path between the input terminal and the output terminal of the gate drive circuit 230 to be conductive, then the first power supply line VG1 and the second power supply line VG2 are electrically connected to the same power supply signal terminal, and the power supply signal terminal provides a low-level signal.

[0096] It should be noted that, Figure 9 to Figure 11 The various display devices shown are only examples, and the circuit structure of the display device in the present application includes but is not limited to the above-mentioned examples, and related professionals can reasonably design the circuit structure of the display device according to product needs; for example, the first switch device M1 can be an N-type transistor, and the second switch device M2 can be a P-type transistor, but not limited thereto.

[0097] Figure 12 is a schematic diagram of another driving timing of a display device provided by an embodiment of the present application. In combination with Figure 9 and Figure 12 As shown, the first switch unit 220 can include an N-type transistor. The first power supply line VG1 and the second power supply line VG2 provide the same high-level signal. The switch device M3 in the gate drive circuit 230 can be an N-type transistor.

[0098] In the first stage T11, the first switch control line CKA provides a high level signal to control the first switch units 220 to be turned on simultaneously, and the first power supply line VG1 provides a first power supply signal to the scanning line SL to turn on the pixel 121. Meanwhile, the second switch control line CKC provides a low level signal to control the first switch device M1 to be turned on and the second switch device M2 to be turned off, and the second power supply line VG2 provides a high level signal to the control terminal CT of the gate-on driving circuit 230 through the first switch device M1, so that the switch device M3 in the gate-on driving circuit 230 is turned on simultaneously, and the transmission path between the input terminal and the output terminal of the gate-on driving circuit 230 is turned on, and the pre-charge data signal Vt provided by the data source line SIL is transmitted to each data line DL to write the pre-charge data signal into the pixel 121.

[0099] In the second stage T12, the first switch control line CKA provides a low level signal to control the first switch units 220 to be turned off simultaneously. The gate driving circuit 210 provides a scanning signal to the plurality of scanning lines SL to drive the pixel rows to be turned on row by row in a row-by-row scanning mode. Meanwhile, the second switch control line CKC provides a high level signal to control the first switch device M1 to be turned off and the second switch device M2 to be turned on, and the clock control line CKB1 provides a clock signal to the control terminal CT1 of the gate-on driving circuit 230, the clock control line CKB2 provides a clock signal to the control terminal CT2 of the gate-on driving circuit 230, and the clock control line CKB3 provides a clock signal to the control terminal CT3 of the gate-on driving circuit 230. The gate-on driving circuit 230 transmits the image data signal provided by the data source line SIL to the corresponding data line DL based on the clock signals provided by the clock control lines CKB1, CKB2 and CKB3 to write the image data signal into the turned-on pixel 121.

[0100] The display device can include at least two display panels, and the at least two display panels can include a first display panel and a second display panel arranged along a second direction; the display device can include at least two backlight modules, and one backlight module can correspond to one display panel; in a refresh stage of one frame of image, a second stage of the second display panel can be started after a second stage of the first display panel is ended.

[0101] Figure 13 is a schematic diagram of another display device provided by an embodiment of the present application, as Figure 13As shown, the display device includes a first display panel 120A and a second display panel 120B arranged along a F2 direction, and the display device includes a first backlight module 110A and a second backlight module 110B arranged along the F2 direction. The first backlight module 110A corresponds to the first display panel 120A and is configured to provide backlight for the first display panel 120A. The second backlight module 110B corresponds to the second display panel 120B and is configured to provide backlight for the second display panel 120B. The F2 direction can be parallel to the direction of the data line DL, and the F1 direction intersecting the F2 direction can be parallel to the direction of the scan line SL. If the display device is in a line-by-line scanning mode, the display device performs line-by-line scanning along the F2 direction. The display operation of the first display panel 120A and the second display panel 120B can be independent of each other, and the backlight operation of the first backlight module 110A and the second backlight module 110B can be independent of each other.

[0102] Figure 14 is Figure 13 a schematic diagram of the driving timing of the display device. As Figure 13 and Figure 14 shown, in the refresh stage of the 1 frame image, after the second stage T12(A) of the first display panel 120A ends, the second stage T12(B) of the second display panel 120B starts.

[0103] The display device displays the (x)th frame image, and the first display panel 120A and the second display panel 120B can optionally perform the first stage in time. For example, in the refresh stage of the 1 frame image, after the second stage of the first display panel 120A ends and before the second stage of the second display panel 120B starts, the second display panel 120B performs the first stage, and the working process of the (x)th frame image includes at least the first stage T11(A), the second stage T12(A), the first stage T11(B), and the second stage T12(B) performed in sequence. In the first stage T11(A), the pre-charge data signal is written to the pixels of the first display panel 120A; in the second stage T12(A), the image data signal is written to the pixels of the first display panel 120A; in the first stage T11(B), the pre-charge data signal is written to the pixels of the second display panel 120B; and in the second stage T12(B), the image data signal is written to the pixels of the second display panel 120B.

[0104] The working process of the (x)th frame image further includes a first backlight lighting stage T20(A), which is after the second stage T12(A), as Figure 14The optional first backlight lighting stage T20(A) is shown after the second stage T12(B). However, in other embodiments, the first backlight lighting stage T20(A) can also overlap with the second stage T12(B) based on the liquid crystal response time. In the first backlight lighting stage T20(A), the liquid crystal response of the first display panel 120A has been completed, and the first backlight module 110A is controlled to be lit to provide backlight for the first display panel 120A.

[0105] The display device displays A frames of images, 0 < x < A, A > 2; and a part of the refresh stage of the (x+1) frame of the first display panel overlaps with the backlight lighting stage of the x frame of the second display panel.

[0106] Reference Figure 14 As shown, for the (x) frame of image, after the image data signal is written to the pixel of the first display panel 120A, the pixel performs liquid crystal response; sequentially, after the image data signal is written to the pixel of the second display panel 120B, the pixel performs liquid crystal response. Obviously, in the 1 frame of image, the liquid crystal response of the first display panel 120A is completed first, and then the first backlight module 110A is lit during the stage that the pixel of the second display panel 120B performs image data signal or during the stage that the pixel of the second display panel 120B performs liquid crystal response. After the backlight process of the first backlight module 110A is completed, the first display panel 120A enters the (x+1) frame of image. For the (x+1) frame of image, during the stage that the image data signal is written to the pixel of the first display panel 120A, the liquid crystal response of the second display panel 120B in the (x) frame of image can be completed, and then the second backlight module 110B is lit to provide backlight for the second display panel 120B. Therefore, a part of the refresh stage of the (x+1) frame of image of the first display panel 120A overlaps with the backlight lighting stage of the x frame of image of the second display panel 120B. This is beneficial to realize high-frequency display.

[0107] After the display device is powered on, the initial 1-3 frames of boot image can not be pre-charged, and after the display device enters the normal display image, the pre-charging is started, for example, the pre-charging is started from the 3rd frame.

[0108] Based on the same inventive concept, the embodiments of the present application also provide a display device, which comprises the display device as described in any of the above embodiments. Figure 15 is a schematic diagram of a display device provided by the embodiments of the present application, as Figure 15 As shown, the display device 1 comprises the display device. Therefore, the display device also has the beneficial effects of the display device in the above embodiments, and the same parts can be understood with reference to the above explanation and description of the display device, and the following will not be repeated.

[0109] The display device 1 provided by the embodiment of the present application can be Figure 15 a smart phone as shown in the figure, or any electronic product with display function, including but not limited to the following categories: VR display device, television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, industrial control device, medical display screen, touch interactive terminal, etc., which are not specially limited by the embodiment of the present application.

[0110] Based on the same inventive concept, the embodiment of the present application further provides a driving method of a display device, which is suitable for the display device as described in any of the above embodiments, and can be executed by a driving structure which can be realized in the form of hardware and / or software and can be configured in the display device. Figure 16 is a schematic diagram of a driving method of a display device provided by the embodiment of the present application, as shown in the figure, the driving method of the display device comprises: Figure 16

[0111] Step 310, in the first stage, a pre-charge data signal is written to the pixel, the voltage corresponding to the pre-charge data signal is the first voltage, and the gray scale corresponding to the first voltage is greater than 0;

[0112] Step 320, in the second stage, an image data signal is written to the pixel;

[0113] Step 330, in the backlight lighting stage, the backlight module is controlled to be turned on.

[0114] The optional driving method comprises: at least part of the pixel rows simultaneously execute the first stage.

[0115] Optionally, Vt=(Vmax+Vmin) / 2; wherein, Vt is the absolute value of the first voltage, Vmax is the maximum value of the absolute value of the voltage corresponding to the data signal of 1 frame of image, and Vmin is the minimum value of the absolute value of the voltage corresponding to the data signal of 1 frame of image.

[0116] Optionally, the gray scale corresponding to the first voltage is the first gray scale; the total number of gray scales allowed to be displayed by one pixel is M, the M gray scales include one first gray scale and (M-1) second gray scales; ta≤tb; wherein, ta is the sum of the time from the first gray scale to each gray scale, and tb is the sum of the time from the second gray scale to each gray scale.

[0117] The driving method provided by the embodiment of the present application is suitable for the display device as described in any of the above embodiments, and the driving process of the display device has been described in the above embodiments, which will not be described in detail here. It can be understood that the driving method also has the beneficial effects of the display device in the above embodiments, and the same parts can be understood by referring to the above explanation and description of the display device, which will not be described hereinafter.​

[0118] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps described in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0119] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display device, characterized in that, include: Display panel and backlight module; The display panel includes a plurality of pixels arranged in an array, wherein the plurality of pixels arranged along a first direction form a pixel row, and the plurality of pixels arranged along a second direction form a pixel column, wherein the first direction and the second direction intersect. When the display panel displays one frame of image, its working process includes a refresh phase and a backlight illumination phase. The refresh phase includes a first phase and a second phase executed sequentially; in the first phase, a precharge data signal is written to the pixel, the voltage corresponding to the precharge data signal is a first voltage, and the gray level corresponding to the first voltage is greater than 0; in the second phase, an image data signal is written to the pixel. During the backlight illumination phase, the backlight module is controlled to turn on. The display device includes at least two display panels, the at least two display panels including a first display panel and a second display panel arranged along the second direction; The display device includes at least two backlight modules, and one backlight module corresponds to one display panel; During the refresh phase of the 1-frame image, the second phase of the second display panel begins after the second phase of the first display panel ends. The display device displays an A-frame image, where 0 < x ≤ A and A is greater than 2; A portion of the time period during the refresh phase of the (x+1)th frame image of the first display panel overlaps with the backlight illumination phase of the xth frame image of the second display panel.

2. The display device according to claim 1, characterized in that, At least some of the pixel rows simultaneously perform the first phase.

3. The display device according to claim 1, characterized in that, The display panel contains two adjacent pixel rows, wherein the end time of the second stage of one pixel row is earlier than or equal to the start time of the first stage of the other pixel row.

4. The display device according to claim 1, characterized in that, Vt = (Vmax + Vmin) / 2; Wherein, Vt is the absolute value of the first voltage, Vmax is the maximum absolute value of the voltage corresponding to the data signal of the 1 frame image, and Vmin is the minimum absolute value of the voltage corresponding to the data signal of the 1 frame image.

5. The display device according to claim 1, characterized in that, The absolute value of the first voltage is equal to the average absolute value of the voltage corresponding to the data signal of the 1 frame image.

6. The display device according to claim 1, characterized in that, Gt≈(Gmax+Gmin) / 2; Wherein, Gt is the gray level corresponding to the first voltage, Gmax is the maximum gray level value allowed to be displayed by the pixel, and Gmin is the minimum gray level value allowed to be displayed by the pixel.

7. The display device according to claim 1, characterized in that, The gray level corresponding to the first voltage is Gt, and Gt is equal to the average gray level value displayed by each pixel in the 1-frame image.

8. The display device according to claim 1, characterized in that, The gray level corresponding to the first voltage is the first gray level; The total number of gray levels that a pixel is allowed to display is M, and the M gray levels include one first gray level and (M-1) second gray levels; ta≤tb; Where ta is the sum of the time required to transition from the first gray level to each of the gray levels, and tb is the sum of the time required to transition from the second gray level to each of the gray levels.

9. The display device according to claim 1, characterized in that, The gray level corresponding to the first voltage is the third gray level; The image frame includes N different gray levels, where N is greater than 1, and the N gray levels include one third gray level and (N-1) fourth gray levels; tc≤td; Wherein, tc is the sum of the times for the transition from the third gray level to each of the gray levels in the 1-frame image, and td is the sum of the times for the transition from the fourth gray level to each of the gray levels in the 1-frame image.

10. The display device according to claim 1, characterized in that, The display device also includes multiple scan lines, a gate driving circuit, a first switching unit, a first power supply line, and a first switching control line; The gate driving circuit is electrically connected to the plurality of scan lines, and each scan line is electrically connected to one pixel row. The input terminal of the first switching unit is electrically connected to the first power supply line, the output terminal of the first switching unit is electrically connected to the scan line, and the control terminal of the first switching unit is electrically connected to the first switch control line. The refresh phase includes: In the first stage, the first switch control line controls the first switch unit to turn on, and the first power signal provided by the first power line is transmitted to the scan line through the first switch unit. In the second stage, the first switch control line controls the first switch unit to turn off.

11. The display device according to claim 10, characterized in that, The display device also includes multiple data lines, multiple data source lines, a gating drive circuit, multiple second switch units, multiple clock control lines, a second power supply line, and a second switch control line; One of the data lines is electrically connected to one of the pixel columns; The gating drive circuit includes multiple output terminals electrically connected to each of the multiple data lines, multiple input terminals electrically connected to each of the multiple data source lines, and multiple control terminals electrically connected to each of the multiple second switch units. The gating drive circuit is used to transmit the data signal of the data source line to the data line based on the control of the output signal of the second switch unit. The second switching unit includes a first input terminal, a second input terminal, a total output terminal, and a total control terminal. The first input terminal is electrically connected to the second power supply line, the second input terminal is electrically connected to the clock control line, the total output terminal is electrically connected to the control terminal of the gating drive circuit, and the total control terminal is electrically connected to the second switch control line. The refresh phase includes: In the first stage, the signal provided by the second switch control line controls the transmission path between the first input terminal of the second switch unit and the total output terminal to be connected. The second power signal provided by the second power line is transmitted to the control terminal of the gating drive circuit through the second switch unit, so that the transmission path between the input terminal and the output terminal of the gating drive circuit is connected. The data source line provides the precharge data signal. In the second stage, the signal provided by the second switch control line controls the transmission path between the second input terminal of the second switch unit and the total output terminal to be connected, the clock signal provided by the clock control line is transmitted to the control terminal of the gating drive circuit through the second switch unit, and the data source line provides the image data signal.

12. The display device according to claim 11, characterized in that, The second switching unit includes a first switching device and a second switching device; The second switch control line includes a first sub-switch control line and a second sub-switch control line; The control terminal of the first switching device is electrically connected to the control line of the first sub-switch, and the input terminal of the first switching device is electrically connected to the second power line; The control terminal of the second switching device is electrically connected to the control line of the second sub-switch, and the input terminal of the second switching device is electrically connected to the corresponding clock control line; The output terminals of the first and second switching devices are both electrically connected to the total output terminal of the second switching unit; The refresh phase includes: In the first stage, the signal provided by the first sub-switch control line controls the first switching device to turn on, the signal provided by the second sub-switch control line controls the second switching device to turn off, and the second power signal provided by the second power line is transmitted to the control terminal of the gating drive circuit through the first switching device. In the second stage, the signal provided by the first sub-switch control line controls the first switching device to turn off, the signal provided by the second sub-switch control line controls the second switching device to turn on, and the clock signal provided by the clock control line is transmitted to the control terminal of the gating drive circuit through the second switching device.

13. The display device according to claim 11, characterized in that, The first power line and the second power line are electrically connected to the same power signal terminal.

14. The display device according to claim 1, characterized in that, During the refresh phase of the 1-frame image, the second display panel executes the first phase after the second phase of the first display panel ends and before the second phase of the second display panel begins.

15. A display device, characterized in that, Includes the display device according to any one of claims 1-14.

16. A driving method for a display device, characterized in that, The display device includes a display panel and a backlight module; the display panel includes a plurality of pixels arranged in an array, the plurality of pixels arranged along a first direction forming a pixel row, and the plurality of pixels arranged along a second direction forming a pixel column, the first direction and the second direction intersecting; when the display panel displays one frame of image, its working process includes a refresh stage and a backlight illumination stage; The refresh phase includes a first phase and a second phase executed sequentially. The driving method includes: In the first stage, a precharge data signal is written to the pixel, the voltage corresponding to the precharge data signal is a first voltage, and the gray level corresponding to the first voltage is greater than 0; In the second stage, image data signals are written to the pixels; During the backlight illumination phase, the backlight module is controlled to turn on. The display device includes at least two display panels, each including a first display panel and a second display panel arranged along the second direction; the display device includes at least two backlight modules, each corresponding to one display panel; during the refresh phase of a frame image, the second phase of the second display panel begins after the second phase of the first display panel ends; the display device displays A frames of image, where 0 < x ≤ A and A is greater than 2; a portion of the refresh phase of the (x+1)th frame of the first display panel overlaps with the backlight illumination phase of the xth frame of the second display panel.

17. The driving method according to claim 16, characterized in that, The driving method includes: at least a portion of the pixel rows simultaneously executing the first phase.

18. The driving method according to claim 16, characterized in that, Vt = (Vmax + Vmin) / 2; Wherein, Vt is the absolute value of the first voltage, Vmax is the maximum absolute value of the voltage corresponding to the data signal of the 1 frame image, and Vmin is the minimum absolute value of the voltage corresponding to the data signal of the 1 frame image.

19. The driving method according to claim 16, characterized in that, The gray level corresponding to the first voltage is the first gray level; The total number of gray levels that a pixel is allowed to display is M, and the M gray levels include one first gray level and (M-1) second gray levels; ta≤tb; Where ta is the sum of the time required to transition from the first gray level to each of the gray levels, and tb is the sum of the time required to transition from the second gray level to each of the gray levels.

Images