Shift register, drive circuit, drive method, and display device

Abstract

The present disclosure provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises: an input circuit configured to provide a first power supply voltage of a first power supply end to a first node and provide an input signal from an input end to a second node under the control of a first clock signal from a first clock end; a control circuit configured to provide a potential of the second node to a third node under the control of a first enable signal from a first enable end and provide the potential of the second node to a fourth node under the control of a second enable signal of a second enable end; and an output circuit configured to output a signal through an output end under the control of potentials of the first node, the second node, the third node and the fourth node.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Technology

[0002] Light-emitting diode (LED) displays are widely used in various aspects of daily life. Different applications require different viewing angles. For example, in some privacy scenarios, a narrow viewing angle is needed to prevent peeping. In some public scenarios, a wide viewing angle is required to facilitate screen sharing. Therefore, display devices that combine both privacy and sharing modes urgently need to be developed. Summary of the Invention

[0003] This disclosure provides a shift register, a driving circuit, a driving method, and a display device.

[0004] According to a first aspect, this disclosure provides a shift register, comprising: an input circuit configured to provide a first power supply voltage from a first power supply terminal to a first node under the control of a first clock signal from a first clock terminal, and to provide an input signal from an input terminal to a second node; a control circuit configured to provide a potential of the second node to a third node under the control of a first enable signal from a first enable terminal, and to provide a potential of the second node to a fourth node under the control of a second enable signal from a second enable terminal; and an output circuit configured to output a signal through an output terminal under the control of the potentials of the first node, the second node, the third node, and the fourth node.

[0005] For example, the input circuit includes a scan input circuit, the control circuit includes a scan control circuit, the output circuit includes a scan output circuit, the input terminal includes a scan input terminal, the first node includes a first scan node, the second node includes a second scan node, the third node includes a third scan node, the fourth node includes a fourth scan node, and the output terminal includes a first scan output terminal, a second scan output terminal, and a third scan output terminal; wherein, the scan input circuit is electrically connected to the scan input terminal, a first power supply terminal, and a first clock terminal, and is configured to, under the control of a first clock signal, provide a first power supply voltage from the first power supply terminal to the first scan node, and provide a scan input signal from the scan input terminal to the second scan node; the scan control circuit is electrically connected to a first enable terminal, a second enable terminal, and a second scan node, and is configured to, under the control of a first enable signal... The system provides the potential of the second scan node to the third scan node, and under the control of the second enable signal, provides the potential of the second scan node to the fourth scan node; and a scan output circuit, electrically connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the first scan node, the second scan node, the third scan node, and the fourth scan node, is configured to provide the second power supply voltage or the second clock signal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node, provide the second power supply voltage or the second clock signal to the second scan output terminal under the control of the potential of the first scan node and the potential of the fourth scan node, and provide the second power supply voltage or the second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node, and the first power supply voltage.

[0006] For example, the scan control circuit includes: a first scan control sub-circuit electrically connected to a first enable terminal, a second scan node, and a third scan node, configured to provide the potential of the second scan node to the third scan node under the control of a first enable signal; and a second scan control sub-circuit electrically connected to a second enable terminal, a second scan node, and a fourth scan node, configured to provide the potential of the second scan node to the fourth scan node under the control of a second enable signal.

[0007] For example, the scan output circuit includes: a first scan output sub-circuit electrically connected to a second clock terminal, a second power supply terminal, a first scan node, and a third scan node, configured to provide a second power supply voltage or a second clock signal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node; a second scan output sub-circuit electrically connected to the second clock terminal, the second power supply terminal, the first scan node, and a fourth scan node, configured to provide a second power supply voltage or a second clock signal to the second scan output terminal under the control of the potential of the first scan node and the potential of the fourth scan node; and a third scan output sub-circuit electrically connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the first scan node, and the second scan node, configured to provide a second power supply voltage or a second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node, and the first power supply voltage.

[0008] For example, the scan input circuit is also electrically connected to a second clock terminal and a second power supply terminal, and is configured to provide a second power supply voltage to the second scan node under the control of the potential of the first scan node and the second clock signal, and to provide a first clock signal to the first scan node under the control of the potential of the second scan node.

[0009] For example, the scan input circuit includes: a first scan transistor, a second scan transistor, a third scan transistor, a fourth scan transistor, and a fifth scan transistor; wherein, the control electrode of the first scan transistor is electrically connected to a first clock terminal, the first electrode of the first scan transistor is electrically connected to a scan input terminal, and the second electrode of the first scan transistor is electrically connected to a second scan node; the control electrode of the second scan transistor is electrically connected to the first clock terminal, the first electrode of the second scan transistor is electrically connected to a first power supply terminal, and the second electrode of the second scan transistor is electrically connected to the first scan node; the control electrode of the third scan transistor is electrically connected to the second scan node, the first electrode of the third scan transistor is electrically connected to the first clock terminal, and the second electrode of the third scan transistor is electrically connected to the first scan node; the control electrode of the fourth scan transistor is electrically connected to the first scan node, the first electrode of the fourth scan transistor is electrically connected to a second power supply terminal, and the second electrode of the fourth scan transistor is electrically connected to the first electrode of the fifth scan transistor; and the control electrode of the fifth scan transistor is electrically connected to a second clock terminal, and the second electrode of the fifth scan transistor is electrically connected to the second scan node.

[0010] For example, the first scan control sub-circuit includes a sixth scan transistor and a seventh scan transistor; wherein the control electrode of the sixth scan transistor is electrically connected to the first enable terminal, the first electrode of the sixth scan transistor is electrically connected to the second scan node, and the second electrode of the sixth scan transistor is electrically connected to the third scan node; and the control electrode and the first electrode of the seventh scan transistor are both electrically connected to the third scan node, and the second electrode of the seventh scan transistor is electrically connected to the first enable terminal.

[0011] For example, the second scan control sub-circuit includes an eighth scan transistor and a ninth scan transistor; wherein the control electrode of the eighth scan transistor is electrically connected to the second enable terminal, the first electrode of the eighth scan transistor is electrically connected to the second scan node, and the second electrode of the eighth scan transistor is electrically connected to the fourth scan node; and the control electrode and the first electrode of the ninth scan transistor are both electrically connected to the fourth scan node, and the second electrode of the ninth scan transistor is electrically connected to the second enable terminal.

[0012] For example, the first scan output sub-circuit includes a tenth scan transistor, an eleventh scan transistor, a first scan capacitor, and a second scan capacitor; wherein, the control electrode of the tenth scan transistor is electrically connected to the first scan node, the first electrode of the tenth scan transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth scan transistor is electrically connected to the first scan output terminal; the control electrode of the eleventh scan transistor is electrically connected to the third scan node, the first electrode of the eleventh scan transistor is electrically connected to the second clock terminal, and the second electrode of the eleventh scan transistor is electrically connected to the first scan output terminal; the first terminal of the first scan capacitor is electrically connected to the first scan node, and the second terminal of the first scan capacitor is electrically connected to the second power supply terminal; and the first terminal of the second scan capacitor is electrically connected to the third scan node, and the second terminal of the second scan capacitor is electrically connected to the first scan output terminal.

[0013] For example, the second scan output sub-circuit includes a twelfth scan transistor, a thirteenth scan transistor, a third scan capacitor, and a fourth scan capacitor; wherein, the control electrode of the twelfth scan transistor is electrically connected to the first scan node, the first electrode of the twelfth scan transistor is electrically connected to the second power supply terminal, and the second electrode of the twelfth scan transistor is electrically connected to the second scan output terminal; the control electrode of the thirteenth scan transistor is electrically connected to the fourth scan node, the first electrode of the thirteenth scan transistor is electrically connected to the second clock terminal, and the second electrode of the thirteenth scan transistor is electrically connected to the second scan output terminal; the first terminal of the third scan capacitor is electrically connected to the first scan node, and the second terminal of the third scan capacitor is electrically connected to the second power supply terminal; and the first terminal of the fourth scan capacitor is electrically connected to the fourth scan node, and the second terminal of the fourth scan capacitor is electrically connected to the second scan output terminal.

[0014] For example, the third scan output sub-circuit includes a fourteenth scan transistor, a fifteenth scan transistor, a sixteenth scan transistor, a fifth scan capacitor, and a sixth scan capacitor; wherein, the control electrode of the fourteenth scan transistor is electrically connected to the first scan node, the first electrode of the fourteenth scan transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth scan transistor is electrically connected to the third scan output terminal; the control electrode of the fifteenth scan transistor is electrically connected to the first electrode of the sixteenth scan transistor, the first electrode of the fifteenth scan transistor is electrically connected to the second clock terminal, and the second electrode of the fifteenth scan transistor is electrically connected to the third scan output terminal; the control electrode of the sixteenth scan transistor is electrically connected to the first power supply terminal, and the second electrode of the sixteenth scan transistor is electrically connected to the second scan node; the first terminal of the fifth scan capacitor is electrically connected to the first scan node, and the second terminal of the fifth scan capacitor is electrically connected to the second power supply terminal; and the first terminal of the sixth scan capacitor is electrically connected to the first electrode of the sixteenth scan transistor, and the second terminal of the sixth scan capacitor is electrically connected to the third scan output terminal.

[0015] For example, the input circuit includes a light-emitting control input circuit, the control circuit includes a light-emitting control circuit, the output circuit includes a light-emitting control output circuit, the input terminal includes a light-emitting control input terminal, the first node includes a first light-emitting control node, the second node includes a second light-emitting control node, the third node includes a third light-emitting control node, the fourth node includes a fourth light-emitting control node, and the output terminal includes a first light-emitting control output terminal, a second light-emitting control output terminal, and a third light-emitting control output terminal; wherein, the light-emitting control input circuit is electrically connected to the light-emitting control input terminal, a first power supply terminal, and a first clock terminal, and is configured to provide a first power supply voltage to the first light-emitting control node under the control of a first clock signal, and to provide a light-emitting control input signal from the light-emitting control input terminal to the second light-emitting control node; the light-emitting control circuit is electrically connected to a first enable terminal, a second enable terminal, a first power supply terminal, a second power supply terminal, a second clock terminal, the first light-emitting control node, and the second light-emitting control node, and is configured to provide the potential of the second light-emitting control node to the third light-emitting control node under the control of a first enable signal. The system comprises a control node that, under the control of a second enable signal, provides the potential of the second light-emitting control node to the fourth light-emitting control node, and under the control of a first power supply voltage, the potential of the second light-emitting control node, the potential of the first light-emitting control node, and a second clock signal, provides the second clock signal or the second power supply voltage to the fifth light-emitting control node; and a light-emitting control output circuit electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node, the third light-emitting control node, the fourth light-emitting control node, and the fifth light-emitting control node, configured to, under the control of the potentials of the third light-emitting control node and the fifth light-emitting control node, provide the first power supply voltage or the second power supply voltage to the first light-emitting control output terminal, under the control of the potentials of the fourth light-emitting control node and the fifth light-emitting control node, provide the first power supply voltage or the second power supply voltage to the second light-emitting control output terminal, and under the control of the potentials of the second light-emitting control node, the potential of the fifth light-emitting control node, and the first power supply voltage, provide the first power supply voltage or the second power supply voltage to the third light-emitting control output terminal.

[0016] For example, the light-emitting control circuit includes: a first light-emitting control sub-circuit electrically connected to a first enable terminal, a second clock terminal, a second light-emitting control node, and a third light-emitting control node, configured to provide the potential of the second light-emitting control node to the third light-emitting control node under the control of a first enable signal and a second clock signal; a second light-emitting control sub-circuit electrically connected to a second enable terminal, a second clock terminal, a second light-emitting control node, and a fourth light-emitting control node, configured to provide the potential of the second light-emitting control node to the fourth light-emitting control node under the control of a second enable signal and a second clock signal; and a third light-emitting control sub-circuit electrically connected to a first power supply terminal, a second power supply terminal, a second clock terminal, a first light-emitting control node, a second light-emitting control node, and a fifth light-emitting control node, configured to provide a second clock signal or a second power supply voltage to the fifth light-emitting control node under the control of a first power supply voltage, the potential of the second light-emitting control node, the potential of the first light-emitting control node, and a second clock signal.

[0017] For example, the light-emitting control output circuit includes: a first light-emitting control output sub-circuit electrically connected to a first power supply terminal, a second power supply terminal, a third light-emitting control node, and a fifth light-emitting control node, configured to provide a first power supply voltage or a second power supply voltage to the first light-emitting control output terminal under the control of the potential of the third light-emitting control node and the potential of the fifth light-emitting control node; a second light-emitting control output sub-circuit electrically connected to the first power supply terminal, the second power supply terminal, a fourth light-emitting control node, and the fifth light-emitting control node, configured to provide a first power supply voltage or a second power supply voltage to the second light-emitting control output terminal under the control of the potential of the fourth light-emitting control node and the potential of the fifth light-emitting control node; and a third light-emitting control output sub-circuit electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node, and the fifth light-emitting control node, configured to provide a first power supply voltage or a second power supply voltage to the third light-emitting control output terminal under the control of the potential of the second light-emitting control node, the potential of the fifth light-emitting control node, and the first power supply voltage.

[0018] For example, the light-emitting control input circuit is also electrically connected to the second clock terminal and the second power supply terminal, and is configured to provide the second power supply voltage to the second light-emitting control node under the control of the potential of the first light-emitting control node and the second clock signal, and to provide the first clock signal to the first light-emitting control node under the control of the potential of the second light-emitting control node.

[0019] For example, the light-emitting control input circuit includes: a first light-emitting control transistor, a second light-emitting control transistor, a third light-emitting control transistor, a fourth light-emitting control transistor, and a fifth light-emitting control transistor; wherein, the control electrode of the first light-emitting control transistor is electrically connected to a first clock terminal, the first electrode of the first light-emitting control transistor is electrically connected to a light-emitting control input terminal, and the second electrode of the first light-emitting control transistor is electrically connected to a second light-emitting control node; the control electrode of the second light-emitting control transistor is electrically connected to the first clock terminal, the first electrode of the second light-emitting control transistor is electrically connected to a first power supply terminal, and the second electrode of the second light-emitting control transistor is electrically connected to the first light-emitting control node; the control electrode of the third light-emitting control transistor is electrically connected to the second light-emitting control node, the first electrode of the third light-emitting control transistor is electrically connected to the first clock terminal, and the second electrode of the third light-emitting control transistor is electrically connected to the first light-emitting control node; and the control electrode of the fifth light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the fifth light-emitting control transistor is electrically connected to the second light-emitting control node.

[0020] For example, the first light-emitting control sub-circuit includes a sixth light-emitting control transistor, a seventh light-emitting control transistor, and a first light-emitting control capacitor; wherein, the control electrode of the sixth light-emitting control transistor is electrically connected to the first enable terminal, the first electrode of the sixth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the sixth light-emitting control transistor is electrically connected to the third light-emitting control node; the control electrode and the first electrode of the seventh light-emitting control transistor are both electrically connected to the third light-emitting control node, and the second electrode of the seventh light-emitting control transistor is electrically connected to the first enable terminal; and the first terminal of the first light-emitting control capacitor is electrically connected to the third light-emitting control node, and the second terminal of the first light-emitting control capacitor is electrically connected to the second clock terminal.

[0021] For example, the second light-emitting control sub-circuit includes an eighth light-emitting control transistor, a ninth light-emitting control transistor, and a second light-emitting control capacitor; wherein, the control electrode of the eighth light-emitting control transistor is electrically connected to the second enable terminal, the first electrode of the eighth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the eighth light-emitting control transistor is electrically connected to the fourth light-emitting control node; the control electrode and the first electrode of the ninth light-emitting control transistor are both electrically connected to the fourth light-emitting control node, and the second electrode of the ninth light-emitting control transistor is electrically connected to the second enable terminal; and the first terminal of the second light-emitting control capacitor is electrically connected to the fourth light-emitting control node, and the second terminal of the second light-emitting control capacitor is electrically connected to the second clock terminal.

[0022] For example, the third light-emitting control sub-circuit includes a tenth light-emitting control transistor, an eleventh light-emitting control transistor, a twelfth light-emitting control transistor, a thirteenth light-emitting control transistor, and a third light-emitting control capacitor; wherein, the control electrode of the tenth light-emitting control transistor is electrically connected to the first power supply terminal, the first electrode of the tenth light-emitting control transistor is electrically connected to the first light-emitting control node, and the second electrode of the tenth light-emitting control transistor is electrically connected to the control electrode of the eleventh light-emitting control transistor; the first electrode of the eleventh light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the eleventh light-emitting control transistor is electrically connected to the first electrode of the twelfth light-emitting control transistor; the control electrode of the twelfth light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the twelfth light-emitting control transistor is electrically connected to the fifth light-emitting control node; the control electrode of the thirteenth light-emitting control transistor is electrically connected to the second light-emitting control node, the first electrode of the thirteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node; and the first terminal of the third light-emitting control capacitor is electrically connected to the control electrode of the eleventh light-emitting control transistor, and the second terminal of the third light-emitting control capacitor is electrically connected to the second electrode of the eleventh light-emitting control transistor.

[0023] For example, the first light-emitting control output sub-circuit includes a fourteenth light-emitting control transistor, a fifteenth light-emitting control transistor, and a fourth light-emitting control capacitor; wherein, the control electrode of the fourteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the fourteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth light-emitting control transistor is electrically connected to the first light-emitting control output terminal; the control electrode of the fifteenth light-emitting control transistor is electrically connected to the third light-emitting control node, the first electrode of the fifteenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth light-emitting control transistor is electrically connected to the first light-emitting control output terminal; and the first terminal of the fourth light-emitting control capacitor is electrically connected to the fifth light-emitting control node, and the second terminal of the fourth light-emitting control capacitor is electrically connected to the second power supply terminal.

[0024] For example, the second light-emitting control output sub-circuit includes a sixteenth light-emitting control transistor, a seventeenth light-emitting control transistor, and a fifth light-emitting control capacitor; wherein, the control electrode of the sixteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the sixteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth light-emitting control transistor is electrically connected to the second light-emitting control output terminal; the control electrode of the seventeenth light-emitting control transistor is electrically connected to the fourth light-emitting control node, the first electrode of the seventeenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth light-emitting control transistor is electrically connected to the second light-emitting control output terminal; and the first terminal of the fifth light-emitting control capacitor is electrically connected to the fifth light-emitting control node, and the second terminal of the fifth light-emitting control capacitor is electrically connected to the second power supply terminal.

[0025] For example, the third light-emitting control output sub-circuit includes an eighteenth light-emitting control transistor, a nineteenth light-emitting control transistor, a twentieth light-emitting control transistor, and a sixth light-emitting control capacitor; wherein, the control electrode of the eighteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the eighteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth light-emitting control transistor is electrically connected to the third light-emitting control output terminal; the control electrode of the nineteenth light-emitting control transistor is electrically connected to the first electrode of the twentieth light-emitting control transistor, the first electrode of the nineteenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth light-emitting control transistor is electrically connected to the third light-emitting control output terminal; the control electrode of the twentieth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the twentieth light-emitting control transistor is electrically connected to the second light-emitting control node; and the first terminal of the sixth light-emitting control capacitor is electrically connected to the control electrode of the nineteenth light-emitting control transistor, and the second terminal of the sixth light-emitting control capacitor is electrically connected to the second clock terminal.

[0026] According to the second aspect, this disclosure provides a driving circuit including M cascaded shift registers provided in embodiments of this disclosure, where M is a positive integer greater than 1; the input terminal of the m-th shift register is electrically connected to the output terminal of the (m-1)-th shift register, where 1 < m ≤ M.

[0027] According to a third aspect, this disclosure provides a display device, including a display panel; and a driving circuit provided in an embodiment of this disclosure; wherein the display panel includes a plurality of pixel units, each pixel unit including a first sub-pixel group and a second sub-pixel group, the first sub-pixel group being electrically connected to a first scan output terminal and a first light emission control output terminal in the driving circuit, and the second sub-pixel group being electrically connected to a second scan output terminal and a second light emission control output terminal in the driving circuit, wherein the light emission angle of the plurality of first sub-pixels included in the first sub-pixel group is smaller than the light emission angle of the plurality of second sub-pixels included in the second sub-pixel group, and the light emission angle is the angle between the emitted light and the direction perpendicular to the display panel.

[0028] According to a fourth aspect, this disclosure provides a driving method applied to a scan shift register provided in an embodiment of this disclosure, comprising: a first enable signal from a first enable terminal being at a first level and a second enable signal from a second enable terminal being at a second level, controlling a first scan output terminal to output a pulse signal and a second scan output terminal to output a DC signal; the first enable signal being at a second level and the second enable signal being at a first level, controlling the first scan output terminal to output a DC signal and the second scan output terminal to output a pulse signal; and both the first enable signal and the second enable signal being at a first level, controlling both the first scan output terminal and the second scan output terminal to output pulse signals. Attached Figure Description

[0029] Figure 1This is a schematic diagram of the structure of the display panel according to an embodiment of the present disclosure;

[0030] Figure 2A This is a schematic diagram of an example pixel circuit.

[0031] Figure 2B This is a schematic diagram of another example of a pixel circuit;

[0032] Figure 3A This is a schematic diagram of the structure of a scan shift register according to an embodiment of the present disclosure;

[0033] Figure 3B This is a schematic diagram of the structure of the light emission control shift register according to an embodiment of the present disclosure;

[0034] Figure 4A This is a schematic diagram of the structure of a scan shift register according to another embodiment of the present disclosure;

[0035] Figure 4B This is a schematic diagram of the structure of a light-emitting control shift register according to another embodiment of the present disclosure;

[0036] Figure 5A This is a schematic diagram of the structure of a scan shift register according to another embodiment of the present disclosure;

[0037] Figure 5B and Figure 5C yes Figure 5A Timing diagram of the mid-scan shift register;

[0038] Figure 6A This is a schematic diagram of the structure of a light-emitting control shift register according to another embodiment of the present disclosure;

[0039] Figure 6B and Figure 6C yes Figure 6A Signal timing diagram of the light-emitting control shift register;

[0040] Figure 7A This is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0041] Figure 7B This is a schematic diagram of the gate drive circuit according to an embodiment of the present disclosure;

[0042] Figure 7C This is a schematic diagram of the structure of the light-emitting control driving circuit according to an embodiment of the present disclosure;

[0043] Figure 8A This is a schematic diagram of the structure of a pixel unit according to an embodiment of the present disclosure;

[0044] Figure 8B This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0045] Figure 9A This is a schematic diagram of the structure of a pixel unit according to another embodiment of the present disclosure;

[0046] Figure 9B This is a schematic diagram of the structure of a display device according to another embodiment of the present disclosure;

[0047] Figure 10 This is a flowchart of a driving method according to an embodiment of the present disclosure;

[0048] Figure 11A This is a flowchart of a driving method according to another embodiment of the present disclosure;

[0049] Figure 11B This is a flowchart of a driving method according to another embodiment of the present disclosure; and

[0050] Figure 12 This is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0052] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0053] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0054] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to their function, the gate can be called the control electrode, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0055] Furthermore, in the description of the embodiments of this disclosure, the terms "first power supply voltage" and "second power supply voltage" are used only to distinguish the different amplitudes of the two power supply voltages. For example, the following description uses "first power supply voltage" as a relatively high voltage and "second power supply voltage" as a relatively low voltage. Those skilled in the art will understand that this disclosure is not limited thereto.

[0056] It should be noted that in the description of the embodiments of this disclosure, the symbol GOUT can represent both a gate drive signal and the level of the gate drive signal. Similarly, the symbol EOUT can represent both a light emission control signal and the level of the light emission control signal, the symbol GIN can represent both a scan input signal and the level of the scan input signal, the symbol EIN can represent both a light emission control input signal and the level of the light emission control input signal, the symbol VINT can represent both a predetermined initial voltage terminal and the voltage of the initial signal, the symbol ELVDD can represent both a power supply and the power supply voltage provided by the power supply, INPUT can represent both an input signal terminal and the input signal provided by the input signal terminal, OUTPUT can represent both an output signal terminal and the output signal output by the output signal terminal, and VGH and VGL can represent both a power supply terminal and the power supply voltage provided by the power supply terminal. For example, the first power supply terminal VGL can provide a low voltage, such as ground. The second power supply terminal VGH can provide a high level. The voltage provided by the first power supply terminal VGL is lower than the voltage of the second power supply terminal VGH. The following embodiments are the same, and similar parts will not be described again.

[0057] Figure 1 This is a schematic diagram of the structure of the display panel according to an embodiment of the present disclosure.

[0058] like Figure 1 As shown, the display panel 100 includes pixel units 101, 102, 103, and 104. It should be noted that the number of pixel units included in the display panel 100 is for illustrative purposes only, and this disclosure does not limit the number of pixel units.

[0059] In this embodiment of the disclosure, pixel unit 101, pixel unit 102, pixel unit 103 and pixel unit 104 have the same structure, and each pixel unit includes two sets of sub-pixel units.

[0060] The structure of pixel unit 102 will be used as an example for explanation.

[0061] In this embodiment of the disclosure, pixel unit 102 includes a first sub-pixel group 121 and a second sub-pixel group 122. For example, the first sub-pixel group 121 is used for privacy display, and the second sub-pixel group 122 is used for normal display. The first sub-pixel group 121 includes three first sub-pixel units. For example, the three first sub-pixels can be a red sub-pixel, a blue sub-pixel, and a green sub-pixel, respectively. The second sub-pixel group 122 includes three second sub-pixel units. For example, the three second sub-pixels can be a red sub-pixel, a blue sub-pixel, and a green sub-pixel, respectively.

[0062] For example, the first subpixel group 121 includes multiple subpixels that are privacy subpixels, and the second subpixel group 122 includes multiple subpixels that are display subpixels.

[0063] For example, the first subpixel group 121 and the second subpixel group 122 may each include two subpixels. This disclosure does not limit the number of subpixels included in each subpixel group.

[0064] In this embodiment of the disclosure, the light emission angle of the first sub-pixel of the first sub-pixel group 121 is smaller than the light emission angle of the second sub-pixel of the second sub-pixel group 122. The light emission angle is the angle between the emitted light and the direction perpendicular to the display panel.

[0065] For example, a light-shielding layer is provided on the surface of the first sub-pixel group 121 and the second sub-pixel group 122, and the sub-pixels of the first sub-pixel group 121 and the second sub-pixel group 122 can emit light normally through an opening in the light-shielding layer. The opening area corresponding to the first sub-pixel group 121 is smaller than the opening area corresponding to the second sub-pixel group 122, so that the light-emitting range of the first sub-pixel of the first sub-pixel group 121 is smaller than the light-emitting range of the second sub-pixel of the second sub-pixel group 122.

[0066] For example, the light emission angle of the first sub-pixel of the first sub-pixel group 121 can be in the range of 0-45°, and the light emission angle of the second sub-pixel of the second sub-pixel group 122 can be in the range of 0-90°.

[0067] For example, when the first sub-pixel of the first sub-pixel group 121 is illuminated and the second sub-pixel of the second sub-pixel group 122 is not illuminated, the maximum viewing angle for the user to view the display screen can be 90°. That is, when the user views the display screen from the left or right side, the maximum angle between the user's line of sight and the direction perpendicular to the display panel is 45°, thus achieving the purpose of screen privacy protection. When the first sub-pixel of the first sub-pixel group 121 is not illuminated and the second sub-pixel of the second sub-pixel group 122 is illuminated, the maximum viewing angle for the user to view the display screen can be 180°. That is, when the user is located on the left or right side of the display screen, the maximum angle between the user's line of sight and the direction perpendicular to the display panel is 90°, thus achieving a wide viewing angle for screen content display.

[0068] For example, when the first sub-pixel of the first sub-pixel group 121 and the second sub-pixel of the second sub-pixel group 122 are both illuminated, the maximum viewing angle of the user's view of the display screen is also 180°, realizing the display of screen content with a wide viewing angle.

[0069] In this embodiment of the disclosure, the first sub-pixel of the first sub-pixel group 121 and the second sub-pixel of the second sub-pixel group 122 are driven by different driving signals, thereby enabling one group of sub-pixels to work while the other group of sub-pixels does not work.

[0070] Figure 2A This is a schematic diagram of an example pixel circuit. Figure 2B This is a schematic diagram of another example of a pixel circuit. Figure 2A Shown in Figure 1 The pixel circuit of the first sub-pixel of the first sub-pixel group 121. Figure 2B Shown in Figure 1 The pixel circuit of the first sub-pixel of the second sub-pixel group 122.

[0071] like Figure 2A and Figure 2B As shown, the pixel circuit of a sub-pixel can be a 7T1C structure, meaning each pixel unit consists of 7 thin-film transistors (TFTs) and 1 capacitor (C). It should be noted that the pixel circuit of a sub-pixel can also be an 8T1C or 7T2C circuit structure, etc. Figure 2A and Figure 2B The pixel circuit shown is merely an illustrative example, and this disclosure does not limit the circuit structure of the pixel circuit.

[0072] like Figure 2A As shown, transistors T1 through T7 are all P-type transistors. The gates of transistors T1, T2, T4, and T7 are controlled by the first gate drive signal GOUT_O, while the gates of transistors T5 and T6 are controlled by the first light emission control signal EOUT_O.

[0073] like Figure 2B As shown, transistors T1 through T7 are all P-type transistors. The gates of transistors T1, T2, T4, and T7 are controlled by the second gate drive signal GOUT_E, while the gates of transistors T5 and T6 are controlled by the second light emission control signal EOUT_E.

[0074] By controlling the first gate drive signal GOUT_O, the first light emission control signal to control EOUT_O, and the second gate drive signal GOUT_E, the second light emission control signal to control EOUT_E, the system can be controlled. Figure 1 The working states of the first sub-pixel of the first sub-pixel group 121 and the second sub-pixel of the second sub-pixel group 122 are shown.

[0075] The first gate drive signal GOUT_O and the second gate drive signal GOUT_E can be provided by the gate drive (Gate On Array, GOA) circuit, and the first emission control signal controlling EOUT_O and the second emission control signal controlling EOUT_E are provided by the emission control signal drive (Emission On Array, EOA) circuit.

[0076] For example, a GOA circuit may include multiple cascaded GOA units, each GOA unit providing a drive signal to a row of pixel units in a pixel array. Figure 2A The gate drive signal GOUT(n)_O shown can be the gate drive signal provided by the nth level GOA cell, and the gate drive signal Gate(n-1)_O can be the gate drive signal provided by the (n-1)th level GOA cell.

[0077] Similarly, the EOA circuit includes multiple cascaded EOA units, each of which provides an emission control signal EM to a row of pixel units in the pixel array.

[0078] Therefore, in one example, by Figure 2A and Figure 2B The pixel circuit, composed of the pixel units shown, requires two sets of driving circuits to provide driving signals. Each set of driving circuits includes a GOA circuit and an EOA circuit. In a display device, these two sets of driving circuits occupy a significant amount of space, which makes it difficult to narrow the bezel of the display and also increases the power consumption of the display device.

[0079] To address the aforementioned issues, this disclosure provides a scan shift register and a light emission control shift register. By controlling the signal output of the scan shift register and the light emission control shift register with an enable signal, a GOA circuit and an EOA circuit can respectively provide gate drive signals and light emission control signals to two sub-pixel groups.

[0080] Figure 3A This is a schematic diagram of the structure of a scan shift register according to an embodiment of the present disclosure.

[0081] like Figure 3A As shown, the scan shift register 300a includes a scan input circuit 310, a scan control circuit 320, and a scan output circuit 330.

[0082] In this embodiment of the disclosure, the scan input circuit 310 is electrically connected to the scan input terminal GIN_n, the first power supply terminal VGL, and the first clock terminal CK. The scan input circuit 310 is configured to, under the control of the first clock signal CK from the first clock terminal CK, provide the first power supply voltage VGL of the first power supply terminal VGL to the first scan node SN1, and provide the scan input signal GIN_n from the scan input terminal GIN_n to the second scan node SN2.

[0083] In this embodiment of the present disclosure, the scan control circuit 320 is electrically connected to a first enable terminal EN_O, a second enable terminal EN_E, and a second scan node SN2. The scan control circuit 320 is configured to provide the potential of the second scan node SN2 to a third scan node SN3 under the control of a first enable signal EN_O from the first enable terminal EN_O, and to provide the potential of the second scan node SN2 to a fourth scan node SN4 under the control of a second enable signal EN_E from the second enable terminal EN_E.

[0084] In this embodiment of the present disclosure, the scan output circuit 330 is electrically connected to the second clock terminal CB, the first power supply terminal VGL, the second power supply terminal VGH, the first scan node SN1, the second scan node SN2, the third scan node SN3, and the fourth scan node SN4. The scan output circuit 330 is configured to, under the control of the potentials of the first scan node SN1 and the third scan node SN3, provide either the second power supply voltage VGH of the second power supply terminal VGH or the second clock signal CB from the second clock terminal CB to the first scan output terminal GOUT_O; under the control of the potentials of the first scan node SN1 and the fourth scan node SN4, provide either the second power supply voltage VGH or the second clock signal CB to the second scan output terminal GOUT_E; and under the control of the potentials of the first scan node SN1, the second scan node SN2, and the first power supply voltage VGL, provide either the second power supply voltage VGH or the second clock signal CB to the third scan output terminal GOUT_n.

[0085] In this embodiment of the disclosure, the scan shift register 300a can be a driving unit in the gate driving circuit. The scan shift register 300a can output a first gate driving signal GOUT_O, a second gate driving signal GOUT_E, and a third gate driving signal GOUT_n.

[0086] For example, the first gate drive signal GOUT_O is used to drive Figure 2A The pixel circuit, the second gate drive signal GOUT_E is used to drive Figure 2B The pixel circuit. The third gate drive signal GOUT_n is provided to the next stage scan shift register.

[0087] In this embodiment, the scan input signal GIN_n at the scan input terminal GIN_n can be the third gate drive signal GOUT_n-1 output from the previous stage scan shift register, and the third scan output terminal GOUT_n can be the scan input signal GIN_n+1 provided by the next stage scan shift register in the drive circuit. When the scan shift register 300a is the first stage scan shift register, the scan input signal GIN_1 can be the gate start vertical (GSTV) signal.

[0088] In this embodiment, the output of the first scan output terminal GOUT_O is controlled by the first enable terminal EN_O, and the output of the second scan output terminal GOUT_E is controlled by the second enable terminal EN_E. This allows control over the driving of two sets of sub-pixels in the display panel, enabling both privacy-protected and normal display. Using a shift register 300a as a driving unit to provide gate drive signals to the two sets of sub-pixels reduces the space occupied by the gate drive circuit, which is beneficial for narrowing the display bezel.

[0089] It should be noted that the first node SN1, the second node SN2, the third node SN3, and the fourth node SN4 do not represent actual existing components, but rather the junction points of related circuit connections in the circuit diagram.

[0090] Figure 3B This is a schematic diagram of the structure of the light emission control shift register according to an embodiment of the present disclosure.

[0091] like Figure 3B As shown, the light emission control shift register 300b includes a light emission control input circuit 340, a light emission control circuit 350, and a light emission control output circuit 360.

[0092] In this embodiment, the light emission control input circuit 340 is electrically connected to the light emission control input terminal EIN, the first power supply terminal VGL, and the first clock terminal CK. The light emission control input circuit 340 is configured to, under the control of the first clock signal CK from the first clock terminal CK, provide the first power supply voltage VGL of the first power supply terminal VGL to the first light emission control node EMN1, and provide the light emission control input signal EIN_n from the light emission control input terminal EIN_n to the second light emission control node EMN2.

[0093] In this embodiment, the light-emitting control circuit 350 is electrically connected to a first enable terminal EN_O, a second enable terminal EN_E, a first power supply terminal VGL, a second power supply terminal VGH, a second clock terminal CB, a first light-emitting control node EMN1, a second light-emitting control node EMN2, a third light-emitting control node EMN3, a fourth light-emitting control node EMN4, and a fifth light-emitting control node EMN5. The light-emitting control circuit 350 is configured to, under the control of a first enable signal EN_O from the first enable terminal EN_O, provide the potential of the second light-emitting control node EMN2 to the third light-emitting control node EMN3; under the control of a second enable signal EN_E from the second enable terminal EN_E, provide the potential of the second light-emitting control node EMN2 to the fourth light-emitting control node EMN4; and under the control of the first power supply voltage VGL, the potential of the second light-emitting control node EMN2, the potential of the first light-emitting control node EMN1, and a second clock signal CB from the second clock terminal CB, provide the second clock signal CB or the second power supply voltage VGH from the second power supply terminal VGH to the fifth light-emitting control node EMN5.

[0094] In this embodiment, the light-emitting control output circuit 360 is electrically connected to a first power supply terminal VGL, a second power supply terminal VGH, a second light-emitting control node EMN2, a third light-emitting control node EMN3, a fourth light-emitting control node EMN4, and a fifth light-emitting control node EMN5. The light-emitting control output circuit 360 is configured to provide either the first power supply voltage VGL or the second power supply voltage VGH to the first light-emitting control output terminal EOUT_O under the control of the potentials of the third light-emitting control node EMN3 and the fifth light-emitting control node EMN5; to provide either the first power supply voltage VGL or the second power supply voltage VGH to the second light-emitting control output terminal EOUT_E under the control of the potentials of the fourth light-emitting control node EMN4 and the fifth light-emitting control node EMN5; and to provide either the first power supply voltage VGL or the second power supply voltage VGH to the third light-emitting control output terminal EOUT_N under the control of the potentials of the second light-emitting control node EMN2, the fifth light-emitting control node EOUT_5, and the first power supply voltage VGL.

[0095] In this embodiment, the light emission control shift register 300b can be a driving unit in the light emission control driving circuit. The light emission control shift register 300b can output a first light emission control driving signal EOUT_O, a second light emission control driving signal EOUT_E, and a third light emission control driving signal EOUT_n.

[0096] For example, the first light-emitting control drive signal EOUT_O is used to drive... Figure 2A The pixel circuit, the second light-emitting control drive signal EOUT_E is used to drive Figure 2B The pixel circuit. The third light emission control drive signal EOUT_n is provided to the next-stage light emission control shift register.

[0097] In this embodiment, the light emission control input signal EIN_n at the light emission control input terminal EIN_n can be the third light emission control signal EOUT_n-1 output from the previous stage light emission control shift register, and the third light emission control output terminal EOUT_n can be the light emission control input signal EIN_n+1 provided by the next stage light emission control shift register in the driving circuit. When the light emission control shift register 300b is the first stage light emission control shift register, the light emission control input signal EIN_1 can be the light emission control trigger (Emission Start Vertical, ESTV) signal.

[0098] In this embodiment, the output of the first light-emitting control output terminal EOUT_O is controlled by the first enable terminal EN_O, and the output of the second light-emitting control output terminal EOUT_E is controlled by the second enable terminal EN_E. This allows control over the driving of two sets of sub-pixels in the display panel, enabling both privacy-protected and normal display. Using a single light-emitting control shift register 300b as a driving unit to provide light-emitting control signals to the two sets of sub-pixels reduces the space occupied by the light-emitting control driving circuit, which is beneficial for narrowing the display bezel.

[0099] It should be noted that the first node EMN1, the second node EMN2, the third node EMN3, the fourth node EMN4, and the fifth node EMN5 do not represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0100] In this embodiment, the scan shift register 300a and the light emission control shift register 300b can share a clock signal terminal, a power supply terminal, and an enable terminal, or they can each have their own separate clock signal terminal, power supply terminal, and enable terminal. For example, the first clock terminal CK can include a first clock terminal GCK and a first clock terminal ECK, and the second clock terminal CB can include a second clock terminal GCB and a second clock terminal ECB. The first clock terminal GCK and the second clock terminal GCB are used to provide a clock signal for the scan shift register 300a, and the first clock terminal ECK and the second clock terminal ECB are used to provide a clock signal for the light emission control shift register 300b.

[0101] Figure 4A This is a schematic diagram of the structure of a scan shift register according to another embodiment of the present disclosure.

[0102] like Figure 4A As shown, the scan shift register 400a includes a scan input circuit 410, a scan control circuit 420, and a scan output circuit 430. The scan input circuit 410, scan control circuit 420, and scan output circuit 430 are similar to the scan input circuit 310, scan control circuit 320, and scan output circuit 330 described above. For the sake of simplicity, the same parts will not be described again here.

[0103] In this embodiment, the scan input circuit 410 is electrically connected to the scan input terminal GIN_n, the first power supply terminal VGL, the first clock terminal CK, the second clock terminal CB, and the second power supply terminal VGH. The scan input circuit 410 is configured to provide the second power supply voltage VGH to the second scan node SN2 under the control of the potential of the first scan node SN1 and the second clock signal CB, and to provide the first clock signal CK to the first scan node SN1 under the control of the potential of the second scan node SN2.

[0104] In this embodiment of the disclosure, the scanning control circuit 420 includes a first scanning control sub-circuit 421 and a second scanning control sub-circuit 422.

[0105] The first scan control sub-circuit 421 is electrically connected to the first enable terminal EN_O, the second scan node SN2, and the third scan node SN3. The first scan control sub-circuit 421 is configured to provide the potential of the second scan node SN2 to the third scan node SN3 under the control of the first enable signal EN_O.

[0106] The second scan control sub-circuit 422 is electrically connected to the second enable terminal EN_E, the second scan node SN2, and the fourth scan node SN4. The second scan control sub-circuit 422 is configured to provide the potential of the second scan node SN2 to the fourth scan node SN4 under the control of the second enable signal EN_E.

[0107] In this embodiment, the on / off state between the second scan node SN2 and the third scan node SN3 can be controlled by the first enable signal EN_O. The on / off state between the second scan node SN2 and the fourth scan node SN4 can be controlled by the second enable signal EN_E. For example, when the second scan node SN2 and the third scan node SN3 are connected, the potential of the second scan node SN2 is provided to the fourth scan node SN4. When the second scan node SN2 and the fourth scan node SN4 are connected, the potential of the second scan node SN2 is provided to the fourth scan node SN4.

[0108] In this embodiment of the disclosure, the first enable signal EN_O and the second enable signal EN_E can be signals indicating the display mode of the display device. For example, based on the first enable signal EN_O, the display device can be controlled to be in a privacy mode, and the scan shift register 400a can be used to drive the privacy sub-pixels. Based on the second enable signal EN_E, the display device can be controlled to be in a normal mode, and the scan shift register 400a can be used to drive the display sub-pixels.

[0109] In this embodiment of the disclosure, the scan output circuit 430 includes a first scan output sub-circuit 431, a second scan output sub-circuit 432, and a third scan output sub-circuit 433.

[0110] The first scan output sub-circuit 431 is electrically connected to the second clock terminal CB, the second power supply terminal VGH, the first scan node SN1, and the third scan node SN3. The first scan output sub-circuit 431 is configured to provide the second power supply voltage VGH or the second clock signal CB to the first scan output terminal GOUT_O under the control of the potential of the first scan node SN1 and the potential of the third scan node SN3.

[0111] The second scan output sub-circuit 432 is electrically connected to the second clock terminal CB, the second power supply terminal VGH, the first scan node SN1, and the fourth scan node SN4. The second scan output sub-circuit 432 is configured to provide the second power supply voltage VGH or the second clock signal CB to the second scan output terminal GOUT_E under the control of the potential of the first scan node SN1 and the potential of the fourth scan node SN4.

[0112] The third scan output sub-circuit 433 is electrically connected to the second clock terminal CB, the first power supply terminal VGL, the second power supply terminal VGH, the first scan node SN1, and the second scan node SN2. The third scan output sub-circuit 433 is configured to provide the second power supply voltage VGH or the second clock signal CB to the third scan output terminal GOUT_n under the control of the potential of the first scan node SN1, the potential of the second scan node SN2, and the first power supply voltage VGL.

[0113] In this embodiment, the first scan output terminal GOUT_O outputs a first gate drive signal GOUT_O to drive the privacy sub-pixel. The second scan output terminal GOUT_E outputs a second gate drive signal GOUT_E to drive the display sub-pixel. The third scan output terminal GOUT_n outputs a third gate drive signal GOUT_n to drive the next-stage scan shift register.

[0114] In this embodiment of the disclosure, the second power supply voltage VGH provides a high potential for the first gate drive signal GOUT_O, the second gate drive signal GOUT_E, and the third gate drive signal GOUT_n, and the second clock signal CB provides a low potential for the first gate drive signal GOUT_O, the second gate drive signal GOUT_E, and the third gate drive signal GOUT_n.

[0115] Figure 4B This is a schematic diagram of the structure of a light-emitting control shift register according to another embodiment of the present disclosure.

[0116] like Figure 4B As shown, the light-emitting control shift register 400b includes a light-emitting control input circuit 440, a light-emitting control circuit 450, and a light-emitting control output circuit 460. The light-emitting control input circuit 440, the light-emitting control circuit 450, and the light-emitting control output circuit 460 are similar to the light-emitting control input circuit 340, the light-emitting control circuit 350, and the light-emitting control output circuit 360 described above. For the sake of simplicity, the same parts will not be described again here.

[0117] In this embodiment, the light-emitting control input circuit 440 is electrically connected to the light-emitting control input terminal EIN_n, the first clock terminal CK, the second clock terminal CB, the first power supply terminal VGL, and the second power supply terminal VGH. The light-emitting control input circuit 440 is configured to provide the second power supply voltage VGH to the second light-emitting control node EMN2 under the control of the potential of the first light-emitting control node EMN1 and the second clock signal CB, and to provide the first clock signal CK to the first light-emitting control node EMN1 under the control of the potential of the second light-emitting control node EMN2.

[0118] In this embodiment of the disclosure, the light-emitting control circuit 450 includes a first light-emitting control sub-circuit 451, a second light-emitting control sub-circuit 452, and a third light-emitting control sub-circuit 453.

[0119] The first light-emitting control sub-circuit 451 is electrically connected to the first enable terminal EN_O, the second clock terminal, the second light-emitting control node EMN2, and the third light-emitting control node EMN3. The first light-emitting control sub-circuit 451 is configured to provide the potential of the second light-emitting control node EMN2 to the third light-emitting control node EMN3 under the control of the first enable signal EN_O and the second clock signal CB.

[0120] The second light-emitting control sub-circuit 452 is electrically connected to the second enable terminal EN_E, the second clock terminal CB, the second light-emitting control node EMN2, and the fourth light-emitting control node EMN4. The second light-emitting control sub-circuit 452 is configured to provide the potential of the second light-emitting control node EMN2 to the fourth light-emitting control node EMN4 under the control of the second enable signal EN_E and the second clock signal CB.

[0121] The third light-emitting control sub-circuit 453 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the second clock terminal CB, the first light-emitting control node EMN1, the second light-emitting control node EMN2, and the fifth light-emitting control node EMN5. The third light-emitting control sub-circuit 453 is configured to provide the second clock signal CB or the second power supply voltage VGH to the fifth light-emitting control node EMN5 under the control of the first power supply voltage VGL, the potential of the second light-emitting control node EMN2, the potential of the first light-emitting control node EMN1, and the second clock signal CB.

[0122] In this embodiment, the on / off state between the second light-emitting control node EMN2 and the third light-emitting control node EMN3 can be controlled by the first enable signal EN_O. The on / off state between the second light-emitting control node EMN2 and the fourth light-emitting control node EMN4 can be controlled by the second enable signal EN_E. For example, when the second light-emitting control node EMN2 and the third light-emitting control node EMN3 are connected, the potential of the second light-emitting control node EMN2 is provided to the third light-emitting control node EMN3. When the second light-emitting control node EMN2 and the fourth light-emitting control node EMN4 are connected, the potential of the second light-emitting control node EMN2 is provided to the fourth light-emitting control node EMN4.

[0123] In this embodiment of the disclosure, the first enable signal EN_O and the second enable signal EN_E can be signals indicating the display mode of the display device. For example, based on the first enable signal EN_O, the display device can be controlled to be in a privacy mode, and the light emission control shift register 400b can be used to drive the privacy sub-pixel. Based on the second enable signal EN_E, the display device can be controlled to be in a normal mode, and the light emission control shift register 400a can be used to drive the display sub-pixel.

[0124] In this embodiment of the disclosure, the light emission control output circuit 460 includes a first light emission control output sub-circuit 461, a second light emission control output sub-circuit 462, and a third light emission control output sub-circuit 463.

[0125] The first light-emitting control output sub-circuit 461 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the third light-emitting control node EMN3, and the fifth light-emitting control node EMN5. The first light-emitting control output sub-circuit 461 is configured to provide either the first power supply voltage VGL or the second power supply voltage VGH to the first light-emitting control output terminal EOUT_O under the control of the potential of the third light-emitting control node EMN3 and the fifth light-emitting control node EMN5.

[0126] The second light-emitting control output sub-circuit 462 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the fourth light-emitting control node EMN4, and the fifth light-emitting control node EMN5. The second light-emitting control output sub-circuit 462 is configured to provide either the first power supply voltage VGL or the second power supply voltage VGH to the second light-emitting control output terminal EOUT_E under the control of the potential of the fourth light-emitting control node EMN4 and the fifth light-emitting control node EMN5.

[0127] The third light-emitting control output sub-circuit 463 is electrically connected to the first power supply terminal VGL, the second power supply terminal VGH, the second light-emitting control node EMN2, and the fifth light-emitting control node EMN5. The third light-emitting control output sub-circuit 463 is configured to supply either the first power supply voltage VGL or the second power supply voltage VGH to the third light-emitting control output terminal EOUT_n under the control of the potential of the second light-emitting control node EMN2, the potential of the fifth light-emitting control node EMN5, and the first power supply voltage VGL.

[0128] In this embodiment, the first light emission control output terminal EOUT_O outputs a first light emission control signal EOUT_O to drive the privacy sub-pixel. The second light emission control output terminal EOUT_E outputs a second light emission control signal EOUT_E to drive the display sub-pixel. The third light emission control output terminal EOUT_n outputs a third light emission control signal EOUT_n to drive the next-level light emission control shift register.

[0129] In this embodiment of the disclosure, the second power supply voltage VGH provides a high potential for the first light emission control signal EOUT_O, the second light emission control signal EOUT_E, and the third light emission control signal EOUT_n, and the second clock signal CB provides a low potential for the first light emission control signal EOUT_O, the second light emission control signal EOUT_E, and the third light emission control signal EOUT_n.

[0130] Figure 5A This is a schematic diagram of the structure of a scan shift register according to another embodiment of the present disclosure.

[0131] like Figure 5A As shown, the scan shift register 500 includes a scan input circuit 510, a scan control circuit 520, and a scan output circuit 530.

[0132] The scan control circuit 520 includes a first scan control sub-circuit 521 and a second scan control sub-circuit 522. The scan output circuit 530 includes a first scan output sub-circuit 531, a second scan output sub-circuit 532, and a second scan output sub-circuit 533.

[0133] The scan input circuit 510, scan control circuit 520, and scan output circuit 530 are similar to the scan input circuit 410, scan control circuit 420, and scan output circuit 430 described above, respectively. The first scan control sub-circuit 521 and the second scan control sub-circuit 522 are similar to the first scan control sub-circuit 421 and the second scan control sub-circuit 422 described above, respectively. The first scan output sub-circuit 531, the second scan output sub-circuit 532, and the second scan output sub-circuit 533 are similar to the first scan output sub-circuit 431, the second scan output sub-circuit 432, and the second scan output sub-circuit 433 described above, respectively. For the sake of simplicity, the same parts will not be described again here.

[0134] In this embodiment, the scanning input circuit 510 includes a first scanning transistor T1, a second scanning transistor T2, a third scanning transistor T3, a fourth scanning transistor T4, and a fifth scanning transistor T5. The first scanning transistor T1, the second scanning transistor T2, the third scanning transistor T3, the fourth scanning transistor T4, and the fifth scanning transistor T5 are P-type transistors and are used as switching transistors.

[0135] The control electrode of the first scanning transistor T1 is electrically connected to the first clock terminal GCK, the first electrode of the first scanning transistor T1 is electrically connected to the scan input terminal GIN_n, and the second electrode of the first scanning transistor T1 is electrically connected to the second scan node SN2. The control electrode of the second scanning transistor T2 is electrically connected to the first clock terminal GCK, the first electrode of the second scanning transistor T2 is electrically connected to the first power supply terminal VGL, and the second electrode of the second scanning transistor T2 is electrically connected to the first scan node SN1. The control electrode of the third scanning transistor T3 is electrically connected to the second scan node SN2, the first electrode of the third scanning transistor T3 is electrically connected to the first clock terminal GCK, and the second electrode of the third scanning transistor T3 is electrically connected to the first scan node SN1.

[0136] The control electrode of the fourth scanning transistor T4 is electrically connected to the first scanning node SN1, the first electrode of the fourth scanning transistor T4 is electrically connected to the second power supply terminal VGH, and the second electrode of the fourth scanning transistor T4 is electrically connected to the first electrode of the fifth scanning transistor strip. The control electrode of the fifth scanning transistor T5 is electrically connected to the second clock terminal GCB, and the second electrode of the fifth scanning transistor T5 is electrically connected to the second scanning node SN2.

[0137] In this embodiment of the disclosure, the first scan control sub-circuit 521 includes a sixth scan transistor T6 and a seventh scan transistor T7. The sixth scan transistor T6 and the seventh scan transistor T7 are P-type transistors and are used as switching transistors.

[0138] The control electrode of the sixth scanning transistor T6 is electrically connected to the first enable terminal EN O, the first electrode of the sixth scanning transistor T6 is electrically connected to the second scanning node SN2, and the second electrode of the sixth scanning transistor T6 is electrically connected to the third scanning node SN3. The control electrode and the first electrode of the seventh scanning transistor T7 are both electrically connected to the third scanning node SN3, and the second electrode of the seventh scanning transistor T7 is electrically connected to the first enable terminal EN O.

[0139] In this embodiment of the disclosure, the second scan control sub-circuit 522 includes an eighth scan transistor T8 and a ninth scan transistor T9. The eighth scan transistor T8 and the ninth scan transistor T9 are P-type transistors and are used as switching transistors.

[0140] The control electrode of the eighth scanning transistor T8 is electrically connected to the second enable terminal ENE, the first electrode of the eighth scanning transistor T8 is electrically connected to the second scanning node SN2, and the second electrode of the eighth scanning transistor T8 is electrically connected to the fourth scanning node SN4. The control electrode and the first electrode of the ninth scanning transistor T9 are both electrically connected to the fourth scanning node SN4, and the second electrode of the ninth scanning transistor T9 is electrically connected to the second enable terminal ENE.

[0141] In this embodiment of the disclosure, the first scan output sub-circuit 531 includes a tenth scan transistor T10, an eleventh scan transistor T11, a first scan capacitor C1, and a second scan capacitor C2.

[0142] The control electrode of the tenth scanning transistor T10 is electrically connected to the first scanning node SN1, the first electrode of the tenth scanning transistor T10 is electrically connected to the second power supply terminal VGH, and the second electrode of the tenth scanning transistor T10 is electrically connected to the first scanning output terminal GOUT_O. The control electrode of the eleventh scanning transistor T11 is electrically connected to the third scanning node SN3, the first electrode of the eleventh scanning transistor T11 is electrically connected to the second clock terminal GCB, and the second electrode of the eleventh scanning transistor T11 is electrically connected to the first scanning output terminal GOUT_O. The first terminal of the first scanning capacitor C1 is electrically connected to the first scanning node SN1, and the second terminal of the first scanning capacitor C1 is electrically connected to the second power supply terminal VGH. The first terminal of the second scanning capacitor C2 is electrically connected to the third scanning node SN3, and the second terminal of the second scanning capacitor C2 is electrically connected to the first scanning output terminal GOUT_O.

[0143] In this embodiment of the disclosure, the second scan output sub-circuit 532 includes a twelfth scan transistor T12, a thirteenth scan transistor T13, a third scan capacitor C3, and a fourth scan capacitor C4.

[0144] The control electrode of the twelfth scan transistor T12 is electrically connected to the first scan node SN1, the first electrode of the twelfth scan transistor T12 is electrically connected to the second power supply terminal VGH, and the second electrode of the twelfth scan transistor T12 is electrically connected to the second scan output terminal GOUT_E. The control electrode of the thirteenth scan transistor T13 is electrically connected to the fourth scan node SN4, the first electrode of the thirteenth scan transistor T13 is electrically connected to the second clock terminal GCB, and the second electrode of the thirteenth scan transistor T13 is electrically connected to the second scan output terminal GOUT_E. The first terminal of the third scan capacitor C3 is electrically connected to the first scan node SN1, and the second terminal of the third scan capacitor C3 is electrically connected to the second power supply terminal VGH. The first terminal of the fourth scan capacitor C4 is electrically connected to the fourth scan node SN4, and the second terminal of the fourth scan capacitor C4 is electrically connected to the second scan output terminal GOUT_E.

[0145] In this embodiment of the disclosure, the third scan output sub-circuit 533 includes a fourteenth scan transistor T14, a fifteenth scan transistor T15, a sixteenth scan transistor T16, a fifth scan capacitor C5, and a sixth scan capacitor C6.

[0146] The control electrode of the fourteenth scan transistor T14 is electrically connected to the first scan node SN1, the first electrode of the fourteenth scan transistor T14 is electrically connected to the second power supply terminal VGH, and the second electrode of the fourteenth scan transistor T14 is electrically connected to the third scan output terminal GOUT_n. The control electrode of the fifteenth scan transistor T15 is electrically connected to the first electrode of the sixteenth scan transistor T16, the first electrode of the fifteenth scan transistor T15 is electrically connected to the second clock terminal GCB, and the second electrode of the fifteenth scan transistor T15 is electrically connected to the third scan output terminal GOUT_n. The control electrode of the sixteenth scan transistor T16 is electrically connected to the first power supply terminal VGL, and the second electrode of the sixteenth scan transistor T16 is electrically connected to the second scan node SN2. The first terminal of the fifth scan capacitor C5 is electrically connected to the first scan node SN1, and the second terminal of the fifth scan capacitor C5 is electrically connected to the second power supply terminal VGH. The first terminal of the sixth scan capacitor C6 is electrically connected to the first electrode of the sixth scan transistor T16, and the second terminal of the sixth scan capacitor C6 is electrically connected to the third scan output terminal GOUT_n.

[0147] exist Figure 5A In the example, the first scanning transistor T1 to the sixteenth scanning transistor T16 are all P-type transistors, such as thin-film transistors with low-temperature doped polysilicon (LTPS) as the active layer. Those skilled in the art will understand that, according to the embodiments of this disclosure, the first scanning transistor T1 to the sixteenth scanning transistor T16 can also be N-type transistors, such as thin-film transistors with indium gallium zinc oxide (IGZO) as the active layer, by correspondingly changing the level of the gate conduction signal of each transistor.

[0148] Furthermore, those skilled in the art will understand that the scanning capacitor can be implemented as a single capacitor or multiple capacitor units connected in parallel or series, as long as it can achieve its corresponding function.

[0149] Figure 5B and Figure 5C yes Figure 5A Timing diagram of the mid-scan shift register. Figure 5B and Figure 5C The timing waveforms of each signal in each stage are shown. The following example... Figure 5A Taking the structure of the scan shift register shown as an example, combined with... Figure 5B and Figure 5C The signal timing diagram shown describes the operation of the scan shift register provided in this embodiment of the invention. The operation of the shift register includes four stages.

[0150] For example, Figure 5BThe timing diagram shows the output signals of the first scan output terminal GOUT_O, the second scan output terminal GOUT_E, and the third scan output terminal GOUT_n when the first enable signal EN_O is low and the second enable pixel EN_E is high.

[0151] In the first stage S1, the first scan input signal GIN_n is low, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0152] Under the control of the first clock signal GCK, the first scan transistor T1 and the second scan transistor T2 are turned on. The first scan input signal GIN_n is provided to the second scan node SN2 through the first scan transistor T1, at which time the potential of the second scan node SN2 is low. The first power supply voltage VGL is provided to the first scan node SN1 through the second scan transistor T2, at which time the potential of the first scan node SN1 is low.

[0153] Under the control of the low level of the first scan node N1, the fourth scan transistor T4, the tenth scan transistor T10, the twelfth scan transistor T12, and the fourteenth scan transistor T14 are turned on. Under the control of the low level of the second scan node SN2, the third scan transistor T3 is turned on. The fifth scan transistor T5 is turned off by the high level of the second clock signal GCB.

[0154] Since both the first power supply voltage VGL and the first clock signal GCK are low, this low level is supplied to the first terminals of the first scanning capacitor C1, the third scanning capacitor C3, and the fifth scanning capacitor C5, while the second power supply voltage VGH is supplied to the second terminals of the same capacitors. Therefore, the first power supply voltage VGL and the first clock signal GCK charge the first scanning capacitors C1, C3, and C5, causing their first terminals to store a low level.

[0155] Under the control of the first enable signal EN_O, the sixth scan transistor T6 is turned on, and the low level of the second scan node SN2 is applied to the third scan node SN3. Under the potential control of the third scan node SN3, the seventh scan transistor T7 is turned on, and the first enable signal EN_O is provided to the third scan node SN3. Under the control of the low level of the third scan node SN3, the eleventh scan transistor T11 is turned on.

[0156] When both the tenth scanning transistor T10 and the eleventh scanning transistor T11 are turned on, the first power supply voltage VGH and the second clock signal GCB are provided to the first scan output terminal GOUT_O. At this time, the first gate drive signal GOUT_O output by the first scan output terminal GOUT_O is at a high level.

[0157] Since the second terminal of the second scanning capacitor C2 is at a high level, the first terminal of the second scanning capacitor C2 is charged by the low level of the third scanning node SN3, and the first terminal of the second scanning capacitor C2 stores a low level.

[0158] The eighth scan transistor T8 is turned off by the high level of the second enable signal EN_E. When the twelfth scan transistor T12 is turned on, the first power supply voltage VGH is provided to the second scan output terminal GOUT_E, and at this time, the second gate drive signal GOUT_E output by the second scan output terminal GOUT_E is at a high level.

[0159] Under the control of the first power supply voltage VGL, the sixteenth scan transistor T16 is turned on, and the high level of the second scan node SN2 is provided to the control electrode of the fifteenth scan transistor T15. The fifteenth scan transistor T15 is turned off at a high level. When the fourteenth scan transistor T14 is turned on, the first power supply voltage VGH is provided to the third scan output terminal GOUT_n. At this time, the third gate drive signal GOUT_n output by the third scan output terminal GOUT_n is at a high level.

[0160] Since the second terminal of the sixth scanning capacitor C6 is at a high level, the first terminal of the sixth scanning capacitor C6 is charged by using the low level of the second scanning node SN2, and the first terminal of the sixth scanning capacitor C6 stores a low level.

[0161] In the second stage S2, the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0162] The first scanning transistor T1 and the second scanning transistor T2 are off when the first clock signal GCK is high. Under the control of the first power supply voltage VGL, the sixteenth scanning transistor T16 is turned on. Under the control of the first enable signal EN_O, the sixth scanning transistor T6 is turned on. With the low level stored at the first terminals of the second scanning capacitor C2 and the sixth scanning capacitor C6, a low level is provided to the eleventh scanning transistor T11 and the fifteenth scanning transistor T15, turning them on. The low level stored at the first terminals of the second scanning capacitor C2 and the sixth scanning capacitor C6 is provided to the second scanning node SN2 via the sixth scanning transistor T6 and the sixteenth scanning transistor T16. Under the control of the low level of the second scanning node SN2, the third scanning transistor T3 is turned on.

[0163] The first clock signal GCK is provided to the first scan node SN1 via the third scan transistor T3. At this time, the level of the first scan node SN1 is high. The fourth scan transistor T4, the tenth scan transistor T10, the twelfth scan transistor T12, and the fourteenth scan transistor T14 are turned off by the high level of the first scan node SN1. The eighth scan transistor T8 is turned off by the high level of the second enable signal EN_E.

[0164] When the tenth scan transistor T10 is off and the eleventh scan transistor T11 is on, the second clock signal GCB is provided to the first scan output terminal GOUT_O. At this time, the first gate drive signal GOUT_O output by the first scan output terminal GOUT_O is low.

[0165] When the fourteenth scan transistor T14 is off and the fifteenth scan transistor T15 is on, the second clock signal GCB is provided to the third scan output terminal GOUT_n. At this time, the third gate drive signal GOUT_n output by the third scan output terminal GOUT_n is low.

[0166] During phase S1, the second gate drive signal GOUT_E output from the second scan output terminal GOUT_E is at a high level, which charges the second terminal of the fourth scan capacitor C4, storing the high level signal. Therefore, during phase S2, the second terminal of the fourth scan capacitor C4 discharges, and the second gate drive signal GOUT_E output from the second scan output terminal GOUT_E becomes high.

[0167] In the third stage S3, the first scan input signal GIN_n is high, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0168] Under the control of the first clock signal GCK, the first scan transistor T1 and the second scan transistor T2 are turned on. The first scan input signal GIN_n is provided to the second scan node SN2 through the first scan transistor T1, at which time the potential of the second scan node SN2 is high. The first power supply voltage VGL is provided to the first scan node SN1 through the second scan transistor T2, at which time the potential of the first scan node SN1 is low.

[0169] Under the control of the low level of the first scan node N1, the fourth scan transistor T4, the tenth scan transistor T10, the twelfth scan transistor T12, and the fourteenth scan transistor T14 are turned on. The first terminals of the first scan capacitor C1, the third scan capacitor C3, and the fifth scan capacitor C5 store a low level. Under the control of the high level of the second scan node SN2, the third scan transistor T3 is turned on. The fifth scan transistor T5 is turned off by the high level of the second clock signal GCB.

[0170] Under the control of the first enable signal EN_O, the sixth scan transistor T6 is turned on. Under the action of the first power supply voltage VGL, the sixteenth scan transistor T16 is turned on. The high level of the second scan node SN2 is applied to the control electrode of the third scan node SN3 and the fifteenth scan transistor T15. The seventh scan transistor T7, the eleventh scan transistor T11, and the fifteenth scan transistor T15 are turned off at a high potential, and the first terminals of the second scan capacitor C2 and the sixth scan capacitor C6 store a high level.

[0171] When the tenth scanning transistor T10 is turned on and the eleventh scanning transistor T11 is turned off, the first power supply voltage VGH is provided to the first scanning output terminal GOUT_O. At this time, the first gate drive signal GOUT_O output by the first scanning output terminal GOUTO is at a high level.

[0172] When the eighth scanning transistor T8 is turned off by the high level of the second enable signal EN_E and the twelfth scanning transistor T12 is turned on, the first power supply voltage VGH is provided to the second scanning output terminal GOUT_E. At this time, the second gate drive signal GOUT_E output by the second scanning output terminal GOUT_E is at a high level.

[0173] When the fourteenth scan transistor T14 is turned on and the fifteenth scan transistor T15 is turned off, the first power supply voltage VGH is provided to the third scan output terminal GOUT_n. At this time, the third gate drive signal GOUT_n output by the third scan output terminal GOUT_n is at a high level.

[0174] In the fourth stage S4, the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0175] The first scanning transistor T1 and the second scanning transistor T2 are off when the first clock signal GCK is high. Under the control of the first power supply voltage VGL, the sixteenth scanning transistor T16 is turned on. Under the control of the first enable signal EN_E, the sixth scanning transistor T6 is turned on.

[0176] Since the first terminals of the second scanning capacitor C2 and the sixth scanning capacitor C6 are stored at high levels during the S3 stage, the first terminals of the second scanning capacitor C2 and the sixth scanning capacitor C6 are discharged, and the eleventh scanning transistor T11 and the fifteenth scanning transistor T15 are cut off at high potential.

[0177] Because the first terminals of the first scanning capacitor C1, the third scanning capacitor C3, and the fifth scanning capacitor C5 are stored at low levels during the S3 phase, the fourth scanning transistor T4, the tenth scanning transistor T10, the twelfth scanning transistor T12, and the fourteenth scanning transistor T14 are turned on.

[0178] When the tenth scanning transistor T10 is turned on and the eleventh scanning transistor T11 is turned off, the first power supply voltage VGH is provided to the first scanning output terminal GOUT_O. At this time, the first gate drive signal GOUT_O output by the first scanning output terminal GOUT_O is at a high level.

[0179] When the eighth scanning transistor T8 is turned off by the high level of the second enable signal EN_E and the twelfth scanning transistor T12 is turned on, the first power supply voltage VGH is provided to the second scanning output terminal GOUT_E. At this time, the second gate drive signal GOUT_E output by the second scanning output terminal GOUT_E is at a high level.

[0180] When the fourteenth scan transistor T14 is turned on and the fifteenth scan transistor T15 is turned off, the first power supply voltage VGH is provided to the third scan output terminal GOUT_n. At this time, the third gate drive signal GOUT_n output by the third scan output terminal GOUT_n is at a high level.

[0181] In this embodiment, by controlling the first enable signal EN_O to be low and the second enable signal EN_E to be high, the first gate drive signal GOUT_O output from the first scan output terminal GOUT_O is a pulse waveform, and the second gate drive signal GOUT_E output from the second scan output terminal GOUT_E is a DC signal, which remains at a high level. In this case, when the first gate drive signal GOUT_O drives the privacy sub-pixel, the privacy sub-pixel operates, and the light-emitting element in its pixel circuit emits light. When the second gate drive signal GOUT_E drives the display sub-pixel, under the DC drive of the second gate drive signal GOUT_E, the display sub-pixel does not operate, and the light-emitting element in its pixel circuit does not emit light.

[0182] Since the second gate drive signal GOUT_E is a DC signal, the logic power consumption caused by the voltage transition of the second gate drive signal GOUT_E can be reduced when the display sub-pixels are not working.

[0183] For example, Figure 5C The timing diagram shows the output signals of the first scan output terminal GOUT_O, the second scan output terminal GOUT_E, and the third scan output terminal GOUT_n when the first enable signal EN_O is high and the second enable pixel EN_E is low.

[0184] Figure 5C Under signal control Figure 5A The operation of the scan shift register 500 shown is similar to... Figure 5B Under signal control Figure 5A The operation of the scan shift register 500 shown is similar, and for the sake of simplicity, similar parts will not be described again.

[0185] In the first stage S1, the first scan input signal GIN_n is low, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0186] The first scan transistor T1 to the fourth scan transistor T4, the eighth scan transistor T8, the ninth scan transistor T9, and the twelfth scan transistor T12 to the sixteenth scan transistor T16 are turned on, while the fifth scan transistor T5 to the seventh scan transistor T7 and the eleventh scan transistor T11 are turned off. The potential of the first scan node SN1 is low, the potential of the second scan node SN2 is low, and the potential of the fourth scan node SN4 is low.

[0187] The first gate drive signal GOUT_O output from the first scan output terminal GOUT_O is at a high level. The second gate drive signal GOUT_E output from the second scan output terminal GOUT_E is at a high level. The third gate drive signal GOUT_n output from the third scan output terminal GOUT_n is at a high level.

[0188] In the second stage S2, the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0189] The third scanning transistor T3, the fifth scanning transistor T5, the eighth scanning transistor T8, the ninth scanning transistor T9, the thirteenth scanning transistor T13, the fifteenth scanning transistor T15, and the sixteenth scanning transistor T16 are turned on, while the first scanning transistor T1, the second scanning transistor T2, the fourth scanning transistor T4, the sixth scanning transistor T6, the seventh scanning transistor T7, the tenth to twelfth scanning transistors T10 through T12, and the fourteenth scanning transistor T14 are turned off. The potential of the first scanning node SN1 is high, the potential of the second scanning node SN2 is low, and the potential of the fourth scanning node SN4 is low.

[0190] The first gate drive signal GOUT_O output from the first scan output terminal GOUT_O is at a high level. The second gate drive signal GOUT_E output from the second scan output terminal GOUT_E is at a low level. The third gate drive signal GOUT_n output from the third scan output terminal GOUT_n is at a low level.

[0191] In the third stage S3, the first scan input signal GIN_n is high, the first clock signal GCK is low, the second clock signal GCB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0192] The first scanning transistor T1, the second scanning transistor T2, the fourth scanning transistor T4, the eighth scanning transistor T8, the tenth scanning transistor T10, the twelfth scanning transistor T12, the fourteenth scanning transistor T14, and the sixteenth scanning transistor T16 are turned on. The third scanning transistor T3, the fifth scanning transistor T5 through the seventh scanning transistor T7, the ninth scanning transistor T9, the eleventh scanning transistor T11, the thirteenth scanning transistor T13, and the fifteenth scanning transistor T15 are turned off. The potential of the first scanning node SN1 is low, the potential of the second scanning node SN2 is high, and the potential of the fourth scanning node SN4 is high.

[0193] The first gate drive signal GOUT_O output from the first scan output terminal GOUT_O is at a high level. The second gate drive signal GOUT_E output from the second scan output terminal GOUT_E is at a high level. The third gate drive signal GOUT_n output from the third scan output terminal GOUT_n is at a high level.

[0194] In the fourth stage S4, the first scan input signal GIN_n is high, the first clock signal GCK is high, the second clock signal GCB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0195] The fourth scan transistor T4, the fifth scan transistor T5, the eighth scan transistors T8 through T10, the twelfth scan transistor T12, the fourteenth scan transistor T14, and the sixteenth scan transistor T16 are turned on, while the first scan transistors T1 through T3, the sixth scan transistor T6, the seventh scan transistor T7, the eleventh scan transistor T11, the thirteenth scan transistor T13, and the fifteenth scan transistor T15 are turned off. The potential of the first scan node SN1 is low, the potential of the second scan node SN2 is high, and the potential of the fourth scan node SN4 is high.

[0196] The first gate drive signal GOUT_O output from the first scan output terminal GOUT_O is at a high level. The second gate drive signal GOUT_E output from the second scan output terminal GOUT_E is at a high level. The third gate drive signal GOUT_n output from the third scan output terminal GOUT_n is at a high level.

[0197] In this embodiment, by controlling the first enable signal EN_O to be high and the second enable signal EN_E to be low, the first gate drive signal GOUT_O output from the first scan output terminal GOUT_O is a DC signal, and the first gate drive signal GOUT_O remains at a high level. The second gate drive signal GOUT_E output from the second scan output terminal GOUT_E is a pulse waveform. In this case, when the first gate drive signal GOUT_O is used to drive the privacy sub-pixel, the privacy sub-pixel does not work under the DC drive of the first gate drive signal GOUT_O, and the light-emitting element in the pixel circuit of the privacy sub-pixel does not emit light. When the second gate drive signal GOUT_E is used to drive the display sub-pixel, the display sub-pixel works, and the light-emitting element in the pixel circuit of the display sub-pixel emits light.

[0198] Since the first gate drive signal GOUT_O is a DC signal, the logic power consumption caused by the voltage transition of the first gate drive signal GOUT_O can be reduced when the privacy pixel is not working.

[0199] When the first enable signal EN_O is low and the second enable signal EN_E is high, the timing of the first gate drive signal GOUT_O output by the first scan output terminal GOUT_O is the same as the timing of the third gate drive signal GOUT_n output by the third scan output terminal GOUT_n.

[0200] When the first enable signal EN_O is high and the second enable signal EN_E is low, the timing of the second gate drive signal GOUT_E output by the second scan output terminal GOUT_E is the same as the timing of the third gate drive signal GOUT_n output by the third scan output terminal GOUT_n.

[0201] In this embodiment, the output of the first gate drive signal GOUT_O is controlled based on the first enable signal EN_O, and the output of the second gate drive signal GOUT_E is controlled based on the second enable signal EN_E. When the first gate drive signal GOUT_O drives the privacy sub-pixel and the second gate drive signal GOUT_E drives the display sub-pixel, the operating state of the privacy sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the display sub-pixel can be controlled by controlling the level of the second enable signal EN_E. Correspondingly, when the first gate drive signal GOUT_O drives the display sub-pixel and the second gate drive signal GOUT_E drives the privacy sub-pixel, the operating state of the display sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the privacy sub-pixel can be controlled by controlling the level of the second enable signal EN_E.

[0202] For example, when the first gate drive signal GOUT_O drives the privacy screen sub-pixel and the second gate drive signal GOUT_E drives the display sub-pixel, the privacy screen sub-pixel can be independently controlled to be in an active state by controlling the level of the first enable signal EN_O to be low. The privacy screen sub-pixel can be independently controlled to be in an inactive state by controlling the level of the first enable signal EN_O to be high. Similarly, the display sub-pixel can be independently controlled to be in an active state by controlling the level of the second enable signal EN_E to be low. And the display sub-pixel can be independently controlled to be in an inactive state by controlling the level of the second enable signal EN_E to be high.

[0203] In this embodiment of the present disclosure, the control electrode of the eleventh scan transistor T11 is prevented from being in a floating state by using the seventh scan transistor T7. Similarly, the control electrode of the thirteenth scan transistor T13 is prevented from being in a floating state by using the ninth scan transistor T9.

[0204] In this embodiment of the disclosure, by setting the signal terminals of the second poles of the seventh scanning transistor T7 and the ninth scanning transistor T9 to be electrically connected, partial refresh of the display screen in the display panel can be achieved.

[0205] For example, the scan shift register 500 can be used to set different refresh rates for different rows of pixels in the pixel array. For example, the displayed image can include static and dynamic images. For example, a static image can be the unchanging background portion of the displayed image, while a dynamic image can be the portion of the displayed image where the image changes. When a monitor displays an image, a static image may appear for a period of time. If both static and dynamic images are refreshed at the same refresh rate (e.g., a high frequency), it will result in high power consumption. If the dynamic image portion is set to maintain its original high refresh rate, while the static image portion is set to refresh at a relatively lower refresh rate, refresh power consumption can be reduced.

[0206] For example, the frame refresh rate for dynamic scenes can be set to 120Hz. The display will refresh 120 frames per second. Similarly, the frame refresh rate for static scenes can be set to 60Hz or 30Hz. At a frame refresh rate of 60Hz, the display will refresh 60 frames per second. At a frame refresh rate of 30Hz, the display will refresh 30 frames per second.

[0207] By setting the signal timing of the signal output from the second terminal electrically connected to the seventh scanning transistor T7 and the ninth scanning transistor T9, the on / off state of the eleventh scanning transistor T11 and the thirteenth scanning transistor T13 can be controlled, thereby controlling whether the first scanning input terminal GOUT_O and the second scanning input terminal GOUT_E output signals or not output signals.

[0208] For example, when the first scan input terminal GOUT_O outputs the first gate drive signal GOUT_O, the privacy sub-pixel driven by the first gate drive signal GOUT_O refreshes its pixel value. When the first scan input terminal GOUT_O does not output the first gate drive signal GOUT_O, the privacy sub-pixel driven by the first gate drive signal GOUT_O does not refresh its pixel value.

[0209] Therefore, by setting the signal timing of the signal output from the second terminal of the seventh scanning transistor T7 and the ninth scanning transistor T9, gate drive signals with corresponding frame refresh rates can be provided for different pixel rows. This allows for flexible control of the refresh rate of different regions in the pixel array, enabling different regions in the pixel array to be refreshed at different refresh rates and reducing refresh power consumption.

[0210] Figure 6A This is a schematic diagram of the structure of a light-emitting control shift register according to another embodiment of the present disclosure.

[0211] like Figure 6A As shown, the light emission control shift register 600 includes a light emission control input circuit 640, a light emission control circuit 650, and a light emission control output circuit 660.

[0212] The light emission control input circuit 650 includes a first light emission control sub-circuit 651, a second light emission control sub-circuit 652, and a third light emission control sub-circuit 653. The light emission control output circuit 660 includes a first light emission control output sub-circuit 661, a second light emission control output sub-circuit 662, and a second light emission control output sub-circuit 663.

[0213] The light-emitting control input circuit 640, light-emitting control circuit 650, and light-emitting control output circuit 660 are similar to the light-emitting control input circuit 440, light-emitting control circuit 450, and light-emitting control output circuit 460 described above. The first light-emitting control sub-circuit 651, the second light-emitting control sub-circuit 652, and the third light-emitting control sub-circuit 653 are similar to the first light-emitting control sub-circuit 451, the second light-emitting control sub-circuit 452, and the third light-emitting control sub-circuit 453 described above. The first light-emitting control output sub-circuit 661, the second light-emitting control output sub-circuit 662, and the second light-emitting control output sub-circuit 663 are similar to the first light-emitting control output sub-circuit 461, the second light-emitting control output sub-circuit 462, and the second light-emitting control output sub-circuit 463 described above. For the sake of simplicity, the same parts will not be described again here.

[0214] In this embodiment of the disclosure, the light emission control input circuit 640 includes a first light emission control transistor T1, a second light emission control transistor T2, a third light emission control transistor T3, a fourth light emission control transistor T4, and a fifth light emission control transistor T5.

[0215] The control electrode of the first light-emitting control transistor T1 is connected to the first clock terminal ECK, the first electrode of the first light-emitting control transistor T1 is connected to the light-emitting control input terminal EIN_n, and the second electrode of the first light-emitting control transistor T1 is connected to the second light-emitting control node EMN2. The control electrode of the second light-emitting control transistor T2 is connected to the first clock terminal ECK, the first electrode of the second light-emitting control transistor T2 is connected to the first power supply terminal VGL, and the second electrode of the second light-emitting control transistor T2 is connected to the first light-emitting control node EMN1. The control electrode of the third light-emitting control transistor T3 is connected to the second light-emitting control node EMN2, the first electrode of the third light-emitting control transistor T3 is connected to the first clock terminal ECK, and the second electrode of the third light-emitting control transistor T3 is connected to the first light-emitting control node EMN1. The control electrode of the fourth light-emitting control transistor T4 is connected to the first light-emitting control node EMN1, the first electrode of the fourth light-emitting control transistor T4 is connected to the second power supply terminal VGH, and the second electrode of the fourth light-emitting control transistor T4 is connected to the first electrode of the fifth light-emitting control transistor T5. The control electrode of the fifth light-emitting control transistor T5 is connected to the second clock terminal ECB, and the second electrode of the fifth light-emitting control transistor T5 is connected to the second light-emitting control node EMN2.

[0216] In this embodiment, the first light-emitting control sub-circuit 651 includes a sixth light-emitting control transistor T6, a seventh light-emitting control transistor T7, and a first light-emitting control capacitor C1. The control electrode of the sixth light-emitting control transistor T6 is electrically connected to the first enable terminal EN_O, the first electrode of the sixth light-emitting control transistor T6 is electrically connected to the second light-emitting control node EMN2, and the second electrode of the sixth light-emitting control transistor T6 is electrically connected to the third light-emitting control node EMN3. The control electrode and the first electrode of the seventh light-emitting control transistor T7 are both electrically connected to the third light-emitting control node EMN3, and the second electrode of the seventh light-emitting control transistor T7 is electrically connected to the first enable terminal EN_O. The first terminal of the first light-emitting control capacitor C1 is electrically connected to the third light-emitting control node EMN3, and the second terminal of the first light-emitting control capacitor C1 is electrically connected to the second clock terminal ECB.

[0217] In this embodiment, the second light-emitting control sub-circuit 652 includes an eighth light-emitting control transistor T8, a ninth light-emitting control transistor T9, and a second light-emitting control capacitor C2. The control electrode of the eighth light-emitting control transistor T8 is electrically connected to the second enable terminal EN_E, the first electrode of the eighth light-emitting control transistor T8 is electrically connected to the second light-emitting control node EMN2, and the second electrode of the eighth light-emitting control transistor T8 is electrically connected to the fourth light-emitting control node EMN4. The control electrode and the first electrode of the ninth light-emitting control transistor T9 are both electrically connected to the fourth light-emitting control node EMN4, and the second electrode of the ninth light-emitting control transistor T9 is electrically connected to the second enable terminal EN_E. The first terminal of the second light-emitting control capacitor C2 is electrically connected to the fourth light-emitting control node EMN4, and the second terminal of the second light-emitting control capacitor C2 is electrically connected to the second clock terminal ECB.

[0218] In this embodiment, the third light-emitting control sub-circuit 653 includes a tenth light-emitting control transistor T10, an eleventh light-emitting control transistor T11, a twelfth light-emitting control transistor T12, a thirteenth light-emitting control transistor T13, and a third light-emitting control capacitor C3. The control electrode of the tenth light-emitting control transistor T10 is electrically connected to the first power supply terminal VGL, the first electrode of the tenth light-emitting control transistor T10 is electrically connected to the first light-emitting control node EMN1, and the second electrode of the tenth light-emitting control transistor T10 is electrically connected to the control electrode of the eleventh light-emitting control transistor T11. The first electrode of the eleventh light-emitting control transistor T11 is electrically connected to the second clock terminal ECB, and the second electrode of the eleventh light-emitting control transistor T11 is electrically connected to the first electrode of the twelfth light-emitting control transistor T12. The control electrode of the twelfth light-emitting control transistor T12 is electrically connected to the second clock terminal ECB, and the second electrode of the twelfth light-emitting control transistor T12 is electrically connected to the fifth light-emitting control node EMN5. The control electrode of the thirteenth light-emitting control transistor T13 is electrically connected to the second light-emitting control node EMN2. The first electrode of the thirteenth light-emitting control transistor T13 is electrically connected to the second power supply terminal VGH. The second electrode of the thirteenth light-emitting control transistor T13 is electrically connected to the fifth light-emitting control node EMN5. The first terminal of the third light-emitting control capacitor C3 is electrically connected to the control electrode of the eleventh light-emitting control transistor T11. The second terminal of the third light-emitting control capacitor C3 is electrically connected to the second electrode of the eleventh light-emitting control transistor T11.

[0219] In this embodiment, the first light-emitting control output sub-circuit 661 includes a fourteenth light-emitting control transistor T14, a fifteenth light-emitting control transistor T15, and a fourth light-emitting control capacitor C4. The control electrode of the fourteenth light-emitting control transistor T14 is electrically connected to the fifth light-emitting control node EMN5, the first electrode of the fourteenth light-emitting control transistor T14 is electrically connected to the second power supply terminal VGH, and the second electrode of the fourteenth light-emitting control transistor T14 is electrically connected to the first light-emitting control output terminal EOUT_O. The control electrode of the fifteenth light-emitting control transistor T15 is electrically connected to the third light-emitting control node EMN3, the first electrode of the fifteenth light-emitting control transistor T15 is electrically connected to the first power supply terminal VGL, and the second electrode of the fifteenth light-emitting control transistor T15 is electrically connected to the first light-emitting control output terminal EOUT_O. The first terminal of the fourth light-emitting control capacitor C4 is electrically connected to the fifth light-emitting control node EMN5, and the second terminal of the fourth light-emitting control capacitor C4 is electrically connected to the second power supply terminal VGH.

[0220] In this embodiment, the second light-emitting control output sub-circuit 662 includes a sixteenth light-emitting control transistor T16, a seventeenth light-emitting control transistor T17, and a fifth light-emitting control capacitor C5. The control electrode of the sixteenth light-emitting control transistor T16 is electrically connected to the fifth light-emitting control node EMN5, the first electrode of the sixteenth light-emitting control transistor T16 is electrically connected to the second power supply terminal VGH, and the second electrode of the sixteenth light-emitting control transistor T16 is electrically connected to the second light-emitting control output terminal EOUT_E. The control electrode of the seventeenth light-emitting control transistor T17 is electrically connected to the fourth light-emitting control node, the first electrode of the seventeenth light-emitting control transistor T17 is electrically connected to the first power supply terminal VGL, and the second electrode of the seventeenth light-emitting control transistor T17 is electrically connected to the second light-emitting control output terminal EOUT_E. The first terminal of the fifth light-emitting control capacitor C5 is electrically connected to the fifth light-emitting control node EMN5, and the second terminal of the fifth light-emitting control capacitor C5 is electrically connected to the second power supply terminal VGH.

[0221] In this embodiment, the third light-emitting control output sub-circuit 663 includes an eighteenth light-emitting control transistor T18, a nineteenth light-emitting control transistor T19, a twentieth light-emitting control transistor T20, and a sixth light-emitting control capacitor C6. The control electrode of the eighteenth light-emitting control transistor T18 is electrically connected to the fifth light-emitting control node EMN5, the first electrode of the eighteenth light-emitting control transistor T18 is electrically connected to the second power supply terminal VGH, and the second electrode of the eighteenth light-emitting control transistor T18 is electrically connected to the third light-emitting control output terminal EOUT_n. The control electrode of the nineteenth light-emitting control transistor T19 is electrically connected to the first electrode of the twentieth light-emitting control transistor T20, the first electrode of the nineteenth light-emitting control transistor T19 is electrically connected to the first power supply terminal VGL, and the second electrode of the nineteenth light-emitting control transistor T19 is electrically connected to the third light-emitting control output terminal EOUT_n. The control electrode of the twentieth light-emitting control transistor T20 is electrically connected to the first power supply terminal VGL, and the second electrode of the twentieth light-emitting control transistor T20 is electrically connected to the second light-emitting control node EMN2. The first terminal of the sixth light-emitting control capacitor C6 is electrically connected to the control electrode of the nineteenth light-emitting control transistor T19, and the second terminal of the sixth light-emitting control capacitor C6 is electrically connected to the second clock terminal ECB.

[0222] exist Figure 6A In the example, the first light-emitting control transistor T1 to the twentieth light-emitting control transistor T20 are all P-type transistors, such as thin-film transistors with low-temperature doped polycrystalline silicon (LTPS) as the active layer. Those skilled in the art will understand that, according to the embodiments of this disclosure, the first light-emitting control transistor T1 to the twentieth light-emitting control transistor T20 can also be N-type transistors, such as thin-film transistors with indium gallium zinc oxide (IGZO) as the active layer, by correspondingly changing the level of the gate conduction signal of each transistor.

[0223] Furthermore, those skilled in the art will understand that the light-emitting control capacitor can be implemented as a single capacitor or multiple capacitor units connected in parallel or series, as long as it can achieve its corresponding function.

[0224] Figure 6B and Figure 6C yes Figure 6A The signal timing diagram of the light-emitting control shift register. Figure 6B and Figure 6C The timing waveforms of each signal in each stage are shown. The following example... Figure 6A Taking the structure of the light-emitting control shift register shown as an example, combined with... Figure 6B and Figure 6C The signal timing diagram shown illustrates the operation of the light-emitting control shift register provided in this embodiment of the invention. The operation of the light-emitting control shift register includes five stages.

[0225] For example, Figure 6BThe timing diagram shows the output signals of the first light emission control output terminal EOUT_O, the second light emission control output terminal EOUT_E, and the third light emission control output terminal EOUT_n when the first enable signal EN_O is low and the second enable pixel EN_E is high.

[0226] In the first stage S1, the first light emission control input signal EIN_n is low, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0227] Under the control of the first clock signal ECK, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on. The first light-emitting control input signal EIN_n is provided to the second light-emitting control node EMN2 through the first light-emitting control transistor T1, at which time the potential of the second light-emitting control node EMN2 is high. The first power supply voltage VGL is provided to the first light-emitting control node EMN1 through the second light-emitting control transistor T2, at which time the potential of the first light-emitting control node EMN1 is low.

[0228] Under the control of the first power supply voltage VGL, the tenth light-emitting control transistor T10 is turned on. The potential of the first light-emitting control node EMN1 is supplied to the control electrode of the eleventh light-emitting control transistor T11 through the tenth light-emitting control transistor T10, and the eleventh light-emitting control transistor T11 is turned on. The potential of the first light-emitting control node EMN1 charges the first terminal of the third light-emitting control capacitor C3, and the first terminal of the third light-emitting control capacitor C3 is charged and stored at a low level.

[0229] The twelfth light-emitting control transistor T12 is cut off by the high potential of the second clock signal ECB, and the first light-emitting control node EMN1 and the fifth light-emitting control node EMN5 are disconnected.

[0230] Under the control of the first enable signal EN_O, the sixth light-emitting control transistor T6 is turned on, and the high level of the second light-emitting control node EMN2 is provided to the third light-emitting control node EMN3. The seventh light-emitting control transistor T7 and the fifteenth light-emitting control transistor T15 are turned off by the high level of the third light-emitting control node EMN3. The thirteenth light-emitting control transistor T13 is turned off by the high level of the second light-emitting control node EMN2.

[0231] The high level of the second light-emitting control node EMN2 charges the first terminal of the seventh light-emitting control capacitor C7 through the twentieth light-emitting control transistor T20. The high level of the second light-emitting control node EMN2 charges the first terminal of the first light-emitting control capacitor C1 through the sixth light-emitting control transistor T6. The first terminals of the first light-emitting control capacitor C1 and the seventh light-emitting control capacitor C7 are charged and stored as high level.

[0232] The eighth light-emitting control transistor T8 is turned off by the high level of the second enable signal EN_E. The second light-emitting control node EMN2 is disconnected from the fourth light-emitting control node EMN4.

[0233] Under the control of the first power supply voltage VGL, the twentieth light-emitting control transistor T20 is turned on, and the high level of the second light-emitting control node EMN2 is provided to the control electrode of the nineteenth light-emitting control transistor T19 through the twentieth light-emitting control transistor T20, and the nineteenth light-emitting control transistor T19 is turned off.

[0234] The fifth light-emitting control node EMN5 remains at the high level of the previous stage, and the potential of the fifth light-emitting control node EMN5 in the previous stage is the same as the potential of the fifth light-emitting control node EMN5 in stage S5. The fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are cut off by the fifth light-emitting control node EMN5, which remains at the high level of the previous stage.

[0235] With both the fifteenth light-emitting control transistor T15 and the fourteenth light-emitting control transistor T14 turned off, the first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is the same as in the previous stage, and the first light-emitting control signal EOUT_O is at a low level. The previous stage can be considered as the fifth stage S5 of the previous frame refresh process.

[0236] When both the nineteenth light-emitting control transistor T19 and the eighteenth light-emitting control transistor T18 are turned off, the third light-emitting control signal EOUT_n output by the third light-emitting control output terminal EOUT_n is the same as in the previous stage, and the third light-emitting control signal EOUT_n is at a low level.

[0237] When both the eighth light-emitting control transistor T18 and the sixteenth light-emitting control transistor T16 are turned off, the second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is the same as in the previous stage, and the second light-emitting control signal EOUT_E is at a high level.

[0238] In the second stage S2, the first light emission control input signal EIN_n is high, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0239] The first light-emitting control transistor T1 and the second light-emitting control transistor T2 are off when the first clock signal ECK is high. Under the control of the first power supply voltage VGL, the tenth light-emitting control transistor T10 and the twentieth light-emitting control transistor T20 are turned on. Under the control of the first enable signal EN_O, the sixth light-emitting control transistor T6 is turned on.

[0240] Under the control of the high level stored at the first terminal of the first light-emitting control capacitor C1 and the seventh light-emitting control capacitor C7, the third light-emitting control transistor T3, the fifteenth light-emitting control transistor T15 and the nineteenth light-emitting control transistor T19 are turned off.

[0241] Under the control of the low level stored at the first terminal of the third light-emitting control capacitor C3, the eleventh light-emitting control transistor T11 is turned on. Under the control of the second clock signal ECB, the twelfth light-emitting control transistor T12 is turned on. The second clock signal ECB is provided to the fifth light-emitting control node EMN5 through the twelfth light-emitting control transistor T12. At this time, the potential of the fifth light-emitting control node EMN5 is low.

[0242] Under the control of the low level of the fifth light-emitting control node EMN5, the fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned on. The low level of the fifth light-emitting control node EMN5 charges the first terminals of the fourth light-emitting control capacitor C4, the fifth light-emitting control capacitor C5, and the sixth light-emitting control capacitor C6, storing a low level at their first terminals. The eighth light-emitting control transistor T8 is turned off by the high level of the second enable signal EN_E.

[0243] When the fifteenth light-emitting control transistor T15 is turned off and the fourteenth light-emitting control transistor T14 is turned on, the second power supply voltage VGH is provided to the first light-emitting control output terminal EOUT_O. At this time, the first light-emitting control signal EOUT_O output by the first light-emitting control output terminal EOUT_O is at a high level.

[0244] When the nineteenth light-emitting control transistor T19 is off and the eighteenth light-emitting control transistor T18 is on, the second power supply voltage VGH is provided to the third light-emitting control output terminal EOUT_n. At this time, the third light-emitting control signal EOUT_n output by the third light-emitting control output terminal EOUT_n is at a high level.

[0245] When the eighth light-emitting control transistor T18 is off and the sixteenth light-emitting control transistor T16 is on, the second power supply voltage VGH is provided to the second light-emitting control output terminal EOUT_E. At this time, the second light-emitting control signal EOUT_E output by the second light-emitting control output terminal EOUT_E is at a high level.

[0246] In the third stage S3, the first light emission control input signal EIN_n is high, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0247] Under the control of the first clock signal ECK, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on. The first light-emitting control input signal EIN_n is provided to the second light-emitting control node EMN2 through the first light-emitting control transistor T1, at which time the potential of the second light-emitting control node EMN2 is high. The first power supply voltage VGL is provided to the first light-emitting control node EMN1 through the second light-emitting control transistor T2, at which time the potential of the first light-emitting control node EMN1 is low.

[0248] Under the control of the first power supply voltage VGL, the tenth light-emitting control transistor T10 and the twentieth light-emitting control transistor T20 are turned on. The potential of the first light-emitting control node EMN1 is provided to the control electrode of the eleventh light-emitting control transistor T11 through the tenth light-emitting control transistor T10, and the eleventh light-emitting control transistor T11 is turned on. The potential of the first light-emitting control node EMN1 charges the first terminal of the third light-emitting control capacitor C3, and the first terminal of the third light-emitting control capacitor C3 is charged and stored at a low level.

[0249] The twelfth light-emitting control transistor T12 is cut off by the high potential of the second clock signal ECB, and the first light-emitting control node EMN1 and the fifth light-emitting control node EMN5 are disconnected.

[0250] Under the control of the low level stored at the first terminals of the fourth light-emitting control capacitor C4, the fifth light-emitting control capacitor C5, and the sixth light-emitting control capacitor C6, the fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned on.

[0251] Under the control of the first enable signal EN_O, the sixth light-emitting control transistor T6 is turned on, and the high level of the second light-emitting control node EMN2 is provided to the third light-emitting control node EMN3. The seventh light-emitting control transistor T7 and the fifteenth light-emitting control transistor T15 are turned off by the high level of the third light-emitting control node EMN3. The thirteenth light-emitting control transistor T13 is turned off by the high level of the second light-emitting control node EMN2.

[0252] The high level of the second light-emitting control node EMN2 is charged through the twentieth light-emitting control transistor T20 and the first terminal of the seventh light-emitting control capacitor C7. The high level of the second light-emitting control node EMN2 is charged through the sixth light-emitting control transistor T6 to the first terminal of the first light-emitting control capacitor C1. The first terminals of the first light-emitting control capacitor C1 and the seventh light-emitting capacitor C7 are charged and stored as high level.

[0253] The high level of the second light-emitting control node EMN2 is provided to the control electrode of the nineteenth light-emitting control transistor T19 through the twentieth light-emitting control transistor T20, and the nineteenth light-emitting control transistor T19 is turned off.

[0254] The eighth light-emitting control transistor T8 is turned off by the high level of the second enable signal EN_E. The second light-emitting control node EMN2 is disconnected from the fourth light-emitting control node EMN4.

[0255] When the fifteenth light-emitting control transistor T15 is turned off and the fourteenth light-emitting control transistor T14 is turned on, the second power supply voltage VGH is provided to the first light-emitting control output terminal EOUT_O. At this time, the first light-emitting control signal EOUT_O output by the first light-emitting control output terminal EOUT_O is at a high level.

[0256] When the nineteenth light-emitting control transistor T19 is off and the eighteenth light-emitting control transistor T18 is on, the second power supply voltage VGH is provided to the third light-emitting control output terminal EOUT_n. At this time, the third light-emitting control signal EOUT_n output by the third light-emitting control output terminal EOUT_n is at a high level.

[0257] When the eighth light-emitting control transistor T8 is off and the sixteenth light-emitting control transistor T16 is on, the second power supply voltage VGH is provided to the second light-emitting control output terminal EOUT_E. At this time, the second light-emitting control signal EOUT_E output by the second light-emitting control output terminal EOUT_E is at a high level.

[0258] In the fourth stage S4, the first light emission control input signal EIN_n is low, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0259] The first light-emitting control transistor T1 and the second light-emitting control transistor T2 are off when the first clock signal ECK is high. Under the control of the first power supply voltage VGL, the tenth light-emitting control transistor T10 and the twentieth light-emitting control transistor T20 are turned on. Under the control of the first enable signal EN_O, the sixth light-emitting control transistor T6 is turned on.

[0260] Under the control of the low level stored at the first terminal of the third light-emitting control capacitor C3, the eleventh light-emitting control transistor T11 is turned on. The low level stored at the first terminal of the third light-emitting control capacitor C3 is provided to the first light-emitting control node EMN1 through the tenth light-emitting control transistor T10. Under the control of the low level of the first light-emitting control node EMN1, the fourth light-emitting control transistor T4 is turned on.

[0261] Under the control of the second clock signal ECB, the fifth light-emitting control transistor T5 and the twelfth light-emitting control transistor T12 are turned on. The second clock signal ECB is provided to the fifth light-emitting control node EMN5 through the eleventh light-emitting control transistor T11 and the twelfth light-emitting control transistor T12. At this time, the potential of the fifth light-emitting control node EMN5 is low. The second power supply voltage VGH is provided to the second light-emitting control node EMN2 through the fourth light-emitting control transistor T4 and the fifth light-emitting control transistor T5.

[0262] The high level of the second light-emitting control node EMN2 is provided to the control terminal of the nineteenth light-emitting control transistor T19 via the twentieth light-emitting control transistor T20. The high level of the second light-emitting control node EMN2 is provided to the control terminal of the fifteenth light-emitting control transistor T15 via the sixth light-emitting control transistor T6, and the fifteenth light-emitting control transistor T15 and the nineteenth light-emitting control transistor T19 are turned off.

[0263] Under the control of the low level of the fifth light-emitting control node EMN5, the fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned on. The low level of the fifth light-emitting control node EMN5 charges the first terminals of the fourth light-emitting control capacitor C4, the fifth light-emitting control capacitor C5, and the sixth light-emitting control capacitor C6, storing a low level at their first terminals. The eighth light-emitting control transistor T8 is turned off by the high level of the second enable signal EN_E.

[0264] When the fifteenth light-emitting control transistor T15 is turned off and the fourteenth light-emitting control transistor T14 is turned on, the second power supply voltage VGH is provided to the first light-emitting control output terminal EOUT_O. At this time, the first light-emitting control signal EOUT_O output by the first light-emitting control output terminal EOUT_O is at a high level.

[0265] When the nineteenth light-emitting control transistor T19 is off and the eighteenth light-emitting control transistor T18 is on, the second power supply voltage VGH is provided to the third light-emitting control output terminal EOUT_n. At this time, the third light-emitting control signal EOUT_n output by the third light-emitting control output terminal EOUT_n is at a high level.

[0266] When the eighth light-emitting control transistor T8 is off and the sixteenth light-emitting control transistor T16 is on, the second power supply voltage VGH is provided to the second light-emitting control output terminal EOUT_E. At this time, the second light-emitting control signal EOUT_E output by the second light-emitting control output terminal EOUT_E is at a high level.

[0267] In the fifth stage S5, the first light emission control input signal EIN_n is low, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is low, and the second enable signal EN_E is high.

[0268] Under the control of the first clock signal ECK, the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are turned on. The first light-emitting control input signal EIN_n is provided to the second light-emitting control node EMN2 through the first light-emitting control transistor T1, at which time the potential of the second light-emitting control node EMN2 is low. The first power supply voltage VGL is provided to the first light-emitting control node EMN1 through the second light-emitting control transistor T2, at which time the potential of the first light-emitting control node EMN1 is low.

[0269] Under the control of the first power supply voltage VGL, the tenth light-emitting control transistor T10 and the twentieth light-emitting control transistor T20 are turned on. The potential of the first light-emitting control node EMN1 is provided to the control electrode of the eleventh light-emitting control transistor T11 through the tenth light-emitting control transistor T10, and the eleventh light-emitting control transistor T11 is turned on. The potential of the first light-emitting control node EMN1 charges the first terminal of the third light-emitting control capacitor C3, and the first terminal of the third light-emitting control capacitor C3 is charged and stored at a low level.

[0270] The twelfth light-emitting control transistor T12 is cut off by the high potential of the second clock signal ECB, and the first light-emitting control node EMN1 and the fifth light-emitting control node EMN5 are disconnected.

[0271] Under the control of the first enable signal EN_O, the sixth light-emitting control transistor T6 is turned on, the low level of the second light-emitting control node EMN2 is provided to the third light-emitting control node EMN3, and the seventh light-emitting control transistor T7 and the fifteenth light-emitting control transistor T15 are turned on.

[0272] Under the control of the low level of the second light-emitting control node EMN2, the thirteenth light-emitting control transistor T13 is turned on, and the second power supply voltage VGH is provided to the fifth light-emitting control node EMN5 through the thirteenth light-emitting control transistor T13. The fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned off by the high level of the fifth light-emitting control node EMN5.

[0273] The high level of the second light-emitting control node EMN2 is provided to the control electrode of the nineteenth light-emitting control transistor T19 through the twentieth light-emitting control transistor T20, and the nineteenth light-emitting control transistor T19 is turned on.

[0274] The eighth light-emitting control transistor T8 is turned off by the high level of the second enable signal EN_E. The second light-emitting control node EMN2 is disconnected from the fourth light-emitting control node EMN4.

[0275] When the fifteenth light-emitting control transistor T15 is turned on and the fourteenth light-emitting control transistor T14 is turned off, the first power supply voltage VGL is provided to the first light-emitting control output terminal EOUT_O. At this time, the first light-emitting control signal EOUT_O output by the first light-emitting control output terminal EOUT_O is at a low level.

[0276] When the nineteenth light-emitting control transistor T19 is turned on and the eighteenth light-emitting control transistor T18 is turned off, the first power supply voltage VGL is provided to the third light-emitting control output terminal EOUT_n. At this time, the third light-emitting control signal EOUT_n output by the third light-emitting control output terminal EOUT_n is at a low level.

[0277] When both the eighth light-emitting control transistor T8 and the sixteenth light-emitting control transistor T16 are turned off, the second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is the same as that in the previous stage S4, and the second light-emitting control signal EOUT_E is at a high level.

[0278] In this embodiment, by controlling the first enable signal EN_O to be low and the second enable signal EN_E to be high, the first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is a pulse waveform, and the second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is a DC signal, which remains at a high level. In this case, when the first light-emitting control signal EOUT_O drives the privacy sub-pixel, the privacy sub-pixel operates, and the light-emitting element in its pixel circuit emits light. When the second light-emitting control signal EOUT_E drives the display sub-pixel, under the DC drive of the second light-emitting control signal EOUT_E, the display sub-pixel does not operate, and the light-emitting element in its pixel circuit does not emit light.

[0279] By enabling a group of sub-pixels and turning them off, the system eliminates the need to write data voltage to these sub-pixels when they are not in operation, thus reducing power consumption. Since the second light-emitting control signal EOUT_E is a DC signal, it also reduces logic power consumption caused by voltage fluctuations in the second light-emitting control signal EOUT_E when the sub-pixels are not in operation.

[0280] For example, Figure 6C The timing diagram shows the output signals of the first light emission control output terminal EOUT_O, the second light emission control output terminal EOUT_E, and the third light emission control output terminal EOUT_n when the first enable signal EN_O is high and the second enable pixel EN_E is low.

[0281] Figure 6C Under signal control Figure 6A The working process of the light-emitting control shift register 600 shown is similar to... Figure 6B Under signal control Figure 6A The operation of the light-emitting control shift register 600 shown is similar, and for the sake of simplicity, similar parts will not be described again.

[0282] In the first stage S1, the first light emission control input signal EIN_n is high, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0283] The first light-emitting control transistor T1, the second light-emitting control transistor T2, the fourth light-emitting control transistor T4, the eighth light-emitting control transistor T8, the tenth light-emitting control transistor T10, the eleventh light-emitting control transistor T11, and the twentieth light-emitting control transistor T20 are turned on. The third light-emitting control transistor T3, the fifth light-emitting control transistors T5 to T7, the ninth light-emitting control transistor T9, and the twelfth light-emitting control transistors T12 to T19 are turned off. The potential of the first light-emitting control node EMN1 is low, the potential of the second light-emitting control node EMN2 is high, the potential of the fourth light-emitting control node EMN4 is high, and the potential of the fifth light-emitting control node EMN5 is high.

[0284] The first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is at a high level. The second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is at a low level. The third light-emitting control signal EOUT_n output from the third light-emitting control output terminal EOUT_n is at a low level.

[0285] In the second stage S2, the first light emission control input signal EIN_n is high, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0286] The fourth light-emitting control transistor T4, the fifth light-emitting control transistor T5, the eighth light-emitting control transistor T8, the tenth to twelfth light-emitting control transistors T10 to T12, the fourteenth to sixteenth light-emitting control transistors T16, the eighteenth light-emitting control transistor T18, and the twentieth light-emitting control transistor T20 are turned on. The first to third light-emitting control transistors T3, the sixth to seventh light-emitting control transistor T6, the seventh to ninth light-emitting control transistor T9, the thirteenth to fifteenth light-emitting control transistor T15, the seventeenth to nineteenth light-emitting control transistor T19 are turned off. The potential of the first light-emitting control node EMN1 is low, the potential of the second light-emitting control node EMN2 is high, the potential of the fourth light-emitting control node EMN4 is high, and the potential of the fifth light-emitting control node EMN5 is low.

[0287] The first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is at a high level. The second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is at a high level. The third light-emitting control signal EOUT_n output from the third light-emitting control output terminal EOUT_n is at a high level.

[0288] In the third stage S3, the first light emission control input signal EIN_n is high, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0289] The first light-emitting control transistor T1, the second light-emitting control transistor T2, the fourth light-emitting control transistor T4, the eighth light-emitting control transistor T8, the tenth light-emitting control transistor T10, the eleventh light-emitting control transistor T11, the fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, the eighteenth light-emitting control transistor T18, and the twentieth light-emitting control transistor T20 are turned on. The third light-emitting control transistor T3, the fifth light-emitting control transistor T5 to the seventh light-emitting control transistor T7, the ninth light-emitting control transistor T9, the twelfth light-emitting control transistor T12, the thirteenth light-emitting control transistor T13, the fifteenth light-emitting control transistor T15, the seventeenth light-emitting control transistor T17, and the nineteenth light-emitting control transistor T19 are turned off. The potential of the first light-emitting control node EMN1 is low, the potential of the second light-emitting control node EMN2 is high, the potential of the fourth light-emitting control node EMN4 is high, and the potential of the fifth light-emitting control node EMN5 is low.

[0290] The first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is at a high level. The second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is at a high level. The third light-emitting control signal EOUT_n output from the third light-emitting control output terminal EOUT_n is at a high level.

[0291] In the fourth stage S4, the first light emission control input signal EIN_n is low, the first clock signal ECK is high, the second clock signal ECB is low, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0292] The fourth light-emitting control transistor T4, the fifth light-emitting control transistor T5, the eighth light-emitting control transistor T8, the tenth light-emitting control transistor T10, the eleventh light-emitting control transistor T11, the fourteenth light-emitting control transistor T14, the sixteenth light-emitting control transistor T16, the eighteenth light-emitting control transistor T18, and the twentieth light-emitting control transistor T20 are turned on. The first light-emitting control transistors T1 to T3, the sixth light-emitting control transistor T6, the seventh light-emitting control transistor T7, the ninth light-emitting control transistor T9, the thirteenth light-emitting control transistor T13, the fifteenth light-emitting control transistor T15, the seventeenth light-emitting control transistor T17, and the nineteenth light-emitting control transistor T19 are turned off. The potential of the first light-emitting control node EMN1 is low, the potential of the second light-emitting control node EMN2 is high, the potential of the fourth light-emitting control node EMN4 is high, and the potential of the fifth light-emitting control node EMN5 is low.

[0293] The first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is at a high level. The second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is at a high level. The third light-emitting control signal EOUT_n output from the third light-emitting control output terminal EOUT_n is at a high level.

[0294] In the fifth stage S5, the first light emission control input signal EIN_n is low, the first clock signal ECK is low, the second clock signal ECB is high, the first enable signal EN_O is high, and the second enable signal EN_E is low.

[0295] The first light-emitting control transistor T1 to the fourth light-emitting control transistor T4, the eighth light-emitting control transistor T8 to the eleventh light-emitting control transistor T11, the thirteenth light-emitting control transistor T13, the seventeenth light-emitting control transistor T17, the nineteenth light-emitting control transistor T190, and the twentieth light-emitting control transistor T20 are turned on. The fifth light-emitting control transistor T5 to the seventh light-emitting control transistor T7, the twelfth light-emitting control transistor T12, the fourteenth light-emitting control transistor T14 to the sixteenth light-emitting control transistor T16, and the eighteenth light-emitting control transistor T18 are turned off. The potential of the first light-emitting control node EMN1 is low, the potential of the second light-emitting control node EMN2 is low, the potential of the fourth light-emitting control node EMN4 is high, and the potential of the fifth light-emitting control node EMN5 is low.

[0296] The first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is at a high level. The second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is at a low level. The third light-emitting control signal EOUT_n output from the third light-emitting control output terminal EOUT_n is at a low level.

[0297] In this embodiment, by controlling the first enable signal EN_O to be high and the second enable signal EN_E to be low, the first light-emitting control signal EOUT_O output from the first light-emitting control output terminal EOUT_O is a DC signal, which remains at a high level. The second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is a pulse waveform. In this case, when the first light-emitting control signal EOUT_O is used to drive the privacy sub-pixel, the privacy sub-pixel does not work under the drive of the DC first light-emitting control signal EOUT_O, and the light-emitting element in the pixel circuit of the privacy sub-pixel does not emit light. When the second light-emitting control signal EOUT_E is used to drive the display sub-pixel, the display sub-pixel works, and the light-emitting element in the pixel circuit of the display sub-pixel emits light.

[0298] Since the first light emission control signal EOUT_O is a DC signal, the logic power consumption caused by the voltage jump of the first light emission control signal EOUT_O can be reduced when the privacy pixel is not working.

[0299] When the first enable signal EN_O is low and the second enable signal EN_E is high, the timing of the first light emission control signal EOUT_O output from the first light emission control output terminal EOUT_O is the same as the timing of the third gate drive signal EOUT_n output from the third light emission control output terminal EOUT_n.

[0300] When the first enable signal EN_O is high and the second enable signal EN_E is low, the timing of the second light-emitting control signal EOUT_E output from the second light-emitting control output terminal EOUT_E is the same as the timing of the third light-emitting control signal EOUT_n output from the third light-emitting control output terminal EOUT_n.

[0301] In this embodiment, the output of the first light-emitting control signal EOUT_O is controlled based on the first enable signal EN_O, and the output of the second light-emitting control signal EOUT_E is controlled based on the second enable signal EN_E. When the first light-emitting control signal EOUT_O drives the privacy sub-pixel and the second light-emitting control signal EOUT_E drives the display sub-pixel, the operating state of the privacy sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the display sub-pixel can be controlled by controlling the level of the second enable signal EN_E. Correspondingly, when the first light-emitting control signal EOUT_O drives the display sub-pixel and the second light-emitting control signal EOUT_E drives the privacy sub-pixel, the operating state of the display sub-pixel can be independently controlled by controlling the first enable signal EN_O, and the operating state of the privacy sub-pixel can be controlled by controlling the level of the second enable signal EN_E.

[0302] For example, when the first light-emitting control signal EOUT_O drives the privacy sub-pixel and the second light-emitting control signal EOUT_E drives the display sub-pixel, the privacy sub-pixel can be independently controlled to be in an active state by controlling the level of the first enable signal EN_O to be low. The privacy sub-pixel can be independently controlled to be in an inactive state by controlling the level of the first enable signal EN_O to be high. Similarly, the display sub-pixel can be independently controlled to be in an active state by controlling the level of the second enable signal EN_E to be low. And the display sub-pixel can be independently controlled to be in an inactive state by controlling the level of the second enable signal EN_E to be high.

[0303] In this embodiment of the disclosure, the control electrode of the fifteenth light-emitting control transistor T15 can be prevented from being in a floating state by using the seventh light-emitting control transistor T7. Similarly, the control electrode of the seventeenth light-emitting control transistor T17 can be prevented from being in a floating state by using the ninth light-emitting control transistor T9.

[0304] In this embodiment of the disclosure, by setting the signal terminals of the second poles of the seventh scanning transistor T7 and the ninth scanning transistor T9 to be electrically connected, partial refresh of the display screen in the display panel can be achieved.

[0305] In some embodiments, this disclosure also provides a shift register. The shift register can be used for both scanning shift registers and illumination control shift registers.

[0306] In this embodiment of the disclosure, the scan shift register can be the scan shift register 300a, scan shift register 400a, and scan shift register 500 described above. The light emission control shift register can be the light emission control shift register 300b, light emission control shift register 400b, and light emission control shift register 600 described above.

[0307] In this embodiment of the disclosure, a scan shift register and a light emission control shift register form a driving unit in the driving circuit, which can provide gate driving signals and light emission control signals for a row of pixels in the pixel array.

[0308] Figure 7A This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present disclosure.

[0309] like Figure 7A As shown, the drive circuit 700a includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include shift register 710_1, shift register 710_2, ..., scan shift register 710M.

[0310] In this embodiment of the disclosure, the shift register can be the scan shift register 300a, scan shift register 400a, and scan shift register 500 described above, and it can also be the light emission control shift register 300b, light emission control shift register 400b, and light emission control shift register 600 described above. The shift register may also include any one of the scan shift registers 300a, 400a, and 500 described above, and any one of the light emission control shift registers 300b, 400b, and 600 described above.

[0311] In this embodiment of the disclosure, the input terminal of the m-th stage shift register is electrically connected to the output terminal of the (m-1)-th stage shift register, where 1 < m ≤ M.

[0312] In this embodiment of the disclosure, the input terminal INPUT of the first-stage shift register 710_1 is electrically connected to the trigger signal terminal STV.

[0313] In this embodiment of the disclosure, each shift register of the driving circuit 700a can provide a gate driving signal and a light emission control signal for a row of pixels in the pixel array.

[0314] Figure 7B This is a schematic diagram of the gate drive circuit according to an embodiment of the present disclosure.

[0315] like Figure 7B As shown, the gate drive circuit 700b includes M cascaded scan shift registers, where M is a positive integer greater than 1. The M scan shift registers include scan shift register ST1, scan shift register ST2, ..., scan shift register STM.

[0316] In this embodiment of the disclosure, the scan shift register can be the scan shift register 300a, scan shift register 400a and scan shift register 500 mentioned above.

[0317] In this embodiment of the disclosure, in the cascaded M scan shift registers, the scan input terminal INPUT of the m-th scan shift register is electrically connected to the third scan output terminal OUTPUT3 of the (m-1)-th scan shift register, and the third scan output terminal OUTPUT3 of the m-th scan shift register is electrically connected to the scan input terminal INPUT of the (m+1)-th scan shift register, where 1 < m ≤ M-1.

[0318] For example, the scan input terminal INPUT of the second-stage scan shift register ST2 is electrically connected to the third scan output terminal OUTPUT3 of the first-stage scan shift register ST1. The third gate drive signal GOUT(1) output by the third scan output terminal OUTPUT3 of the first-stage scan shift register ST1 is the input signal of the scan input terminal INPUT of the second-stage scan shift register ST2.

[0319] In this embodiment of the disclosure, the scan input terminal INPUT of the first-stage scan shift register ST1 is electrically connected to the scan trigger signal terminal GSTV, and the third scan output terminal OUTPUT3 of the M-stage scan shift register STM is electrically connected to the anti-static terminal ESD.

[0320] In this embodiment of the disclosure, the first power supply terminal VGL of the cascaded M scan shift registers is electrically connected to the power supply terminal Vgl, which provides a low-potential voltage. The second power supply terminal VGH of the cascaded M scan shift registers is electrically connected to the power supply terminal Vgh, which provides a high-potential voltage.

[0321] In this embodiment of the disclosure, the first clock terminal GCK of the cascaded M scan shift registers is electrically connected to the clock signal terminal CK to receive the first clock signal GCK. The second clock terminal GCB of the cascaded M scan shift registers is electrically connected to the clock signal terminal CB to receive the second clock signal GCB.

[0322] In this embodiment of the present disclosure, the first enable terminal EN_O of the cascaded M scan shift registers is electrically connected to enable terminal EN1 and receives the first enable signal EN_O. The second enable terminal EN_E of the cascaded M scan shift registers is electrically connected to enable terminal EN2 and receives the second enable signal EN_E.

[0323] Figure 7C This is a schematic diagram of the structure of a light-emitting control driving circuit according to an embodiment of the present disclosure.

[0324] like Figure 7C As shown, the light-emitting control drive circuit 700c includes M cascaded light-emitting control shift registers, where M is a positive integer greater than 1. The M light-emitting control shift registers include light-emitting control shift register ET1, light-emitting control shift register ET2, ..., light-emitting control shift register ETM.

[0325] In this embodiment of the disclosure, the light emission control shift register can be the light emission control shift register 300b, light emission control shift register 400b and light emission control shift register 600 mentioned above.

[0326] In this embodiment of the disclosure, in the cascaded M light-emitting control shift registers, the light-emitting control input terminal INPUT of the m-th level light-emitting control shift register is electrically connected to the third light-emitting control output terminal OUTPUT3 of the (m-1)-th level light-emitting control shift register, and the third light-emitting control output terminal OUTPUT3 of the m-th level light-emitting control shift register is electrically connected to the light-emitting control input terminal INPUT of the (m+1)-th level light-emitting control shift register, where 1 < m ≤ M-1.

[0327] For example, the light-emitting control input terminal INPUT of the second-stage light-emitting control shift register ET2 is electrically connected to the third light-emitting control output terminal OUTPUT3 of the first-stage light-emitting control shift register ET1. The third light-emitting control signal EOUT(1) output by the third light-emitting control output terminal OUTPUT3 of the first-stage light-emitting control shift register ET1 is the input signal of the light-emitting control input terminal INPUT of the second-stage light-emitting control shift register ET2.

[0328] In this embodiment of the disclosure, the light-emitting control input terminal INPUT of the first-stage light-emitting control shift register ET1 is electrically connected to the light-emitting control trigger signal terminal ESTV, and the third light-emitting control output terminal OUTPUT3 of the M-stage light-emitting control shift register ETM is electrically connected to the anti-static terminal ESD.

[0329] In this embodiment of the disclosure, the first power supply terminal VGL of the cascaded M light-emitting control shift registers is electrically connected to the power supply terminal Vgl, which provides a low-potential voltage. The second power supply terminal VGH of the cascaded M light-emitting control shift registers is electrically connected to the power supply terminal Vgh, which provides a high-potential voltage.

[0330] In this embodiment of the disclosure, the first clock terminal ECK of the cascaded M light-emitting control shift registers is electrically connected to the clock signal terminal CK to receive the first clock signal ECK. The second clock terminal ECB of the cascaded M light-emitting control shift registers is electrically connected to the clock signal terminal CB to receive the second clock signal ECB.

[0331] In this embodiment of the present disclosure, the first enable terminal EN_O of the cascaded M light-emitting control shift registers is electrically connected to enable terminal EN1 and receives a first enable signal EN_O. The second enable terminal EN_E of the cascaded M light-emitting control shift registers is electrically connected to enable terminal EN2 and receives a second enable signal EN_E.

[0332] Figure 8A This is a schematic diagram of the structure of a pixel unit according to an embodiment of the present disclosure.

[0333] like Figure 8A As shown, pixel unit P1 includes a first sub-pixel group Pixel O1 and a second sub-pixel group Pixel E1.

[0334] In this embodiment of the disclosure, the first sub-pixel group Pixel O1 may include a first sub-pixel Sub-Pixel O1_1, a first sub-pixel Sub-Pixel O1_2, and a first sub-pixel Sub-Pixel O1_3. The second sub-pixel group Pixel E1 may include a second sub-pixel Sub-Pixel E1_1, a second sub-pixel Sub-Pixel E1_2, and a second sub-pixel Sub-Pixel E1_3.

[0335] For example, first sub-pixels O1_1, O1_2, and O1_3 can be privacy sub-pixels. Second sub-pixels E1_1, E1_2, and E1_3 can be display sub-pixels. When first sub-pixels O1_1, O1_2, and O1_3 are active, and second sub-pixels E1_1, E1_2, and E1_3 are inactive, the display device is in privacy mode. When first sub-pixels O1_1, O1_2, and O1_3 are inactive, and second sub-pixels E1_1, E1_2, and E1_3 are active, the display device is in normal display mode.

[0336] For example, the first sub-pixel O1_1, the first sub-pixel O1_2, and the first sub-pixel O1_3 can also be display sub-pixels. The second sub-pixel E1_1, the second sub-pixel E1_2, and the second sub-pixel E1_3 can be privacy sub-pixels.

[0337] In this embodiment of the disclosure, the first sub-pixel Sub-Pixel O1_1, the first sub-pixel Sub-Pixel O1_2, and the first sub-pixel Sub-Pixel O1_3 can be considered as sub-pixels in the same row. The second sub-pixel Sub-Pixel E1_1, the second sub-pixel Sub-Pixel E1_2, and the second sub-pixel Sub-Pixel E1_3 can also be considered as sub-pixels in the same row.

[0338] For example, the first sub-pixels Sub-Pixel O1_1, Sub-Pixel O1_2, and Sub-Pixel O1_3 can be sub-pixels in the first row of the pixel array, and the second sub-pixels Sub-Pixel E1_1, Sub-Pixel E1_2, and Sub-Pixel E1_3 can be sub-pixels in the second row of the pixel array. A single-stage shift register provides gate drive signals and light emission control signals to the two rows of sub-pixels.

[0339] In this embodiment of the disclosure, the odd-numbered rows of sub-pixels in the pixel array of the display panel can be set to be privacy sub-pixels, and the even-numbered rows of sub-pixels can be set to be display sub-pixels.

[0340] Figure 8B This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0341] like Figure 8B As shown, the display device 800 includes a display panel 810 and a driving circuit 820.

[0342] In this embodiment of the disclosure, the display panel 810 includes a plurality of pixel units. The structure of each pixel unit can be as follows: Figure 8A As shown.

[0343] For example, pixel unit 810_1 includes a first sub-pixel group Pixel O1 and a second sub-pixel group Pixel E1. The first sub-pixel group Pixel O1 is electrically connected to the first scan output terminal GOUT(1)_O of the first-stage scan shift register ST1 of the shift register 820_1 in the driving circuit 820 and the first light emission control output terminal EOUT(1)_O of the first-stage light emission control shift register ET1. The second sub-pixel group Pixel E1 is electrically connected to the second scan output terminal GOUT(1)_E of the first-stage scan shift register ST1 of the shift register 820_1 in the driving circuit 820 and the second light emission control output terminal EOUT(1)_E of the first-stage light emission control shift register ET1.

[0344] In this embodiment of the disclosure, the light emission angle of the plurality of first sub-pixels included in the first sub-pixel group Pixel O1 is smaller than the light emission angle of the plurality of second sub-pixels included in the second sub-pixel group Pixel E1. The light emission angle is the angle between the emitted light and the direction perpendicular to the display panel. For example, the plurality of first sub-pixels included in the first sub-pixel group Pixel O1 can be privacy sub-pixels, and the plurality of second sub-pixels included in the second sub-pixel group Pixel E1 can be display sub-pixels.

[0345] Figure 9A This is a schematic diagram of the structure of a pixel unit according to another embodiment of the present disclosure.

[0346] like Figure 9A As shown, pixel unit P2 includes a first sub-pixel group Pixel O2 and a second sub-pixel group Pixel E2.

[0347] In this embodiment of the disclosure, the first sub-pixel group Pixel O2 may include a first sub-pixel Sub-Pixel O2_1, a first sub-pixel Sub-Pixel O2_2, and a first sub-pixel Sub-Pixel O2_3. The second sub-pixel group Pixel E2 may include a second sub-pixel Sub-Pixel E2_1, a second sub-pixel Sub-Pixel E2_2, and a second sub-pixel Sub-Pixel E2_3.

[0348] For example, the first sub-pixels Sub-Pixel O2_1, Sub-Pixel O2_2, and Sub-Pixel O2_3 can be privacy sub-pixels. The second sub-pixels Sub-Pixel E2_1, Sub-Pixel E2_2, and Sub-Pixel E2_3 can be display sub-pixels. When the first sub-pixels Sub-Pixel O2_1, Sub-Pixel O2_2, and Sub-Pixel O2_3 are active, and the second sub-pixels Sub-Pixel E2_1, Sub-Pixel E2_2, and Sub-Pixel E2_3 are inactive, the display device is in privacy mode. When the first sub-pixels Sub-Pixel O2_1, Sub-Pixel O2_2, and Sub-Pixel O2_3 are inactive, and the second sub-pixels Sub-Pixel E2_1, Sub-Pixel E2_2, and Sub-Pixel E2_3 are active, the display device is in normal display mode.

[0349] For example, the first sub-pixel O2_1, the first sub-pixel O2_2, and the first sub-pixel O2_3 can also be display sub-pixels. The second sub-pixel E2_1, the second sub-pixel E2_2, and the second sub-pixel E2_3 can be privacy sub-pixels.

[0350] In this embodiment, the first sub-pixels Sub-Pixel O2_1, Sub-Pixel O2_2, and Sub-Pixel O2_3, the second sub-pixels Sub-Pixel E2_1, Sub-Pixel E2_2, and Sub-Pixel E2_3 can be considered as sub-pixels in the same row. The first sub-pixels Sub-Pixel O2_1, Sub-Pixel O2_2, and Sub-Pixel O2_3 can be considered as sub-pixels in the same column. Similarly, the second sub-pixels Sub-Pixel E2_1, Sub-Pixel E2_2, and Sub-Pixel E2_3 can be considered as sub-pixels in the same column.

[0351] For example, the first sub-pixels Sub-Pixel O2_1, Sub-Pixel O2_2, and Sub-Pixel O2_3, the second sub-pixels Sub-Pixel E2_1, Sub-Pixel E2_2, and Sub-Pixel E2_3 are all sub-pixels in the first row, and the same shift register provides the gate drive signal and light emission control signal for the row of sub-pixels. Specifically, the first sub-pixels Sub-Pixel O2_1, Sub-Pixel O2_2, and Sub-Pixel O2_3 can be sub-pixels in the first column of the pixel array, while the first sub-pixels Sub-Pixel E2_1, Sub-Pixel E2_2, and Sub-Pixel E2_3 can be sub-pixels in the second column of the pixel array.

[0352] In this embodiment of the disclosure, the odd-numbered columns of sub-pixels in the pixel array of the display panel can be set to be privacy sub-pixels, and the even-numbered columns of sub-pixels can be set to be display sub-pixels.

[0353] Figure 9B This is a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0354] like Figure 9B As shown, the display device 900 includes a display panel 910 and a driving circuit 920.

[0355] In this embodiment of the disclosure, the display panel 910 includes a plurality of pixel units. The structure of each pixel unit can be as follows: Figure 9A As shown.

[0356] For example, pixel unit 9101 includes a first sub-pixel group Pixel O2 and a second sub-pixel group Pixel E2. The first sub-pixel group Pixel O2 is electrically connected to the first scan output terminal GOUT(1)_O of the first-stage scan shift register ST1 of the shift register 920_1 in the driving circuit 920 and the first light emission control output terminal EOUT(1)_O of the first-stage light emission control shift register ET1. The second sub-pixel group Pixel E2 is electrically connected to the second scan output terminal GOUT(1)_E of the first-stage scan shift register ST1 of the shift register 920_1 in the driving circuit 920 and the second light emission control output terminal EOUT(1)_E of the first-stage light emission control shift register ET1.

[0357] In this embodiment, the light emission angle of the plurality of first sub-pixels included in the first sub-pixel group Pixel O2 is smaller than the light emission angle of the plurality of second sub-pixels included in the second sub-pixel group Pixel E2. The light emission angle is the angle between the emitted light and the direction perpendicular to the display panel. For example, the plurality of first sub-pixels included in the first sub-pixel group Pixel O2 can be privacy sub-pixels, and the plurality of second sub-pixels included in the second sub-pixel group Pixel E2 can be display sub-pixels.

[0358] Figure 10 This is a flowchart of a driving method according to an embodiment of the present disclosure.

[0359] like Figure 10 As shown, the driving method can be applied to the scan shift registers 300a, 400a, and 500 described above. The driving method can also be applied to the light emission control shift registers 300b, 400b, and 600 described above. Furthermore, the driving method can be applied to any one of the scan shift registers 300a, 400a, and 500 described above, as well as any one of the light emission control shift registers 300b, 400b, and 600 described above.

[0360] In this embodiment of the disclosure, the driving method may include operations S1010 to S1030.

[0361] In operation S1010, the first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, controlling the first output terminal in the input terminal to output a pulse signal and the second output terminal in the input terminal to output a DC signal.

[0362] In operation S1020, the first enable signal is at the second level and the second enable signal is at the first level, controlling the first output terminal to output a DC signal and the second output terminal to output a pulse signal.

[0363] When operating S1030, both the first enable signal and the second enable signal are at the first level, controlling both the first output terminal and the second output terminal to output pulse signals.

[0364] Figure 11A This is a flowchart of a driving method according to another embodiment of the present disclosure.

[0365] like Figure 11A As shown, the driving method can be applied to the scan shift registers 300a, 400a, and 500 described above. The driving method may include operations S11 10a to S11 30a.

[0366] In operation S11 10a, the first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, controlling the first scan output terminal to output a pulse signal and the second scan output terminal to output a DC signal.

[0367] When operating S1120a, the first enable signal is at the second level and the second enable signal is at the first level, controlling the first scan output terminal to output a DC signal and the second scan output terminal to output a pulse signal.

[0368] When operating S1130a, both the first enable signal and the second enable signal are at the first level, controlling both the first scan output terminal and the second scan output terminal to output pulse signals.

[0369] In this embodiment of the disclosure, operations S1110a to S1130a are similar to those performed by the scan shift register 500 described above, and will not be repeated here.

[0370] In this embodiment, the first level is low and the second level is high. Those skilled in the art can also set the first level to high and the second level to low depending on the type of transistor in the shift register.

[0371] Figure 11B This is a flowchart of a driving method according to another embodiment of the present disclosure.

[0372] like Figure 11B As shown, the driving method can be applied to the light emission control shift registers 300b, 400b, and 600 described above. The driving method may include operations S1110b to S1130b.

[0373] In operation S1110b, the first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, controlling the first light-emitting control output terminal to output a pulse signal and the second light-emitting control output terminal to output a DC signal.

[0374] When operating S1120b, the first enable signal is at the second level and the second enable signal is at the first level, controlling the first light-emitting control output terminal to output a DC signal and the second light-emitting control output terminal to output a pulse signal.

[0375] When operating S1130b, both the first enable signal and the second enable signal are at the first level, controlling both the first light-emitting control output terminal and the second light-emitting control output terminal to output pulse signals.

[0376] In this embodiment of the disclosure, operations S1110b to S1130b are similar to the operations performed by the light emission control shift register 600 described above, and will not be repeated here.

[0377] In this embodiment, the first level is low and the second level is high. Those skilled in the art can also set the first level to high and the second level to low depending on the type of transistor in the shift register.

[0378] Figure 12 This is a schematic diagram of the structure of a scan shift register according to an embodiment of the present disclosure.

[0379] like Figure 12 As shown, the shift register 1200 includes an input circuit 1210, a control circuit 1220, and an output circuit 1230.

[0380] In this embodiment of the disclosure, the driving method described above, including operations S1010 to S1030, can be applied to shift register 1200.

[0381] In this embodiment of the disclosure, the input circuit 1210 is configured to provide a first power supply voltage VGL from the first power supply terminal VGL to the first node N1, and to provide an input signal INPUT from the input terminal INPUT to the second node N, under the control of a first clock signal CK from the first clock terminal CK. The control circuit 1220 is configured to provide the potential of the second node N2 to the third node N3, under the control of a first enable signal EN0 from the first enable terminal EN0, and to provide the potential of the second node N2 to the fourth node N4, under the control of a second enable signal ENE from the second enable terminal ENE. The output circuit 1230 is configured to output a signal through the output terminal OUTPUT, under the control of the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N3.

[0382] In this embodiment, shift register 1200 can be the scan shift register 300a, scan shift register 400a, and scan shift register 500 described above. Shift register 1200 can also be the light emission control shift register 300b, light emission control shift register 400b, and light emission control shift register 600 described above. Shift register 1200 can also include any one of the scan shift registers 300a, 400a, and 500 described above, and any one of the light emission control shift registers 300b, 400b, and 600 described above.

[0383] In this embodiment, the input circuit 1210 can be the scanning input circuit 310, scanning input circuit 410, and scanning input circuit 510 described above. The input circuit 1210 can also be the light emission control input circuit 340, light emission control input circuit 440, and light emission control input circuit 640. The input circuit 1210 may also include any one of the scanning input circuits 310, 410, and 510, and any one of the light emission control input circuits 340, 440, and 640.

[0384] In this embodiment, the control circuit 1220 can be the scanning control circuit 320, scanning control circuit 420, and scanning control circuit 520 described above. The control circuit 1220 can also be the light emission control circuit 350, light emission control circuit 450, and light emission control circuit 650. The control circuit 1220 may also include any one of the scanning control circuits 320, 420, and 520, and any one of the light emission control circuits 350, 450, and 650.

[0385] In this embodiment, the output circuit 1230 can be the scanning output circuit 330, scanning output circuit 430, and scanning output circuit 530 described above. The output circuit 1230 can also be the light emission control output circuit 360, light emission control output circuit 460, and light emission control output circuit 660. The output circuit 1230 may also include any one of the scanning output circuits 330, 430, and 530, and any one of the light emission control output circuits 360, 460, and 660.

[0386] In this embodiment, the first node N1 can be either the first scanning node SN1 or the first light-emitting control node EMN1 described above. The first node N1 may also include both the first scanning node SN1 and the first light-emitting control node EMN1. The second node N2 can be either the second scanning node SN2 or the second light-emitting control node EMN2 described above. The second node N2 may also include both the second scanning node SN2 and the second light-emitting control node EMN2. The third node N3 can be either the third scanning node SN3 or the third light-emitting control node EMN3 described above. The third node N3 may also include both the third scanning node SN3 and the third light-emitting control node EMN3. The fourth node N4 can be either the fourth scanning node SN4 or the fourth light-emitting control node EMN4 described above. The fourth node N4 may also include both the first scanning node SN4 and the fourth light-emitting control node EMN4.

[0387] In this embodiment of the disclosure, the input terminal INPUT can be the scanning input terminal GIN_n described above, or the light emission control input terminal EIN_n described above. The input terminal INPUT may also include the scanning input terminal GIN_n and the light emission control input terminal EIN_n.

[0388] In this embodiment of the disclosure, the output terminal OUTPUT may include the first scan output terminal GOUT_O, the second scan output terminal GOUT_E, and the third scan output terminal GOUT_n described above. The output terminal OUTPUT may also include the first light emission control output terminal EOUT_O, the second light emission control output terminal EOUT_E, and the third light emission control output terminal EOUT_n described above.

[0389] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0390] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0391] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register, comprising: The input circuit, electrically connected to the input terminal, the first power supply terminal and the first clock terminal, is configured to provide the first power supply voltage of the first power supply terminal to the first node and provide the input signal from the input terminal to the second node under the control of the first clock signal from the first clock terminal; The control circuit, electrically connected to the first enable terminal, the second enable terminal and the second node, is configured to provide the potential of the second node to the third node under the control of the first enable signal from the first enable terminal, and to provide the potential of the second node to the fourth node under the control of the second enable signal from the second enable terminal. as well as An output circuit is electrically connected to a second clock terminal, a first power supply terminal, a second power supply terminal, a first node, a second node, a third node, and a fourth node. The output terminals include a first scan output terminal, a second scan output terminal, and a third scan output terminal. The output circuit is configured to provide a second power supply voltage from the second power supply terminal or a second clock signal from the second clock terminal to the first scan output terminal under the control of the potential of the first node and the potential of the third node; to provide a second power supply voltage or a second clock signal to the second scan output terminal under the control of the potential of the first node and the potential of the fourth node; and to provide a second power supply voltage or a second clock signal to the third scan output terminal under the control of the potential of the first node, the potential of the second node, and the first power supply voltage.

2. The shift register according to claim 1, wherein, The input circuit includes a scan input circuit, the control circuit includes a scan control circuit, the output circuit includes a scan output circuit, the input terminal includes a scan input terminal, the first node includes a first scan node, the second node includes a second scan node, the third node includes a third scan node, the fourth node includes a fourth scan node, and the output terminal includes a first scan output terminal, a second scan output terminal, and a third scan output terminal. The scanning input circuit is electrically connected to the scanning input terminal, the first power supply terminal, and the first clock terminal. It is configured to provide the first power supply voltage to the first scanning node and provide the scanning input signal from the scanning input terminal to the second scanning node under the control of the first clock signal. The scan control circuit, electrically connected to the first enable terminal, the second enable terminal, and the second scan node, is configured to, under the control of the first enable signal, provide the potential of the second scan node to the third scan node, and under the control of the second enable signal, provide the potential of the second scan node to the fourth scan node; and The scan output circuit is electrically connected to a second clock terminal, a first power supply terminal, a second power supply terminal, a first scan node, a second scan node, a third scan node, and a fourth scan node. It is configured to provide a second power supply voltage from the second power supply terminal or a second clock signal from the second clock terminal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node; to provide a second power supply voltage or a second clock signal to the second scan output terminal under the control of the potential of the first scan node and the potential of the fourth scan node; and to provide a second power supply voltage or a second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node, and the first power supply voltage.

3. The shift register according to claim 2, wherein, The scanning control circuit includes: A first scan control subcircuit, electrically connected to the first enable terminal, the second scan node, and the third scan node, is configured to, under the control of the first enable signal, provide the potential of the second scan node to the third scan node; and The second scan control sub-circuit, electrically connected to the second enable terminal, the second scan node, and the fourth scan node, is configured to provide the potential of the second scan node to the fourth scan node under the control of the second enable signal.

4. The shift register according to claim 2, wherein, The scan output circuit includes: The first scan output sub-circuit is electrically connected to the second clock terminal, the second power supply terminal, the first scan node, and the third scan node, and is configured to provide the second power supply voltage or the second clock signal to the first scan output terminal under the control of the potential of the first scan node and the potential of the third scan node. The second scan output sub-circuit, electrically connected to the second clock terminal, the second power supply terminal, the first scan node, and the fourth scan node, is configured to provide the second power supply voltage or the second clock signal to the second scan output terminal under the control of the potentials of the first scan node and the fourth scan node; and The third scan output sub-circuit is electrically connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the first scan node, and the second scan node. It is configured to provide the second power supply voltage or the second clock signal to the third scan output terminal under the control of the potential of the first scan node, the potential of the second scan node, and the first power supply voltage.

5. The shift register according to claim 2, wherein, The scanning input circuit is also electrically connected to the second clock terminal and the second power supply terminal, and is configured to provide the second power supply voltage to the second scanning node under the control of the potential of the first scanning node and the second clock signal, and to provide the first clock signal to the first scanning node under the control of the potential of the second scanning node.

6. The shift register according to claim 5, wherein, The scanning input circuit includes: First scan transistor, second scan transistor, third scan transistor, fourth scan transistor, and fifth scan transistor; Wherein, the control electrode of the first scanning transistor is electrically connected to the first clock terminal, the first electrode of the first scanning transistor is electrically connected to the scanning input terminal, and the second electrode of the first scanning transistor is electrically connected to the second scanning node; The control electrode of the second scanning transistor is electrically connected to the first clock terminal, the first electrode of the second scanning transistor is electrically connected to the first power supply terminal, and the second electrode of the second scanning transistor is electrically connected to the first scanning node. The control electrode of the third scanning transistor is electrically connected to the second scanning node, the first electrode of the third scanning transistor is electrically connected to the first clock terminal, and the second electrode of the third scanning transistor is electrically connected to the first scanning node. The control electrode of the fourth scanning transistor is electrically connected to the first scanning node, the first electrode of the fourth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth scanning transistor is electrically connected to the first electrode of the fifth scanning transistor; and The control electrode of the fifth scanning transistor is electrically connected to the second clock terminal, and the second electrode of the fifth scanning transistor is electrically connected to the second scanning node.

7. The shift register according to claim 3, wherein, The first scan control sub-circuit includes a sixth scan transistor and a seventh scan transistor; Wherein, the control electrode of the sixth scanning transistor is electrically connected to the first enable terminal, the first electrode of the sixth scanning transistor is electrically connected to the second scanning node, and the second electrode of the sixth scanning transistor is electrically connected to the third scanning node; and The control electrode and the first electrode of the seventh scanning transistor are both electrically connected to the third scanning node, and the second electrode of the seventh scanning transistor is electrically connected to the first enable terminal.

8. The shift register according to claim 3, wherein, The second scan control sub-circuit includes an eighth scan transistor and a ninth scan transistor; Wherein, the control electrode of the eighth scanning transistor is electrically connected to the second enable terminal, the first electrode of the eighth scanning transistor is electrically connected to the second scanning node, and the second electrode of the eighth scanning transistor is electrically connected to the fourth scanning node; and The control electrode and the first electrode of the ninth scanning transistor are both electrically connected to the fourth scanning node, and the second electrode of the ninth scanning transistor is electrically connected to the second enable terminal.

9. The shift register according to claim 4, wherein, The first scan output sub-circuit includes a tenth scan transistor, an eleventh scan transistor, a first scan capacitor, and a second scan capacitor; The control electrode of the tenth scanning transistor is electrically connected to the first scanning node, the first electrode of the tenth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth scanning transistor is electrically connected to the first scanning output terminal. The control electrode of the eleventh scanning transistor is electrically connected to the third scanning node, the first electrode of the eleventh scanning transistor is electrically connected to the second clock terminal, and the second electrode of the eleventh scanning transistor is electrically connected to the first scanning output terminal. The first terminal of the first scanning capacitor is electrically connected to the first scanning node, and the second terminal of the first scanning capacitor is electrically connected to the second power supply terminal; and The first end of the second scanning capacitor is electrically connected to the third scanning node, and the second end of the second scanning capacitor is electrically connected to the first scanning output terminal.

10. The shift register according to claim 4, wherein, The second scan output sub-circuit includes a twelfth scan transistor, a thirteenth scan transistor, a third scan capacitor, and a fourth scan capacitor; The control electrode of the twelfth scanning transistor is electrically connected to the first scanning node, the first electrode of the twelfth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the twelfth scanning transistor is electrically connected to the second scanning output terminal. The control electrode of the thirteenth scanning transistor is electrically connected to the fourth scanning node, the first electrode of the thirteenth scanning transistor is electrically connected to the second clock terminal, and the second electrode of the thirteenth scanning transistor is electrically connected to the second scanning output terminal. The first terminal of the third scanning capacitor is electrically connected to the first scanning node, and the second terminal of the third scanning capacitor is electrically connected to the second power supply terminal; and The first end of the fourth scanning capacitor is electrically connected to the fourth scanning node, and the second end of the fourth scanning capacitor is electrically connected to the second scanning output terminal.

11. The shift register according to claim 4, wherein, The third scan output sub-circuit includes a fourteenth scan transistor, a fifteenth scan transistor, a sixteenth scan transistor, a fifth scan capacitor, and a sixth scan capacitor; The control electrode of the fourteenth scanning transistor is electrically connected to the first scanning node, the first electrode of the fourteenth scanning transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth scanning transistor is electrically connected to the third scanning output terminal. The control electrode of the fifteenth scanning transistor is electrically connected to the first electrode of the sixteenth scanning transistor, the first electrode of the fifteenth scanning transistor is electrically connected to the second clock terminal, and the second electrode of the fifteenth scanning transistor is electrically connected to the third scanning output terminal. The control electrode of the sixteenth scanning transistor is electrically connected to the first power supply terminal, and the second electrode of the sixteenth scanning transistor is electrically connected to the second scanning node; The first terminal of the fifth scanning capacitor is electrically connected to the first scanning node, and the second terminal of the fifth scanning capacitor is electrically connected to the second power supply terminal; and The first terminal of the sixth scanning capacitor is electrically connected to the first terminal of the sixteenth scanning transistor, and the second terminal of the sixth scanning capacitor is electrically connected to the third scanning output terminal.

12. The shift register according to claim 1, wherein, The input circuit includes a light-emitting control input circuit, the control circuit includes a light-emitting control circuit, the output circuit includes a light-emitting control output circuit, the input terminal includes a light-emitting control input terminal, the first node includes a first light-emitting control node, the second node includes a second light-emitting control node, the third node includes a third light-emitting control node, the fourth node includes a fourth light-emitting control node, and the output terminal includes a first light-emitting control output terminal, a second light-emitting control output terminal, and a third light-emitting control output terminal. The light emission control input circuit is electrically connected to the light emission control input terminal, the first power supply terminal, and the first clock terminal, and is configured to provide the first power supply voltage to the first light emission control node under the control of the first clock signal, and to provide the light emission control input signal from the light emission control input terminal to the second light emission control node. The light-emitting control circuit, electrically connected to the first enable terminal, the second enable terminal, the first power supply terminal, the second power supply terminal, the second clock terminal, the first light-emitting control node, and the second light-emitting control node, is configured to, under the control of the first enable signal, provide the potential of the second light-emitting control node to the third light-emitting control node; under the control of the second enable signal, provide the potential of the second light-emitting control node to the fourth light-emitting control node; and under the control of the first power supply voltage, the potential of the second light-emitting control node, the potential of the first light-emitting control node, and the second clock signal, provide the second clock signal or the second power supply voltage to the fifth light-emitting control node; and The light-emitting control output circuit is electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node, the third light-emitting control node, the fourth light-emitting control node, and the fifth light-emitting control node. It is configured to provide the first power supply voltage or the second power supply voltage to the first light-emitting control output terminal under the control of the potential of the third light-emitting control node and the potential of the fifth light-emitting control node; to provide the first power supply voltage or the second power supply voltage to the second light-emitting control output terminal under the control of the potential of the fourth light-emitting control node and the potential of the fifth light-emitting control node; and to provide the first power supply voltage or the second power supply voltage to the third light-emitting control output terminal under the control of the potential of the second light-emitting control node, the potential of the fifth light-emitting control node, and the first power supply voltage.

13. The shift register according to claim 12, wherein, The light-emitting control circuit includes: The first light-emitting control sub-circuit is electrically connected to the first enable terminal, the second clock terminal, the second light-emitting control node, and the third light-emitting control node, and is configured to provide the potential of the second light-emitting control node to the third light-emitting control node under the control of the first enable signal and the second clock signal. The second light-emitting control sub-circuit, electrically connected to the second enable terminal, the second clock terminal, the second light-emitting control node, and the fourth light-emitting control node, is configured to provide the potential of the second light-emitting control node to the fourth light-emitting control node under the control of the second enable signal and the second clock signal; and The third light-emitting control sub-circuit is electrically connected to the first power supply terminal, the second power supply terminal, the second clock terminal, the first light-emitting control node, the second light-emitting control node, and the fifth light-emitting control node. It is configured to provide the second clock signal or the second power supply voltage to the fifth light-emitting control node under the control of the first power supply voltage, the potential of the second light-emitting control node, the potential of the first light-emitting control node, and the second clock signal.

14. The shift register according to claim 12, wherein, The light emission control output circuit includes: The first light-emitting control output sub-circuit is electrically connected to the first power supply terminal, the second power supply terminal, the third light-emitting control node, and the fifth light-emitting control node. It is configured to provide the first power supply voltage or the second power supply voltage to the first light-emitting control output terminal under the control of the potential of the third light-emitting control node and the potential of the fifth light-emitting control node. The second light-emitting control output sub-circuit, electrically connected to the first power supply terminal, the second power supply terminal, the fourth light-emitting control node, and the fifth light-emitting control node, is configured to provide either the first power supply voltage or the second power supply voltage to the second light-emitting control output terminal under the control of the potential of the fourth light-emitting control node and the potential of the fifth light-emitting control node; and The third light-emitting control output sub-circuit is electrically connected to the first power supply terminal, the second power supply terminal, the second light-emitting control node, and the fifth light-emitting control node. It is configured to provide the first power supply voltage or the second power supply voltage to the third light-emitting control output terminal under the control of the potential of the second light-emitting control node, the potential of the fifth light-emitting control node, and the first power supply voltage.

15. The shift register according to claim 12, wherein, The light-emitting control input circuit is also electrically connected to the second clock terminal and the second power supply terminal. It is configured to provide the second power supply voltage to the second light-emitting control node under the control of the potential of the first light-emitting control node and the second clock signal, and to provide the first clock signal to the first light-emitting control node under the control of the potential of the second light-emitting control node.

16. The shift register according to claim 15, wherein, The light emission control input circuit includes: First light-emitting control transistor, second light-emitting control transistor, third light-emitting control transistor, fourth light-emitting control transistor, fifth light-emitting control transistor; Wherein, the control electrode of the first light-emitting control transistor is electrically connected to the first clock terminal, the first electrode of the first light-emitting control transistor is electrically connected to the light-emitting control input terminal, and the second electrode of the first light-emitting control transistor is electrically connected to the second light-emitting control node. The control electrode of the second light-emitting control transistor is electrically connected to the first clock terminal, the first electrode of the second light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the second light-emitting control transistor is electrically connected to the first light-emitting control node. The control electrode of the third light-emitting control transistor is electrically connected to the second light-emitting control node, the first electrode of the third light-emitting control transistor is electrically connected to the first clock terminal, and the second electrode of the third light-emitting control transistor is electrically connected to the first light-emitting control node. The control electrode of the fourth light-emitting control transistor is electrically connected to the first light-emitting control node, the first electrode of the fourth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth light-emitting control transistor is electrically connected to the first electrode of the fifth light-emitting control transistor; and The control electrode of the fifth light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the fifth light-emitting control transistor is electrically connected to the second light-emitting control node.

17. The shift register according to claim 13, wherein, The first light-emitting control sub-circuit includes a sixth light-emitting control transistor, a seventh light-emitting control transistor, and a first light-emitting control capacitor; Wherein, the control electrode of the sixth light-emitting control transistor is electrically connected to the first enable terminal, the first electrode of the sixth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the sixth light-emitting control transistor is electrically connected to the third light-emitting control node; The control electrode and the first electrode of the seventh light-emitting control transistor are both electrically connected to the third light-emitting control node, and the second electrode of the seventh light-emitting control transistor is electrically connected to the first enable terminal; and The first terminal of the first light-emitting control capacitor is electrically connected to the third light-emitting control node, and the second terminal of the first light-emitting control capacitor is electrically connected to the second clock terminal.

18. The shift register according to claim 13, wherein, The second light-emitting control sub-circuit includes an eighth light-emitting control transistor, a ninth light-emitting control transistor, and a second light-emitting control capacitor. Wherein, the control electrode of the eighth light-emitting control transistor is electrically connected to the second enable terminal, the first electrode of the eighth light-emitting control transistor is electrically connected to the second light-emitting control node, and the second electrode of the eighth light-emitting control transistor is electrically connected to the fourth light-emitting control node; The control electrode and first electrode of the ninth light-emitting control transistor are both electrically connected to the fourth light-emitting control node, and the second electrode of the ninth light-emitting control transistor is electrically connected to the second enable terminal; and The first terminal of the second light-emitting control capacitor is electrically connected to the fourth light-emitting control node, and the second terminal of the second light-emitting control capacitor is electrically connected to the second clock terminal.

19. The shift register according to claim 13, wherein, The third light-emitting control sub-circuit includes a tenth light-emitting control transistor, an eleventh light-emitting control transistor, a twelfth light-emitting control transistor, a thirteenth light-emitting control transistor, and a third light-emitting control capacitor; Wherein, the control electrode of the tenth light-emitting control transistor is electrically connected to the first power supply terminal, the first electrode of the tenth light-emitting control transistor is electrically connected to the first light-emitting control node, and the second electrode of the tenth light-emitting control transistor is electrically connected to the control electrode of the eleventh light-emitting control transistor; The first terminal of the eleventh light-emitting control transistor is electrically connected to the second clock terminal, and the second terminal of the eleventh light-emitting control transistor is electrically connected to the first terminal of the twelfth light-emitting control transistor; The control electrode of the twelfth light-emitting control transistor is electrically connected to the second clock terminal, and the second electrode of the twelfth light-emitting control transistor is electrically connected to the fifth light-emitting control node; The control electrode of the thirteenth light-emitting control transistor is electrically connected to the second light-emitting control node, the first electrode of the thirteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node; and The first terminal of the third light-emitting control capacitor is electrically connected to the control electrode of the eleventh light-emitting control transistor, and the second terminal of the third light-emitting control capacitor is electrically connected to the second electrode of the eleventh light-emitting control transistor.

20. The shift register according to claim 14, wherein, The first light-emitting control output sub-circuit includes a fourteenth light-emitting control transistor, a fifteenth light-emitting control transistor, and a fourth light-emitting control capacitor; The control electrode of the fourteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the fourteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth light-emitting control transistor is electrically connected to the first light-emitting control output terminal. The control electrode of the fifteenth light-emitting control transistor is electrically connected to the third light-emitting control node, the first electrode of the fifteenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the fifteenth light-emitting control transistor is electrically connected to the first light-emitting control output terminal; and The first end of the fourth light-emitting control capacitor is electrically connected to the fifth light-emitting control node, and the second end of the fourth light-emitting control capacitor is electrically connected to the second power supply terminal.

21. The shift register according to claim 14, wherein, The second light-emitting control output sub-circuit includes a sixteenth light-emitting control transistor, a seventeenth light-emitting control transistor, and a fifth light-emitting control capacitor; The control electrode of the sixteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the sixteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth light-emitting control transistor is electrically connected to the second light-emitting control output terminal. The control electrode of the seventeenth light-emitting control transistor is electrically connected to the fourth light-emitting control node, the first electrode of the seventeenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the seventeenth light-emitting control transistor is electrically connected to the second light-emitting control output terminal; and The first end of the fifth light-emitting control capacitor is electrically connected to the fifth light-emitting control node, and the second end of the fifth light-emitting control capacitor is electrically connected to the second power supply terminal.

22. The shift register according to claim 14, wherein, The third light-emitting control output sub-circuit includes an eighteenth light-emitting control transistor, a nineteenth light-emitting control transistor, a twentieth light-emitting control transistor, and a sixth light-emitting control capacitor; The control electrode of the eighteenth light-emitting control transistor is electrically connected to the fifth light-emitting control node, the first electrode of the eighteenth light-emitting control transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth light-emitting control transistor is electrically connected to the third light-emitting control output terminal. The control electrode of the nineteenth light-emitting control transistor is electrically connected to the first electrode of the twentieth light-emitting control transistor, the first electrode of the nineteenth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth light-emitting control transistor is electrically connected to the third light-emitting control output terminal. The control electrode of the twentieth light-emitting control transistor is electrically connected to the first power supply terminal, and the second electrode of the twentieth light-emitting control transistor is electrically connected to the second light-emitting control node; and The first terminal of the sixth light-emitting control capacitor is electrically connected to the control electrode of the nineteenth light-emitting control transistor, and the second terminal of the sixth light-emitting control capacitor is electrically connected to the second clock terminal.

23. A driving circuit comprising M cascaded shift registers as described in any one of claims 1-22, where M is a positive integer greater than 1; The input of the m-th stage shift register is electrically connected to the output of the (m-1)-th stage shift register, where 1 < m ≤ M.

24. A display device, comprising: Display panel; as well as The driving circuit as described in claim 23; The display panel includes multiple pixel units, each pixel unit including a first sub-pixel group and a second sub-pixel group. The first sub-pixel group is electrically connected to the first scan output terminal and the first light emission control output terminal in the driving circuit, and the second sub-pixel group is electrically connected to the second scan output terminal and the second light emission control output terminal in the driving circuit. The light emission angle of the multiple first sub-pixels included in the first sub-pixel group is smaller than the light emission angle of the multiple second sub-pixels included in the second sub-pixel group. The light emission angle is the angle between the emitted light and the direction perpendicular to the display panel.

25. A driving method applied to a shift register as described in any one of claims 1-22, comprising: The first enable signal from the first enable terminal is at a first level and the second enable signal from the second enable terminal is at a second level, controlling the first output terminal in the input terminal to output a pulse signal and the second output terminal in the input terminal to output a DC signal; The first enable signal is at a second level and the second enable signal is at a first level, controlling the first output terminal to output a DC signal and the second output terminal to output a pulse signal; as well as Both the first enable signal and the second enable signal are at a first level, controlling both the first output terminal and the second output terminal to output pulse signals.

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