Array substrate, display panel

Abstract

This application relates to an array substrate and a display panel. The array substrate includes a substrate and a gate driving circuit. The gate driving circuit is located on one side of the substrate and includes a multi-stage shift register. The shift register includes a first output transistor, a second output transistor, and a control module. The first output transistor is connected between a first signal line and the output terminal of the shift register, and the second output transistor is connected between a second signal line and the output terminal of the shift register. The gates of the first and second output transistors are electrically connected to the control module. The orthographic projections of the first and second output transistors on the substrate are located on the same side as the orthographic projection of the control module on the substrate. This design saves space and facilitates narrow bezel design of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the development of technology and the advancement of the display industry, consumers have increasingly higher requirements for the bezels of display products, and narrow bezels or even zero bezels are gradually becoming a trend. Therefore, how to further narrow the bezels of display products is a problem that needs to be solved. Summary of the Invention

[0003] Therefore, it is necessary to provide an array substrate and display panel that can make the bezels of display products narrower, in order to address the above-mentioned technical problems.

[0004] The first aspect of this application provides an array substrate, comprising:

[0005] Substrate;

[0006] A gate driving circuit is located on one side of the substrate. The gate driving circuit includes a multi-stage shift register. The shift register includes a first output transistor, a second output transistor, and a control module. The first output transistor is connected between a first signal line and the output terminal of the shift register. The second output transistor is connected between a second signal line and the output terminal of the shift register. The gates of the first and second output transistors are electrically connected to the control module. The orthographic projections of the first and second output transistors on the substrate are located on the same side as the orthographic projection of the control module on the substrate.

[0007] In some embodiments, the orthographic projections of the first and second output transistors on the substrate are located between the orthographic projection of the control module on the substrate and the edge of the array substrate.

[0008] In some embodiments, one of the first signal line and the second signal line is a high-voltage power line and the other is a low-voltage power line.

[0009] And / or, the first signal line and the second signal line extend along the first direction and are arranged along the second direction.

[0010] And / or, the gate drive circuit is a light-emitting control drive circuit.

[0011] And / or, the array substrate further includes signal output lines electrically connected to the output of the shift register, the signal output lines extending along a second direction, and the signal output lines and the orthographic projection of the control module on the substrate arranged along a first direction.

[0012] In some embodiments, the multi-stage shift registers are arranged along a first direction, and the orthographic projections of the first output transistor and the second output transistor on the substrate are located on one side of the opposite sides of the orthographic projection of the control module on the substrate along a second direction, with the first direction intersecting the second direction.

[0013] In some embodiments, the array substrate further includes a first clock signal line, a second clock signal line, and a first power supply line electrically connected to the control module, wherein the first clock signal line, the second clock signal line, and the first power supply line are arranged on the same layer.

[0014] In some embodiments, the orthographic projection of the first clock signal line on the substrate overlaps with the orthographic projection of the control module on the substrate.

[0015] In some embodiments, the orthographic projection of the second clock signal line on the substrate overlaps with the orthographic projection of the control module on the substrate.

[0016] In some embodiments, the orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the control module on the substrate.

[0017] In some embodiments, the first clock signal line, the second clock signal line, and the first power line extend along a first direction and are arranged along a second direction.

[0018] In some embodiments, the orthographic projection of the first signal line onto the substrate overlaps with the orthographic projections of the first output transistor and the second output transistor onto the substrate.

[0019] In some embodiments, the first clock signal line, the second clock signal line, the first power line, and the first signal line are arranged on the same layer.

[0020] In some embodiments, the first power line and the first signal line have different potentials.

[0021] In some embodiments, the first power line and the second signal line have the same potential.

[0022] In some embodiments, each shift register is connected to a first power line via two vias.

[0023] In some embodiments, the control module includes a plurality of first transistors, the gates of which are electrically connected via a first conductive trace, which is electrically connected to one of a first clock signal line and a second clock signal line.

[0024] In some embodiments, the first conductive trace is disposed on the same layer as the gates of a plurality of first transistors.

[0025] And / or, the control module includes a plurality of second transistors, the gates of which are electrically connected via second conductive traces, which are electrically connected to another of the first clock signal line and the second clock signal line.

[0026] In some embodiments, the second conductive trace is disposed on a different layer from the gate of a plurality of second transistors.

[0027] And / or, the control module includes multiple third transistors, the gates of which are electrically connected via third conductive traces, which are electrically connected to a first power line.

[0028] In some embodiments, the third conductive trace is disposed on the same layer as the gate of a plurality of third transistors.

[0029] In some embodiments, the third conductive trace is electrically connected to the first power line through a third via.

[0030] In some embodiments, the gate of the second transistor in the 2i-1 stage shift register is electrically connected to a second conductive trace, and the gate of the first transistor in the 2i stage shift register is electrically connected to a first conductive trace.

[0031] In some embodiments, the gates of the first transistor in the 2i-1 stage shift register and the gates of the second transistor in the 2i stage shift register are electrically connected to the first clock signal line.

[0032] The gate of the second transistor in the 2i-1 stage shift register and the gate of the first transistor in the 2i stage shift register are electrically connected to the second clock signal line. Here, n / 2 ≥ i ≥ 1, and i is a positive integer, and n is the number of shift registers.

[0033] In some embodiments, the clock signals on the first clock signal line and the second clock signal line have the same frequency but opposite phase.

[0034] In some embodiments, the control module includes a first set of transistors and a second set of transistors.

[0035] The second group of transistors in the control module of the 2j-1 stage shift register is electrically connected to the fourth conductive trace. The first group of transistors in the control module of the 2j-1 stage shift register is electrically connected to the fourth conductive trace. The fourth conductive trace is electrically connected to the second clock signal line through the first via.

[0036] And / or, the second group of transistors in the control module of the 2j-th stage shift register is electrically connected to the fifth conductive trace, and the first group of transistors in the control module of the 2j+1-th stage shift register is electrically connected to the fifth conductive trace. The fifth conductive trace is electrically connected to the first clock signal line through the second via. Where n / 2 ≥ j ≥ 1, and j is a positive integer, and n is the number of shift registers.

[0037] In some embodiments, the orthographic projections of two adjacent shift register stages on the substrate overlap with the orthographic projection of a first via on the substrate. The orthographic projections of two adjacent shift register stages on the substrate overlap with the orthographic projection of a second via on the substrate.

[0038] In some embodiments, the spacing between two adjacent first vias is equal to twice the size of a shift register along the first direction. The spacing between two adjacent second vias is also equal to twice the size of a shift register along the first direction.

[0039] In some embodiments, the array substrate further includes a third power line, and the orthographic projections of the first output transistor and the second output transistor on the substrate are located between the orthographic projection of the control module on the substrate and the orthographic projection of the third power line on the substrate.

[0040] In some embodiments, the array substrate further includes a fourth power line, and the orthographic projections of the first and second output transistors on the substrate overlap with the orthographic projections of the fourth power line on the substrate. The orthographic projections of the third power line on the substrate overlap with the orthographic projections of the fourth power line on the substrate. The third and fourth power lines are electrically connected, with the fourth power line located on the side of the third power line away from the substrate.

[0041] In some embodiments, the first signal line, the second signal line, and the third power line are arranged on the same layer.

[0042] In some embodiments, the array substrate further includes a fourth power line and a fifth power line, the third power line, the fourth power line and the fifth power line are stacked sequentially in a direction away from the substrate, and the third power line, the fourth power line and the fifth power line are electrically connected.

[0043] In some embodiments, the control module includes:

[0044] The fifth transistor, sixth transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, thirteenth transistor, fourteenth transistor, fifteenth transistor, sixteenth transistor, seventeenth transistor, first capacitor, second capacitor, and third capacitor, or all of them, wherein:

[0045] The first terminal of the fifth transistor is used to receive the input signal. The second terminal of the fifth transistor is connected to the gate of the sixth transistor, the first terminal of the tenth transistor, the first terminal of the fifteenth transistor, and the gate of the eleventh transistor. The gate of the fifth transistor is used to receive the first clock signal. The first terminal of the sixth transistor is used to receive the first clock signal. The second terminal of the sixth transistor is connected to the second terminal of the eighth transistor and the first terminal of the seventeenth transistor. The first terminal of the eighth transistor is used to receive the first level signal, and its gate is used to receive the first clock signal. The gate of the seventeenth transistor is used to receive the first level signal. The second terminal of the seventeenth transistor is connected to the first terminal of the first capacitor, the first terminal of the sixteenth transistor, and the gate of the fourteenth transistor. The gate of the sixteenth transistor is used to receive the first level signal. The second terminal of the sixteenth transistor is connected to the gate of the ninth transistor. The second terminal of the ninth transistor is connected to the second terminal of the tenth transistor. The first terminal of the ninth transistor is used to receive the second level signal. The signal is provided in the following configuration: the second terminal of the first capacitor is connected to the second terminal of the fourteenth transistor and the first terminal of the thirteenth transistor, respectively. The first terminal of the fourteenth transistor is used to receive the second clock signal. The gate of the thirteenth transistor is used to receive the second clock signal. The second terminal of the thirteenth transistor is connected to the first terminal of the third capacitor, the gate of the first output transistor, and the second terminal of the eleventh transistor, respectively. The second terminal of the third capacitor is connected to the first terminal of the first output transistor. The first terminal of the first output transistor is electrically connected to the first signal line. The second terminal of the first output transistor serves as the output terminal of the shift register. The first terminal of the eleventh transistor is used to receive the second level signal. The second terminal of the fifteenth transistor is connected to the first terminal of the second capacitor and the gate of the second output transistor, respectively. The gate of the fifteenth transistor is used to receive the first level signal. The second terminal of the second capacitor is used to receive the second clock signal. The first terminal of the second output transistor is electrically connected to the second signal line. The second terminal of the second output transistor serves as the output terminal of the shift register.

[0046] In some embodiments, the first clock signal connected to the transistor in the 2i-1 stage shift register is provided by a first clock signal line, and the second clock signal connected to the transistor in the 2i-1 stage shift register is provided by a second clock signal line.

[0047] The first clock signal connected to the transistors in the 2i-th stage shift register is provided by the second clock signal line, and the second clock signal connected to the transistors in the 2i-th stage shift register is provided by the first clock signal line. n / 2 ≥ i ≥ 1, where i is a positive integer and n is the number of shift registers.

[0048] In some embodiments, the first level signal connected to the transistor in the control module is provided by the first power supply line.

[0049] In some embodiments, the second-level signal connected to the transistor in the control module is provided by the first signal line.

[0050] In some embodiments, the first end of the eighth transistor is electrically connected to the first power line through a fourth via.

[0051] A second aspect of this application provides an array substrate, comprising:

[0052] Substrate;

[0053] A gate driving circuit is located on one side of the substrate. The gate driving circuit includes a multi-stage shift register. The shift register includes a first group of transistors and a second group of transistors. The second group of transistors in the 2j-1 stage shift register is electrically connected to a fourth conductive trace. The first group of transistors in the 2j stage shift register is electrically connected to the fourth conductive trace. The fourth conductive trace is electrically connected to a second clock signal line through a first via.

[0054] And / or, the second group of transistors in the 2j-th stage shift register is electrically connected to the fifth conductive trace, the first group of transistors in the 2j+1-th stage shift register is electrically connected to the fifth conductive trace, and the fifth conductive trace is electrically connected to the first clock signal line through the second via; where n / 2≥j≥1, and j is a positive integer, and n is the number of shift registers.

[0055] A third aspect of this application provides a display panel including a light-emitting device layer and an array substrate as described above. The light-emitting device layer is located on one side of the substrate and includes a first electrode, a light-emitting layer, and a second electrode sequentially stacked in a direction away from the substrate.

[0056] In some embodiments, the array substrate further includes a third power line electrically connected to the second electrode.

[0057] In some embodiments, the array substrate further includes a fourth power line and a fifth power line. The third, fourth, and fifth power lines are stacked sequentially in a direction away from the substrate. The third, fourth, and fifth power lines are electrically connected. The fifth power line is disposed in the same layer as the first electrode.

[0058] In some embodiments, the display panel further includes a touch layer located on the side of the light-emitting device layer away from the substrate, and the overlapping area of ​​the orthographic projections of the fourth power line and the fifth power line on the substrate overlaps with the overlapping area of ​​the orthographic projections of the touch layer on the substrate and the orthographic projections of the gate driving circuit on the substrate.

[0059] The aforementioned array substrate and display panel utilize a gate driving circuit located on one side of the substrate. This gate driving circuit includes a multi-stage shift register, comprising a first output transistor, a second output transistor, and a control module. The first output transistor is connected between a first signal line and the output terminal of the shift register, and the second output transistor is connected between a second signal line and the output terminal of the shift register. The gates of the first and second output transistors are electrically connected to the control module. The orthographic projections of the first and second output transistors onto the substrate are located on the same side as the orthographic projection of the control module onto the substrate. This design facilitates narrow bezel designs for the array substrate. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a schematic cross-sectional view of the array substrate in one embodiment;

[0062] Figure 2 This is a planar schematic diagram of the array substrate in one embodiment;

[0063] Figure 3 This is a circuit diagram of the gate drive circuit in one embodiment;

[0064] Figure 4 This is a second schematic cross-sectional view of the array substrate in one embodiment;

[0065] Figure 5 This is a layout of the second conductive layer of the array substrate in one embodiment;

[0066] Figure 6 This is the third cross-sectional structural schematic diagram of the array substrate in one embodiment;

[0067] Figure 7 This is a layout of the gate layer of an array substrate in one embodiment;

[0068] Figure 8 This is a planar schematic diagram of the layout structure of the array substrate in one embodiment;

[0069] Figure 9 This is a layout of the first conductive layer of the array substrate in one embodiment;

[0070] Figure 10 This is the fourth cross-sectional structural schematic diagram of the array substrate in one embodiment;

[0071] Figure 11 This is a layout of the active layer of the array substrate in one embodiment;

[0072] Figure 12 This is a layout of the capacitor plate layer of an array substrate in one embodiment;

[0073] Figure 13 This is a second planar schematic diagram of the layout structure of the array substrate in one embodiment;

[0074] Figure 14 This is the fifth cross-sectional structural schematic diagram of the array substrate in one embodiment;

[0075] Figure 15 This is a sixth schematic diagram of the cross-sectional structure of the array substrate in one embodiment;

[0076] Figure 16 This is the seventh cross-sectional structural diagram of the array substrate in one embodiment.

[0077] Explanation of reference numerals in the attached figures:

[0078] 10 - Substrate, 20 - Shift Register, 21 - First Output Transistor, 22 - Second Output Transistor, 23 - Control Module, 100 - First Clock Signal Line, 200 - Second Clock Signal Line, 300 - First Power Supply Line, 400 - First Signal Line, 401 - Second Signal Line, 501 - First Conductive Trace, 502 - Second Conductive Trace, 503 - Third Conductive Trace, 504 - Fourth Conductive Trace, 505 - Fifth Conductive Trace, 50 - First Via, 51 - Second Via, 5 2-Third via, 53-Fourth via, 31-Active layer, 32-Gate insulating layer, 33-Gate layer, 34-First conductive layer, 35-Capacitor plate layer, 36-Second conductive layer, 54-Drain, 55-Capacitor, 500-Third power line, 600-Fourth power line, 700-Fifth power line, 800-Signal output line, 60-Light-emitting device layer, 61-First electrode, 62-Light-emitting layer, 63-Second electrode, 70-Encapsulation layer, 80-Touch layer, 90-Pixel circuit. Detailed Implementation

[0079] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0080] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0081] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0082] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0083] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0084] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0085] The array substrate provided in this application embodiment can be used in a display panel, and can provide a layout design structure that makes the gate driving circuits such as the light-emitting control driving circuit and the scanning circuit occupy less space. Since the gate driving circuits such as the light-emitting control driving circuit and the scanning circuit occupy less space, the width can be narrower, which is beneficial to the narrow bezel design of the display panel.

[0086] The display panels in the related technology suffer from a problem of wide bezels. The inventors' research revealed that this problem arises because the bezel area of ​​the display panels in the related technology requires the arrangement of gate driving circuits such as light-emitting control driving circuits and scanning circuits. However, these gate driving circuits contain a large number of transistors and timing signal lines, resulting in a complex circuit structure that occupies a large amount of space and requires significant wiring space, thus making it difficult to narrow the bezel of the display panel.

[0087] Based on the aforementioned technical problems, the inventors discovered that by designing the wiring along the vertical direction of the array substrate, more wiring space can be provided for gate driving circuits such as the light-emitting control driving circuit and the scanning circuit in the thickness direction, thereby saving lateral space. Furthermore, by redesigning the layout structure of the light-emitting control driving circuit through multiplexing traces and sharing vias, the space required for gate driving circuits such as the light-emitting control driving circuit and the scanning circuit is further reduced, thus overcoming the design bottleneck of narrow bezels in display panels.

[0088] In one embodiment, combined Figures 1 to 3 As shown, an array substrate is provided, including: a substrate 10 and a gate driving circuit, wherein:

[0089] The gate driving circuit is located on one side of the substrate 10. The gate driving circuit includes a multi-stage shift register 20, and the shift register 20 includes a first output transistor 21 (which may be...). Figure 3 M9), second output transistor 22 (can be ... Figure 3 The first output transistor 21 is connected to the first signal line 400 (which can be M10) and the control module 23. Figure 3 Between the output terminals of the first output transistor 21 and the shift register 20, the second output transistor 22 is connected between the second signal line 401 and the output terminal of the shift register 20. The gate of the first output transistor 21 and the gate of the second output transistor 22 are electrically connected to the control module 23. The orthographic projections of the first output transistor 21 and the second output transistor 22 on the substrate 10 are located on the same side of the orthographic projection of the control module 23 on the substrate 10.

[0090] In this embodiment, the gate driving circuit is located on one side of the substrate. The gate driving circuit includes a multi-stage shift register, which includes a first output transistor, a second output transistor, and a control module. The first output transistor is connected between a first signal line and the output terminal of the shift register, and the second output transistor is connected between a second signal line and the output terminal of the shift register. The gates of the first and second output transistors are electrically connected to the control module. The orthographic projections of the first and second output transistors on the substrate are located on the same side as the orthographic projection of the control module on the substrate. This design is more advantageous for narrow bezel designs of the array substrate.

[0091] The gate drive circuit may include multiple cascaded shift registers. In two adjacent shift register stages, the output of the previous stage shift register is connected to the input of the next stage shift register.

[0092] In one embodiment, please see [link to embodiment]. Figure 1 The orthographic projections of the first output transistor 21 and the second output transistor 22 on the substrate 10 are located between the orthographic projection of the control module 23 on the substrate 10 and the edge of the array substrate.

[0093] like Figure 2 As shown, the multi-stage shift register 20 is arranged along a first direction. The orthographic projections of the first output transistor 21 and the second output transistor 22 onto the substrate 10 are located on one side of the opposite sides of the orthographic projection of the control module 23 onto the substrate 10 along a second direction. The first direction intersects the second direction, for example, they can be perpendicular. That is, the first output transistor 21 and the second output transistor 22 can be disposed on either side of the control module 23.

[0094] In this embodiment, by placing the first output transistor 21 and the second output transistor 22 close to the edge of the array substrate, and since the negative power line ELVSS is disposed at the edge of the array substrate, the first output transistor 21 and the second output transistor 22 are placed close to the negative power line ELVSS. The empty space above the first output transistor 21 and the second output transistor 22 (e.g., the second conductive layer, the conductive film layer containing the anode layer, etc.) can be used to route the negative power line ELVSS, thereby widening the width of the negative power line ELVSS, reducing the line resistance of the negative power line ELVSS, reducing the voltage drop when the power signal is transmitted on the negative power line ELVSS, and improving the light-emitting effect of the light-emitting element.

[0095] In one embodiment, such as Figure 3 As shown, the control module 23 includes: a fifth transistor M1, a sixth transistor (which may be a dual-gate transistor, for example, it may include transistors M2a and M2b connected in series), an eighth transistor M3, a ninth transistor M4, a tenth transistor M5, an eleventh transistor (which may be a dual-gate transistor, for example, it may include transistors M6a and M6b connected in series), a thirteenth transistor M7, a fourteenth transistor M8, a fifteenth transistor M11, a sixteenth transistor M12, a seventeenth transistor M13, a first capacitor C1, a second capacitor C2, and a third capacitor C3, some or all of which:

[0096] The first terminal of the fifth transistor M1 is used to receive the input signal EIN. The second terminal of the fifth transistor M1 is connected to the gate of the second output transistor M10 via the fifteenth transistor M11, or the second terminal of the fifth transistor M1 is directly connected to the gate of the second output transistor M10. The gate of the fifth transistor M1 is used to receive the first clock signal ECK1.

[0097] The gate of the sixth transistor is connected to the second terminal of the fifth transistor M1, the first terminal of the sixth transistor is used to receive the first clock signal ECK1, and the second terminal of the sixth transistor is connected to the second terminal of the eighth transistor M3.

[0098] The first terminal of the eighth transistor M3 is used to receive the first level signal PVGL, the gate of the eighth transistor M3 is used to receive the first clock signal ECK1, and the second terminal of the eighth transistor M3 is connected to the gate of the fourteenth transistor M8 via the seventeenth transistor M13, or the second terminal of the eighth transistor M3 is directly connected to the gate of the fourteenth transistor M8.

[0099] The gate of the seventeenth transistor M13 is used to receive the first level signal PVGL.

[0100] The first terminal of the tenth transistor M5 is connected to the second terminal of the fifth transistor M1. The gate of the tenth transistor M5 is used to receive the second clock signal ECK2. The second terminal of the tenth transistor M5 is connected to the second terminal of the ninth transistor M4.

[0101] The first terminal of the ninth transistor M4 is used to receive the second level signal PVGH. The gate of the ninth transistor M4 is connected to the gate of the fourteenth transistor M8 via the sixteenth transistor M12, or the gate of the ninth transistor M4 is directly connected to the gate of the fourteenth transistor M8.

[0102] The gate of the sixteenth transistor M12 is used to receive the first level signal PVGL.

[0103] The first terminal of the fourteenth transistor M8 is used to receive the second clock signal ECK2. The second terminal of the fourteenth transistor M8 is connected to the first terminal of the thirteenth transistor M7. The gate of the thirteenth transistor M7 is used to receive the second clock signal ECK2.

[0104] The first terminal of the first capacitor C1 is connected to the gate of the fourteenth transistor M8. The second terminal of the first capacitor C1 is connected to the second terminal of the fourteenth transistor M8.

[0105] The first terminal of the second capacitor C2 is connected to the gate of the second output transistor M10, and the second terminal of the second capacitor C2 is used to receive the second clock signal ECK2.

[0106] The second terminal of the third capacitor C3 is connected to the first terminal of the first output transistor M9, and the first terminal of the third capacitor C3 is connected to the gate of the first output transistor M9.

[0107] The first terminal of the first output transistor M9 is electrically connected to the first signal line 400, and the second terminal of the first output transistor M9 serves as the output terminal of the shift register.

[0108] The first terminal of the second output transistor M10 is electrically connected to the second signal line 401, and the second terminal of the second output transistor M10 serves as the output terminal of the shift register.

[0109] The first terminal of the fifth transistor is used to receive the input signal. The second terminal of the fifth transistor is connected to the gate of the sixth transistor, the first terminal of the tenth transistor, the first terminal of the fifteenth transistor, and the gate of the eleventh transistor. The gate of the fifth transistor is used to receive the first clock signal. The first terminal of the sixth transistor is used to receive the first clock signal. The second terminal of the sixth transistor is connected to the second terminal of the eighth transistor and the first terminal of the seventeenth transistor. The first terminal of the eighth transistor is used to receive the first level signal, and its gate is used to receive the first clock signal. The gate of the seventeenth transistor is used to receive the first level signal. The second terminal of the seventeenth transistor is connected to the first terminal of the first capacitor, the first terminal of the sixteenth transistor, and the gate of the fourteenth transistor. The gate of the sixteenth transistor is used to receive the first level signal. The second terminal of the sixteenth transistor is connected to the gate of the ninth transistor. The second terminal of the ninth transistor is connected to the second terminal of the tenth transistor. The first terminal of the ninth transistor is used to receive the second level signal. The signal is provided in the following configuration: the second terminal of the first capacitor is connected to the second terminal of the fourteenth transistor and the first terminal of the thirteenth transistor, respectively. The first terminal of the fourteenth transistor is used to receive the second clock signal. The gate of the thirteenth transistor is used to receive the second clock signal. The second terminal of the thirteenth transistor is connected to the first terminal of the third capacitor, the gate of the first output transistor, and the second terminal of the eleventh transistor, respectively. The second terminal of the third capacitor is connected to the first terminal of the first output transistor. The first terminal of the first output transistor is electrically connected to the first signal line. The second terminal of the first output transistor serves as the output terminal of the shift register. The first terminal of the eleventh transistor is used to receive the second level signal. The second terminal of the fifteenth transistor is connected to the first terminal of the second capacitor and the gate of the second output transistor, respectively. The gate of the fifteenth transistor is used to receive the first level signal. The second terminal of the second capacitor is used to receive the second clock signal. The first terminal of the second output transistor is electrically connected to the second signal line. The second terminal of the second output transistor serves as the output terminal of the shift register.

[0110] The first terminal of transistor M1 is used to receive the input signal EIN. The second terminal of transistor M1 is connected to the gate of transistor M2a, the gate of transistor M2b, the first terminal of transistor M5, the first terminal of transistor M11, the gate of transistor M6a, and the gate of transistor M6b, respectively. The gate of transistor M1 is used to receive the first clock signal ECK1. The first terminal of transistor M2a is also used to receive the first clock signal ECK1. The second terminal of transistor M2b is connected to the first terminal of transistor M2b. The second terminal of transistor M2a is connected to the second terminal of transistor M3 and the first terminal of transistor M13, respectively. The first terminal of transistor M3 is used to connect to the first level signal PVGL. The gate of transistor M3 is used to connect to the first clock signal ECK1. The gate of transistor M13 is used to connect to the first level signal PVGL. The second terminal of transistor M13 is connected to the first terminal of the first capacitor C1, the first terminal of transistor M12, and the gate of transistor M8. The gate of transistor M12 is used to connect to the first level signal PVGL. The second terminal of transistor M12 is connected to the gate of transistor M4. The second terminal of transistor M4 is connected to the second terminal of transistor M5. The first terminal of transistor M4 is used to connect to the second level signal PVGH. The second terminal of the first capacitor C1 is connected to the second terminal of transistor M8 and the first terminal of transistor M7, respectively. The first terminal of M8 is used to receive the second clock signal ECK2. The gate of transistor M7 is also used to receive the second clock signal ECK2. The second terminal of transistor M7 is connected to the first terminal of the third capacitor C3, the gate of transistor M9, and the second terminal of transistor M6a, respectively. The second terminal of the third capacitor C3 is connected to the first terminal of transistor M9. The first terminal of transistor M9 is used to receive the second level signal PVGH. The second terminal of transistor M9 serves as the output terminal of shift register 20, outputting the gate signal, for example, for light control. The shift register 20 outputs a gate signal, such as the light emission control signal EM, through a combination of input signals EIN, ECK1, ECK2, PVGL, and PVGH. The first terminal of transistor M6a is connected to the second terminal of transistor M6b, and the first terminal of transistor M11 is connected to the first terminal of the second capacitor C2 and the gate of transistor M10. The gate of transistor M11 is connected to the first clock signal PVGL, the second terminal of the second capacitor C2 is connected to the second clock signal ECK2, and the first terminal of transistor M10 is connected to the first clock signal PVGL. The second terminal of transistor M10 serves as the output terminal of the shift register 20, outputting a gate signal, such as the light emission control signal EM. This shift register 20 outputs a gate signal, such as the light emission control signal EM, to the pixel circuit under the coordinated control of the input signals EIN, ECK1, ECK2, PVGL, and PVGH. Its working principle is well known to those skilled in the art and will not be elaborated further here.

[0111] In some embodiments, the first clock signal ECK1 connected to the transistor in the 2i-1 stage shift register (e.g., an odd-stage shift register) is provided by the first clock signal line 100, and the second clock signal ECK2 connected to the transistor in the 2i-1 stage shift register is provided by the second clock signal line 200.

[0112] The first clock signal ECK1 connected to the transistors in the 2i-th stage shift register (e.g., an even-stage shift register) is provided by the second clock signal line 200, and the second clock signal ECK2 connected to the transistors in the 2i-th stage shift register is provided by the first clock signal line 100. n / 2 ≥ i ≥ 1, where i is a positive integer and n is the number of shift registers.

[0113] In some embodiments, the first level signal PVGL connected to the transistor in the control module is provided by the first power line 300.

[0114] In some embodiments, the second-level signal PVGH connected to the transistor in the control module is provided by the first signal line 400.

[0115] In some embodiments, the first end of the eighth transistor M3 is electrically connected to the first power line 300 through a fourth via 53.

[0116] In some embodiments, each shift register is connected to the first power line 300 via two vias (e.g., a fourth via 53 and a third via 52, which may be two organic vias that penetrate the organic planarization layer).

[0117] In the same shift register, the fifth transistor M1, the sixth transistor (which can be a dual-gate transistor, for example, it can include transistors M2a and M2b connected in series), and the eighth transistor M3 are located in the first sub-region; the ninth transistor M4, the tenth transistor M5, the eleventh transistor (which can be a dual-gate transistor, for example, it can include transistors M6a and M6b connected in series), the thirteenth transistor M7, and the fourteenth transistor M8 are located in the second sub-region; and the fifteenth transistor M11, the sixteenth transistor M12, and the seventeenth transistor M13 are located in the third sub-region. The first and third sub-regions can be arranged along a first direction. The second sub-region can be located between the first sub-region and the first output transistor M9. The first sub-region and the first output transistor M9 are located on opposite sides of the second sub-region along a second direction. The second sub-region can be located between the third sub-region and the second output transistor M10. The third sub-region and the second output transistor M10 are located on opposite sides of the second sub-region along a second direction. The orthogonal projections of the first output transistor M9 and the second output transistor M10 onto the substrate can be arranged along the first direction.

[0118] In two adjacent shift registers, the first and third sub-regions can be arranged alternately along the first direction.

[0119] In one embodiment, such as Figure 4 As shown, the array substrate also includes a first clock signal line 100, a second clock signal line 200, and a first power supply line 300, which are electrically connected to the control module 23.

[0120] The first clock signal line 100 can be used to transmit clock signals, for example, as the first clock signal ECK1 of the 2i-1 stage shift register, and as the second clock signal ECK2 of the 2i stage shift register. The second clock signal line 200 can be used to transmit clock signals, for example, as the second clock signal ECK2 of the 2i-1 stage shift register, and as the first clock signal ECK1 of the 2i stage shift register. The first power supply line 300 can be used to transmit the first level signal PVGL. The first signal line 400 can be used to transmit the second level signal PVGH. The second signal line can be used to transmit the first level signal PVGL.

[0121] Optionally, the first clock signal line 100, the second clock signal line 200, and the first power supply line 300 are disposed on the same layer, for example, in the second conductive layer. The second clock signal line 200 may be located between the first clock signal line 100 and the first power supply line 300.

[0122] In one embodiment, please see [link to embodiment]. Figure 4 The orthographic projection of the first clock signal line 100 on the substrate 10 overlaps with the orthographic projection of the control module 23 on the substrate 10.

[0123] In this embodiment, by designing the space occupied by the first clock signal line 100 and the control module 23 to overlap in the thickness direction, the lateral space is saved, which is more conducive to the narrow bezel design of the array substrate.

[0124] In one embodiment, please see [link to embodiment]. Figure 4 The orthographic projection of the second clock signal line 200 on the substrate 10 overlaps with the orthographic projection of the control module 23 on the substrate 10.

[0125] In this embodiment, by designing the space occupied by the second clock signal line 200 and the control module 23 to overlap in the thickness direction, the horizontal space is saved, which is more conducive to the narrow bezel design of the array substrate.

[0126] In one embodiment, please see [link to embodiment]. Figure 4 The orthographic projection of the first power line 300 on the substrate 10 overlaps with the orthographic projection of the control module 23 on the substrate 10.

[0127] In this embodiment, by designing the space occupied by the first power line 300 and the control module 23 to overlap in the thickness direction, lateral space is saved, which is more conducive to the narrow bezel design of the array substrate.

[0128] The first clock signal line 100 may extend along the first direction. The second clock signal line 200 may extend along the first direction. The first power supply line 300 may extend along the first direction.

[0129] In one embodiment, such as Figure 5 As shown, the first clock signal line 100, the second clock signal line 200, and the first power supply line 300 extend along the first direction and are arranged along the second direction. This arrangement saves lateral space and is more conducive to the narrow bezel design of the array substrate.

[0130] Optionally, the first signal line 400 and the second signal line 401 are disposed on the same layer, for example, they may be located in the first conductive layer.

[0131] Optionally, such as Figure 6 As shown, the orthographic projection of the first signal line 400 on the substrate 10 overlaps with the orthographic projections of the first output transistor 21 and the second output transistor 22 on the substrate 10. This arrangement saves lateral space and is more conducive to the narrow bezel design of the array substrate.

[0132] Optionally, such as Figure 6 As shown, the first clock signal line 100, the second clock signal line 200, the first power supply line 300 and the first signal line 400 are disposed on the same layer, for example, in the second conductive layer (which may be called the second source-drain layer).

[0133] Optionally, the first signal line 400 and the second signal line 401 are arranged on different layers. This arrangement saves lateral space and is more conducive to the narrow bezel design of the array substrate. The second signal line 401 can be located in the first conductive layer.

[0134] Optionally, the first power line 300 and the first signal line 400 may have different potentials.

[0135] Optionally, the first power line 300 and the second signal line 401 have the same potential.

[0136] In one embodiment, such as Figure 7-9 As shown, the control module includes multiple first transistors, the gates of which are electrically connected through a first conductive trace 501. The first conductive trace 501 is electrically connected to one of a first clock signal line 100 and a second clock signal line 200. Figure 7 This is a schematic diagram of the gate layer layout.

[0137] For example, with Figure 3The circuit shown is used as an example for illustration. Multiple first transistors include transistors M1 and M3 connected to the first clock signal ECK1. This is equivalent to multiple first transistors in the (2i-1)th stage shift register being connected to the first clock signal line 100. Similarly, multiple first transistors in the 2i-th stage shift register are connected to the second clock signal line 200.

[0138] Optionally, the first conductive trace 501 is disposed on the same layer as the gates of the plurality of first transistors, which helps to reduce the number of vias. A portion of the first conductive trace 501 can serve as the gate of the first transistor.

[0139] And / or, the control module includes a plurality of second transistors, the gates of which are electrically connected via a second conductive trace 502, which is electrically connected to another of the first clock signal line 100 and the second clock signal line 200.

[0140] For example, with Figure 3 The circuit shown is used as an example for illustration. Multiple second transistors include transistors M5 and M7 connected to the second clock signal ECK2. This is equivalent to multiple second transistors in the (2i-1)th stage shift register being connected to the second clock signal line 200. It is also equivalent to multiple second transistors in the 2i-th stage shift register being connected to the first clock signal line 100.

[0141] Optionally, the second conductive trace 502 is disposed on a different layer from the gates of a plurality of second transistors. For example, the second conductive trace 502 is located in, for example, Figure 9 The first conductive layer shown (which may be a first source-drain layer) may have multiple source-drain electrodes of the second transistors disposed on the first conductive layer.

[0142] And / or, please continue to see Figure 7 The control module includes multiple third transistors, the gates of which are electrically connected through a third conductive trace 503, which is electrically connected to a first power line 300.

[0143] In this configuration, the gates of multiple third transistors are connected via third conductive traces 503, and the third conductive traces 503 are connected to the first power line 300 via a third via 52. Since the gates of each transistor are disposed on the gate layer, the gates of at least two third transistors on the same film layer can be directly connected together via the third conductive traces 503 without the need for vias, making the connection convenient. Then, they are connected to the first power line 300 via a third via 52. Only one third via 52 is needed to connect the gates of multiple third transistors to the first power line 300, reducing the number of vias required. Multiple third transistors share one third via 52, thereby minimizing the number of vias and saving space that would otherwise be required for vias.

[0144] For example, please continue to see Figure 3 The third transistor may include at least two of M13, M12, and M11, all of which are used to receive the first level signal PVGL through their gates.

[0145] Optionally, the third via 52 is located in the area between two adjacent shift registers, so that the setting position of the third via 52 is designed on the outside of the shift register. The third via 52 is set on one side of the shift register along the first direction, so that the space occupied by the third via 52 is the space in the first direction and does not occupy the space in the second direction. Therefore, the space in the second direction can be saved. Saving the space in the second direction narrows the width of the array substrate's bezel, which is beneficial for the narrow bezel design of the array substrate.

[0146] Optionally, the third conductive trace 503 is disposed on the same layer as the gates of multiple third transistors, which helps to reduce the number of vias. A portion of the third conductive trace 503 can serve as the gate of the third transistor.

[0147] Optionally, the second conductive trace 502, which is electrically connected to the gate of the second transistor in the 2i-1 stage shift register, and the first conductive trace 501, which is electrically connected to the gate of the first transistor in the 2i stage shift register, are electrically connected, which helps to reduce the number of vias.

[0148] Optionally, the gate of the first transistor in the 2i-1 stage shift register and the gate of the second transistor in the 2i stage shift register are electrically connected to the first clock signal line 100.

[0149] The gates of the second transistor in the 2i-1 stage shift register and the first transistor in the 2i stage shift register are electrically connected to the second clock signal line 200. Here, n / 2 ≥ i ≥ 1, and i is a positive integer, while n is the number of shift registers.

[0150] Optionally, the clock signals on the first clock signal line 100 and the second clock signal line 200 have the same frequency but opposite phase.

[0151] Specifically, for the 2i-th stage shift register and the (2i-1)-th stage shift register, the first clock signal ECK1 and the second clock signal ECK2 are opposite. That is, the first clock signal ECK1 and the second clock signal ECK2 of adjacent shift register stages are opposite. This can also be understood as the first clock signal ECK1 and the second clock signal ECK2 being the same for odd-numbered stage shift registers, and the first clock signal ECK1 and the second clock signal ECK2 being the same for even-numbered stage shift registers. This wiring design allows for maintaining the characteristics of the shift register while reducing the number of vias, enabling line-by-line output of the light control signal or scan signal. The first clock signal of the 2i-1 stage shift register (equivalent to an odd-level shift register) can come from the first clock signal line, the second clock signal of the 2i-1 stage shift register can come from the second clock signal line, the first clock signal of the 2i stage shift register (equivalent to an even-level shift register) can come from the second clock signal line, and the second clock signal of the 2i stage shift register can come from the first clock signal line.

[0152] For example, such as Figure 8 As shown, Figure 8 This is a planar schematic diagram of the layout structure of the array substrate. Figure 3 The various components of the gate drive circuit and the traces for transmitting the first clock signal ECK1, the second clock signal ECK2, the first level signal PVGL, and the second level signal PVGH are all located in... Figure 8 As shown in the image.

[0153] in, Figure 8 The schematic planar view of the array substrate layout shown includes all the film layers in the array substrate, namely, active layer 31, gate layer 33, capacitor plate layer 35, first conductive layer 34, and second conductive layer 36. These film layers are stacked in the order of active layer 31, gate layer 33, capacitor plate layer 35, first conductive layer 34, and second conductive layer 36, from the direction furthest from the substrate, to obtain the structure shown. Figure 8 The diagram shows a schematic layout of the array substrate. Figure 8 The positions of the first via 50 and the second via 51 are schematically marked in the diagram.

[0154] For example, since capacitor C2 is also connected to the second clock signal ECK2, that is, capacitor C2 of the (2i-1)th stage shift register is connected to the second clock signal ECK2, and capacitor C2 of the 2i-th stage shift register is connected to the first clock signal ECK1, the position of the first via 50 is designed directly above capacitor C2 of the 2i-1th stage shift register (the position of the first via 50 in the orthographic projection of the substrate 10 is within the orthographic projection of capacitor C2 of the 2i-1th stage shift register in the substrate 10), and the second via 51... The position is designed directly above the capacitor C2 of the 2i-th stage shift register (the position of the second via 51 is located within the orthogonal projection of the capacitor C2 of the 2i-th stage shift register on the substrate 10). This design allows the capacitor C2 of the 2i-1-th stage shift register to be connected to the second clock signal line 200 through the first via 50, and the capacitor C2 of the 2i-th stage shift register to be connected to the first clock signal line 100 through the second via 51. The distance of the wire can be kept as short as possible, saving space.

[0155] On the one hand, by using only two clock signal lines, the transistors in adjacent shift registers that need to receive the same clock signal are connected via traces and then via a via, minimizing the number of vias and saving space that would otherwise be required for drilling. This is beneficial for the narrow bezel design of the array substrate. Adjacent shift registers can reuse the same clock signal line, further reducing the number of clock signal lines and saving space. On the other hand, the two clock signal lines are located on a separate second conductive layer, thus utilizing space in the thickness direction. The space occupied by the clock signal lines and the gate drive circuit can overlap in the thickness direction, saving lateral space and further facilitating the narrow bezel design of the array substrate.

[0156] Optionally, the control module includes a first set of transistors and a second set of transistors. The first set of transistors may include one or more transistors. The second set of transistors may include one or more transistors.

[0157] In one embodiment, such as Figure 9 As shown, Figure 9 This is a schematic diagram of the first metal layer. The second group of transistors in the control module of the 2j-1 level shift register is electrically connected to the fourth conductive trace 504. The first group of transistors in the control module of the 2j level shift register is electrically connected to the fourth conductive trace 504. The fourth conductive trace 504 is electrically connected to the second clock signal line 200 through the first via 50.

[0158] The orthographic projection of the fourth conductive trace 504 on the substrate overlaps with the orthographic projection of the 2j-1 stage shift register on the substrate.

[0159] For example, the first group of transistors in the control module of the second-j stage shift register is electrically connected to the fourth conductive line 504 via the first conductive line 501.

[0160] Among them, with Figure 3 Taking the control module circuit shown as an example, the second group of transistors in the control module of the 2j-1 stage shift register may include M5, M7, and M8, and the first group of transistors in the control module of the 2j stage shift register may include M1, M3, M2a, and M2b.

[0161] And / or, the second group of transistors in the control module of the 2j-th stage shift register is electrically connected to the fifth conductive trace 505, and the first group of transistors in the control module of the 2j+1-th stage shift register is electrically connected to the fifth conductive trace 505. The fifth conductive trace 505 is electrically connected to the first clock signal line 100 through the second via 51. Wherein, n / 2 ≥ j ≥ 1, and j is a positive integer, and n is the number of shift registers.

[0162] The orthographic projection of the fifth conductive trace 505 on the substrate overlaps with the orthographic projection of the 2j-stage shift register on the substrate. The orthographic projection of the fifth conductive trace 505 on the substrate overlaps with the orthographic projection of the 2j+1-stage shift register on the substrate.

[0163] Among them, with Figure 3 Taking the control module circuit shown as an example, the second group of transistors in the control module of the 2j-th stage shift register may include M5, M7, and M8, and the first group of transistors in the control module of the 2j+1-th stage shift register may include M1, M3, M2a, and M2b.

[0164] Among them, the first transistors in the 2i-stage shift register (refer to) Figure 3 The circuits shown, such as M1 and M3, are connected via the first conductive trace 501. The second transistors in the (2i-1)th stage shift register (refer to...) Figure 3The circuit shown (e.g., M5, M7) is connected via a second conductive trace 502, and the first conductive trace 501 and the second conductive trace 502 are connected. The second conductive trace 502 can be connected to the second clock signal line 200 through a first via 50. Similarly, each second transistor (e.g., M5, M7) in the 2i-th stage shift register is connected via the second conductive trace 502, and each first transistor (e.g., M1, M3) in the 2i+1-th stage shift register is connected via the first conductive trace 501, and the first conductive trace 501 and the second conductive trace 502 are connected. Then, the second conductive trace 502 can be connected to the first clock signal line 100 through a second via 51. Only one first via 50 is needed to connect the first transistors in the 2i-th stage shift register and the second transistors in the (2i-1)-th stage shift register to the second clock signal line 200. This reduces the number of vias required, as the first transistors in the 2i-th stage shift register and the second transistors in the (2i-1)-th stage shift register share a single first via 50, thus minimizing the number of vias and saving space that would otherwise be required for drilling. Similarly, only one second via 51 is needed to connect the second transistors in the 2i-th stage shift register and the first transistors in the (2i+1)-th stage shift register to the first clock signal line 100. This also reduces the number of vias required, as the second transistors in the 2i-th stage shift register and the first transistors in the (2i+1)-th stage shift register share a single second via 51, further minimizing the number of vias and saving space that would otherwise be required for drilling. For example, i can be equal to j.

[0165] At least a portion of the second conductive trace 502 may serve as the fourth conductive trace 504. At least a portion of the second conductive trace 502 may serve as the fifth conductive trace 505. For example, a portion of the second conductive trace 502 may serve as the fourth conductive trace 504, and a portion of the second conductive trace 502 may serve as the fifth conductive trace 505.

[0166] Optionally, the orthographic projections of two adjacent shift registers on the substrate 10 overlap with the orthographic projection of a first via 50 on the substrate 10. The orthographic projections of two adjacent shift registers on the substrate 10 overlap with the orthographic projection of a second via 51 on the substrate 10.

[0167] Optionally, the spacing between two adjacent first vias 50 is equal to twice the size of a shift register along the first direction. The spacing between two adjacent second vias 51 is equal to twice the size of a shift register along the first direction.

[0168] In this embodiment, transistors in two adjacent shift registers that need to receive the same clock signal are connected by traces and then by a via to the corresponding clock signal line. This minimizes the number of vias, saving space that would otherwise be required for drilling, which is beneficial for the narrow bezel design of the array substrate. Adjacent shift registers can reuse the same clock signal line, further reducing the number of clock signal lines and saving space. Furthermore, since the two clock signal lines are located on a separate second conductive layer, space in the thickness direction is utilized. The space occupied by the clock signal lines and shift registers can overlap in the thickness direction, saving lateral space and further facilitating the narrow bezel design of the array substrate.

[0169] In one embodiment, such as Figure 10 As shown, the array substrate includes, in sequence away from the substrate 10, an active layer 31, a gate insulating layer 32, a gate layer 33, a capacitor dielectric layer, a capacitor electrode layer 35, an interlayer insulating layer, a first conductive layer 34, an organic planarization layer, and a second conductive layer 36. The first via can be an organic via penetrating the organic planarization layer. The second via can be an organic via penetrating the organic planarization layer. The third via can be an organic via penetrating the organic planarization layer. The fourth via can be an organic via penetrating the organic planarization layer.

[0170] The gate layer 33 may include the gates of each transistor in the light-emitting control driving circuit.

[0171] The first conductive layer 34 may include the source and drain 54 of at least some of the transistors in the light-emitting control driving circuit.

[0172] In this configuration, the source and drain of each transistor 54 are connected to the corresponding source and drain regions of the active layer 31 via corresponding vias. For example, Figure 10 Only one transistor is shown in the diagram, and the traces are not shown. The traces should be connected according to the circuit connection method. Figure 10 Not all vias are shown in the image, which is understandable. Figure 10 This is merely a schematic diagram of the membrane structure, used to illustrate the relationships between the various membrane layers.

[0173] For example, Figure 11 For the layout of active layer 31, such as Figure 3 The active regions of each transistor in the circuit shown are as follows on the active layer 31: Figure 11 As shown. Figure 7 The layout of gate layer 33 is as follows: Figure 3 The positions of the gates of each transistor in the circuit shown are as follows on the gate layer 33: Figure 7 As shown. Figure 9 The layout of the first conductive layer 34 is as follows: Figure 3The positions of the source and drain of each transistor in the circuit shown are on the first conductive layer 34 as follows: Figure 9 As shown.

[0174] The capacitor plate layer 35 is disposed between the gate layer 33 and the second conductive layer 36, and the capacitor plate layer 35 includes a plurality of capacitors 55 in the gate drive circuit.

[0175] Among them, multiple capacitors 55 are respectively connected to corresponding transistors and signal lines through corresponding vias, for example, by directly drilling holes in the thickness direction of the array substrate to connect to the first conductive layer 34 and the gate layer 33.

[0176] For example, such as Figure 12 As shown, Figure 12 The layout of capacitor plate layer 35 is shown below. Each shift register includes some or all of capacitors C1, C2, and C3. (See reference below.) Figure 3 The circuit diagram shown.

[0177] In this embodiment, the light-emitting control driving layer includes an active layer 31, a gate insulating layer 32, a gate layer 33, a capacitor plate layer 35, a first conductive layer 34, and a second conductive layer 36 disposed sequentially away from the substrate 10. Thus, each device of the gate driving circuit can be disposed on the corresponding film layer to realize the wiring of the gate driving circuit.

[0178] In one embodiment, please see [link to embodiment]. Figure 9 One of the first signal line 400 and the second signal line is a high-voltage power supply line used to transmit the second level signal PVGH, and the other is a low-voltage power supply line used to transmit the first level signal PVGL.

[0179] And / or, the first signal line 400 and the second signal line extend along the first direction and are arranged along the second direction.

[0180] Optionally, the gate driving circuit includes a light-emitting control driving circuit and / or a scanning circuit. Optionally, the gate driving circuit is a light-emitting control driving circuit.

[0181] And / or, such as Figure 7-8 As shown, the array substrate also includes a signal output line 800, which is electrically connected to the output terminal of the shift register. The signal output line 800 extends along a second direction, and the signal output line 800 and the orthographic projection of the control module 23 on the substrate 10 are arranged along a first direction. The signal output line 800 may be located in the gate layer.

[0182] In this embodiment, the signal output line and the orthographic projection of the control module on the substrate 10 are arranged along the first direction, so that the position of the signal output line is designed on one side of the control module along the first direction. Therefore, the signal output line will not occupy the space in the second direction, thus saving the space in the second direction. Saving the space in the second direction narrows the width of the array substrate's border, which is beneficial for the narrow border design of the array substrate.

[0183] Among them, such as Figure 13 As shown, the signal line PVGH is routed using the empty space above the first output transistor M9 and the second output transistor M10. By utilizing the space in the thickness direction, the signal line PVGH, which was originally routed using the horizontal space, can be routed using the vertical space, thus saving the horizontal space of the array substrate.

[0184] In one embodiment, such as Figure 14 As shown, the array substrate also includes a third power line 500, a first output transistor 21, and a second output transistor (…). Figure 14 (Not shown in the diagram, but the second output transistor is obscured by the first output transistor 21 in the cross-sectional view) The orthogonal projection of the second output transistor on the substrate 10 is located between the orthogonal projection of the control module 23 on the substrate 10 and the orthogonal projection of the third power line 500 on the substrate 10.

[0185] The third power line 500 may be located in the first conductive layer.

[0186] Optionally, please continue to see Figure 14 The array substrate also includes a fourth power line 600, and the orthographic projections of the first output transistor 21 and the second output transistor on the substrate 10 overlap with the orthographic projections of the fourth power line 600 on the substrate 10.

[0187] Optionally, the orthographic projection of the third power line 500 on the substrate 10 overlaps with the orthographic projection of the fourth power line 600 on the substrate 10. The third power line 500 and the fourth power line 600 are electrically connected, with the fourth power line 600 located on the side of the third power line 500 away from the substrate 10.

[0188] The fourth power line 600 may be located in the second conductive layer.

[0189] Optionally, the first signal line 400, the second signal line, and the third power line 500 are disposed on the same layer, for example, they may be located on the first conductive layer.

[0190] Optionally, please see Figure 15The array substrate also includes a fourth power line 600 and a fifth power line 700. The third power line 500, fourth power line 600, and fifth power line 700 are sequentially stacked along a direction away from the substrate 10, and are electrically connected. The fourth power line 600 and fifth power line 700 are power lines on other film layers of the array substrate, such as other metal layers or anode layers disposed on the same layer. The fifth power line 700 can be disposed on the same layer as the first electrode 61.

[0191] Specifically, the third power line 500 and / or the fourth power line 600 and / or the fifth power line 700 are the negative power lines ELVSS of the display panel, which can provide negative power signals to the cathodes of the light-emitting elements. As the bezel width becomes narrower, the wiring space for the negative power signal lines ELVSS is also compressed. However, it is necessary to ensure that the negative power signal lines ELVSS have a certain width to avoid excessive line resistance and burnout during power signal transmission. The fourth power line 600 and / or the fifth power line 700 are located in the empty space above the first and second output transistors, which is equivalent to widening the space occupied by the third power line 500 and reducing line resistance.

[0192] In this embodiment, by designing the fourth power line 600 and / or the fifth power line 700 on the second conductive layer, and utilizing the empty space above the first output transistor and the second output transistor to route the fourth power line 600 and / or the fifth power line 700, the line resistance of the line transmitting voltage to the cathode is reduced, thereby reducing the voltage drop of the voltage transmitted to the cathode and making the voltage transmitted to the cathode consistent.

[0193] This invention provides yet another array substrate. The array substrate includes:

[0194] Substrate;

[0195] A gate driving circuit is located on one side of the substrate. The gate driving circuit includes a multi-stage shift register. The shift register includes a first group of transistors and a second group of transistors. The second group of transistors in the 2j-1 stage shift register is electrically connected to a fourth conductive trace. The first group of transistors in the 2j stage shift register is electrically connected to the fourth conductive trace. The fourth conductive trace is electrically connected to a second clock signal line through a first via.

[0196] And / or, the second group of transistors in the 2j-th stage shift register is electrically connected to the fifth conductive trace, the first group of transistors in the 2j+1-th stage shift register is electrically connected to the fifth conductive trace, and the fifth conductive trace is electrically connected to the first clock signal line through the second via; where n / 2≥j≥1, and j is a positive integer, and n is the number of shift registers.

[0197] In this embodiment, transistors in two adjacent shift registers that need to receive the same clock signal are connected by traces and then connected to the corresponding clock signal line through a via. This can minimize the number of vias, thereby saving the space that would otherwise be required to drill holes. This is beneficial for the narrow bezel design of the array substrate. Two adjacent shift registers can reuse the same clock signal line, thereby saving the number of clock signal lines and saving space.

[0198] The array substrate in this embodiment has the same or similar structure as the array substrate in the above embodiments, and its functions and effects are the same or similar, so it will not be described again here.

[0199] Optionally, the shift register includes one or more first-group transistors. The shift register also includes one or more second-group transistors.

[0200] In one embodiment, such as Figure 16 As shown, a display panel is provided, including a light-emitting device layer 60 and an array substrate as described above; the light-emitting device layer 60 is located on one side of the substrate 10, and the light-emitting device layer 60 includes a first electrode 61, a light-emitting layer 62 and a second electrode 63 sequentially stacked in a direction away from the substrate 10.

[0201] The first electrode 61 can be the anode. The second electrode 63 can be the cathode.

[0202] In one embodiment, please see [link to embodiment]. Figure 16 The third power line 500 is electrically connected to the second electrode 63 (the connection line is not shown in the figure).

[0203] Optionally, the array substrate further includes a fourth power line 600 and / or a fifth power line 700. The fourth power line 600 and the fifth power line 700 are stacked sequentially in a direction away from the substrate 10.

[0204] Optionally, the third power line 500, the fourth power line 600 and the fifth power line 700 are stacked sequentially in a direction away from the substrate 10.

[0205] Optionally, the third power cord 500, the fourth power cord 600, and the fifth power cord 700 are electrically connected.

[0206] Optionally, the fifth power line 700 is arranged on the same layer as the first electrode 61.

[0207] In this embodiment, a display panel including the array substrate of any of the foregoing embodiments is provided, thereby making the bezel of the display panel narrower.

[0208] In one embodiment, please see [link to embodiment]. Figure 16The display panel also includes a touch layer 80, which is located on the side of the light-emitting device layer 60 away from the substrate 10. The overlapping area of ​​the orthographic projections of the fourth power line 600 and the fifth power line 700 on the substrate 10 overlaps with the overlapping area of ​​the orthographic projections of the touch layer 80 on the substrate 10 and the orthographic projections of the gate driving circuit on the substrate 10. The touch layer 80 is located on the side of the fourth power line 600 and the fifth power line 700 away from the substrate. By increasing the width of the fourth power line 600 and the fifth power line 700, and by using two shielding layers (equivalent to the fourth power line 600 and the fifth power line 700), interference from the touch layer to the gate driving circuit can be shielded.

[0209] The display panel includes a display area and a non-display area. The shift register 20 is located in the non-display area, and the pixel circuit 90 is located in the display area.

[0210] Optionally, the display panel may also include an encapsulation layer 70, which may be located between the touch layer 80 and the light-emitting device layer 60.

[0211] The touch layer is a film layer that enables the display panel to have touch functionality. It is a mature existing technology and will not be described in detail here.

[0212] In this embodiment, a display panel including the array substrate of any of the foregoing embodiments is provided, thereby making the bezel of the display panel narrower.

[0213] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0214] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0215] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A gate driving circuit is located on one side of the substrate. The gate driving circuit includes a multi-stage shift register. The shift register includes a first output transistor, a second output transistor, and a control module. The first output transistor is connected between a first signal line and the output terminal of the shift register. The second output transistor is connected between a second signal line and the output terminal of the shift register. The gates of the first and second output transistors are electrically connected to the control module. The orthographic projections of the first and second output transistors on the substrate are located on the same side as the orthographic projection of the control module on the substrate. The control module includes a first group of transistors and a second group of transistors. The second group of transistors in the control module of the shift register of the 2j-1 stage is electrically connected to the fourth conductive trace, the first group of transistors in the control module of the shift register of the 2j stage is electrically connected to the fourth conductive trace, and the fourth conductive trace is electrically connected to the second clock signal line through the first via. And / or, the second group of transistors in the control module of the shift register of the 2jth stage is electrically connected to the fifth conductive trace, and the first group of transistors in the control module of the shift register of the 2j+1th stage is electrically connected to the fifth conductive trace, and the fifth conductive trace is electrically connected to the first clock signal line through the second via; wherein, n / 2≥j≥1, and j is a positive integer, and n is the number of shift registers.

2. The array substrate according to claim 1, characterized in that, The orthographic projections of the first and second output transistors on the substrate are located between the orthographic projection of the control module on the substrate and the edge of the array substrate.

3. The array substrate according to claim 1, characterized in that, One of the first signal line and the second signal line is a high-voltage power supply line, and the other is a low-voltage power supply line; And / or, the first signal line and the second signal line extend along a first direction and are arranged along a second direction; And / or, the gate driving circuit is a light-emitting control driving circuit; And / or, the array substrate further includes a signal output line electrically connected to the output terminal of the shift register, the signal output line extending along a second direction, and the signal output line and the orthographic projection of the control module on the substrate arranged along a first direction.

4. The array substrate according to claim 1, characterized in that, The multi-stage shift registers are arranged along a first direction, and the orthogonal projections of the first and second output transistors on the substrate are located on one side of the opposite sides of the orthogonal projection of the control module on the substrate along a second direction, wherein the first direction intersects the second direction.

5. The array substrate according to claim 1, characterized in that, The array substrate also includes a first clock signal line, a second clock signal line, and a first power line that are electrically connected to the control module, and the first clock signal line, the second clock signal line, and the first power line are arranged on the same layer.

6. The array substrate according to claim 5, characterized in that, The orthographic projection of the first clock signal line on the substrate overlaps with the orthographic projection of the control module on the substrate.

7. The array substrate according to claim 5, characterized in that, The orthographic projection of the second clock signal line on the substrate overlaps with the orthographic projection of the control module on the substrate.

8. The array substrate according to claim 5, characterized in that, The orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the control module on the substrate.

9. The array substrate according to claim 5, characterized in that, The first clock signal line, the second clock signal line, and the first power line extend along a first direction and are arranged along a second direction.

10. The array substrate according to claim 1, characterized in that, The orthographic projection of the first signal line on the substrate overlaps with the orthographic projections of the first output transistor and the second output transistor on the substrate.

11. The array substrate according to claim 5, characterized in that, The first clock signal line, the second clock signal line, the first power line, and the first signal line are arranged on the same layer.

12. The array substrate according to claim 5, characterized in that, The first power line and the first signal line have different potentials.

13. The array substrate according to claim 5, characterized in that, The first power line and the second signal line have the same potential.

14. The array substrate according to claim 5, characterized in that, Each of the shift registers is connected to the first power line via two vias.

15. The array substrate according to claim 1, characterized in that, The control module includes a plurality of first transistors, the gates of which are electrically connected through a first conductive trace. The first conductive trace is electrically connected to one of a first clock signal line and a second clock signal line. And / or, the control module includes a plurality of second transistors, the gates of which are electrically connected via second conductive traces, the second conductive traces being electrically connected to another of a first clock signal line and a second clock signal line. And / or, the control module includes a plurality of third transistors, the gates of the plurality of third transistors being electrically connected through a third conductive trace, the third conductive trace being electrically connected to a first power line.

16. The array substrate according to claim 15, characterized in that, The first conductive trace is disposed on the same layer as the gate of the plurality of first transistors.

17. The array substrate according to claim 15, characterized in that, The second conductive trace is disposed on a different layer from the gate of the plurality of second transistors.

18. The array substrate according to claim 15, characterized in that, The third conductive trace is disposed on the same layer as the gate of the plurality of third transistors.

19. The array substrate according to claim 15, characterized in that, The third conductive trace is electrically connected to the first power line through a third via.

20. The array substrate according to claim 15, characterized in that, The second conductive trace electrically connected to the gate of the second transistor in the shift register of the 2i-1 stage is electrically connected to the first conductive trace electrically connected to the gate of the first transistor in the shift register of the 2i stage. The gates of the first transistor in the shift register of stage 2i-1 and the second transistor in the shift register of stage 2i are electrically connected to the first clock signal line. The gate of the second transistor in the shift register of the 2i-1 stage and the gate of the first transistor in the shift register of the 2i stage are electrically connected to the second clock signal line; wherein, n / 2≥i≥1, and i is a positive integer, and n is the number of shift registers.

21. The array substrate according to claim 5, characterized in that, The clock signals on the first clock signal line and the second clock signal line have the same frequency but opposite phase.

22. The array substrate according to claim 1, characterized in that, The first group of transistors includes one or more transistors, and the second group of transistors includes one or more transistors.

23. The array substrate according to claim 1, characterized in that, The orthographic projections of two adjacent shift registers on the substrate overlap with the orthographic projection of a first via on the substrate; the orthographic projections of two adjacent shift registers on the substrate overlap with the orthographic projection of a second via on the substrate.

24. The array substrate according to claim 1, characterized in that, The spacing between two adjacent first vias is equal to twice the size of the shift register along the first direction; the spacing between two adjacent second vias is equal to twice the size of the shift register along the first direction.

25. The array substrate according to any one of claims 1-24, characterized in that, The array substrate further includes a third power line, and the orthographic projections of the first output transistor and the second output transistor on the substrate are located between the orthographic projection of the control module on the substrate and the orthographic projection of the third power line on the substrate.

26. The array substrate according to claim 25, characterized in that, The array substrate further includes a fourth power line, and the orthographic projections of the first output transistor and the second output transistor on the substrate overlap with the orthographic projections of the fourth power line on the substrate. The orthographic projection of the third power line on the substrate overlaps with the orthographic projection of the fourth power line on the substrate; The third power line and the fourth power line are electrically connected, and the fourth power line is located on the side of the third power line away from the substrate.

27. The array substrate according to claim 25, characterized in that, The first signal line, the second signal line, and the third power line are arranged on the same layer.

28. The array substrate according to claim 25, characterized in that, The array substrate further includes a fourth power line and a fifth power line. The third power line, the fourth power line and the fifth power line are stacked sequentially in a direction away from the substrate, and the third power line, the fourth power line and the fifth power line are electrically connected.

29. The array substrate according to claim 1, characterized in that, The control module includes: The fifth transistor, sixth transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, thirteenth transistor, fourteenth transistor, fifteenth transistor, sixteenth transistor, seventeenth transistor, first capacitor, second capacitor, and third capacitor, or all of them, wherein: The first terminal of the fifth transistor is used to receive an input signal. The second terminal of the fifth transistor is connected to the gate of the sixth transistor, the first terminal of the tenth transistor, the first terminal of the fifteenth transistor, and the gate of the eleventh transistor. The gate of the fifth transistor is used to receive a first clock signal. The first terminal of the sixth transistor is used to receive a first clock signal. The second terminal of the sixth transistor is connected to the second terminal of the eighth transistor and the first terminal of the seventeenth transistor. The first terminal of the eighth transistor is used to receive a first level signal. The gate of the eighth transistor is used to receive the first clock signal. The gate of the seventeenth transistor is used to receive a first level signal. The second terminal of the seventeenth transistor is connected to the first terminal of the first capacitor, the first terminal of the sixteenth transistor, and the gate of the fourteenth transistor. The gate of the sixteenth transistor is used to receive a first level signal. The second terminal of the sixteenth transistor is connected to the gate of the ninth transistor. The second terminal of the ninth transistor is connected to the second terminal of the tenth transistor. The first terminal of the ninth transistor is used to receive a second level signal. The second terminal of the first capacitor is connected to the second terminal of the fourteenth transistor and the first terminal of the thirteenth transistor, respectively. The first terminal of the fourteenth transistor is used to receive the second clock signal, and the gate of the thirteenth transistor is used to receive the second clock signal. The second terminal of the thirteenth transistor is connected to the first terminal of the third capacitor, the gate of the first output transistor, and the second terminal of the eleventh transistor, respectively. The second terminal of the third capacitor is connected to the first terminal of the first output transistor, and the first terminal of the first output transistor is electrically connected to the first signal line. The second terminal of the first output transistor serves as the output terminal of the shift register. The first terminal of the eleventh transistor is used to receive the second level signal. The second terminal of the fifteenth transistor is connected to the first terminal of the second capacitor and the gate of the second output transistor, respectively. The gate of the fifteenth transistor is used to receive the first level signal. The second terminal of the second capacitor is used to receive the second clock signal, and the first terminal of the second output transistor is electrically connected to the second signal line. The second terminal of the second output transistor serves as the output terminal of the shift register.

30. The array substrate according to claim 29, characterized in that, The first clock signal connected to the transistor in the shift register of stage 2i-1 is provided by the first clock signal line, and the second clock signal connected to the transistor in the shift register of stage 2i-1 is provided by the second clock signal line. The first clock signal connected to the transistor in the shift register of the second i-th stage is provided by the second clock signal line, and the second clock signal connected to the transistor in the shift register of the second i-th stage is provided by the first clock signal line; n / 2≥i≥1, and i is a positive integer, and n is the number of shift registers.

31. The array substrate according to claim 29, characterized in that, The first level signal connected to the transistor in the control module is provided by the first power supply line.

32. The array substrate according to claim 29, characterized in that, The second-level signal connected to the transistor in the control module is provided by the first signal line.

33. The array substrate according to claim 29, characterized in that, The first end of the eighth transistor is electrically connected to the first power line through the fourth via.

34. An array substrate, characterized in that, include: Substrate; A gate driving circuit is located on one side of the substrate. The gate driving circuit includes a multi-stage shift register. The shift register includes a first group of transistors and a second group of transistors. The second group of transistors in the 2j-1 stage shift register is electrically connected to a fourth conductive trace. The first group of transistors in the 2j stage shift register is electrically connected to the fourth conductive trace. The fourth conductive trace is electrically connected to a second clock signal line through a first via. And / or, the second group of transistors in the shift register of the 2jth stage is electrically connected to the fifth conductive trace, and the first group of transistors in the shift register of the 2j+1th stage is electrically connected to the fifth conductive trace, and the fifth conductive trace is electrically connected to the first clock signal line through the second via; wherein, n / 2≥j≥1, and j is a positive integer, and n is the number of shift registers.

35. A display panel, characterized in that, It includes a light-emitting device layer and an array substrate as described in any one of claims 1-34; the light-emitting device layer is located on one side of the substrate, and the light-emitting device layer includes a first electrode, a light-emitting layer and a second electrode sequentially stacked in a direction away from the substrate.

36. The display panel according to claim 35, characterized in that, The array substrate also includes a third power line, which is electrically connected to the second electrode.

37. The display panel according to claim 36, characterized in that, The array substrate further includes a fourth power line and a fifth power line. The third power line, the fourth power line and the fifth power line are stacked sequentially in a direction away from the substrate. The third power line, the fourth power line and the fifth power line are electrically connected. The fifth power line is disposed in the same layer as the first electrode.

38. The display panel according to claim 36, characterized in that, The display panel further includes a touch layer located on the side of the light-emitting device layer away from the substrate. The overlapping area of ​​the orthographic projections of the fourth power line and the fifth power line on the substrate overlaps with the overlapping area of ​​the orthographic projections of the touch layer on the substrate and the orthographic projections of the gate driving circuit on the substrate.

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