FPGA-based HDMI video DDC signal optical communication processing system

Abstract

The application discloses an FPGA-based HDMI video DDC signal optical communication processing system, which comprises a sending end and a receiving end adopting FPGA chips, wherein the sending end and the receiving end each comprise a direction identification and control module for identifying and controlling the direction of a bus bidirectional signal, an encoding, framing and parallel-to-serial conversion module for processing the bus signal and converting the bus signal into a serial signal, an optical module for optoelectrical / electrooptical conversion of the signal, and a serial-to-parallel conversion, framing and decoding module for processing the serial signal; and the sending end and the receiving end are connected through optical communication. The application realizes automatic identification and control of the direction of I2C bidirectional signals through FPGA, oversamples the HPD signal, the 5V power signal, the I2C clock and data signals in DDC communication, converts the above-mentioned oversampled signals into parallel-to-serial conversion and serial-to-parallel conversion through a self-defined encoding mode, and then performs optical fiber long-distance transmission after electrooptical conversion, so that real-time transparent transmission of the I2C bidirectional signal is realized, and the real-time performance of HDMI video DDC communication is ensured.

Description

Technical Field

[0001] This invention belongs to the field of video optical transmission technology, specifically relating to an FPGA-based HDMI video DDC signal optical communication processing system. Background Technology

[0002] Commercially available HDMI video optical transmission solutions cannot achieve automatic direction recognition of I2C bidirectional signals and cannot perform transparent optical transmission of I2C bidirectional signals in the video DDC channel. Therefore, they are not suitable for scenarios with high real-time requirements for I2C communication (such as HDCP 1.4 / 2.2). Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an FPGA-based HDMI video DDC signal optical communication processing system.

[0004] The objective of this invention is achieved through the following technical solution. According to this invention, an HDMI video DDC signal optical communication processing system based on an FPGA includes a transmitter and a receiver using an FPGA chip. Both the transmitter and receiver include a direction identification and control module for identifying and controlling the direction of bidirectional bus signals, an encoding and framing module for processing bus signals and converting them into serial signals, an optical module for photoelectric / electro-optical conversion of signals, and a serial-to-parallel conversion, deframing, and decoding module for processing serial signals. The transmitter and receiver are connected via optical communication.

[0005] Furthermore, the direction recognition and control module processes the bidirectional bus signals and then transmits them to the encoding frame and parallel-to-serial conversion module for further processing.

[0006] Furthermore, the power signal and SCL signal in the bus signal are processed by the asynchronous oversampling module and then transmitted to the encoding frame and parallel-to-serial conversion module.

[0007] Furthermore, both the receiving end and the transmitting end are equipped with fiber breakage handling modules.

[0008] Furthermore, the direction identification and control module of the transmitting end is used to receive the host SDA signal and the optical receiver SDA signal, and to control the direction of the SDA signal according to the received signal.

[0009] Furthermore, when the direction identification and control module at the transmitting end is working, it first controls the direction of the SDA signal based on whether the system is reset. If a reset is performed, the direction of the SDA signal is controlled from the transmitting end to the receiving end. If no reset is performed, it continues to control the direction based on the following level states: whether the level states of the SDA signals at both ends of the direction identification and control module are both low. If they are low, the direction of the SDA signal remains unchanged. If the level state of the host SDA signal is high and the level state of the optical receiver SDA signal is low, the direction of the SDA signal is controlled from the receiving end to the transmitting end. If the level state of the host SDA signal is low and the level state of the optical receiver SDA signal is high, the direction of the SDA signal is controlled from the transmitting end to the receiving end. If the level states of the SDA signals at both ends of the module are both high, the direction of the SDA signal is controlled from the transmitting end to the receiving end.

[0010] Furthermore, the direction recognition and control module of the receiving end is used to control the direction of the SDA signal according to the optical receiving SDA signal. When the optical receiving SDA signal is high, the direction of the SDA signal is controlled to be from the receiving end to the transmitting end; when the optical receiving SDA signal is low, the direction of the SDA signal is controlled to be from the transmitting end to the receiving end.

[0011] Furthermore, in the encoding format of the encoding frame and parallel-to-serial conversion module, the frame header is a fixed 1111, the frame tail is a fixed 0000, the low-level encoding of the data line is 0101, and the high-level encoding is 1010. The three data lines at the transmitting end are used to represent the level states of the SDA signal, SCL signal, and power signal, respectively, and the three data lines at the receiving end are used to represent the SDA signal, HPD signal, and reserved signal, respectively.

[0012] Furthermore, the receiving process of the serial-to-parallel conversion, deframe, and decoding module is as follows: The FPGA uses a 200MHz operating clock to process the received serial signal with a rate of 40Mbps in 6-step processing, asynchronous sampling, and real-time detection of the rising and falling edges of the serial signal;

[0013] The serial clock counter is set to count the received serial signals. The counting range is 0 to 4. When the rising edge and falling edge of the serial signal are detected or the serial clock counter value is equal to 4, the serial clock counter is cleared to zero.

[0014] Set a serial data counter to count the high level of the serial signal; when the serial clock counter value is 0, take the initial value according to the level state of the serial signal. If the level is high, the initial value of the serial clock counter is 1, otherwise the initial value is 0; when the serial clock counter value is not greater than 4, the serial data counter counts the high level of the serial signal.

[0015] When the serial clock counter value is 0, the value of the currently received bits is determined based on the serial data counter value: when the serial data counter value is greater than or equal to 3, the serial data is 1; when the serial data counter value is equal to 0, the serial data is 0; when the serial data counter value is equal to 1 or 2, the serial data remains unchanged.

[0016] Furthermore, the serial-to-parallel conversion process of the serial-to-parallel conversion, de-framing, and decoding module is as follows: When the FPGA receives the frame header data 1111 and the received data before the frame header data is the frame tail data 0000, the frame data valid flag is set to a high level.

[0017] After all three data lines have been received, the system determines whether the received data line encoding information is high-level code 1010 or low-level code 0101 based on the encoding format, and decodes the corresponding data level state.

[0018] If the received data line encoding information is neither high-level encoding 1010 nor low-level encoding 0101, it indicates that the received data is incorrect. In this case, the data frame is discarded, and the data level state remains unchanged.

[0019] Compared with the prior art, the advantages of the present invention are:

[0020] This invention achieves automatic direction recognition and control of I2C bidirectional signals through FPGA. It oversamples the hot-plug HPD signal (hot-plug detection signal), 5V power signal, I2C clock and data signals in DDC communication, converts the sampled signals from parallel to serial through a custom encoding method, performs electro-optical conversion, transmits them over long distances through optical fiber, and then performs photoelectric conversion, thereby realizing real-time transparent transmission of I2C bidirectional signals and ensuring the real-time performance of HDMI video DDC communication.

[0021] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a functional block diagram of an embodiment of an FPGA-based HDMI video DDC signal optical communication processing system according to the present invention.

[0023] Figure 2 for Figure 1 A flowchart of SDA signal direction identification and control at the transmitting end;

[0024] Figure 3 for Figure 1A flowchart of SDA signal direction identification and control at the receiving end;

[0025] Figure 4 A flowchart for serial data signal reception and processing;

[0026] Figure 5 This is a flowchart for serial-to-parallel conversion processing. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] like Figure 1 The diagram shown is a functional block diagram of an embodiment of an HDMI video DDC signal optical communication processing system based on FPGA according to the present invention. The system includes a transmitter and a receiver, both of which use FPGA chips. The transmitter is located at the host end, and the receiver is located at the display end. The transmitter communicates with the host end and the receiver communicates with the display end via an I2C bus. The receiver communicates with the transmitter via optical fiber.

[0029] The transmitting end includes an asynchronous oversampling module, an encoding and framing module and a parallel-to-serial conversion module, a direction identification and control module, a fiber breakage handling module, and a serial-to-parallel conversion, deframing, and decoding module. The asynchronous oversampling module periodically samples the signal, and the fiber breakage handling module detects fiber breaks. If a fiber breakage is encountered, the system is kept in a reset state.

[0030] The direction identification and control module at the transmitting end is used to receive I2C data signals (hereinafter referred to as host SDA signals) input through the I2C host. Figure 1 The host SDA signal is input to this module via the DDC_sda data line, and the optical receiver I2C data signal (hereinafter referred to as the optical receiver SDA signal) is also input. Figure 1 The SDA signal received by the optical fiber is transmitted from the receiving end to the transmitting end. After being processed by the serial-to-parallel conversion, deframe, and decoding module at the transmitting end, it is transmitted to the direction identification and control module. The direction of the SDA signal is controlled according to the level of the received signal.

[0031] The direction identification and control module controls the direction of the I2C data signal (i.e., the SDA signal) based on whether the system is reset, the level state of the host SDA signal, and the level state of the optical receiver SDA signal. When the system is reset, the default direction of the SDA signal is from the transmitter to the receiver. The specific control logic of the direction identification and control module is shown in Table 1, where 0 in system reset indicates a reset and 1 indicates no reset; 0 in the host SDA signal level and 1 in the optical receiver SDA signal level indicate a low level and a high level, respectively.

[0032]

[0033] Table 1

[0034] The workflow diagram of the direction recognition and control module that determines the direction of the SDA signal at the transmitting end is as follows: Figure 2 As shown, when this module starts working, it first controls the direction of the SDA signal based on whether the system is reset. If a reset is performed, the direction of the SDA signal is controlled from the transmitting end to the receiving end. If no reset is performed, it continues to control the direction based on the following level states: whether the level states of the SDA signals at both ends of the module (i.e., the host SDA signal and the optical receiver SDA signal) are both low. If they are low, the direction of the SDA signal remains unchanged. If the level state of the host SDA signal is high and the level state of the optical receiver SDA signal is low, the direction of the SDA signal is controlled from the receiving end to the transmitting end. If the level state of the host SDA signal is low and the level state of the optical receiver SDA signal is high, the direction of the SDA signal is controlled from the transmitting end to the receiving end. If the level states of the SDA signals at both ends of the module are high, the direction of the SDA signal is controlled from the transmitting end to the receiving end.

[0035] The receiver includes a serial-to-parallel conversion and de-framing module, an encoding and framing module and a parallel-to-serial conversion module, a fiber breakage processing module, and a direction identification and control module.

[0036] The direction recognition and control module at the receiver is used to determine the direction of the received optical SDA signal (hereinafter referred to as the optical received SDA signal) based on the received optical SDA signal. Figure 1 In the optical fiber receiver, the SDA signal is transmitted from the transmitting end to the receiving end via optical fiber. At the receiving end, after processing by the serial-to-parallel conversion, deframe, and decoding module, it is transmitted to the direction identification and control module to control the direction of the SDA signal. When the optical SDA signal is high, the direction of the SDA signal is controlled from the receiving end to the transmitting end; when the optical SDA signal is low, the direction of the SDA signal is controlled from the transmitting end to the receiving end. The flowchart of the receiving end SDA signal direction identification and control is as follows: Figure 3 As shown.

[0037] The encoding, framing, and parallel-to-serial conversion module at the transmitting end is used to encode, frame, and convert SDA signals, SCL signals (I2C clock signals), and 5V power signals into parallel-to-serial signals. Figure 1 In the transmitting end, the SDA signal, processed by the direction recognition and control module, is transmitted to the encoding framing and parallel-to-serial conversion module. The SCL signal (I2C clock signal) is transmitted to the asynchronous oversampling module for processing via the DDC_scl data line, and then transmitted to the encoding framing and parallel-to-serial conversion module. The 5V power supply signal is transmitted to the asynchronous oversampling module for processing via the DDC_5v data line, and then transmitted to the encoding framing and parallel-to-serial conversion module.

[0038] The encoding, framing, and parallel-to-serial conversion module at the receiver is used to encode, frame, and convert HPD and SDA signals into parallel-to-serial signals. Figure 1 In the receiving end, the SDA signal, processed by the direction recognition and control module, is transmitted to the encoding frame and parallel-to-serial conversion module, and the HPD signal is transmitted to the encoding frame and parallel-to-serial conversion module through the DDC_hpd data line.

[0039] The encoding format for parallel-to-serial conversion is shown in Table 2. The frame header is a fixed 1111, the frame trailer is a fixed 0000, and the low-level encoding for the data line is 0101, while the high-level encoding is 1010. After encoding, since there are no long 1s or long 0s in the data line, the receiving end can more easily identify the frame header and trailer data, thus avoiding decoding errors.

[0040] Data row 1 bit 1 bit 2 bit 3 bit 4 Data row 2 bit 1 bit 2 bit 3 bit 4 Data row 3 bit 1 bit 2 bit 3 bit 4 Frame end 0 0 0 0

[0041] Table 2

[0042] (1) Definition of data line at the sending end:

[0043] Data row 1 (bit1~bit4): Used to indicate the level state of the SDA signal, with 0101 for low level and 1010 for high level;

[0044] Data row 2 (bit1~bit4): Used to indicate the level state of the SCL signal, with 0101 for low level and 1010 for high level;

[0045] Data row 3 (bit1~bit4): Used to indicate the level state of the 5V power supply signal, with 0101 for low level and 1010 for high level.

[0046] (2) Receiver data line definition:

[0047] Data row 1 (bit1~bit4): Used to indicate the level state of the SDA signal, with 0101 for low level and 1010 for high level;

[0048] Data row 2 (bit1~bit4): Used to indicate the level state of HPD signal, low level is 0101, high level is 1010;

[0049] Data row 3 (bit1~bit4): Reserved, fill with 0101.

[0050] The encoding, framing, and parallel-to-serial conversion modules at both the transmitting and receiving ends encode and frame the signal to achieve parallel-to-serial conversion. The transmitting end transmits the converted signal to the receiving end via electro-optical conversion by the optical module and optical fiber. The optical signal is processed by the receiving end's optical module's photoelectric conversion, serial-to-parallel conversion, deframing, and decoding modules to restore the signal. The SDA signal requires further processing by the receiving end's direction recognition and control module. The receiving end transmits the converted signal to the transmitting end via electro-optical conversion by the receiving end's optical module and optical fiber. The optical signal is processed by the transmitting end's optical module's photoelectric conversion, serial-to-parallel conversion, deframing, and decoding modules to restore the signal. The SDA signal requires further processing by the transmitting end's direction recognition and control module.

[0051] The serial-to-parallel conversion, deframe, and decoding modules at the transmitting and receiving ends process the serial signal (the signal after parallel-to-serial conversion) after photoelectric conversion as follows:

[0052] (1) The FPGA uses a 200MHz operating clock to process the received serial signal (rate of 40Mbps) in 6 steps, then performs asynchronous sampling, and detects the rising and falling edges of the serial signal in real time.

[0053] (2) Set the serial clock counter to count the received serial signals. The counting range is 0 to 4. When the rising edge and falling edge of the serial signal are detected or the serial clock counter value is equal to 4, the serial clock counter is cleared to zero.

[0054] (3) Set the serial data counter to count the high level of the serial signal; when the serial clock counter value is 0, take the initial value according to the level state of the serial signal. If the level is high, the initial value of the serial clock counter is 1, otherwise the initial value is 0; when the serial clock counter value is not greater than 4, the serial data counter counts the high level of the serial signal.

[0055] (4) When the serial clock counter value is 0, the value of the currently received bits is determined according to the serial data counter value: when the serial data counter value is greater than or equal to 3, that is, the high level is greater than half of the serial bit, the serial data is 1; when the serial data counter value is equal to 0, the serial data is 0; when the serial data counter value is equal to 1 or 2, that is, the high level is not greater than half of the serial bit, the sampled data is invalid, and the serial data remains unchanged.

[0056] The serial signal receiving and processing flow is as follows: Figure 4 As shown. This method can handle distortion of no more than 25% per bit of serial signal waveform during serial signal reception.

[0057] The serial-to-parallel conversion, deframe, and decoding modules at the transmitting and receiving ends perform serial-to-parallel conversion processing on the serial signal as follows: Figure 5 As shown:

[0058] (1) When the FPGA receives the frame header data 1111 and the received data before the frame header data is the frame tail data 0000, the frame data valid flag is set to high level, indicating that the received data after the frame header data is valid frame data.

[0059] (2) After all three data lines have been received, determine whether the received data line encoding information is high-level encoding 1010 or low-level encoding 0101 according to the encoding format, and decode the corresponding data level state.

[0060] (3) If the received data line encoding information is neither high-level encoding 1010 nor low-level encoding 0101, it means that the received data is incorrect. In this case, the data frame is discarded and the data level remains unchanged.

[0061] This invention uses FPGA to automatically identify and control the direction of I2C bidirectional signals. The processing time is only 3 processing clocks (clock frequency of 80MHz, processing time of 37.5ns), which is convenient and flexible. It realizes real-time transparent transmission of I2C bidirectional signals and solves the problem of real-time optical transmission of information such as HDMI video EDID and HDCP1.4 / 2.2. It is also applicable to the direction processing of bidirectional signals of other buses.

[0062] This invention uses a custom encoding method and an FPGA to serialize the I2C bidirectional signal, 5V power signal, and hot-plug HPD signal of DDC communication into a pair of differential signals. These signals can be directly connected to an optical module for electro-optical conversion and then transmitted optically. The entire link transmission delay is less than 1 μs, effectively ensuring the real-time performance of DDC communication. This invention also transmits the pair of differential signals through a single optical fiber, while reserving encoding positions for USB signals from keyboards and mice, facilitating the expansion of keyboard and mouse optical transmission communication functionality.

[0063] This invention utilizes a special serial-to-parallel conversion method with an FPGA to receive and convert serial signals. It can handle waveform distortion of no more than 25% per bit of serial signal and solve the serial reception problem caused by waveform distortion during photoelectric / electro-optical conversion.

[0064] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An FPGA-based HDMI video DDC signal optical communication processing system, comprising a transmitter and a receiver using FPGA chips, characterized in that: Both the transmitting end and the receiving end include a direction identification and control module for identifying and controlling the direction of the bidirectional bus signals, an encoding and framing module for processing the bus signals and converting them into serial signals, an optical module for photoelectric / electro-optical conversion of the signals, and a serial-to-parallel conversion, deframing, and decoding module for processing the serial signals. The transmitting end and the receiving end are connected via optical communication. The direction identification and control module of the transmitting end is used to receive the host SDA signal and the optical receiver SDA signal, and control the direction of the SDA signal according to the received signal; When the direction identification and control module at the transmitting end is working, it first controls the direction of the SDA signal based on whether the system is reset. If a reset is performed, the direction of the SDA signal is controlled from the transmitting end to the receiving end. If no reset is performed, it continues to control the direction based on the following level states: whether the level states of the SDA signals at both ends of the direction identification and control module are both low. If they are low, the direction of the SDA signal remains unchanged. If the level state of the host SDA signal is high and the level state of the optical receiver SDA signal is low, the direction of the SDA signal is controlled from the receiving end to the transmitting end. If the level state of the host SDA signal is low and the level state of the optical receiver SDA signal is high, the direction of the SDA signal is controlled from the transmitting end to the receiving end. If the level states of the SDA signals at both ends of the module are both high, the direction of the SDA signal is controlled from the transmitting end to the receiving end. The direction recognition and control module of the receiving end is used to control the direction of the SDA signal according to the optical receiving SDA signal. When the optical receiving SDA signal is high, the direction of the SDA signal is controlled to be from the receiving end to the transmitting end; when the optical receiving SDA signal is low, the direction of the SDA signal is controlled to be from the transmitting end to the receiving end.

2. The FPGA-based HDMI video DDC signal optical communication processing system according to claim 1, characterized in that: The direction recognition and control module processes the bidirectional bus signals and then transmits them to the encoding, framing, and parallel-to-serial conversion module for further processing.

3. The FPGA-based HDMI video DDC signal optical communication processing system according to claim 1, characterized in that: The power signal and SCL signal in the bus signal are processed by the asynchronous oversampling module and then transmitted to the encoding frame and parallel-to-serial conversion module.

4. The FPGA-based HDMI video DDC signal optical communication processing system according to claim 1, characterized in that: Both the receiving end and the transmitting end are equipped with fiber breakage handling modules.

5. The FPGA-based HDMI video DDC signal optical communication processing system according to claim 1, characterized in that: In the encoding format of the encoding frame and parallel-to-serial conversion module, the frame header is a fixed 1111, the frame tail is a fixed 0000, the low level of the data line is encoded as 0101, and the high level is encoded as 1010. The three data lines of the transmitting end are used to represent the level states of the SDA signal, SCL signal, and power signal, respectively, and the three data lines of the receiving end are used to represent the SDA signal, HPD signal, and reserved signal, respectively.

6. The FPGA-based HDMI video DDC signal optical communication processing system according to claim 1, characterized in that: The receiving process of the serial-to-parallel conversion, deframe, and decoding module is as follows: The FPGA uses a 200MHz operating clock to process the received serial signal with a rate of 40Mbps in 6-step processing, asynchronous sampling, and real-time detection of the rising and falling edges of the serial signal. The serial clock counter is set to count the received serial signals. The counting range is 0~4. When the rising edge and falling edge of the serial signal are detected or the serial clock counter value is equal to 4, the serial clock counter is cleared to zero. Set a serial data counter to count the high level of the serial signal; When the serial clock counter value is 0, the initial value is taken according to the level state of the serial signal. If the level is high, the initial value of the serial clock counter is 1; otherwise, the initial value is 0. When the serial clock counter value is not greater than 4, the serial data counter counts the high level of the serial signal; When the serial clock counter value is 0, the value of the currently received bits is determined based on the serial data counter value; when the serial data counter value is greater than or equal to 3, the serial data is 1. When the serial data counter value is equal to 0, the serial data is 0; The serial data remains unchanged when the serial data counter value is equal to 1 or 2.

7. The FPGA-based HDMI video DDC signal optical communication processing system according to claim 1, characterized in that: The serial-to-parallel conversion process of the serial-to-parallel conversion, de-framing and decoding module is as follows: When the FPGA receives the frame header data 1111 and the received data before the frame header data is the frame tail data 0000, the frame data valid flag is set to a high level. After all three data lines have been received, the encoding information of the received data lines is determined according to the encoding format. It is either high-level encoding 1010 or low-level encoding 0101, and the corresponding data level state is decoded. If the received data line encoding information is neither high-level encoding 1010 nor low-level encoding 0101, it indicates that the received data is incorrect. In this case, the data frame is discarded, and the data level state remains unchanged.

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