Scan driving circuit and display panel

Abstract

Embodiments of the present application disclose a scanning driving circuit and a display panel, comprising n cascaded scanning driving units, the scanning driving unit comprising a first maintaining module, a second maintaining module, a first auxiliary pull-down module, a first node and a second node, the first maintaining module being connected to the first node and the second node, the second maintaining module being connected to the first node, the second node and a stage transmission signal output end of a J-b scanning driving unit, the first auxiliary pull-down module being connected to the stage transmission signal output end of the J-b scanning driving unit and the first maintaining module, when the stage transmission signal output end of the J-b scanning driving unit outputs a stage transmission signal and / or the first node is a first potential, the first auxiliary pull-down module controls the first maintaining module to stop charging the second node, and at the same time, the second maintaining module pulls down the second node to a second potential, so as to control the second node to drop to the second potential within a preset time.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to scanning drive circuits and display panels. Background Technology

[0002] Gate Driver Less (GDL) technology utilizes the existing array fabrication process of liquid crystal display panels to fabricate the driving circuitry for horizontal scan lines on the substrate surrounding the display area. This allows it to replace external integrated circuit (IC) boards to drive the horizontal scan lines. GDL technology reduces the soldering steps required for external ICs, making liquid crystal display panels more suitable for manufacturing narrow-bezel or bezel-less display products. The scan driving circuit typically consists of multiple cascaded scan driving units, each of which outputs at least one scan signal to control the pixels for image display.

[0003] Currently, scanning drive units typically have an output control node. The output of the scanning signal is controlled by the voltage change of the output control node. However, when the output control node controls the output of the scanning signal or stops the output, the voltage of the output control node is easily affected, causing the voltage of the output control node to fail to adjust to the preset potential within a preset time. This affects the output of the scanning signal and leads to uneven pixel brightness. Therefore, how to effectively control the voltage of the output control node to change to the preset potential within a preset time is an urgent problem to be solved. Summary of the Invention

[0004] In view of the shortcomings of the prior art, this application provides a scanning drive circuit and a display panel. The output control node in the scanning drive circuit can drop to a low potential within a preset time, thereby eliminating the problem of uneven pixel brightness caused by incomplete node voltage drop.

[0005] This application provides a scan driving circuit, including n cascaded scan driving units, where n is an integer greater than or equal to 1. Each scan driving unit outputs four scan signals to control pixel units for image display. In the J-th scan driving unit, the scan driving unit includes a first signal output subunit, which outputs two scan signals and at least one stage transmission signal. The stage transmission signal is used as a start signal to be transmitted to the cascaded J+a-th scan driving unit to drive the J+a-th scan driving unit to output the scan signals and the stage transmission signal, where 1 ≤ a < n, 1 ≤ J < n, and a and J are integers. The first signal output subunit further includes a first sustaining module, a second sustaining module, a first auxiliary pull-down module, a first node, and a second node. The first sustaining module is connected to the first node and the second node and is used to charge the second node to control the second node to maintain the second node at a first potential. The second sustaining module is connected to the first node, the second node, and the stage transmission signal output terminal of the Jb scan driving unit. The first auxiliary pull-down module is connected to the stage transmission signal output terminal of the Jb scan driving unit and the first sustaining module. When the stage transmission signal output terminal of the Jb scan driving unit outputs a stage transmission signal and / or the first node is at the first potential, the first auxiliary pull-down module controls the first sustaining module to stop charging the second node, and at the same time, the second sustaining module pulls the second node down to the second potential. When the first node is at the first potential, the first signal output subunit outputs a scan signal and a stage transmission signal, where 1≤b<n, and b is an integer.

[0006] Optionally, the first signal output subunit further includes a j-th scan signal output terminal, a j+1-th scan signal output terminal, and a j+1-th stage transmission signal output terminal, used to output scan signals through the j-th scan signal output terminal and the j+1-th scan signal output terminal respectively, and simultaneously output stage transmission signals through the j+1-th stage transmission signal output terminal, where j = 4J-3 and j is an integer. The first signal output subunit also includes a first output module and a second output module. The first output module is connected to the first node and the j-th scan signal output terminal, and the second output module is connected to the first node, the j+1-th scan signal output terminal, and the j+1-th stage transmission signal output terminal. When the voltage of the first node is a first potential, the first output module outputs a scan signal through the j-th scan signal output terminal, and the second output module outputs a scan signal through the j+1-th scan signal output terminal and outputs stage transmission signals through the j+1-th stage transmission signal output terminal.

[0007] Optionally, the first signal output subunit further includes a first pull-up module, a first pull-down module, and a second pull-down module. The first pull-up module is connected to the (j-4)th stage signal output terminal and the first node, and is used to pull the first node to a first potential when the (j-4)th stage signal output terminal outputs a stage signal. The (j-4)th stage signal output terminal is located in the (j-1)th scan drive unit. The first pull-down module is connected to the second node and the j-th scan signal output terminal. The second pull-down module is connected to the second node, the (j+1)th scan signal output terminal, and the (j+1)th stage signal output terminal. When the second node is at the first potential, the first pull-down module pulls the j-th scan signal output terminal down to the second potential to control the j-th scan signal output terminal to stop outputting the scan signal. The second pull-down module pulls the (j+1)th scan signal output terminal and the (j+1)th stage signal output terminal down to the second potential to control the (j+1)th scan signal output terminal to stop outputting the scan signal and the (j+1)th stage signal output terminal to stop outputting the stage signal. The second potential is lower than the first potential.

[0008] Optionally, the pull-up module includes a first switching transistor, the first output module includes a second switching transistor, and the second output module includes a third and a fourth switching transistor. The gate and source of the first switching transistor are connected to the (j-4)th stage transmission signal output terminal, and the drain of the first switching transistor is connected to the first node. It is used to turn on under the control of the stage transmission signal output from the (j-4)th stage transmission signal output terminal, and pull up the first node to the first potential according to the stage transmission signal. The gate of the second switching transistor is connected to the first node, the source of the second switching transistor is connected to the clock signal terminal, and the drain of the second switching transistor is connected to the j-th scan signal output terminal. It is used to turn on when the first node is at the first potential, receive the i-th clock signal from the clock signal terminal, and output the i-th clock signal as a scan signal through the j-th scan signal output terminal, where i is an integer greater than or equal to 1. The gate and source of the third switch are connected to the clock signal terminal, and the drain of the third switch is connected to the (j+1)th stage signal output terminal. It is used to turn on when the first node is at the first potential, receive the (i+1)th clock signal from the clock signal terminal, and output the (i+1)th clock signal as a stage signal through the (j+1)th stage signal output terminal. The gate and source of the fourth switch are connected to the clock signal terminal, and the drain of the fourth switch is connected to the (j+1)th scan signal output terminal. It is used to turn on when the first node is at the first potential, receive the (i+1)th clock signal from the clock signal terminal, and output the (i+1)th clock signal as a scan signal through the (j+1)th scan signal output terminal.

[0009] Optionally, the first pull-down module includes a fifth switch and a sixth switch. The scan drive circuit further includes a second signal output subunit, which outputs two scan signals and at least one stage signal. The second signal output subunit includes a third node. The gate of the fifth switch is connected to the second node, the source of the fifth switch is connected to the j-th scan signal output terminal, and the drain of the fifth switch is connected to a low-voltage terminal. This allows the fifth switch to conduct when the second node is at a first potential. The j-th scan signal output terminal is connected to the low-voltage terminal via the fifth switch to control the potential of the j-th scan signal output terminal to drop to the second potential. The gate of the sixth switch is connected to the third node, the source of the sixth switch is connected to the j-th scan signal output terminal, and the drain of the sixth switch is connected to a low-voltage terminal. This allows the sixth switch to conduct when the third node is at the first potential. The j-th scan signal output terminal is connected to the low-voltage terminal via the sixth switch to control the potential of the j-th scan signal output terminal to drop to the second potential.

[0010] Optionally, the second pull-down module includes a seventh switch, an eighth switch, a ninth switch, and a tenth switch. The second signal output subunit also includes a fourth node. The gate of the seventh switch is connected to the fourth node, the source of the seventh switch is connected to the (j+1)th stage signal output terminal, and the drain of the seventh switch is connected to the low-voltage terminal. The gate of the eighth switch is connected to the fourth node, the source of the eighth switch is connected to the (j+1)th stage scan signal output terminal, and the drain of the eighth switch is connected to the low-voltage terminal. When the fourth node is at the first potential, the seventh and eighth switches are turned on, the potential of the (j+1)th stage scan signal output terminal drops to the second potential, and the potential of the (j+1)th stage signal output terminal drops to the second potential.

[0011] Optionally, the first sustaining module includes an eleventh, twelfth, thirteenth, and fourteenth switch transistors, and the first auxiliary pull-down module includes a fifteenth switch transistor. The source and gate of the eleventh switch transistor are connected to the power supply voltage terminal, and the drain of the eleventh switch transistor is connected to the twelfth and thirteenth switch transistors. The gate of the twelfth switch transistor is connected to the drain of the eleventh switch transistor, the source of the twelfth switch transistor is connected to the power supply voltage terminal, and the drain of the twelfth switch transistor is connected to the second node. The eleventh and twelfth switch transistors are turned on under the control of the power supply voltage terminal to charge the second node, thereby controlling the second node to maintain at the first potential. The gate of the thirteenth switch transistor is connected to the first node, the source of the thirteenth switch transistor is connected to the gate of the twelfth switch transistor, and the drain of the thirteenth switch transistor is connected to the low-voltage terminal. When the first node is reached, the thirteenth switch transistor is turned on to control the twelfth switch transistor to stop charging the second node. The gate of the fourteenth switch is connected to the third node, the source of the fourteenth switch is connected to the gate of the twelfth switch, and the drain of the twelfth switch is connected to the low-voltage terminal. When the third node is at the first potential, the fourteenth switch is turned on to control the twelfth switch to stop charging the second node. The gate of the fifteenth switch is connected to the stage transmission signal output terminal in the Jb scan drive unit, the source of the fifteenth switch is connected to the gate of the twelfth switch, and the drain of the fifteenth switch is connected to the low-voltage terminal. When the fifteenth switch receives the stage transmission signal from the stage transmission signal output terminal in the Jb scan drive unit, it is turned on to control the twelfth switch to stop charging the second node.

[0012] Optionally, the second signal output subunit further includes a third sustaining module, a fourth sustaining module, and a second auxiliary pull-down module. The third sustaining module is connected to the third node and the fourth node and is used to charge the fourth node to control the fourth node to maintain it at the first potential. The fourth sustaining module is connected to the third node, the fourth node, and the stage transmission signal output terminal of the Jb scan driving unit. The second auxiliary pull-down module is connected to the stage transmission signal output terminal of the Jb scan driving unit and the third sustaining module. When the stage transmission signal output terminal of the Jb scan driving unit outputs a stage transmission signal and / or the third node is at the first potential, the second auxiliary pull-down module controls the third sustaining module to stop charging the fourth node, and at the same time, the fourth sustaining module pulls the fourth node down to the second potential. When the third node is at the first potential, the second signal output subunit outputs a scan signal and a stage transmission signal.

[0013] Optionally, the second signal output subunit further includes a second pull-up unit, a third output module, a fourth output module, a third pull-down module, a fourth pull-down module, a (j+2)th scan signal output terminal, a (j+3)th scan signal output terminal, and a (j+3)th stage signal transmission output terminal. The second pull-up unit is connected to the (j-2)th stage signal transmission output terminal and the third node, and is used to pull the third node to the first potential when the (j-2)th stage signal transmission output terminal outputs the stage transmission signal. The third output module is connected to the third node and the (j+2)th scan signal output terminal, and the fourth output module is connected to the third node, the (j+3)th scan signal output terminal, and the (j+3)th stage signal transmission output terminal. When the third node is at the first potential, the first output module outputs the scan signal through the (j+2)th scan signal output terminal, and the fourth output module outputs the scan signal through the (j+3)th scan signal output terminal and outputs the stage transmission signal through the (j+3)th stage signal transmission output terminal. The third pull-down module is connected to the third node and the (j+2)th scan signal output terminal. When the fourth node is at the first potential, the third pull-down module pulls down the potential of the (j+2)th scan signal output terminal to the second potential. The fourth pull-down module is connected to the fourth node, the (j+3)th scan signal output terminal, and the (j+3)th stage signal output terminal. When the fourth node is at the first potential, the fourth pull-down module pulls down the potential of the (j+3)th scan signal output terminal to the second potential and pulls down the potential of the (j+3)th stage signal output terminal to the second potential.

[0014] This application also provides a display panel, including a plurality of pixel units disposed in a display area and arranged in a matrix, a data driving circuit disposed in a non-display area, a timing control circuit, and the aforementioned scan driving circuit. The scan driving circuit outputs a gate output control signal according to the timing control circuit, and together with the data driving circuit outputs a source output control signal according to the timing control circuit, drives the pixel units to display images.

[0015] Compared to the problems of existing technologies, the embodiments of this application, by setting a first auxiliary pull-down module, enable the first auxiliary pull-down module and the second maintenance module to work together to pull down the potential of the second node, thereby controlling the second node to drop to the second potential within a preset time, effectively eliminating the step voltage phenomenon of the second node. Furthermore, by adjusting the position of the cascade signal output terminal, the coupling effect between the cascade signal and the scan signal output in the first output module is eliminated, and the voltage drop of the scan signal output from the (j+1)th scan signal output terminal is eliminated, so that the waveforms of the scan signals output from the j-th scan signal output terminal G(j) and the (j+1)th scan signal output terminal are not significantly different, thus solving the problem of uneven brightness between the two rows of pixels.

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a display device provided in the first embodiment of this application;

[0018] Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel;

[0019] Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the central display panel;

[0020] Figure 4 for Figure 3 The diagram shows the structure of the scanning drive circuit.

[0021] Figure 5 for Figure 4 Equivalent circuit diagram of the scanning drive unit;

[0022] Figure 6 for Figure 5 Schematic diagram of voltage waveform changes at mid-node;

[0023] Figure 7 A second embodiment of this application provides a method such as Figure 4 Equivalent circuit diagram of the scanning drive unit;

[0024] Figure 8 for Figure 7 A schematic diagram of the voltage waveform at the midpoint;

[0025] Figure 9 A third embodiment of this application provides a method such as Figure 4 Equivalent circuit diagram of the scanning drive unit;

[0026] Figure 10 for Figure 9 Schematic diagram of voltage waveform at the mid-node.

[0027] Explanation of reference numerals in the attached drawings: Display device-100, Display panel-10, Power module-20, Support frame-30, Display area-10a, Non-display area-10b, Timing control circuit-11, Data driving circuit-12, Scan driving circuit-13, Pixel unit-P, Backlight module-17, Array substrate-10c, Liquid crystal layer-10e, Color filter substrate-10d, First direction-F1, Second direction-F2, m data lines-S1~Sm, 4n scan lines-G1~G4n, Clock signal-CLK, Start signal-STV, Scan driving unit-GOA, First signal output subunit-GDL1, Second signal output subunit-GDL2, First pull-up module-141, First output module-141, etc. Block-142A, Second Output Module-142B, First Pull-down Module-143A, Second Pull-down Module-143B, First Holding Module 144A, Second Holding Module 144B, First Auxiliary Pull-down Module 145, First Pull-down Control Module-146, First Reset Signal-R1, Second Pull-up Module-151, Third Output Module-152A, Fourth Output Module-152B, Third Pull-down Module-153A, Fourth Pull-down Module-153B, Second Auxiliary Pull-down Module-155, Second Pull-down Control Module-156, First Switch T1, Second Switch T2, Third Switch T3, Fourth Switch T4, Fifth Switch T5, Sixth Switch T6, Seventh Switch T7 8th Switch - T8, 9th Switch - T9, 10th Switch - T10, 11th Switch - T11, 12th Switch - T12, 13th Switch - T13, 14th Switch - T14, 15th Switch - T15, 16th Switch - T16, 17th Switch - T17, 18th Switch - T18, 19th Switch - T19, 20th Switch - T20, 21st Switch - T21, 22nd Switch - T22, 23rd Switch - T23, 24th Switch - T24, 25th Switch - T25, 26th Switch - T26, 27th Switch - T27, 28th Switch - T28, 29th Switch - T29 30th switch transistor - T30, 31st switch transistor - T31, 32nd switch transistor - T32, 33rd switch transistor - T33, 34th switch transistor - T34, 35th switch transistor - T35, 36th switch transistor - T36, 37th switch transistor - T37, 38th switch transistor - T38, 39th switch transistor - T39, 40th switch transistor - T40, 41st switch transistor - T41, 42nd switch transistor - T42, First low-voltage terminal - Vss1, Second low-voltage terminal - Vss2, J-th stage signal output terminal - C(j), J+1-th stage signal output terminal - G(j+1), J+2-th stage signal output terminal - G(j+2), J+3-th stage signal output terminal - G(j+3)The signal output terminals for the (j+1)th stage and (j+3)th stages are -C(j+3), -C(j-2), -C(j-4), -C(j-6), and -C(j+8). Detailed Implementation

[0028] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0029] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0031] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0033] Please see Figure 1 , Figure 1 This is a schematic diagram of a display device according to the first embodiment of this application. The display device 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is disposed on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images, and the support frame 30 provides fixation and protection for the display panel 10 and the power module 20.

[0034] In other embodiments of this application, the display device 100 may not require the support frame 30, for example, it may be a portable electronic device, such as a mobile phone or tablet computer.

[0035] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel.

[0036] The display panel 10 includes an array substrate 10c and a color filter substrate 10d, and a liquid crystal layer 10e sandwiched between the array substrate 10c and the color filter substrate 10d. Driving elements are disposed on the array substrate 10c and the color filter substrate 10d to generate corresponding electric fields according to data signals, thereby driving the liquid crystal molecules in the liquid crystal layer 10e to rotate by an angle to emit light of corresponding brightness, so as to perform image display.

[0037] In this embodiment, the display panel 10 can be a liquid crystal display panel or other types of display panels, and this application does not impose any restrictions.

[0038] Taking a liquid crystal display panel as an example, the display panel 10 also includes a backlight module 17 (BM), which provides light for display to the display area 10a of the display panel 10. The display panel 10 emits corresponding light according to the image signal to be displayed to perform image display. The display panel 10 also includes other elements or components, such as a signal processor module and a signal sensing module.

[0039] Please refer to the following: Figure 3 , Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the array substrate.

[0040] like Figure 3 As shown, corresponding to the non-display area 10b of the display panel 10, the array substrate 10c is also provided with a timing control circuit 11, a data driving circuit 12 and a scanning driving circuit 13.

[0041] Corresponding to the display area 10a of the display panel 10, the array substrate 10c is provided with m data lines S1 to Sm and 4n scan lines G1 to G4n arranged in a grid pattern. The m data lines S1 to Sm extend along a first direction F1, and the 4n scan lines G1 to G4n extend along a second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units P are respectively disposed at the intersections of the 4n scan lines G1 to G4n and the data lines S1 to Sm.

[0042] The timing control circuit 11 receives the image signal representing image information from an external signal source, obtains the clock signal CLK, the horizontal synchronization signal Hsyn, and the vertical synchronization signal Vsyn for synchronization, and outputs the gate output control signal Cg for the scan drive circuit 13, the source output control signal Cs for the data drive circuit 12, and the data signal representing image information.

[0043] m data lines S1 to Sm are connected to the data driving circuit 12 to receive data signals provided by the data driving circuit 12, which are stored and transmitted in the form of grayscale values. 4n scan lines G1 to G4n are connected to the scan driving circuit 13 to receive scan signals.

[0044] Under the control of 4n scan lines G1 to G4n, the pixel unit P receives the grayscale data voltage of the corresponding data signal provided by the data lines S1 to Sm within a predetermined time period, and drives the liquid crystal layer 10e to deflect at a corresponding angle, thereby emitting light of corresponding brightness according to the corresponding deflection angle, so as to achieve image display by emitting light of corresponding brightness according to the image signal.

[0045] Please see Figure 4 , Figure 4 for Figure 3 The diagram shows the structure of the scanning drive circuit.

[0046] like Figure 4 As shown, the scan drive circuit 13 includes n cascaded scan drive units GOA, M clock signals CLK1-CLKM and a start signal STV, where n and M are integers greater than or equal to 1.

[0047] In this embodiment, M=8, meaning that eight clock signals CLK1-CLK8 are used to provide the scan drive timing for the scan signals output by the n scan drive units GOA. The start signal STV is the enable start signal for the first scan drive unit GOA1, and the other scan drive units use the cascaded transmission signals output by the cascaded scan drive units as their start signals.

[0048] Each scan driving unit, under the control of four clock signals, outputs four scan signals to the four scan lines in the display area 10a. During the display of one frame of image, n scan driving units sequentially output 4n scan signals. Taking the J-th scan driving unit as an example, the J-th scan driving unit includes a j-th scan signal output terminal, a (j+1)-th scan signal output terminal, a (j+2)-th scan signal output terminal, and a (j+3)-th scan signal output terminal, used to output scan signals through these four scan signal output terminals respectively, where 1 ≤ J < n, j = 4J - 3, and J and j are integers. Simultaneously, the J-th scan driving unit also includes at least two cascade signal output terminals, such as the j-th scan signal output terminal and the (j+1)-th scan signal output terminal, used to output cascade signals through the j-th scan signal output terminal and the (j+1)-th scan signal output terminal respectively, and transmit them to the (J+a)-th scan driving unit as the start signal for the (J+a)-th scan driving unit to control the output of scan signals by the (J+a)-th scan driving unit, where 1 ≤ a < n, and a is an integer.

[0049] In an exemplary embodiment, 'a' can be set according to specific needs, that is, the cascading relationship of the scan driving unit GOA can be set according to specific needs. For example, 'a' can be set to 1, in which case the Jth scan driving unit and the (J+1)th scan driving unit are cascaded. 'a' can also be set to 2, in which case the Jth scan driving unit and the (J+2)th scan driving unit are cascaded, etc. This application does not impose any restrictions on this.

[0050] Please see Figure 5 , Figure 5 for Figure 4 Equivalent circuit diagram of the scanning drive unit.

[0051] like Figure 5As shown, each scan drive unit includes two signal output subunits: a first signal output subunit GDL1 and a second signal output subunit GDL2. Taking the J-th scan drive unit as an example, the first signal output subunit GDL1 outputs two scan signals and one cascading signal, while the second signal output subunit GDL2 outputs two scan signals and one cascading signal. The scan signals are used to control the pixel unit P to receive data signals for image display, and the cascading signal serves as the start signal for the cascaded scan drive units.

[0052] The first signal output subunit GDL1 includes a first pull-up module 141, a first output module 142A, a second output module 142B, and a first node Q1. The first pull-up module 141 is connected to the first node Q1 and the (j-4)th stage signal output terminal C(j-4), and is used to pull up the first node Q1 to the first potential under the control of the stage signal output from the (j-4)th stage signal output terminal C(j-4).

[0053] The first output module 142A is connected to the first node Q1, the clock signal terminal (unidentified), the j-th scan signal output terminal G(j), and the j-th stage transmission signal output terminal C(j). The second output module 142B is connected to the first node Q1, the clock signal terminal (unidentified), and the (j+1)-th scan signal output terminal G(j+1). When the first node Q1 is at the first potential, the first output module 142A is used to receive the i-th clock signal CLK(i) from the clock signal terminal under the control of the first node Q1 and output the scan signal through the j-th scan signal output terminal G(j) according to the i-th clock signal CLK(i), and output the stage transmission signal through the j-th stage transmission signal output terminal C(j). The second output module 142B is used to receive the (i+1)-th clock signal CLK(i+1) from the clock signal terminal under the control of the first node Q1 and output the scan signal through the (j+1)-th scan signal output terminal G(j+1) according to the (i+1)-th clock signal CLK(i+1).

[0054] The first signal output subunit GDL1 also includes a first pull-down module 143A, a second pull-down module 143B, a first sustaining module 144A, a second sustaining module 144B, and a first pull-down control module 146.

[0055] The first pull-down module 143A is connected to the second node Q2, the j-th stage signal output terminal C(j), and the j-th scan signal output terminal G(j). When the second node Q2 is at the first potential, the first pull-down module 143A pulls down the potential of the j-th stage signal output terminal C(j) to the second potential, thus stopping the output of the j-th stage signal. Simultaneously, it pulls down the potential of the j-th scan signal output terminal G(j) to the second potential, thus stopping the output of the j-th scan signal. The first node Q1 and the second node Q2 are the output control nodes, used to control the output of the scan signal.

[0056] The second pull-down module 143B is connected to the second node Q2 and the output terminal G(j+1) of the (j+1)th scan signal. When the second node is at the first potential, the second pull-down module 143B pulls down the potential of the output terminal G(j+1) of the (j+1)th scan signal to the second potential, thereby controlling the (j+1)th scan signal to stop outputting.

[0057] The first sustaining module 144A connects the first node Q1 and the second node Q2. When the first node Q1 is at the second potential, that is, when the first pull-up module 141 does not pull up the potential of the first node Q1, the first sustaining module 144A charges the second node Q2 to control the second node Q2 to maintain the first potential. When the first node Q1 is at the first potential, the first sustaining module 144A stops charging the second node Q2.

[0058] The second sustaining module 144B connects the first node Q1, the second node Q2, and the signal output terminal C(j-6) of the (j-6)th stage. When the first node Q is at the first potential, the second sustaining module 144B pulls down and maintains the second node Q2 at the second potential. When the second sustaining module 144B receives the stage transmission signal from the signal output terminal C(j-6) of the (j-6)th stage, the second sustaining module 144B pulls down and maintains the second node Q2 at the second potential.

[0059] The first pull-down control module 146 is connected to the first node Q1, the second node Q2, the output terminal C(j+8) of the (j+8)th stage signal transmission, and the first reset signal R1. When the first pull-down control module 146 receives the (j+8)th stage signal transmission, it pulls down the potential of the first node Q1 to the second potential. It also pulls down the first node Q1 to the second potential when it receives the first reset signal R1, and pulls down the first node Q1 to the second potential when the second node Q2 is at the first potential.

[0060] The second signal output subunit GDL2 includes a second pull-up module 151, a third output module 152A, a fourth output module 152B, and a third node Q3. The second pull-up module 151 is connected to the third node Q3 and the (j-2)th stage signal output terminal C(j-2), and is used to pull up the third node Q3 to the first potential under the control of the stage signal output from the (j-2)th stage signal output terminal C(j-2).

[0061] The third output module 152A is connected to the third node Q3, the clock signal terminal (unidentified), the (j+2)th scan signal output terminal G(j+2), and the (j+1)th stage transmission signal output terminal C(j+1). The fourth output module 152B is connected to the third node Q3, the clock signal terminal (unidentified), and the (j+3)th scan signal output terminal G(j+3). When the first node Q1 is at the first potential, the third output module 152A is used to receive the (i+2)th clock signal CLK(i+2) from the clock signal terminal under the control of the first node Q1, and output the scan signal through the (j+2)th scan signal output terminal G(j+2) according to the (i+2)th clock signal CLK(i+2), and output the stage transmission signal through the (j+1)th stage transmission signal output terminal C(j+1). The fourth output module 152B is used to receive the (i+3)th clock signal CLK(i+3) from the clock signal terminal under the control of the third node Q3, and output the scan signal through the (j+3)th scan signal output terminal G(j+3) according to the (i+3)th clock signal CLK(i+3).

[0062] The second signal output subunit GDL2 also includes a third pull-down module 153A, a fourth pull-down module 153B, a third sustaining module 154A, a fourth sustaining module 154B, and a second pull-down control module 156. The third pull-down module 153A is connected to the fourth node Q4, the (j+1)th stage transmission signal C(j+1), and the (j+2)th scan signal output terminal G(j+2). When the fourth node Q4 is at the first potential, the third pull-down module 153A pulls down the potential of the (j+1)th stage transmission signal output terminal C(j+1) to the second potential, thus stopping the output of the (j+1)th stage transmission signal. Simultaneously, it pulls down the potential of the (j+2)th scan signal output terminal G(j+2) to the second potential, thus stopping the output of the (j+2)th scan signal.

[0063] The fourth pull-down module 153B is connected to the fourth node Q4 and the output terminal G(j+3) of the (j+3)th scan signal. When the fourth node Q4 is at the first potential, the fourth pull-down module 153B pulls down the potential of the (j+3)th scan signal output terminal G(j+3) to the second potential, thereby controlling the (j+3)th scan signal to stop outputting.

[0064] The third sustaining module 154A connects the third node Q3 and the fourth node Q4. When the third node Q3 is at the second potential, that is, when the second pull-up module 151 does not pull up the potential of the third node Q3, the third sustaining module 154A charges the fourth node Q4 to control the fourth node Q4 to maintain the first potential. When the third node Q3 is at the first potential, the third sustaining module 154A stops charging the fourth node Q4.

[0065] The fourth sustaining module 154B connects the third node Q3, the fourth node Q4, and the signal output terminal C(j-6) of the (j-6)th stage. When the first node Q is at the first potential, the fourth sustaining module 154B pulls down and maintains the fourth node Q4 at the second potential. When the fourth sustaining module 154B receives the stage transmission signal from the signal output terminal C(j-6) of the (j-6)th stage, the fourth sustaining module 154B pulls down and maintains the fourth node Q4 at the second potential.

[0066] The second pull-down control module 156 is connected to the third node Q3, the fourth node Q4, the output terminal C(j+10) of the (j+10)th level signal transmission, and the second reset signal R2. When the second pull-down control module 156 receives the (j+10)th level signal transmission, it pulls down the potential of the third node Q3 to the second potential. It also pulls down the third node Q3 to the second potential when it receives the second reset signal R2, and pulls down the third node Q3 to the second potential when the fourth node Q4 is at the first potential.

[0067] The first sustaining module 144A is also connected to the third node Q3. When the third node Q3 is at the first potential, the first sustaining module 144A stops charging the second node Q2 and is used to pull down the potential of the second node Q2. The third sustaining module 154A is also connected to the first node Q1. When the first node Q1 is at the first potential, the third sustaining module 154A stops charging the fourth node Q4 and is used to pull down the potential of the fourth node Q4.

[0068] The first pull-down module 143A is also connected to the fourth node Q4, and is used to turn on when the fourth node Q4 is at the first potential, so as to control the j-th stage signal output terminal C(j) and the j-th scan signal output terminal G(j) to stop outputting signals or output low-level signals.

[0069] The third pull-down module 153A is also connected to the second node Q2, and is used to turn on when the second node Q2 is at the first potential, so as to control the output terminal C(j+1) of the j+1 stage signal transmission and the output terminal G(j+2) of the j+2 stage scan signal to stop outputting signals or output low-level signals.

[0070] Specifically, the first pull-up module 141 includes a first switch transistor T1. The gate and source of the first switch transistor T1 are connected to the signal output terminal C(j-4) of the (j-4)th stage, and the drain is connected to the first node Q1. When the first switch transistor T1 receives the signal from the (j-4)th stage, the first switch transistor T1 is turned on, and the signal from the (j-4)th stage charges the first node Q1, pulling the first node Q1 up to the first potential.

[0071] The first output module 142A includes a second switch T2 and a third switch T3. The gate of the second switch T2 is connected to the first node Q1, the source is connected to the clock signal terminal, and the drain is connected to the j-th stage transmission signal output terminal C(j). The gate of the third switch T3 is connected to the first node Q1, the source is connected to the clock signal terminal, and the drain is connected to the j-th scan signal output terminal G(j). When the first node Q1 is at the first potential, the second switch T2 and the third switch T3 are turned on. The second switch T2 is used to receive the i-th clock signal CLK(i) from the clock signal terminal and output the i-th clock signal CLK(i) as the stage transmission signal through the j-th stage transmission signal output terminal C(j). The third switch T3 is used to receive the i-th clock signal CLK(i) from the clock signal terminal and output the i-th clock signal CLK(i) as the scan signal through the j-th scan signal output terminal G(j).

[0072] The second output module 142B includes a fourth switch T4. The gate of the fourth switch T4 is connected to the first node Q1, the source is connected to the clock signal terminal, and the drain is connected to the (j+1)th scan signal output terminal G(j+1). When the first node Q1 is at the first potential, the fourth switch T4 is turned on to receive the (i+1)th clock signal CLK(i+1) from the clock signal terminal and output the (i+1)th clock signal CLK(i+1) as a scan signal through the (j+1)th scan signal output terminal G(j+1).

[0073] The first pull-down module 143A includes a fifth switch T5, a sixth switch T6, a seventh switch T7, and an eighth switch T8. The gate of the fifth switch T5 is connected to the second node Q2, the source is connected to the j-th stage signal output terminal C(j), and the drain is connected to the first low-voltage terminal Vss1. The gate of the sixth switch T6 is connected to the second node Q2, the source is connected to the j-th scan signal output terminal G(j), and the drain is connected to the second low-voltage terminal Vss2. When the second node Q2 is at the first potential, the fifth switch T5 and the sixth switch T6 are turned on, thereby controlling the j-th scan signal output terminal G(j) and the j-th stage signal output terminal C(j) to stop outputting signals.

[0074] The gate of the seventh switch T7 is connected to the fourth node Q4, the source is connected to the j-th scan signal output terminal G(j), and the drain is connected to the second low-voltage terminal Vss2. The gate of the eighth switch T8 is connected to the fourth node Q4, the source is connected to the j-th stage signal output terminal C(j), and the drain is connected to the second low-voltage terminal Vss2. When the fourth node Q4 is at the first potential, the seventh switch T7 and the eighth switch T8 are turned on to control the j-th scan signal output terminal G(j) and the j-th stage signal output terminal C(j) to stop outputting signals.

[0075] The second pull-down module 143B includes a ninth switch T9 and a tenth switch T10. The gate of the ninth switch T9 is connected to the second node Q2, the source is connected to the (j+1)th scan signal output terminal G(j+1), and the drain is connected to the second low-voltage terminal Vss2. It is turned on when the second node Q2 is at the first potential to control the (j+1)th scan signal output terminal G(j+1) to connect to the second low-voltage terminal Vss2, thereby controlling the (j+1)th scan signal output terminal G(j+1) to stop outputting a signal. The gate of the tenth switch T10 is connected to the fourth node Q4, the source is connected to the (j+1)th scan signal output terminal G(j+1), and the drain is connected to the second low-voltage terminal Vss2. It is turned on when the fourth node Q4 is at the first potential to control the (j+1)th scan signal output terminal G(j+1) to connect to the second low-voltage terminal Vss2, thereby controlling the (j+1)th scan signal output terminal G(j+1) to stop outputting a signal.

[0076] The first sustaining module 144A includes an eleventh switch T11, a twelfth switch T12, a thirteenth switch T13, and a fourteenth switch T14. The source and gate of the eleventh switch T11 are connected to the power supply voltage terminal VDD, and its drain is connected to the twelfth and thirteenth switches T13. The gate of the twelfth switch T12 is connected to the drain of the eleventh switch T11, its source is connected to the power supply voltage terminal VDD, and its drain is connected to the second node Q2. The eleventh and twelfth switches T11 and T12 are turned on under the control of the power supply voltage terminal VDD to charge the second node Q2, thereby controlling the second node Q2 to maintain it at a first potential.

[0077] The gate of the thirteenth switch T13 is connected to the first node Q1, its source is connected to the drain of the eleventh switch T11, and its drain is connected to the first low-voltage terminal Vss1. It is used to turn on when the first node Q1 is at the first potential, and to control the drain of the eleventh switch T11 and the gate of the twelfth switch T12 to be connected to the first low-voltage terminal Vss1, thereby controlling the twelfth switch T12 to turn off, and thus controlling the power supply voltage terminal VDD to stop charging the second node Q2.

[0078] The gate of the fourteenth switch T14 is connected to the third node Q3, the source is connected to the drain of the eleventh switch T11, and the drain is connected to the first low-voltage terminal Vss1. It is used to turn on when the third node Q3 is at the first potential, and to control the drain of the eleventh switch T11 and the gate of the twelfth switch T12 to be connected to the first low-voltage terminal Vss1, thereby controlling the twelfth switch T12 to turn off, and thus controlling the power supply voltage terminal VDD to stop charging the second node Q2.

[0079] The second sustaining module 144B includes a sixteenth switch T16 and a seventeenth switch T17. The gate of the sixteenth switch T16 is connected to the first node Q1, the source to the second node Q2, and the drain to the first low-voltage terminal Vss1. When the first node Q1 is at the first potential, it controls the second node Q2 to connect to the first low-voltage terminal Vss1, thereby pulling down the potential of the second node Q2 to the second potential. The gate of the seventeenth switch T17 is connected to the signal output terminal C(j-6) of the (j-6)th stage, the source to the second node Q2, and the drain to the first low-voltage terminal Vss1. Under the control of the signal output terminal C(j-6) of the (j-6)th stage, it controls the second node Q2 to connect to the first low-voltage terminal Vss1, thereby pulling down the potential of the second node Q2 to the second potential.

[0080] The first pull-down control module 146 includes an eighteenth switch T18, a nineteenth switch T19, a twentieth switch T20, and a twenty-first switch T21. The gate of the eighteenth switch T18 is connected to a first reset signal R1, its source is connected to a first node Q1, and its drain is connected to a first low-voltage terminal Vss1. When the first reset signal R1 is received, the eighteenth switch T18 is turned on, controlling the first node Q1 to connect to the first low-voltage terminal Vss1, thereby pulling down the first node Q1 to a second potential. The gate of the nineteenth switch T19 is connected to the second node Q2, its source is connected to the first node Q1, and its drain is connected to the first low-voltage terminal Vss1. When the second node Q2 is at the first potential, the nineteenth switch T19 controls the first node Q1 to connect to the first low-voltage terminal Vss1, thereby pulling down the first node Q1 to the second potential. The gate of the twentieth switch T20 is connected to the signal output terminal C(j+8) of the (j+8)th stage, the source is connected to the first node Q1, and the drain is connected to the first low-voltage terminal Vss1. When the twentieth switch T20 receives a stage transmission signal from the signal output terminal C(j+8), it controls the first node Q1 to connect to the first low-voltage terminal Vss1, thereby pulling down the first node Q1 to the second potential. The gate of the twenty-first switch T21 is connected to the fourth node Q4, the source is connected to the first node Q1, and the drain is connected to the first low-voltage terminal Vss1. When the fourth node Q4 is at the first potential, the twenty-first switch T21 is turned on, controlling the first node Q1 to connect to the first low-voltage terminal Vss1, thereby pulling down the potential of the first node Q1 to the second potential.

[0081] In the second signal output subunit GDL2, the second pull-up module 151 includes a twenty-second switch T22. The gate and source of the twenty-second switch T22 are connected to the (j-2)th stage signal output terminal C(j-2), and the drain is connected to the third node Q3. When the twenty-second switch T22 receives a stage signal from the (j-2)th stage signal output terminal C(j-2), the twenty-second switch T22 is turned on to charge the third node Q3 and pull the third node Q3 up to the first potential.

[0082] The third output module 152A includes a twenty-third switch T23 and a twenty-fourth switch T24. The gate of the twenty-third switch T23 is connected to the third node Q3, the source is connected to the clock signal terminal, and the drain is connected to the (j+1)th stage signal output terminal C(j+1). The gate of the twenty-fourth switch T24 is connected to the third node Q3, the source is connected to the clock signal terminal, and the drain is connected to the (j+2)th scan signal output terminal G(j+2). When the third node Q3 is at the first potential, the twenty-third switch T23 and the twenty-fourth switch T24 are turned on. The twenty-third switch T23 is used to receive the (i+2)th clock signal CLK(i+2) from the clock signal terminal, and uses the (i+2)th clock signal CLK(i+2) as the stage transmission signal and outputs it through the (j+1)th stage transmission signal output terminal C(j+1). The twenty-fourth switch T24 is used to receive the (i+2)th clock signal CLK(i+2) from the clock signal terminal, and uses the (i+2)th clock signal CLK(i+2) as the scan signal and outputs it through the (j+2)th scan signal output terminal G(j+2).

[0083] The fourth output module 152B includes a twenty-fifth switch transistor T25. The gate of the twenty-fifth switch transistor T25 is connected to the third node Q3, the source is connected to the clock signal terminal, and the drain is connected to the (j+3)th scan signal output terminal G(j+3). When the third node Q3 is at the first potential, the twenty-fifth switch transistor T25 is turned on to receive the (i+3)th clock signal CLK(i+3) from the clock signal terminal and output the (i+3)th clock signal CLK(i+3) as a scan signal through the (j+3)th scan signal output terminal G(j+3).

[0084] The first pull-down module 143A includes a 26th switch T26, a 27th switch T27, a 28th switch T28, and a 29th switch T29. The gate of the 26th switch T26 is connected to the fourth node Q4, the source is connected to the (j+1)th stage signal output terminal C(j+1), and the drain is connected to the first low-voltage terminal Vss1. The gate of the 27th switch T27 is connected to the fourth node Q4, the source is connected to the (j+2)th scan signal output terminal G(j+2), and the drain is connected to the second low-voltage terminal Vss2. When the fourth node Q4 is at the first potential, the 26th switch T26 and the 27th switch T27 are turned on, thereby controlling the (j+2)th scan signal output terminal G(j+2) and the (j+1)th stage signal output terminal C(j+1) to stop outputting signals.

[0085] The gate of the 28th switch T28 is connected to the fourth node Q4, the source is connected to the (j+2)th scan signal output terminal G(j+2), and the drain is connected to the second low-voltage terminal Vss2. The gate of the 29th switch T29 is connected to the fourth node Q4, the source is connected to the (j+1)th stage signal output terminal C(j+1), and the drain is connected to the second low-voltage terminal Vss2. When the fourth node Q4 is at the first potential, the 28th switch T28 and the 29th switch T29 are turned on to control the (j+2)th scan signal output terminal G(j+2) and the (j+1)th stage signal output terminal C(j+1) to stop outputting signals.

[0086] The second pull-down module 143B includes a thirtieth switch T30 and a thirty-first switch T31. The gate of the thirtieth switch T30 is connected to the second node Q2, the source is connected to the (j+3)th scan signal output terminal G(j+3), and the drain is connected to the second low-voltage terminal Vss2. It is turned on when the second node Q2 is at the first potential to control the (j+3)th scan signal output terminal G(j+3) to connect to the second low-voltage terminal Vss2, thereby controlling the (j+3)th scan signal output terminal G(j+3) to stop outputting a signal. The gate of the thirty-first switch T31 ​​is connected to the fourth node Q4, the source is connected to the (j+3)th scan signal output terminal G(j+3), and the drain is connected to the second low-voltage terminal Vss2. It is turned on when the fourth node Q4 is at the first potential to control the (j+3)th scan signal output terminal G(j+3) to connect to the second low-voltage terminal Vss2, thereby controlling the (j+3)th scan signal output terminal G(j+3) to stop outputting a signal.

[0087] The first sustaining module 144A includes a 32nd switch T32, a 33rd switch T33, a 34th switch T34, and a 35th switch T35. The source and gate of the 32nd switch T32 are connected to the power supply voltage terminal VDD, and its drain is connected to the 33rd switch T33 and the 34th switch T34. The gate of the 33rd switch T33 is connected to the drain of the 32nd switch T32, its source is connected to the power supply voltage terminal VDD, and its drain is connected to the fourth node Q4. The 32nd switch T32 and the 33rd switch T33 are turned on under the control of the power supply voltage terminal VDD to charge the fourth node Q4, thereby controlling the fourth node Q4 to maintain it at the first potential.

[0088] The gate of the 34th switch T34 is connected to the third node Q3, the source is connected to the drain of the 32nd switch T32, and the drain is connected to the first low-voltage terminal Vss1. It is used to turn on when the third node Q3 is at the first potential, and to control the drain of the 32nd switch T32 and the gate of the 33rd switch T33 to be connected to the first low-voltage terminal Vss1, thereby controlling the 33rd switch T33 to turn off, and thus controlling the power supply voltage terminal VDD to stop charging the fourth node Q4.

[0089] The gate of the 35th switch T35 is connected to the first node Q1, the source is connected to the drain of the 32nd switch T32, and the drain is connected to the first low-voltage terminal Vss1. It is used to turn on when the first node Q1 is at the first potential, and to control the drain of the 32nd switch T32 and the gate of the 33rd switch T33 to be connected to the first low-voltage terminal Vss1, thereby controlling the 33rd switch T33 to turn off, and thus controlling the power supply voltage terminal VDD to stop charging the fourth node Q4.

[0090] The second sustaining module 144B includes a 37th switch T37 and a 38th switch T38. The 37th switch T37 has its gate connected to the third node Q3, its source connected to the fourth node Q4, and its drain connected to the first low-voltage terminal Vss1. When the third node Q3 is at the first potential, it controls the fourth node Q4 to connect to the first low-voltage terminal Vss1, thereby pulling down the potential of the fourth node Q4 to the second potential. The 38th switch T38 has its gate connected to the (j-6)th stage signal output terminal C(j-6), its source connected to the fourth node Q4, and its drain connected to the first low-voltage terminal Vss1. Under the control of the (j-6)th stage signal output terminal C(j-6), it controls the fourth node Q4 to connect to the first low-voltage terminal Vss1, thereby pulling down the potential of the fourth node Q4 to the second potential.

[0091] The second pull-down control module 156 includes a 39th switch T39, a 40th switch T40, a 41st switch T41, and a 42nd switch T42. The gate of the 39th switch T39 is connected to a second reset signal R2, its source is connected to the third node Q3, and its drain is connected to the first low-voltage terminal Vss1. When the second reset signal R2 is received, the 39th switch T39 is turned on, controlling the third node Q3 to connect to the first low-voltage terminal Vss1, thereby pulling down the third node Q3 to the second potential. The gate of the 40th switch T40 is connected to the fourth node Q4, its source is connected to the third node Q3, and its drain is connected to the first low-voltage terminal Vss1. When the fourth node Q4 is at the first potential, the 40th switch T40 controls the third node Q3 to connect to the first low-voltage terminal Vss1, thereby pulling down the third node Q3 to the second potential. The gate of the forty-first switch T41 is connected to the signal output terminal C(j+10) of the (j+10)th stage, the source is connected to the third node Q3, and the drain is connected to the first low-voltage terminal Vss1. When a stage transmission signal is received from the signal output terminal C(j+10) of the (j+10)th stage, the forty-first switch T41 is turned on to control the third node Q3 to connect to the first low-voltage terminal Vss1, thereby pulling down the third node Q3 to the second potential. The gate of the forty-second switch T42 is connected to the fourth node Q4, the source is connected to the third node Q3, and the drain is connected to the first low-voltage terminal Vss1. When the fourth node Q4 is at the first potential, the forty-second switch T42 is turned on to control the third node Q3 to connect to the first low-voltage terminal Vss1, thereby pulling down the potential of the third node Q3 to the second potential.

[0092] Please see Figure 6 , Figure 6 for Figure 5 A schematic diagram of the voltage waveform changes at the mid-node.

[0093] like Figure 6 As shown, when the first signal output subunit GDL1 controls the output of the scan signal, the voltage of the second node Q2 will form a stepped voltage, that is, the second node Q2 does not completely drop to the low potential, i.e., the second potential. As a result, the j-th scan signal output terminal G(j) and the (j+1)-th scan signal output terminal G(j+1) are not at a low potential under the control of the second node Q2, which in turn affects the waveform of the scan signal output by the j-th scan signal output terminal G(j) and the (j+1)-th scan signal output terminal G(j+1), as well as the waveform of the stage transmission signal output by the j-th stage transmission signal output terminal C(j).

[0094] Based on this, the second embodiment of this application provides a scan driving unit to solve the problem of the stepped voltage of the second node Q2 mentioned above.

[0095] Please see Figure 7 , Figure 7 A second embodiment of this application provides, such as Figure 4 A schematic diagram of the equivalent circuit of the scanning drive unit.

[0096] like Figure 7 As shown, the scan drive unit GOA includes a first signal output subunit GDL1 and a second signal output subunit GDL2. The first signal output subunit GDL1 is used to output two scan signals and one stage transmission signal, and the second signal output subunit GDL2 is used to output two scan signals and one stage transmission signal.

[0097] The difference between this embodiment and the first embodiment is that a first auxiliary pull-down module 145 is provided in the first signal output subunit GDL1 and a second auxiliary pull-down module 155 is provided in the second signal output subunit GDL2.

[0098] The first sustaining module 144A is connected to the first node Q1 and the second node Q2. The first sustaining module 144A is used to charge the second node Q2 to control the second node Q2 to maintain it at a first potential. The second sustaining module 144B is connected to the first node Q1, the second node Q2, and the stage transmission signal output terminal of the Jb scan driving unit. The first auxiliary pull-down module 145 is connected to the first sustaining module 144A and the stage transmission signal output terminal of the Jb scan driving unit. When the stage transmission signal output terminal of the Jb scan driving unit outputs a stage transmission signal and / or the first node Q1 is at the first potential, the first auxiliary pull-down module 145 controls the first sustaining module 144A to stop charging the second node Q2. At the same time, the second sustaining module 144B pulls the second node Q2 down to the second potential to control the second node Q2 to drop to the second potential within a preset time, that is, to accelerate the pull-down speed of the second node Q2, thereby eliminating the step voltage of the second node Q2. Here, 1≤b<n, and b is an integer.

[0099] In an exemplary embodiment, b can be set according to specific needs. For example, b can be set to 2, in which case the first auxiliary pull-down module 145 and the second maintenance module 144B are connected to the cascade signal output terminal of the J-2 scan drive unit. The cascade signal output terminal of the J-2 scan drive unit can be the j-6th cascade signal output terminal C(j-6). Of course, b can also be set to other values ​​according to specific needs, that is, to control other scan drive units to be cascaded with the J scan drive unit.

[0100] In the second signal output subunit GDL2, the third sustaining module 154A is connected to the third node Q3 and the fourth node Q4. The third sustaining module 154A is used to charge the fourth node Q4 to control the fourth node Q4 to maintain the fourth node Q4 at the first potential. The fourth sustaining module 154B is connected to the third node Q3, the fourth node Q4 and the stage transmission signal output terminal of the Jb scan driving unit. The second auxiliary pull-down module 155 is connected to the stage transmission signal output terminal of the Jb scan driving unit and the third sustaining module 154A. When the third node Q3 is at the first potential and / or the stage transmission signal output terminal of the Jb scan driving unit outputs a stage transmission signal, the first auxiliary pull-down module 145 controls the third sustaining module 154A to stop charging the fourth node Q4, and at the same time the fourth sustaining module 154B pulls the fourth node Q4 down to the second potential.

[0101] Specifically, the first sustaining module 144A includes an eleventh switch T11, a twelfth switch T12, a thirteenth switch T13, and a fourteenth switch T14, and the first auxiliary pull-down module 145 includes a fifteenth switch T15. The source and gate of the eleventh switch T11 are connected to the power supply voltage terminal VDD, and its drain is connected to the twelfth switch T12 and the thirteenth switch T13. The gate of the twelfth switch T12 is connected to the drain of the eleventh switch T11, its source is connected to the power supply voltage terminal VDD, and its drain is connected to the second node Q2. The eleventh switch T11 and the twelfth switch T12 are turned on under the control of the power supply voltage terminal VDD to charge the second node Q2, thereby controlling the second node Q2 to maintain at the first potential.

[0102] The gate of the thirteenth switch T13 is connected to the first node Q1, its source is connected to the drain of the eleventh switch T11 and the gate of the twelfth switch T12, and its drain is connected to the first low-voltage terminal Vss1. It is used to turn on when the first node Q1 is at the first potential, and to control the drain of the eleventh switch T11 and the gate of the twelfth switch T12 to be connected to the first low-voltage terminal Vss1, thereby controlling the twelfth switch T12 to turn off, and thus controlling the power supply voltage terminal VDD to stop charging the second node Q2.

[0103] The gate of the fourteenth switch T14 is connected to the third node Q3, the source is connected to the drain of the eleventh switch T11, and the drain is connected to the first low-voltage terminal Vss1. It is used to turn on when the third node Q3 is at the first potential, and to control the drain of the eleventh switch T11 and the gate of the twelfth switch T12 to be connected to the first low-voltage terminal Vss1, thereby controlling the twelfth switch T12 to turn off, and thus controlling the power supply voltage terminal VDD to stop charging the second node Q2.

[0104] The gate of the fifteenth switch T15 is connected to the signal output terminal C(j-6) of the (j-6)th stage, its source is connected to the drain of the eleventh switch T11 and the gate of the twelfth switch T12, and its drain is connected to the first low-voltage terminal Vss1. When the fifteenth switch T15 receives the stage transmission signal output from the signal output terminal C(j-6) of the (j-6)th stage, the fifteenth switch T15 is turned on, thereby controlling the drain of the eleventh switch T11 to be connected to the first low-voltage terminal Vss through the fifteenth switch T15, thus controlling the voltage output by the eleventh switch T11 to be transmitted to... The first low-voltage terminal Vss1 controls the power supply voltage terminal VDD to stop charging the second node Q2. At the same time, in conjunction with the seventeenth switch T17 in the second sustaining module 144B, the voltage of the second node Q2 is pulled down, so that the second node Q2 drops to the second potential within a preset time, thereby eliminating the step voltage of the second node Q2, thus eliminating the influence on the scan signals output by the j-th scan signal output terminal G(j) and the j+1-th scan signal output terminal G(j+1), as well as the influence on the stage transmission signal output by the j-th stage transmission signal output terminal C(j).

[0105] The second auxiliary pull-down module 155 includes a thirty-sixth switch T36. The gate of the thirty-sixth switch T36 is connected to the j-6th stage signal output terminal C(j-6), the source is connected to the gate of the thirty-third switch T33, and the drain is connected to the first low-voltage terminal Vss1. When the thirty-sixth switch T36 receives the stage transmission signal output from the j-6th stage signal output terminal C(j-6), the thirty-sixth switch T36 is turned on to control the voltage output by the thirty-second switch T32 to be transmitted to the first low-voltage terminal Vss1, thereby controlling the power supply voltage terminal VDD to stop charging the fourth node Q4. At the same time, in conjunction with the thirty-eighth switch T38 in the fourth sustaining module 154B, the voltage of the fourth node Q4 is pulled down, so that the fourth node Q4 drops to the second potential within a preset time.

[0106] Please see Figure 8 , Figure 8 for Figure 7 A schematic diagram of the voltage waveform at the midpoint.

[0107] like Figure 8 As shown, in the first signal output subunit GDL1, by setting the first auxiliary pull-down module 145, the first auxiliary pull-down module 145 and the second sustaining module 144B cooperate to pull down the potential of the second node Q2, thereby effectively eliminating the step voltage phenomenon of the second node Q2, and thus eliminating the influence on the scan signals output by the j-th scan signal output terminal G(j) and the (j+1)-th scan signal output terminal G(j+1), as well as the influence on the stage transmission signal output by the j-th stage transmission signal output terminal C(j).

[0108] However, through simulation experiments of the scanning drive unit in this embodiment at -20℃, it was found that the minimum driving voltage of each switch is relatively high, about 35V. There is a voltage drop for a period of time during the rise of the first node Q1 to the first potential, which reduces the driving capability of the scanning drive unit. In addition, there is a significant voltage drop in the scanning signal output terminal G(j+1) of the j+1th scanning signal output terminal, which is significantly different from the scanning signal output terminal G(j) of the jth scanning signal output terminal, which can easily cause uneven brightness between the two rows of pixels.

[0109] Based on this, this application provides a third embodiment to solve the above problems.

[0110] Please see Figure 9 , Figure 9 A third embodiment of this application provides a method such as Figure 4 A schematic diagram of the equivalent circuit of the scanning drive unit.

[0111] The scan drive unit GOA includes a first signal output subunit GDL1 and a second signal output subunit GDL2. The first signal output subunit GDL1 is used to output two scan signals and at least one stage transmission signal, and the second signal output subunit GDL2 is used to output two scan signals and at least one stage transmission signal.

[0112] The first signal output subunit GDL1 includes a first pull-up module 141, a first output module 142A, a second output module 142B, and a first node Q1. The first pull-up module 141 is connected to the first node Q1 and the (j-4)th stage signal output terminal C(j-4), and is used to pull up the first node Q1 to the first potential under the control of the stage signal output from the (j-4)th stage signal output terminal C(j-4). The (j-4)th stage signal output terminal C(j-4) is located in the (j-1)th scan drive unit.

[0113] The first output module 142A is connected to the first node Q1, the clock signal terminal (unidentified), and the j-th scan signal output terminal G(j). The second output module 142B is connected to the first node Q1, the clock signal terminal (unidentified), the j+1-th stage transmission signal output terminal C(j+1), and the j+1-th scan signal output terminal G(j+1). When the first node Q1 is at the first potential, the first output module 142A is used to receive the i-th clock signal CLK(i) from the clock signal terminal under the control of the first node Q1 and output the scan signal through the j-th scan signal output terminal G(j) according to the i-th clock signal CLK(i). The second output module 142B is used to receive the i+1-th clock signal CLK(i+1) from the clock signal terminal under the control of the first node Q1 and output the scan signal through the j+1-th scan signal output terminal G(j+1) according to the i+1-th clock signal CLK(i+1), and output the stage transmission signal through the j+1-th stage transmission signal output terminal C(j+1).

[0114] The first signal output subunit GDL1 also includes a first pull-down module 143A and a second pull-down module 143B. The first pull-down module 143A is connected to the second node Q2 and the output terminal G(j) of the j-th scan signal. When the second node Q2 is at the first potential, the first pull-down module 143A pulls down the potential of the output terminal G(j) of the j-th scan signal to the second potential to control the j-th scan signal to stop outputting.

[0115] The second pull-down module 143B is connected to the second node Q2, the j-th stage signal output terminal C(j), and the (j+1)-th scan signal output terminal G(j+1). When the second node is at the first potential, the second pull-down module 143B pulls down the potential of the (j+1)-th scan signal output terminal G(j+1) to the second potential to control the scan signal to stop outputting. At the same time, it pulls down the potential of the (j+1)-th stage signal output terminal C(j+1) to the second potential to control the scan signal to stop outputting.

[0116] The first signal output subunit GDL1 further includes a first sustaining module 144A, a second sustaining module 144B, and a first auxiliary pull-down module 145. The first sustaining module 144A is connected to the first node Q1 and the second node Q2. The first sustaining module 144A is used to charge the second node Q2 to control the second node Q2 to maintain the first potential.

[0117] The second sustaining module 144B is connected to the first node Q1, the second node Q2, and the cascade signal output terminal of the Jb scan driving unit. The first auxiliary pull-down module 145 is connected to the first sustaining module 144A and the cascade signal output terminal of the Jb scan driving unit. When the cascade signal output terminal of the Jb scan driving unit outputs a cascade signal and / or the first node Q1 is at the first potential, the first auxiliary pull-down module 145 controls the first sustaining module 144A to stop charging the second node Q2. At the same time, the second sustaining module 144B pulls down the second node Q2 to the second potential to control the second node Q2 to drop to the second potential within a preset time, that is, to accelerate the pull-down speed of the second node Q2, thereby eliminating the step voltage of the second node Q2. Here, 1≤b<n, and b is an integer.

[0118] The first signal output subunit GDL1 also includes a first pull-down control module 146 connected to the first node Q1, the second node Q2, the output terminal C(j+8) of the (j+8)th stage signal transmission, and a first reset signal R1. The first pull-down control module 146 pulls down the potential of the first node Q1 to a second potential when it receives the (j+8)th stage signal transmission. It also pulls down the first node Q1 to the second potential when it receives the first reset signal R1, and pulls down the first node Q1 to the second potential when the second node Q2 is at the first potential.

[0119] The second signal output subunit GDL2 includes a second pull-up module 151, a third output module 152A, a fourth output module 152B, and a third node Q3. The second pull-up module 151 is connected to the third node Q3 and the (j-2)th stage signal output terminal C(j-2), and is used to pull up the third node Q3 to the first potential under the control of the stage signal output from the (j-2)th stage signal output terminal C(j-2).

[0120] The third output module 152A is connected to the third node Q3, the clock signal terminal (unidentified), and the (j+2)th scan signal output terminal G(j+2). The fourth output module 152B is connected to the third node Q3, the clock signal terminal (unidentified), the (j+3)th stage transmission signal output terminal C(j+3), and the (j+3)th scan signal output terminal G(j+3). When the first node Q1 is at the first potential, the third output module 152A is used to receive the (i+2)th clock signal CLK(i+2) from the clock signal terminal under the control of the first node Q1 and output the scan signal through the (j+2)th scan signal output terminal G(j+2) according to the (i+2)th clock signal CLK(i+2). The fourth output module 152B is used to receive the (i+3)th clock signal CLK(i+3) from the clock signal terminal under the control of the third node Q3 and output the scan signal through the (j+3)th scan signal output terminal G(j+3) according to the (i+3)th clock signal CLK(i+3), and output the stage transmission signal through the (j+3)th stage transmission signal output terminal C(j+3).

[0121] The second signal output subunit GDL2 also includes a third pull-down module 153A and a fourth pull-down module 153B. The third pull-down module 153A is connected to the fourth node Q4 and the (j+2)th scan signal output terminal G(j+2). When the fourth node Q4 is at the first potential, the third pull-down module 153A pulls down the potential of the (j+2)th scan signal output terminal G(j+2) to the second potential to control the (j+2)th scan signal output terminal G(j+2) to stop outputting the scan signal.

[0122] The fourth pull-down module 153B is connected to the fourth node Q4, the (j+3)th scan signal output terminal G(j+3), and the (j+3)th stage signal transmission output terminal C(j+3). When the fourth node Q4 is at the first potential, the fourth pull-down module 153B pulls down the potential of the (j+3)th scan signal output terminal G(j+3) to the second potential to control the (j+3)th scan signal to stop outputting. At the same time, it pulls down the potential of the (j+3)th stage signal transmission output terminal C(j+3) to the second potential to control the (j+3)th stage signal transmission output terminal C(j+3) to stop outputting stage signal transmission.

[0123] The second signal output subunit GDL2 also includes a third sustaining module 154A, a fourth sustaining module 154B, and a second auxiliary pull-down module 155. The third sustaining module 154A is connected to the third node Q3 and the fourth node Q4, and is used to charge the fourth node Q4 to maintain it at a first potential. The fourth sustaining module 154B is connected to the third node Q3, the fourth node Q4, and the stage transmission signal output terminal of the Jb scan drive unit. The second auxiliary pull-down module 155 is connected to the stage transmission signal output terminal of the Jb scan drive unit and the third sustaining module 154A. When the third node Q3 is at the first potential and / or the stage transmission signal output terminal of the Jb scan drive unit outputs a stage transmission signal, the first auxiliary pull-down module 154B controls the third sustaining module 154A to stop charging the fourth node Q4, and simultaneously the fourth sustaining module 154B pulls the fourth node Q4 down to the second potential.

[0124] The second signal output subunit GDL2 also includes a second pull-down control module 156. The second pull-down control module 156 is connected to the third node Q3, the fourth node Q4, the output terminal C(j+10) of the (j+10)th level signal transmission, and the second reset signal R2. When the second pull-down control module 156 receives the (j+10)th level signal transmission, it pulls down the potential of the third node Q3 to the second potential. It also pulls down the third node Q3 to the second potential when it receives the second reset signal R2, and pulls down the third node Q3 to the second potential when the fourth node Q4 is at the first potential.

[0125] The first sustaining module 144A is also connected to the third node Q3. When the third node Q3 is at the first potential, the first sustaining module 144A stops charging the second node Q2 and is used to pull down the potential of the second node Q2. The third sustaining module 154A is also connected to the first node Q1. When the first node Q1 is at the first potential, the third sustaining module 154A stops charging the fourth node Q4 and is used to pull down the potential of the fourth node Q4.

[0126] The first pull-down module 143A is also connected to the fourth node Q4, and is used to turn on when the fourth node Q4 is at the first potential, so as to control the j-th stage signal output terminal C(j) and the j-th scan signal output terminal G(j) to stop outputting signals or output low-level signals.

[0127] The third pull-down module 153A is also connected to the second node Q2, and is used to turn on when the second node Q2 is at the first potential, so as to control the output terminal C(j+1) of the j+1 stage signal transmission and the output terminal G(j+2) of the j+2 stage scan signal to stop outputting signals or output low-level signals.

[0128] The difference between this embodiment and the second embodiment is that the first output module 142A, the second output module 142B, the first pull-down module 143A and the second pull-down module 143B in the first signal output subunit GDL1, and the third output module 152A, the fourth output module 152B, the third pull-down module 153A and the fourth pull-down module 153B in the second signal output subunit GDL2 are configured differently.

[0129] The first output module 142A includes a second switch T2. The gate of the second switch T2 is connected to the first node Q1, the source is connected to the clock signal terminal, and the drain is connected to the j-th scan signal output terminal G(j). When the first node Q1 is at the first potential, the second switch T2 is turned on. The second switch T2 is used to receive the i-th clock signal CLK(i) from the clock signal terminal and output the i-th clock signal CLK(i) as a scan signal through the j-th scan signal output terminal G(j).

[0130] The second output module 142B includes a third switch T3 and a fourth switch T4. The gate of the third switch T3 is connected to the first node Q1, the source is connected to the clock signal terminal, and the drain is connected to the (j+1)th stage signal output terminal C(j+1). The gate of the fourth switch T4 is connected to the first node Q1, the source is connected to the clock signal terminal, and the drain is connected to the (j+1)th stage scan signal output terminal G(j+1). When the first node Q1 is at the first potential, the third switch T3 and the fourth switch T4 are turned on. The third switch T3 is used to receive the (i+1)th clock signal CLK(i+1) from the clock signal terminal and output the (i+1)th clock signal CLK(i+1) as a stage signal through the (j+1)th stage signal output terminal C(j+1). The fourth switch T4 is used to receive the (i+1)th clock signal CLK(i+1) from the clock signal terminal and output the (i+1)th clock signal CLK(i+1) as a scan signal through the (j+1)th stage signal output terminal G(j+1).

[0131] The first pull-down module 143A includes a fifth switch T5 and a sixth switch T6. The gate of the fifth switch T5 is connected to the second node Q2, the source is connected to the j-th scan signal output terminal G(j), and the drain is connected to the second low-voltage terminal Vss2. When the second node Q2 is at the first potential, the fifth switch T5 is turned on to control the j-th scan signal output terminal G(j) to be connected to the second low-voltage terminal Vss2, thereby controlling the j-th scan signal output terminal G(j) to stop outputting a signal. The gate of the sixth switch T6 is connected to the fourth node Q4, the source is connected to the j-th scan signal output terminal G(j), and the drain is connected to the second low-voltage terminal Vss2. When the fourth node Q4 is at the first potential, the sixth switch T6 is turned on to control the j-th scan signal output terminal G(j) to be connected to the second low-voltage terminal Vss2, thereby controlling the j-th scan signal output terminal G(j) to stop outputting a signal.

[0132] The second pull-down module 143B includes a seventh switch T7, an eighth switch T8, a ninth switch T9, and a tenth switch T10. The gate of the seventh switch T7 is connected to the fourth node Q4, the source is connected to the (j+1)th stage signal output terminal C(j+1), and the drain is connected to the second low-voltage terminal Vss2. The gate of the eighth switch T8 is connected to the fourth node Q4, the source is connected to the j-th scan signal output terminal G(j), and the drain is connected to the second low-voltage terminal Vss2. When the fourth node... When Q4 is at the first potential, the seventh switch T7 and the eighth switch T8 are turned on to control the signal output terminal C(j+1) of the (j+1)th stage to be connected to the second low-voltage terminal Vss2 via the seventh switch T7, thereby controlling the potential of the signal output terminal G(j) of the (j+1)th stage to drop to the second potential. The signal output terminal C(j+1) of the (j+1)th stage is connected to the second low-voltage terminal Vss2 via the eighth switch T8 to control the potential of the scan signal output terminal C(j+1) of the (j+1)th stage to drop to the second potential.

[0133] The gate of the ninth switch T9 is connected to the second node Q2, the source is connected to the (j+1)th scan signal output terminal G(j+1), and the drain is connected to the second low-voltage terminal Vss2. The gate of the tenth switch T10 is connected to the second node Q2, the source is connected to the (j+1)th stage signal output terminal C(j+1), and the drain is connected to the second low-voltage terminal Vss2. When the second node Q2 is at the first potential, the ninth switch T9 and the tenth switch T10 are turned on to control the potential of the (j+1)th stage signal output terminal C(j+1) to drop to the second potential, and the potential of the (j+1)th scan signal output terminal G(j+1) to drop to the second potential.

[0134] The third output module 152A includes a twenty-third switch T23. The gate of the twenty-third switch T23 is connected to the third node Q3, the source is connected to the clock signal terminal, and the drain is connected to the (j+2)th scan signal output terminal G(j+2). When the third node Q3 is at the first potential, the twenty-third switch T23 is turned on to receive the (i+2)th clock signal CLK(i+2) from the clock signal terminal and output the (i+2)th clock signal CLK(i+2) as a scan signal through the (j+2)th scan signal output terminal G(j+2).

[0135] The fourth output module 152B includes a twenty-fourth switch T24 and a twenty-fifth switch T25. The gate of the twenty-fourth switch T24 is connected to the third node Q3, the source is connected to the clock signal terminal, and the drain is connected to the (j+3)th stage signal output terminal C(j+3). It is used to receive the (i+2)th clock signal CLK(i+2) from the clock signal terminal and output the (i+2)th clock signal CLK(i+2) as the stage signal through the (j+3)th stage signal output terminal C(j+3). The gate of the twenty-fifth switch T25 is connected to the third node Q3, the source is connected to the clock signal terminal, and the drain is connected to the (j+3)th scan signal output terminal G(j+3). When the third node Q3 is at the first potential, the twenty-fifth switch T25 is turned on. It is used to receive the (i+3)th clock signal CLK(i+3) from the clock signal terminal and output the (i+3)th clock signal CLK(i+3) as the scan signal through the (j+3)th scan signal output terminal G(j+3).

[0136] The fourth pull-down module 153B includes a 28th switch T28, a 29th switch T29, a 30th switch T30, and a 31st switch T31. The gate of the 28th switch T28 is connected to the fourth node Q4, the source is connected to the (j+1)th stage signal output terminal C(j+1), and the drain is connected to the second low-voltage terminal Vss2. The gate of the 29th switch T29 is connected to the fourth node Q4, the source is connected to the (j+3)th scan signal output terminal G(j+3), and the drain is connected to the second low-voltage terminal Vss2. When the fourth node Q4 is at the first potential, the 28th switch T28 and the 29th switch T29 are turned on to control the (j+3)th stage signal output terminal C(j+3) to stop outputting the stage signal and the (j+3)th scan signal output terminal G(j+3) to stop outputting the scan signal. The gate of the 30th switch T30 is connected to the second node Q2, the source is connected to the (j+3)th stage signal output terminal C(j+3), and the drain is connected to the second low-voltage terminal Vss2. The gate of the 31st switch T31 ​​is connected to the second node Q2, the source is connected to the (j+3)th stage scan signal output terminal G(j+3), and the drain is connected to the second low-voltage terminal Vss2. When the second node Q2 is at the first potential, the 30th switch T30 and the 31st switch T31 ​​are turned on to control the (j+3)th stage signal output terminal C(j+3) to stop outputting stage signal and the (j+3)th stage scan signal output terminal G(j+3) to stop outputting scan signal.

[0137] Please see Figure 10 , Figure 10 for Figure 9 Schematic diagram of voltage waveform at the mid-node.

[0138] like Figure 10As shown, by eliminating the intermediate signal output terminal in the first output module 142A and simultaneously setting the intermediate signal output terminal in the second output module 142B, the coupling effect between the intermediate signal and the scan signal output in the first output module 142A is eliminated. Simulation results show that the voltage drop during the rise of the first node Q1 is eliminated, improving the driving capability of the scan drive unit GOA. Simultaneously, the voltage drop of the scan signal output at the (j+1)th scan signal output terminal G(j+1) is eliminated, resulting in no significant difference in the waveforms of the scan signals output at the j-th scan signal output terminal G(j) and the (j+1)-th scan signal output terminal G(j+1), thus solving the problem of uneven brightness between the two rows of pixels. Furthermore, simulation results at a low temperature of approximately -20℃ show that the minimum driving voltage of each switch is approximately 30V, a significant decrease compared to the second embodiment, thereby reducing power consumption.

[0139] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A scanning drive circuit, comprising n cascaded scanning drive units, where n is an integer greater than or equal to 1, each of the scanning drive units being used to output four scanning signals to control pixel units to display an image; Its features are, In the Jth scan driving unit, the scan driving unit includes a first signal output subunit, which is used to output two scan signals and at least one stage transmission signal. The stage transmission signal is used as a start signal to be transmitted to the cascaded J+ath scan driving unit to drive the J+ath scan driving unit to output the scan signals and the stage transmission signal, wherein 1≤a<n, 1≤J<n, and a and J are integers; The first signal output subunit further includes a first sustaining module, a second sustaining module, a first auxiliary pull-down module, a first node, and a second node. The first sustaining module is connected to the first node and the second node and is used to charge the second node to control the second node to maintain it at a first potential. The second sustaining module is connected to the first node, the second node, and the cascade signal output terminal of the Jb scan driving unit. The first auxiliary pull-down module is connected to the cascade signal output terminal of the Jb scan driving unit and the first sustaining module. When the cascade signal output terminal of the Jb scan driving unit outputs the cascade signal and / or the first node is at the first potential, the first auxiliary pull-down module controls the first sustaining module to stop charging the second node, and simultaneously the second sustaining module pulls the second node down to a second potential, which is less than the first potential. When the first node is at the first potential, the first signal output subunit outputs the scan signal and the cascade signal, where 1 ≤ b < n, and b is an integer. The scanning drive circuit further includes a second signal output subunit, which is used to output two scanning signals and at least one stage transmission signal. The second signal output subunit includes a third node and a fourth node. The third node is connected to the gate of the sixth switch in the first signal output subunit. When the third node is at the first potential, it controls the sixth switch to be turned on. The j-th scan signal output terminal of the first signal output subunit is connected to the low voltage terminal through the sixth switch to control the potential of the j-th scan signal output terminal to drop to the second potential, where j = 4J-3 and j is an integer. The second signal output subunit further includes a third sustaining module, a fourth sustaining module, and a second auxiliary pull-down module. The third sustaining module is connected to the third node and the fourth node and is used to charge the fourth node to control the fourth node to maintain it at a first potential. The fourth sustaining module is connected to the third node, the fourth node, and the stage transmission signal output terminal of the Jb scan driving unit. The second auxiliary pull-down module is connected to the stage transmission signal output terminal of the Jb scan driving unit and the third sustaining module. When the stage transmission signal output terminal of the Jb scan driving unit outputs the stage transmission signal and / or the third node is at the first potential, the second auxiliary pull-down module controls the third sustaining module to stop charging the fourth node, and at the same time, the fourth sustaining module pulls the fourth node down to a second potential. When the third node is at the first potential, the second signal output subunit outputs the scan signal and the stage transmission signal.

2. The scanning drive circuit as described in claim 1, characterized in that, The first signal output subunit includes the j-th scan signal output terminal, the (j+1)-th scan signal output terminal, and the (j+1)-th stage transmission signal output terminal, for outputting the scan signal through the j-th scan signal output terminal and the (j+1)-th scan signal output terminal respectively, and outputting the stage transmission signal through the (j+1)-th stage transmission signal output terminal. The first signal output subunit further includes a first output module and a second output module. The first output module is connected to the first node and the j-th scan signal output terminal. The second output module is connected to the first node, the (j+1)-th scan signal output terminal, and the (j+1)-th stage transmission signal output terminal. When the voltage of the first node is a first potential, the first output module outputs the scan signal through the j-th scan signal output terminal, and the second output module outputs the scan signal through the (j+1)-th scan signal output terminal and the stage transmission signal through the (j+1)-th stage transmission signal output terminal.

3. The scanning drive circuit as described in claim 2, characterized in that, The first signal output subunit further includes a first pull-up module, a first pull-down module, and a second pull-down module. The first pull-up module is connected to the j-4th stage signal output terminal and the first node, and is used to pull up the first node to the first potential when the j-4th stage signal output terminal outputs the stage signal. The j-4th stage signal output terminal is located in the J-1th scan drive unit. The first pull-down module is connected to the second node and the j-th scan signal output terminal, and the second pull-down module is connected to the second node, the (j+1)-th scan signal output terminal and the (j+1)-th stage transmission signal output terminal; When the second node is at the first potential, the first pull-down module pulls down the j-th scan signal output terminal to the second potential to control the j-th scan signal output terminal to stop outputting the scan signal. The second pull-down module pulls down the (j+1)-th scan signal output terminal and the (j+1)-th stage transmission signal output terminal to the second potential to control the (j+1)-th scan signal output terminal to stop outputting the scan signal and the (j+1)-th stage transmission signal output terminal to stop outputting the stage transmission signal. The second potential is less than the first potential.

4. The scanning drive circuit as described in claim 3, characterized in that, The pull-up module includes a first switch transistor, the first output module includes a second switch transistor, and the second output module includes a third switch transistor and a fourth switch transistor. The gate and source of the first switch are connected to the output terminal of the (j-4)th stage signal transmission, and the drain of the first switch is connected to the first node. It is used to turn on under the control of the stage transmission signal output at the (j-4)th stage signal transmission output terminal, and to pull up the first node to the first potential according to the stage transmission signal. The gate of the second switch is connected to the first node, the source of the second switch is connected to the clock signal terminal, and the drain of the second switch is connected to the j-th scan signal output terminal. It is used to turn on when the first node is at the first potential, receive the i-th clock signal from the clock signal terminal, and output the i-th clock signal as the scan signal through the j-th scan signal output terminal, where i is an integer greater than or equal to 1. The gate of the third switch is connected to the clock signal terminal, the source of the third switch is connected to the clock signal terminal, and the drain of the third switch is connected to the (j+1)th stage signal output terminal. It is used to turn on when the first node is at the first potential, receive the (i+1)th clock signal from the clock signal terminal, and output the (i+1)th clock signal as the stage signal through the (j+1)th stage signal output terminal. The gate of the fourth switch is connected to the clock signal terminal, the source of the fourth switch is connected to the clock signal terminal, and the drain of the fourth switch is connected to the (j+1)th scan signal output terminal. It is used to turn on when the first node is at the first potential, receive the (i+1)th clock signal from the clock signal terminal, and output the (i+1)th clock signal as the scan signal through the (j+1)th scan signal output terminal.

5. The scanning drive circuit as described in claim 4, characterized in that, The first pull-down module includes a fifth switch and a sixth switch. The scan drive circuit further includes a second signal output subunit. The second signal output subunit is used to output two scan signals and at least one stage transmission signal. The second signal output subunit includes a third node. The gate of the fifth switch is connected to the second node, the source of the fifth switch is connected to the j-th scan signal output terminal, and the drain of the fifth switch is connected to a low-voltage terminal. It is used to turn on when the second node is at the first potential. The j-th scan signal output terminal is connected to the low-voltage terminal through the fifth switch to control the potential of the j-th scan signal output terminal to drop to the second potential. The gate of the sixth switch is connected to the third node, the source of the sixth switch is connected to the j-th scan signal output terminal, and the drain of the sixth switch is connected to the low-voltage terminal.

6. The scanning drive circuit as described in claim 5, characterized in that, The second pull-down module includes a seventh switch, an eighth switch, a ninth switch, and a tenth switch. The gate of the seventh switch is connected to the fourth node, the source of the seventh switch is connected to the (j+1)th stage signal output terminal, and the drain of the seventh switch is connected to the low-voltage terminal. The gate of the eighth switch is connected to the fourth node, the source of the eighth switch is connected to the (j+1)th scan signal output terminal, and the drain of the eighth switch is connected to the low-voltage terminal. When the fourth node is at the first potential, the seventh switch and the eighth switch are turned on, the potential of the (j+1)th scan signal output terminal drops to the second potential, and the potential of the (j+1)th stage signal output terminal drops to the second potential.

7. The scanning drive circuit as described in claim 6, characterized in that, The first maintenance module includes an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch, and the first auxiliary pull-down module includes a fifteenth switch; The source and gate of the eleventh switch are connected to the power supply voltage terminal, the drain of the eleventh switch is connected to the twelfth and thirteenth switches, the gate of the twelfth switch is connected to the drain of the eleventh switch, the source of the twelfth switch is connected to the power supply voltage terminal, and the drain of the twelfth switch is connected to the second node. The eleventh and twelfth switches are turned on under the control of the power supply voltage terminal to charge the second node, thereby controlling the second node to maintain at the first potential. The gate of the thirteenth switch is connected to the first node, the source of the thirteenth switch is connected to the gate of the twelfth switch, and the drain of the thirteenth switch is connected to the low-voltage terminal. When the first node is reached, the thirteenth switch is turned on to control the twelfth switch to stop charging the second node. The gate of the fourteenth switch is connected to the third node, the source of the fourteenth switch is connected to the gate of the twelfth switch, and the drain of the twelfth switch is connected to the low-voltage terminal. When the third node is at the first potential, the fourteenth switch is turned on to control the twelfth switch to stop charging the second node. The gate of the fifteenth switch is connected to the stage transmission signal output terminal in the Jb scan drive unit, the source of the fifteenth switch is connected to the gate of the twelfth switch, and the drain of the fifteenth switch is connected to the low voltage terminal. When the fifteenth switch receives the stage transmission signal from the stage transmission signal output terminal in the Jb scan drive unit, it turns on to control the twelfth switch to stop charging the second node.

8. The scanning drive circuit as described in claim 6, characterized in that, The second signal output subunit further includes a second pull-up unit, a third output module, a fourth output module, a third pull-down module, a fourth pull-down module, a j+2 scan signal output terminal, a j+3 scan signal output terminal, and a j+3 level transmission signal output terminal. The second pull-up unit is connected to the j-2 level transmission signal output terminal and the third node, and is used to pull up the third node to the first potential when the j-2 level transmission signal output terminal outputs the level transmission signal. The third output module is connected to the third node and the (j+2)th scan signal output terminal, and the fourth output module is connected to the third node, the (j+3)th scan signal output terminal, and the (j+3)th stage transmission signal output terminal. When the third node is at the first potential, the first output module outputs the scan signal through the (j+2)th scan signal output terminal, and the fourth output module outputs the scan signal through the (j+3)th scan signal output terminal and outputs the stage transmission signal through the (j+3)th stage transmission signal output terminal. The third pull-down module is connected to the third node and the (j+2)th scan signal output terminal. When the fourth node is at the first potential, the third pull-down module pulls down the potential of the (j+2)th scan signal output terminal to the second potential. The fourth pull-down module is connected to the fourth node, the (j+3)th scan signal output terminal, and the (j+3)th stage signal output terminal. When the fourth node is at the first potential, the fourth pull-down module pulls down the potential of the (j+3)th scan signal output terminal to the second potential and pulls down the potential of the (j+3)th stage signal output terminal to the second potential.

9. A display panel, characterized in that, The device includes multiple pixel units arranged in a matrix in the display area, a data driving circuit in the non-display area, a timing control circuit, and a scan driving circuit as described in any one of claims 1-8. The scan driving circuit outputs a gate output control signal according to the timing control circuit, and the data driving circuit outputs a source output control signal according to the timing control circuit to jointly drive the pixel units to display an image.

Images