A method for improving gate topography
By forming a protective layer at the junction of the dummy gate and the fin sidewall and performing rapid oxidation, the problem of increased gate size was solved, the gate morphology was improved, short circuits and parasitic capacitance were avoided, and device yield and mass production capability were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
- Filing Date
- 2022-09-20
- Publication Date
- 2026-06-26
Smart Images
Figure CN117790291B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, and more particularly to a method for improving gate morphology. Background Technology
[0002] With advancements in manufacturing processes, the linewidth and spacing of Logic FinFETs have been continuously reduced, but this has also led to the problem of enlarged topography at the junction of the gate and the fin.
[0003] Please see Figures 1-4 An existing gate formation method may include the following steps:
[0004] (1) A fin 13 is formed on the substrate 10; an amorphous silicon (a-Si) dummy gate 11 is formed across the fin 13. Due to limitations of current process technology, at the junction of the dummy gate 11 and the sidewall of the fin 13, there may be residual amorphous silicon material in the dummy gate 11 due to incomplete etching, i.e., there is a residual amorphous silicon material 12, which increases the size of the dummy gate 11 at this location.
[0005] (2) Sidewalls 14 are formed on both sides of the dummy gate 11, and source / drain regions 15 are epitaxially formed on the fins 13 on both sides of the dummy gate 11.
[0006] (3) An interlayer dielectric layer 16 covering the fin 13 and the dummy gate 11 is formed on the substrate 10, and the top of the dummy gate 11 is exposed by planarization.
[0007] (4) Remove the dummy gate 11. Since there is residual amorphous silicon material at the junction of the dummy gate 11 and the fin 13, this residual amorphous silicon material 12 will be removed along with the dummy gate 11 (the middle part (channel region) of the fin 13 is exposed in the figure, leaving an enlarged space (the lateral dimension z of this space is the sum of the lateral dimension x of the residual amorphous silicon material 12 and the lateral dimension y of the dummy gate 11). This will cause the gate size to increase after the gate material is filled in situ in the future.
[0008] As gate pitch gradually decreases, the process window for adjusting gate morphology shrinks dramatically. This leads to an increase in size at the gate-fin interface, directly impacting device performance and increasing the risk of short circuits between the gate and source / drain. Therefore, controlling the gate morphology is crucial for successful mass production. Summary of the Invention
[0009] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide a method for improving gate morphology.
[0010] To achieve the above objectives, the technical solution of the present invention is as follows:
[0011] A method for improving gate morphology, comprising:
[0012] A substrate is provided having fins and dummy gates extending across the fins; wherein, at the junction of the dummy gates and the sidewalls of the fins, there is a residual portion of dummy gate material formed during the formation of the dummy gates;
[0013] A first sacrificial layer is formed on the substrate, covering the top surface of the fin, exposing a portion of the dummy gate located above the top surface of the fin;
[0014] A protective layer is formed on the surface of the exposed portion of the dummy gate, and then the first sacrificial layer is removed;
[0015] A rapid oxidation process is performed to oxidize the exposed residual portion of the dummy gate material;
[0016] A second sacrificial layer is formed on the substrate, covering the top surface of the fin, exposing a portion of the dummy gate located above the top surface of the fin and having the protective layer;
[0017] The protective layer and the second sacrificial layer are removed sequentially;
[0018] An interlayer dielectric layer covering the fin and the dummy gate is formed on the substrate, and the top of the dummy gate is exposed by planarization;
[0019] Remove the dummy gate material except for the oxidized dummy gate material residue.
[0020] Further, the method for forming the first sacrificial layer or the second sacrificial layer includes:
[0021] A first sacrificial layer material or a second sacrificial layer material covering the fin and the dummy gate is formed on the substrate;
[0022] The first sacrificial layer material or the second sacrificial layer material is etched back to form the first sacrificial layer or the second sacrificial layer covering the top surface of the fin.
[0023] Further, the method for forming the protective layer includes:
[0024] A protective material layer is formed conformally on the surface of the first sacrificial layer and the exposed portion of the dummy gate;
[0025] The protective material layer located on the first sacrificial layer is removed, while the protective material layer is retained on the surface of the exposed portion of the dummy gate, thereby forming a protective layer on the surface of the exposed portion of the dummy gate.
[0026] Furthermore, the rapid oxidation process includes rapid thermal oxidation.
[0027] Furthermore, before forming an interlayer dielectric layer covering the fin and the dummy gate on the substrate, the method further includes:
[0028] Sidewalls are formed on both sides of the dummy gate, and source / drain regions are formed on the fins on both sides of the dummy gate.
[0029] Furthermore, the source / drain region is formed on the fin using an epitaxial process.
[0030] Furthermore, the planarization includes chemical mechanical polishing.
[0031] Furthermore, after removing the dummy gate material, the process further includes:
[0032] A gate material is filled into the cavity formed after the removal of the dummy gate material to form a gate.
[0033] Furthermore, the pseudo-gate material includes amorphous silicon.
[0034] Furthermore, the gate material includes metal or polycrystalline silicon.
[0035] As can be seen from the above technical solution, the present invention covers the dummy gate portion above the top surface of the fin with a protective layer and exposes the dummy gate material residue at the junction of the dummy gate and the fin sidewall. Therefore, the dummy gate material residue can be converted into oxide by rapid oxidation treatment targeting only the dummy gate material residue. In this way, the difference in selectivity between the two materials can be used to retain the oxidized dummy gate material residue during subsequent removal of the dummy gate material, thereby avoiding the problem of the gate filling cavity being expanded after the dummy gate is removed. Thus, it can avoid problems such as short circuit between the gate and source / drain and increased parasitic capacitance caused by the increase in gate size, improve device yield and performance, and ultimately ensure smooth mass production by improving the gate morphology. Attached Figure Description
[0036] Figures 1-4 This is a schematic diagram of the process steps of an existing gate formation method;
[0037] Figure 5 This is a flowchart of a method for improving gate morphology according to a preferred embodiment of the present invention;
[0038] Figures 6-19 According to a preferred embodiment of the present invention Figure 5 A schematic diagram of the process steps for improving gate morphology using this method. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.
[0040] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0041] Please see Figure 5 , Figure 5 This is a flowchart illustrating a preferred embodiment of a method for improving gate morphology according to the present invention. Figure 5 As shown, a method for improving gate morphology according to the present invention may include the following steps:
[0042] Step S1: Provide a substrate having fins and a dummy gate spanning the fins; wherein, at the junction of the dummy gate and the sidewall of the fin, there is a dummy gate material residue from the formation of the dummy gate.
[0043] Please see Figure 6 Substrate 20 can be a semiconductor substrate. For example, substrate 20 can be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 20 can be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. Other substrates can also be used.
[0044] In some embodiments, the semiconductor material of the substrate 20 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.
[0045] Conventional photolithography and etching processes can be used to pattern the substrate 20, thereby forming a protruding fin structure 23 on the substrate 20.
[0046] Alternatively, epitaxial processes can be used to form the fin structure 23 on the substrate 20.
[0047] The material of the fin 23 may include silicon, germanium, silicon-germanium, silicon carbide, III-V compound semiconductor, II-VI compound semiconductor, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, or GaP.
[0048] In some embodiments, conventional photolithography and etching processes may be used to form a pseudo gate 21 structure that spans across the fin 23.
[0049] The dummy gate 21 is typically made of amorphous silicon or similar materials, but other materials can also be used. An ONO (oxide-nitride-oxide) layer 211, for example, can be further formed on top of the amorphous silicon dummy gate 21. The present invention will now be described using an amorphous silicon dummy gate 21 as an example.
[0050] When the dummy gate 21 is fabricated using the above-mentioned conventional process, at the junction of the dummy gate 21 and the sidewall of the fin 23, there will be residual amorphous silicon material of the dummy gate 21 due to incomplete etching. That is, there is a residual amorphous silicon material 22 at the junction of the dummy gate 21 and the sidewall of the fin 23, which increases the size of the dummy gate 21 at this location.
[0051] When the dummy gate 21 needs to be removed later, since there is residual amorphous silicon material at the junction of the dummy gate 21 and the fin 23, this residual amorphous silicon material 22 will be removed along with the dummy gate 21, leaving the expanded space (see reference). Figure 4 This can lead to an increase in the size of the gate after in-situ filling of the gate material.
[0052] To address the aforementioned issues, this invention employs innovative process technologies to improve gate morphology, thereby avoiding yield and device performance degradation caused by gate morphology defects, and ultimately ensuring successful mass production.
[0053] Step S2: A first sacrificial layer is formed on the substrate, covering the top surface of the fin, exposing the portion of the dummy gate located above the top surface of the fin.
[0054] Please see Figures 7-8 In a preferred embodiment, a conventional deposition process, such as CVD, PECVD, or FCVD, can be used to deposit a first sacrificial layer material 24' on the substrate 20, completely covering the fin 23 and the dummy gate 21. Then, for example, an etch-back process can be used to etch back the first sacrificial layer material 24', so that the top surface of the first sacrificial layer material 24' is brought down to the top surface of the fin 23, forming a first sacrificial layer 24 covering the top surface of the fin 23.
[0055] At this time, the portion of the dummy gate 21 located above the top surface of the fin 23 will be exposed from the top surface of the first sacrificial layer 24 because it is not covered by the first sacrificial layer 24. Meanwhile, the amorphous silicon material residue 22 located at the junction of the dummy gate 21 and the sidewall of the fin 23 will still be covered by the first sacrificial layer 24, and thus located below the top surface of the first sacrificial layer 24.
[0056] In some embodiments, the material of the first sacrificial layer 24 may be silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or a combination thereof.
[0057] In other embodiments, the material of the first sacrificial layer 24 may also be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.
[0058] Step S3: Form a protective layer on the surface of the exposed dummy gate portion, and then remove the first sacrificial layer.
[0059] Please see Figures 9-10 In a preferred embodiment, a conventional deposition process, such as ALD, CVD, PECVD, etc., can be used to form a protective layer 25 on the surface of the exposed portion of the dummy gate 21.
[0060] For example, conventional deposition processes such as ALD, CVD, and PECVD can be used to form a protective material layer 25' on the first sacrificial layer 24 and on the surface of the exposed dummy gate 21 in a conformal manner.
[0061] Then, the protective material layer 25' located on the first sacrificial layer 24 is removed, leaving the protective material layer 25' on the surface of the exposed portion of the dummy gate 21, thereby forming a protective layer 25 composed of the remaining protective material layer 25' material on the surface of the exposed portion of the dummy gate 21, as shown. Figure 10 As shown.
[0062] In some embodiments, the material of the protective layer 25 (the material of the protective material layer 25') may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. Other materials may also be used for the protective layer 25. Furthermore, the material of the protective layer 25 needs to be a different material from the material of the first sacrificial layer 24 and have a higher etching selectivity.
[0063] The protective layer 25 can protect the portion of the dummy gate 21 located above the top surface of the fin 23, preventing it from being oxidized by the subsequent rapid oxidation steps and causing a change in the gate linewidth.
[0064] Please see Figure 11In a preferred embodiment, a conventional etching process can be used, and the first sacrificial layer 24 can be removed by taking advantage of the high etching selectivity between the materials of the first sacrificial layer 24 and the protective layer 25.
[0065] Since the first sacrificial layer 24 is removed, the residual portion 22 of the amorphous silicon pseudo gate material (amorphous silicon material) that was originally covered by the first sacrificial layer 24 is exposed.
[0066] Step S4: Perform a rapid oxidation process to oxidize the exposed dummy gate material residue.
[0067] Please see Figure 12 In a preferred embodiment, the exposed amorphous silicon material of the pseudo-gate material residue 22 can be oxidized using, for example, a rapid thermal oxidation (RTO) process, to transform it into a silicon oxide pseudo-gate material residue 22'.
[0068] Since the surface of the dummy gate 21 located above the top surface of the fin 23 is protected by the protective layer 25, the above-mentioned thermal oxidation only targets the amorphous silicon residue at the junction of the dummy gate 21 and the sidewall of the fin 23. Furthermore, since the amorphous silicon residue at the junction of the dummy gate 21 and the sidewall of the fin 23 has a relatively prominent structural state, its oxidation amount is greater, thus it can be oxidized more thoroughly, forming a silicon oxide dummy gate material residue portion 22' that is different from the amorphous silicon dummy gate 21 material.
[0069] Step S5: Form a second sacrificial layer on the substrate that covers the top surface of the fin, exposing the portion of the dummy gate located above the top surface of the fin and having a protective layer.
[0070] Please see Figures 13-14 In a preferred embodiment, a conventional deposition process, such as CVD, PECVD, or FCVD, can be used to deposit a second sacrificial layer material 26' on the substrate 20, completely covering the fin 23 and the dummy gate 21. Then, for example, an etch-back process can be used to etch back the second sacrificial layer material 26', so that the top surface of the second sacrificial layer material 26' is brought down to the top surface of the fin 23, forming a second sacrificial layer 26 covering the top surface of the fin 23.
[0071] At this time, the portion of the dummy gate 21 located above the top surface of the fin 23 and having the protective layer 25 will be exposed from the top surface of the second sacrificial layer 26 because it is not covered by the second sacrificial layer 26. At the same time, the oxidized dummy gate material residue 22' located at the junction of the dummy gate 21 and the sidewall of the fin 23 will be covered by the second sacrificial layer 26, and thus located below the top surface of the second sacrificial layer 26.
[0072] In some embodiments, the material of the second sacrificial layer 26 may be silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, or a combination thereof.
[0073] In other embodiments, the material of the second sacrificial layer 26 may also be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.
[0074] Furthermore, the material of the second sacrificial layer 26 needs to be different from that of the protective layer 25 and has a higher etching selectivity.
[0075] Step S6: Remove the protective layer and the second sacrificial layer in sequence.
[0076] Please see Figures 15-16 In a preferred embodiment, a conventional etching process can be used, and the protective layer 25 can be removed by taking advantage of the high etching selectivity between the material of the protective layer 25 and the material of the second sacrificial layer 26.
[0077] Next, a conventional etching process can be used, and the second sacrificial layer 26 can be removed by taking advantage of the high etching selectivity between the material of the second sacrificial layer 26 and other structural materials on the device.
[0078] Since the second sacrificial layer 26 is removed, the oxidized silicon oxide pseudo-gate material residue 22' that was originally covered by the second sacrificial layer 26 is exposed again.
[0079] Step S7: Form an interlayer dielectric layer covering the fins and the dummy gate on the substrate, and expose the top of the dummy gate by planarization.
[0080] Please see Figure 17 In a preferred embodiment, a conventional sidewall process can be used to form sidewall 27 structures on both sides of the dummy gate 21. The formed sidewall 27 structures enclose the oxidized silicon oxide dummy gate material residue 22'.
[0081] In some embodiments, the sidewall 27 material may include nitrides, such as silicon nitride, silicon oxynitride, or silicon carbonitride, or combinations thereof.
[0082] Next, conventional epitaxial processes can be used to form source / drain regions 28 on both ends of the fins 23 on both sides of the dummy gate 21.
[0083] For example, grooves can be formed on the surfaces of the fins 23 on both sides of the dummy gate 21, and then, by using an appropriate method (e.g., metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or a combination thereof), semiconductor material can be epitaxially grown in the grooves to form the source / drain region 28.
[0084] In some embodiments, when the resulting FinFET device is an n-type FinFET device, the semiconductor material epitaxially grown in the source / drain regions 28 may include silicon carbide (SiC), silicon phosphide (SiP), phosphorus-doped silicon-carbon (SiCP), etc.
[0085] In some embodiments, when the resulting FinFET device is a p-type FinFET device, the semiconductor material epitaxially grown in the source / drain regions 28 may include SiGe and p-type impurities, such as boron or indium.
[0086] The epitaxial source / drain regions 28 can be formed by implanting dopants, followed by an annealing process. The implantation process may include forming and patterning a mask (e.g., a photoresist) to cover the areas of the FinFET to be protected from the implantation process. P-type impurities such as boron or indium can be implanted into the source / drain regions 28 of a P-type transistor. N-type impurities such as phosphorus or arsenides can be implanted into the source / drain regions 28 of an N-type transistor. In some embodiments, the epitaxial source / drain regions 28 may be doped in situ during growth.
[0087] Please see Figure 18 Next, any suitable method can be used to deposit the interlayer medium layer 29, for example, CVD, PECVD or FCVD.
[0088] In some embodiments, the interlayer dielectric layer 29 is formed of a dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.
[0089] After the interlayer dielectric layer 29 is formed, a planarization process such as CMP can be performed to achieve a horizontal upper surface of the interlayer dielectric layer 29. CMP can also remove the ONO layer 211 disposed above the dummy gate 21.
[0090] In some embodiments, after the planarization process, the upper surface of the interlayer dielectric layer 29 is flush with the upper surface of the dummy gate 21, thereby exposing the top of the dummy gate 21.
[0091] Step S8: Remove the pseudo-gate material except for the oxidized pseudo-gate material residue.
[0092] Please see Figure 19 One or more etching steps can be performed to remove the material such as the dummy gate 21, thereby forming a cavity, i.e., a gate trench 30, between the sidewalls 27. After the dummy gate 21 material is removed, the central region (channel region) of the corresponding fin 23 will be exposed in the gate trench 30.
[0093] Furthermore, after removing the dummy gate 21 material, the gate material can be filled into the gate trench 30 by CVD, PVD, ALD, and / or other suitable deposition processes to form the gate.
[0094] In some embodiments, the gate material may include metals such as tungsten, copper, gold, and cobalt, or polycrystalline silicon.
[0095] It can be seen that when removing the dummy gate 21 (whose lateral dimension is y'), the oxidized dummy gate material residue 22' (whose lateral dimension is x') is not removed along with the dummy gate 21 material because it belongs to a different material. Therefore, it is retained. Thus, when filling the gate trench 30 with gate material, the presence of the oxidized dummy gate material residue 22' maintains the original size of the gate trench 30 (i.e., the lateral dimension z' of the gate trench 30 can remain consistent with the lateral dimension y' of the dummy gate 21). This ensures the desired size of the formed gate, thus avoiding the previous situation where the dummy gate material residue was removed along with the dummy gate material, resulting in a corresponding increase in size (see reference). Figures 3-4 This leads to the problem that the morphology of the gate formed by the filling is stretched at the junction with the sidewall of the fin 23.
[0096] In summary, by covering the portion of the dummy gate 21 above the top surface of the fin 23 with a protective layer 25 and exposing the dummy gate material residue 22 at the junction of the dummy gate 21 and the sidewall of the fin 23, the present invention can convert the dummy gate 21 material in the dummy gate material residue 22 into oxide through rapid oxidation treatment targeting only the dummy gate material residue 22. This allows the oxidized dummy gate material residue 22' to be retained during subsequent removal of the dummy gate 21 material by utilizing the selectivity difference between the two materials, thereby avoiding the problem of the gate filling cavity being enlarged after the removal of the dummy gate 21. Therefore, it can avoid problems such as short circuits between the gate and source / drain and increased parasitic capacitance caused by the increase in gate size, improve device yield and performance, and ultimately ensure smooth mass production by improving the gate morphology.
[0097] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as defined in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A method for improving gate morphology, characterized in that, include: A substrate is provided having fins and dummy gates extending across the fins; wherein, at the junction of the dummy gates and the sidewalls of the fins, there is a residual portion of dummy gate material formed during the formation of the dummy gates; A first sacrificial layer is formed on the substrate, covering the top surface of the fin, exposing a portion of the dummy gate located above the top surface of the fin; A protective layer is formed on the surface of the exposed portion of the dummy gate, and then the first sacrificial layer is removed; A rapid oxidation process is performed to oxidize the exposed residual portion of the dummy gate material; A second sacrificial layer is formed on the substrate, covering the top surface of the fin, exposing a portion of the dummy gate located above the top surface of the fin and having the protective layer; The protective layer and the second sacrificial layer are removed sequentially; An interlayer dielectric layer covering the fin and the dummy gate is formed on the substrate, and the top of the dummy gate is exposed by planarization; Remove the pseudo-gate material except for the oxidized pseudo-gate material residue.
2. The method for improving gate morphology according to claim 1, characterized in that, The method for forming the first sacrificial layer or the second sacrificial layer includes: A first sacrificial layer material or a second sacrificial layer material covering the fin and the dummy gate is formed on the substrate; The first sacrificial layer material or the second sacrificial layer material is etched back to form the first sacrificial layer or the second sacrificial layer covering the top surface of the fin.
3. The method for improving gate morphology according to claim 1, characterized in that, The method for forming the protective layer includes: A protective material layer is formed conformally on the surface of the first sacrificial layer and the exposed portion of the dummy gate; The protective material layer located on the first sacrificial layer is removed, while the protective material layer is retained on the surface of the exposed portion of the dummy gate, thereby forming a protective layer on the surface of the exposed portion of the dummy gate.
4. The method for improving gate morphology according to claim 1, characterized in that, The rapid oxidation process includes rapid thermal oxidation.
5. The method for improving gate morphology according to claim 1, characterized in that, Before forming an interlayer dielectric layer covering the fin and the dummy gate on the substrate, the method further includes: Sidewalls are formed on both sides of the dummy gate, and source / drain regions are formed on the fins on both sides of the dummy gate.
6. The method for improving gate morphology according to claim 5, characterized in that, The source / drain region is formed on the fin using an epitaxial process.
7. The method for improving gate morphology according to claim 1, characterized in that, The planarization includes chemical mechanical polishing.
8. The method for improving gate morphology according to claim 1, characterized in that, After removing the dummy gate material, the method further includes: A gate material is filled into the cavity formed after the removal of the dummy gate material to form a gate.
9. The method for improving gate morphology according to claim 8, characterized in that, The pseudo-gate material includes amorphous silicon.
10. The method for improving gate morphology according to claim 8, characterized in that, The gate material includes metal or polycrystalline silicon.