Method for manufacturing semiconductor device, etching control method, system and storage medium
By adjusting the etching process parameters by collecting the optical signal change curves, the yield and reliability problems caused by the high difficulty of 3D memory manufacturing were solved, and the stability of the aperture size and the improvement of device performance were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-12-29
- Publication Date
- 2026-06-16
AI Technical Summary
As the number of stacked layers of 3D memory increases, the process of forming 3D memory becomes increasingly difficult, leading to a decrease in the yield and reliability of 3D memory.
By collecting the change curve of the optical acquisition signal, the etching process parameters of the second etching are adjusted to ensure that the size of the formed opening is stable. The etching process parameters are adjusted by feedback adjustment to compensate for the differences in the first etching process.
This improved the yield and process capability of semiconductor devices, ensured that the aperture size was within the standard range, and enhanced the reliability of the devices.
Smart Images
Figure CN114284167B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and specifically to a method for fabricating a semiconductor device, an etching control method, a system, and a storage medium. Background Technology
[0002] In recent years, the development of flash memory has been particularly rapid. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, along with advantages such as high integration, fast access speeds, and ease of erasing and rewriting. Consequently, it has found widespread application in microcomputers, automation control, and many other fields. Against this backdrop, to address the challenges of planar flash memory and to pursue lower production costs per unit storage cell, 3D NAND flash memory emerged. 3D flash memory forms multiple layers of alternating stacked data storage cells, transforming the planar structure into a three-dimensional structure to improve storage density and integration. 3D flash memory can support higher storage capacity in a smaller space, resulting in significant cost savings, reduced energy consumption, and substantial performance improvements to fully meet the needs of numerous consumer mobile devices and the most demanding enterprise deployments.
[0003] As the number of stacked layers of 3D memory increases, the process of forming 3D memory becomes increasingly difficult, leading to a decrease in the yield and reliability of 3D memory. Therefore, it is necessary to continuously optimize the process of forming 3D memory in order to continuously improve the yield and reliability of the device. Summary of the Invention
[0004] This invention provides a method for fabricating a semiconductor device, an etching control method, a system, and a storage medium to improve the yield and reliability of the device.
[0005] To at least partially solve the above problems, embodiments of the present invention provide a method for fabricating a semiconductor device. The semiconductor device includes a substrate and a semiconductor structure located on the substrate. The method for fabricating the semiconductor device includes: performing a first etching on the semiconductor device to form a first opening on the semiconductor device; acquiring parameter changes of the first etching during the formation of the first opening and forming a data record; determining etching process parameters for a second etching based on the data record and a preset data record; and performing a second etching on the semiconductor device according to the etching process parameters of the second etching and based on the first opening to form a second opening including the first opening in the semiconductor device.
[0006] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0007] Based on the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0008] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0009] Based on the difference between the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0010] The data recording includes the curves showing the changes in the optical acquisition signals during the formation of the first opening.
[0011] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0012] By comparing the change curves of the optical acquisition signals of the recorded data and the corresponding preset data, and based on the difference between the optical acquisition signals of the recorded data and the corresponding preset data, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0013] The etching process parameters include the reaction time for the second etching.
[0014] The semiconductor structure includes a stacked structure formed along a longitudinal direction perpendicular to the substrate, and the second opening includes a channel that penetrates the stacked structure and extends into the substrate.
[0015] The process includes, after performing a second etching on the semiconductor device according to the etching process parameters of the second etching, based on the first opening, to form a second opening including the first opening in the semiconductor device, the process further includes:
[0016] A functional layer, a channel layer, and an insulating layer are formed sequentially from the outside to the inside of the channel. The functional layer, the channel layer, and the channel insulating layer constitute the channel structure.
[0017] The semiconductor structure includes a stacked structure formed along a longitudinal direction perpendicular to the substrate. The second opening includes a gate line slot, which penetrates the stacked structure and extends into the substrate. The gate line slot divides the stacked structure into several parts.
[0018] The semiconductor structure also includes a dielectric layer, and the second opening is located in the dielectric layer. The second opening includes any one of a contact hole, a through hole, or a groove.
[0019] A mask layer is formed on the side of the semiconductor structure perpendicular to the substrate and away from the substrate. The mask layer has a third opening corresponding to the first opening. The semiconductor device is first etched to form the first opening on the stacked structure, specifically including:
[0020] Based on the third opening, the semiconductor device is first etched to form the first opening on the semiconductor device.
[0021] The third opening has a width in the first direction, and after the first etching is performed on the semiconductor device to form the first opening, the method further includes:
[0022] Adjust the etching process parameters for the second etching step based on the width and the preset width.
[0023] To at least partially solve the above problems, embodiments of the present invention provide an etching control method for etching a semiconductor device. The etching control method includes: acquiring parameter changes during a first etching process on the semiconductor device and forming a data record, wherein the first etching is used to form a first opening on the semiconductor device; and determining etching process parameters for a second etching based on the data record and a preset data record, wherein the second etching is used to form a second opening including the first opening in the semiconductor device.
[0024] The data recording includes the curves showing the changes in the optical acquisition signals during the formation of the first opening.
[0025] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0026] Based on the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0027] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0028] Based on the difference between the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0029] The etching process parameters include the reaction time for the second etching.
[0030] To at least partially solve the above problems, embodiments of the present invention provide an etching control system for etching semiconductor devices. The etching control system includes a processor for executing the steps of any of the above etching control methods.
[0031] To at least partially solve the above problems, embodiments of the present invention provide a computer-readable storage medium storing a plurality of instructions adapted for loading by a processor to execute the steps of any of the above-described etching control methods.
[0032] The beneficial effects of this invention are as follows: Unlike existing technologies, this invention provides a method for fabricating a semiconductor device, an etching control method, a system, and a storage medium. The semiconductor device includes a substrate and a semiconductor structure located on the substrate. The method for fabricating the semiconductor device includes: performing a first etching on the semiconductor device to form a first opening; acquiring parameter changes during the formation of the first opening and forming data records; determining etching process parameters for a second etching based on the data records and preset data records; and performing a second etching on the semiconductor device according to the etching process parameters for the second etching, based on the first opening, to form a second opening including the first opening in the semiconductor device. By determining the etching process parameters for the second etching based on the data records and preset data records, the process dimensions of the formed second opening are ensured to be stable, thereby improving the device yield and process capability. Attached Figure Description
[0033] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.
[0034] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present invention.
[0035] Figures 2a to 2d This is a schematic diagram of the structure of each step in the method for fabricating a semiconductor device according to some embodiments of the present invention.
[0036] Figure 3 A curve comparison chart of preset data records and comparative data records collected during the formation of the channel hole.
[0037] Figure 4 A comparison chart showing the dimensions of the channel holes corresponding to the preset data records and the comparison data records.
[0038] Figure 5 The diagram shows the structure of a semiconductor device provided in some embodiments of the present invention.
[0039] Figure 6 The diagram shows the structure of a semiconductor device provided in some embodiments of the present invention.
[0040] Figure 7 This is a flowchart illustrating a method for fabricating an etching control system for a semiconductor device, as provided in some embodiments of the present invention.
[0041] Figure 8 This is a schematic block diagram of an etching control system provided for some embodiments of the present invention. Detailed Implementation
[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0043] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.
[0044] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.
[0045] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).
[0046] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" means perpendicular to the direction of the substrate.
[0047] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.
[0048] In some embodiments, the formation process for forming a channel hole can be as follows: First, a patterned photoresist layer is formed on a semiconductor device comprising a substrate, a non-stack structure, and a hard mask layer. The photoresist layer has openings that correspond to the channel holes. Then, based on these openings, the pattern of the photoresist layer is transferred to the hard mask layer via an etching process. This results in the hard mask layer having openings corresponding to the photoresist layer openings. Finally, based on these openings, a stacked structure is formed through alternating interlayer sacrificial layers and interlayer insulating layers via an etching process to form the channel hole. With the development of semiconductor devices, the number of layers in the stacked structure is increasing. Correspondingly, the channel holes have high aspect ratios, requiring the etching of hundreds of pairs of repeating interlayer sacrificial layers and interlayer insulating layers. However, the etching rate of each hole cannot be completely uniform; some are faster than others. Generally, the sacrificial layer between layers is typically made of nitride, and the insulating layer is typically made of oxide. In this case, the endpoint (EDP) refers to capturing the nitrogen or oxygen signal within the film. Since the etching rate of each via cannot be perfectly uniform (some are faster, some slower), the number of layers corresponding to the captured nitrogen or oxygen signals for different vias varies. This makes it impossible to accurately determine the etching depth using the endpoint signal method. Therefore, high aspect ratio via etching currently employs a time-controlled method (also known as the by-time method). The EDP method involves stopping the etching reaction by capturing signals indicating changes in the film. For example, capturing a nitrogen or oxygen signal during via etching triggers a stop to the etching reaction. The by-time method uses a set time as the condition for stopping the etching reaction. For example, a set time of 60 minutes triggers a stop to the etching reaction after 60 minutes of etching.
[0049] Because the process steps preceding the formation of vias (i.e., the front-end), such as the size of the photoresist layer openings (PH CD) on the patterned photoresist layer, the thickness of the hard mask (HM), or the size of the hard mask layer openings (HM CD) on the hard mask layer, can vary, the differences introduced in the front-end cannot be compensated for when forming high aspect ratio vias using by-time etching. This results in unstable via dimensions, with some vias exceeding specifications. However, the critical dimension of the via is a very critical process parameter. For every 1nm increase in via size, the contact resistance (Rs) increases by 1000Ω, and when Rs exceeds a certain value, the yield drops sharply.
[0050] Based on this, embodiments of the present invention propose a method for fabricating a semiconductor device to improve the device's yield and reliability. Please refer to... Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present invention. The semiconductor device includes a substrate 110 and a semiconductor structure located on the substrate 110. The specific steps of the method for fabricating the semiconductor device include:
[0051] Step S101: Perform a first etching on the semiconductor device to form a first opening 131 on the semiconductor device.
[0052] In some embodiments, the semiconductor structure includes a stacked structure 120 formed along a longitudinal direction (Z direction) perpendicular to the substrate 110, and the second opening 130 includes a channel that penetrates the stacked structure 120 and extends into the substrate 110.
[0053] In addition, it should be noted that, Figures 2a to 2d Only structures relevant to some embodiments of the invention are shown. The semiconductor device of the invention may further include other components and / or structures for realizing the full functionality of the device.
[0054] Figure 2a The structure formed in step S101 includes: a substrate 110, a stacked structure 120 on the substrate 110, and a first opening 131 on the stacked structure 120. The stacked structure 120 includes alternately stacked interlayer sacrificial layers 121 and interlayer insulating layers 122.
[0055] Specifically, substrate 110 serves as the basis for forming semiconductor devices. Substrate 110 is a semiconductor material, which can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), or other materials, without particular limitation. The semiconductor structure (including stacked structure 120, not shown in the figure) can be formed on substrate 110 through one or more deposition processes, etching processes, chemical mechanical polishing, and cleaning processes, etc. The specific structure and film layers of the semiconductor structure are related to the actual process flow. For example, a first etching process can be used to form a semiconductor structure on stacked structure 120 such as... Figure 2a The first opening 131 is shown.
[0056] Step S102: Obtain the parameter changes of the first etching during the formation of the first opening 131 and form a data record.
[0057] The parameter change in the first etching process can be a change in the etching process parameters or a change in the optical signal collected by the sensor during the first etching process. There are no special limitations on the parameter change in the first etching process.
[0058] The data recording includes the change curve of the optical acquisition signal during the formation of the first opening 131.
[0059] The optical acquisition signal can be the signal intensity acquired during the etching process, such as the optical signal intensity of the plasma emission spectrum (OES) acquired during the etching process.
[0060] Specifically, in-situ optical emission spectroscopy (OES) can be used to monitor the plasma state in a plasma etching machine in real time. The collected OES data is then analyzed using principal element analysis (PCA) to obtain data records related to the etching process. In-situ OES detection provides real-time, in-situ analysis without disturbing or interfering with the plasma or the process itself, offering excellent spatial and temporal resolution. During etching processes, such as dry etching, plasma is typically generated. When atoms or molecules in the plasma are excited to excited states by electrons, they emit light of specific wavelengths as they return to another energy state. Changes in the intensity of this optical signal can be observed through observation holes on the sidewall of the etching machine's reaction chamber. Since different atoms or molecules excite different wavelengths of light, changes in the intensity of the optical signal reflect changes in the concentration of atoms or molecules in the plasma.
[0061] As can be seen from the above, in-situ optical emission spectroscopy (OES) detection technology can be used to collect the optical signal intensity of plasma emission spectrum (OES) during the formation of the first opening 131, thereby obtaining the change curve of the optical acquisition signal during the formation of the first opening 131.
[0062] In addition, the optical acquisition signal can also be other optical acquisition signals collected during the etching process, such as by continuously illuminating the etching hole during the etching process, using a sensor to receive the signal of the reflected light from the etching hole, and obtaining the optical path difference of light illuminating the etching hole at different times. The optical path difference during the formation of the first opening 131 can be collected to obtain the change curve of the optical acquisition signal during the formation of the first opening 131.
[0063] Step S103: Determine the etching process parameters for the second etching based on the data records and preset data records.
[0064] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0065] Based on the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0066] Specifically, the optical acquisition signal of the data recording can be compared with the corresponding preset optical acquisition signal of the data recording, and the preset etching process parameters can be adjusted according to the comparison results, thereby determining the etching process parameters of the second etching.
[0067] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0068] Based on the difference between the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0069] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0070] By comparing the change curves of the optical acquisition signals of the recorded data and the corresponding preset data, and based on the difference between the optical acquisition signals of the recorded data and the corresponding preset data, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0071] It should be understood that the terms "first" and "second" are only used to distinguish the first etching from the second etching. There are no specific restrictions on the timing relationship between the first and second etchings. For example, there may be other intermediate steps between the first and second etchings, or other etching steps different from the first and second etchings, but these other etching steps are not the first and second etchings in this context. The following text follows a similar principle and will not be elaborated upon further.
[0072] Please see Figure 3 This is a comparison curve of a preset data log (datalog) collected during the etching process to form the trench, and a contrasting data log (i.e., another data log different from the preset data log). The horizontal axis represents the time (in seconds) during the etching process, and the vertical axis represents the optical signal intensity of the plasma emission spectrum collected during the etching process (in counts per ms, i.e., the number of photons reaching the photosensor per unit time). Figure 3 The IB3 on the vertical axis refers to a specific wavelength range, which is generally set according to the etching process. For example, the wavelength range of IB3 can be set to 387 + / - 5 nm. Figure 3 As shown, curve 1 represents the preset data records collected and formed during the etching process, while curve 2 represents the comparative data records collected and formed during the etching process.
[0073] Please see Figure 4 This is a comparison chart of the channel dimensions corresponding to the preset data records and the comparison data records. The horizontal axis represents the wafer number corresponding to the channel, and the vertical axis represents the wafer size (in nm). For example... Figure 4 As shown, CD1 represents the dimension of the channel corresponding to the preset data record during the etching process, and CD2 represents the dimension of the channel corresponding to the comparative data record during the etching process. Figure 4 The upper and lower horizontal lines in the diagram represent the upper control limit (UCL) and lower control limit (LCL), respectively. Figure 4 It can be seen that CD1 is within the upper and lower control limits, and is within the standard range, while CD2 is outside the lower control limit, and is not within the standard range.
[0074] Specifically, as described above, the channel can be a second opening 130. The process of forming the channel includes performing a first etching process to form a first opening 131 and performing a second etching process to form a second opening 130 including the first opening 131. The data record for forming the first opening 131 includes three distinct peaks, curves 1 and 2. After forming the first opening 131, a second etching is performed. The etching process parameters of the second etching process corresponding to curve 1 are preset etching process parameters, and the etching process parameters of the second etching affect the size of the second opening 130. Based on this, the relationship between the average peak value of the data record during the formation of the first opening 131 (e.g., the average of the first three peaks), the etching process parameters of the second etching, and the final size CD of the second opening 130 can be studied. By using optical emission spectroscopy (OES) in-situ detection technology to acquire the data record during the formation of the first opening 131 in real time, comparing the signal intensity change curves of the data record with the corresponding preset data record, and determining the etching process parameters of the second etching based on the difference between the signal intensity of the data record and the corresponding preset data record, as well as the preset etching process parameters. By adjusting the etching process parameters of the second etching process through feedback, the difference between the data record of the process forming the first opening 131 and the preset data record is used as a trigger condition for feedback adjustment. The etching process parameters are adjusted according to the difference in the data record so that the size of the formed second opening 130 is within the standard range, thereby ensuring the stability of the size parameters of the formed second opening 130, and thus improving the device yield and process capability index (CPK).
[0075] The etching process parameters include the reaction time for the second etching.
[0076] Specifically, the etching process parameters of the second etching process affect the size of the formed second opening 130. These etching process parameters may include etching reaction time, the flow rate or concentration of etching gas (such as CF2, CF4, C4F6, CH2F2, or O2), power in the etching reaction, or gap (i.e., the gap between the wafer and the inner wall of the top of the etching reaction chamber). The reaction time of the second etching can be determined through feedback adjustment. For example, if the difference between the collected data record and the preset data record is 5% of the preset data record, the reaction time of the second etching is reduced by 5%, that is, the second etching is determined to be 95% of the preset reaction time in the preset etching process parameters. This adjusts the size of the second opening 130 formed by the second etching process, ensuring that the size of the formed second opening 130 is within the specification range, thereby ensuring the stability of the size parameters of the formed second opening 130 and improving the device yield and process capability.
[0077] In addition, it should be noted that, besides adjusting the etching reaction time, the flow rate or concentration of the etching gas, the power or spacing in the etching reaction, etc., can also be adjusted based on the collected data records and preset data records to ensure that the size of the formed second opening 130 is within the standard range, thereby ensuring the stability of the size parameters of the formed second opening 130.
[0078] Step S104: According to the etching process parameters of the second etching, the semiconductor device is etched in the second way according to the first opening 131 to form a second opening 130 including the first opening 131 in the semiconductor device.
[0079] Figure 2b The structure formed in step S104 includes: a substrate 110, a stacked structure 120 on the substrate 110, and a second opening 130 on the stacked structure 120. The second opening 130 is formed by the first opening 131 and the second etched opening 132. After determining the etching process parameters for the second etch, the semiconductor device can be etched according to the first opening 131 based on the etching process parameters, thereby forming the second opening 130 including the first opening 131 in the semiconductor device.
[0080] A mask layer 140 is formed on the side of the semiconductor structure perpendicular to the longitudinal direction (Z direction) of the substrate and away from the substrate 110. The mask layer 140 has a third opening 141 corresponding to the first opening 131. The semiconductor device is first etched to form the first opening 131 on the semiconductor structure, specifically including:
[0081] Based on the third opening 141, the semiconductor device is first etched to form the first opening 131 on the semiconductor device.
[0082] Figure 2c The structure formed by first etching of a semiconductor device according to the third opening 141 includes: a substrate 110, a stacked structure 120 on the substrate 110, a mask layer 140, and a third opening 141 on the stacked structure 120. A mask layer 140 may also be formed on the side of the stacked structure 120 along its longitudinal direction and away from the substrate 110. The mask layer 140 has a third opening 141 corresponding to the first opening 131. The semiconductor device can be first etched according to the third opening 141 to form the first opening 131 on the stacked structure 120.
[0083] The third opening 141 is located in the first direction (parallel to the transverse direction of the substrate 110, such as...) Figure 2c Having a width W in the X direction (as shown), after performing a first etching on the semiconductor device to form a first opening 131 on the semiconductor device, the method further includes:
[0084] Adjust the etching process parameters for the second etching step based on the width W and the preset width.
[0085] Specifically, the thickness and size of the hard mask layer 140 vary, affecting the size of the third opening 141 formed on the hard mask layer 140. When forming a high aspect ratio channel using the by-time etching method, the size difference of the third opening 141 cannot be compensated, resulting in unstable channel size. Some channel sizes may exceed the upper control limit (UCL) or lower control limit (LCL). However, the critical dimension of the channel is a very critical process parameter. For every 1nm increase in channel size, the contact resistance (Rs) of the channel increases by 1000Ω. When Rs exceeds a certain value, the yield will drop sharply.
[0086] Based on the dimensional difference in the formation of the third opening 141, the etching process parameters of the second etching can be adjusted according to the width W of the third opening 141 in the first direction (X direction) and the preset width to compensate for the difference in the second opening 130 formed subsequently due to the dimensional difference in the third opening 141, so that the size of the formed second opening 130 is within the standard range, and further ensures the stability of the dimensional parameters of the formed second opening 130.
[0087] The process includes, after performing a second etching on the semiconductor device according to the etching process parameters of the second etching, based on the first opening 131, to form a second opening 130 including the first opening 131 in the semiconductor device, the process further includes:
[0088] A functional layer, a channel layer, and an insulating layer are formed sequentially from the outside to the inside of the channel wall. The functional layer, the channel layer, and the channel insulating layer constitute the channel structure 150.
[0089] Figure 2d The diagram shows a structure forming the channel structure 150, including: a substrate 110, a stacked structure 120 on the substrate 110, and a mask layer 140. The channel structure 150 includes a functional layer, a channel layer, and an insulating layer (not shown in the figure) located within the channel.
[0090] In some embodiments, after the semiconductor device is etched according to the etching process parameters of the second etching and based on the first opening 131 to form a second opening 130 including the first opening 131 in the semiconductor device, a functional layer, a channel layer, and an insulating layer can be formed sequentially from the outside to the inside of the channel inner wall. The functional layer, the channel layer, and the channel insulating layer constitute the channel structure 150. The functional layer generally includes a tunneling layer, a charge trapping layer, and a blocking layer.
[0091] In some embodiments, the semiconductor structure includes a stacked structure 220 formed along a longitudinal direction perpendicular to the substrate, and a second opening 230 including a gate line slot, the second opening penetrating the stacked structure 220 and extending into the substrate 210, the gate line slot dividing the stacked structure into several portions.
[0092] Specifically, the second opening can also be a structure different from the channel, such as a grid line slot. In some embodiments, such as Figure 5 The diagram illustrates the structure of a semiconductor device formed according to some embodiments, including: a substrate, a stacked structure 220 located on the substrate, and a gate line gap (i.e., a second opening 230). The stacked structure includes alternately stacked interlayer sacrificial layers 221 and interlayer insulating layers 222. The gate line gap 230 penetrates the stacked structure 220 and extends into the substrate 210, dividing the stacked structure 220 into several parts. The first opening 231 and the opening 232 formed by the second etching process constitute the gate line gap.
[0093] In some embodiments, data records are collected during the first etching process to form the first opening 231. Based on these data records and preset data records, etching process parameters for the second etching are determined. Gate line slots including the first opening 231 are then formed according to these second etching parameters. The second etching process parameters are determined through feedback adjustment, and the size of the gate line slots formed by the second etching process is adjusted to ensure that the size of the formed gate line slots is within a standard range. This guarantees the stability of the dimensional parameters of the formed gate line slots 230, thereby improving device yield and process capability.
[0094] In addition, it should be noted that, Figure 5 Only structures relevant to some embodiments of the invention are shown. The semiconductor device of the invention may further include other components and / or structures for realizing the full functionality of the device.
[0095] In some embodiments, the semiconductor structure further includes a dielectric layer 360, and a second opening is located in the dielectric layer. The second opening includes any one of a contact hole 330, a through hole 340, or a groove 350.
[0096] Specifically, the second opening can also be a structure different from the channel hole, such as any of the following: contact hole 330 (CT), through hole 340 (Via), or groove 350 (Metal). Figure 6 As shown, the semiconductor device includes: a substrate 310, a stacked structure 320 on the substrate 310 including alternating gate layers 321 and insulating layers 322, and contact holes 330, through holes 340, or recesses 350. The contact holes 330 can be used to connect the gate layers 321 in the stacked structure 320 to word lines (WL), the through holes 340 can be used to connect the contact holes 330 to word lines, and the recesses 350, after being filled with conductive material, can serve as word lines. These recesses connect to peripheral circuits through the contact holes 330, through holes 340, and recesses 350, thereby enabling control of the gate layers 321 or other components in the stacked structure 320 via the peripheral circuits.
[0097] In some embodiments, based on the collected data records and preset data records, the second etching process parameters are determined, and the dimensions of the contact holes 330, through holes 340, or grooves 350 formed by the second etching process are adjusted so that the dimensions of the formed contact holes 330, through holes 340, or grooves 350 are within the standard range, thereby ensuring the stability of the dimensional parameters of the formed contact holes 330, through holes 340, or grooves 350, and thus improving the yield and process capability of the device.
[0098] In addition, it should be noted that, Figure 6 Only structures relevant to some embodiments of the invention are shown. The semiconductor device of the invention may further include other components and / or structures for realizing the full functionality of the device.
[0099] To at least partially address the above-mentioned problems, embodiments of the present invention also provide an etching control method for etching semiconductor devices. Please refer to [link to relevant documentation]. Figure 7 This is a flowchart illustrating an etching control method for a semiconductor device provided in some embodiments of the present invention. The etching control method includes:
[0100] Step S201: Obtain the parameter changes during the first etching process on the semiconductor device and form a data record, wherein the first etching is used to form a first opening 131 on the semiconductor device;
[0101] Step S202: Determine the etching process parameters for the second etching based on the data record and the preset data record, wherein the second etching is used to form a second opening 130 including the first opening 131 in the semiconductor device.
[0102] The data recording includes the change curve of the optical acquisition signal during the formation of the first opening 131.
[0103] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0104] Based on the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0105] Specifically, the etching process parameters for the second etching are determined based on the recorded data and the preset data, including:
[0106] Based on the difference between the optical acquisition signal recorded in the data record and the corresponding preset optical acquisition signal recorded in the data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
[0107] The etching process parameters include the reaction time for the second etching.
[0108] Specifically, by acquiring data records formed by parameter changes during the first etching process, and comparing the acquired data records with preset data records, the etching process parameters for the second etching are determined. That is, by adjusting the etching process parameters of the second etching through feedback, the comparison between the data records formed by parameter changes during the first etching process and the preset data records is used as a trigger condition for feedback adjustment. The etching process parameters of the second etching can be adjusted according to the difference between the data records and the corresponding preset data records, so that the second etching can make up for the difference brought about by the first etching, thereby ensuring the stability of the etching size parameters formed after the first and second etching processes, and thus improving the device yield and process capability index (CPK).
[0109] It should be understood that the structure and fabrication process of each component of the etching control method in the embodiments of the present invention can be referred to the above-described embodiments of the semiconductor device fabrication method, and will not be repeated here.
[0110] Based on the etching control method described in some embodiments of the present invention above, the present invention also provides an etching control system 400 for etching semiconductor devices. The etching control system 400 includes a processor 401, which is used to execute the steps of any of the etching control methods described above.
[0111] Specifically, such as Figure 8 As shown, the etching control system 400 may include a processor 401. The processor 401 is the control center of the etching control system 400, connecting various parts of the entire etching control system 400 through various interfaces and lines, executing various functions of the etching control system 400 and processing data, thereby controlling the etching process of the semiconductor device.
[0112] In this embodiment of the invention, the processor 401 in the etching control system 400 performs various functions by following the steps below:
[0113] The parameter changes during the first etching process on the semiconductor device are acquired and a data record is formed, wherein the first etching is used to form a first opening 131 on the semiconductor device;
[0114] Based on the data record and the preset data record, the etching process parameters for the second etching are determined, wherein the second etching is used to form a second opening 130 including the first opening 131 in the semiconductor device.
[0115] The etching control system 400 can implement the steps of the etching control method in any embodiment of the present invention. Therefore, it can achieve the beneficial effects that any etching control method in the present invention can achieve, as detailed in the previous embodiments, and will not be repeated here.
[0116] Based on the etching control method described in some embodiments of the present invention above, the present invention also provides a computer-readable storage medium storing a plurality of instructions adapted to be loaded by a processor to execute the steps of any of the etching control methods described above.
[0117] Those skilled in the art will understand that all or part of the steps in the various methods of some embodiments of the present invention described above can be implemented by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. Therefore, embodiments of the present invention provide a storage medium storing multiple instructions that can be loaded by a processor to execute the steps of any embodiment of the etching control method provided by the present invention.
[0118] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.
[0119] Since the instructions stored in the storage medium can execute the steps in any embodiment of the etching control method provided in the embodiments of the present invention, the beneficial effects that any etching control method provided in the embodiments of the present invention can achieve can be realized, as detailed in the preceding embodiments, and will not be repeated here.
[0120] This embodiment includes a semiconductor device fabrication method, etching control method, system, and storage medium, comprising: performing a first etching on the semiconductor device to form a first opening in the semiconductor structure; acquiring parameter changes of the first etching during the formation of the first opening and forming data records; determining etching process parameters for a second etching based on the data records and preset data records; and performing a second etching on the semiconductor device according to the etching process parameters of the second etching, based on the first opening, to form a second opening including the first opening in the semiconductor device. By determining the etching process parameters for the second etching based on the data records and preset data records, the process dimensions of the formed second opening are ensured to be stable, thereby improving the device yield and process capability.
[0121] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a substrate and a semiconductor structure located on the substrate. A mask layer is also formed on the semiconductor structure along a longitudinal direction perpendicular to the substrate and away from the substrate. The mask layer has a third opening corresponding to a first opening, and the third opening has a width in a first direction. Methods for manufacturing semiconductor devices include: Based on the third opening, the semiconductor device is first etched to form the first opening on the semiconductor device; Adjust the etching process parameters for the second etching based on the width and the preset width; The parameter changes of the first etching during the formation of the first opening are obtained and data records are generated; Based on the data records and preset data records, determine the etching process parameters for the second etching; According to the etching process parameters of the second etching, the semiconductor device is etched in a second manner based on the first opening to form a second opening including the first opening in the semiconductor device.
2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Based on the data records and preset data records, the etching process parameters for the second etching are determined, specifically including: The etching process parameters for the second etching are determined based on the difference between the data record and the corresponding preset data record and the preset etching process parameters.
3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The data record includes a curve showing the change in the optical acquisition signal during the formation of the first opening.
4. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The step of determining the etching process parameters for the second etching based on the data records and preset data records specifically includes: Based on the optical acquisition signal of the data record and the corresponding optical acquisition signal of the preset data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The step of determining the etching process parameters for the second etching based on the data records and preset data records specifically includes: Based on the difference between the optical acquisition signal recorded in the data record and the corresponding optical acquisition signal recorded in the preset data record, and the preset etching process parameters, the etching process parameters for the second etching are determined.
6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The etching process parameters include the reaction time of the second etching.
7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor structure includes a stacked structure formed along a longitudinal direction perpendicular to the substrate, and the second opening includes a channel that penetrates the stacked structure and extends into the substrate.
8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, After performing a second etching on the semiconductor device according to the etching process parameters of the second etching, based on the first opening, and forming a second opening including the first opening in the semiconductor device, the method further includes: A functional layer, a channel layer, and an insulating layer are sequentially formed from the outside to the inside of the inner wall of the channel, and the functional layer, the channel layer, and the channel insulating layer constitute the channel structure.
9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor structure includes a stacked structure formed along a longitudinal direction perpendicular to the substrate, the second opening including a gate line slot, the second opening penetrating the stacked structure and extending into the substrate, the gate line slot dividing the stacked structure into several parts.
10. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor structure further includes a dielectric layer, and the second opening is located in the dielectric layer. The second opening includes any one of a contact hole, a through hole, or a groove.
11. An etching control method, characterized in that, For etching a semiconductor device, the semiconductor device includes a substrate and a semiconductor structure located on the substrate, wherein a mask layer is formed on the semiconductor structure along a longitudinal direction perpendicular to the substrate and away from the substrate, the mask layer having a third opening corresponding to a first opening, the third opening having a width in a first direction; The etching control method includes: Based on the third opening, the semiconductor device is first etched to form the first opening on the semiconductor device; Based on the width and the preset width, the etching process parameters of the second etching are adjusted, wherein the second etching is used to form a second opening including the first opening in the semiconductor device; The parameter changes during the first etching process of the semiconductor device are acquired and a data record is generated. Based on the data records and preset data records, the etching process parameters for the second etching are determined.
12. The etching control method as described in claim 11, characterized in that, The data record includes a curve showing the change in the optical acquisition signal during the formation of the first opening.
13. The etching control method as described in claim 11, characterized in that, The step of determining the etching process parameters for the second etching based on the data records and preset data records specifically includes: Based on the optical acquisition signal of the data record and the corresponding optical acquisition signal of the preset data record, as well as the preset etching process parameters, the etching process parameters for the second etching are determined.
14. The etching control method as described in claim 13, characterized in that, The step of determining the etching process parameters for the second etching based on the data records and preset data records specifically includes: Based on the difference between the optical acquisition signal recorded in the data record and the corresponding optical acquisition signal recorded in the preset data record, and the preset etching process parameters, the etching process parameters for the second etching are determined.
15. The etching control method as described in claim 11, characterized in that, The etching process parameters include the reaction time of the second etching.
16. An etching control system, characterized in that, For etching semiconductor devices, the etching control system includes a processor for performing the steps of the etching control method according to any one of claims 11 to 15.
17. A computer-readable storage medium, characterized in that, The computer storage medium stores a plurality of instructions adapted for loading by a processor to perform the steps of the etching control method according to any one of claims 11 to 15.