Method of forming a semiconductor structure and semiconductor structure
By forming capping layers on the top and side surfaces of the bit line structure and controlling its deposition conditions, the problem of bit line structure loss during etching is solved, thereby improving the performance and yield of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-09-22
- Publication Date
- 2026-05-12
AI Technical Summary
In semiconductor devices, when the bottom of a trench with a high depth-to-width ratio is formed in a contact hole, the etching process can easily damage the top of the device structure, leading to performance degradation and reduced yield.
By forming capping layers on the top and side surfaces of the bitline structure, the apex corners of the bitline structure are protected by the capping layers. The deposition pressure, temperature and time of the capping layers are controlled, and the thickness and morphology of the capping layers are gradually adjusted to reduce the loss of the bitline structure during the etching process.
It effectively protects the top of the bit line structure, preventing damage from the etching process and improving the performance and yield of semiconductor devices.
Smart Images
Figure CN117790406B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Technology
[0002] As semiconductor devices have become increasingly integrated, these individual devices must be densely packed within a limited unit area. Due to this large-scale integration, the depth of contact holes has increased, while their width has decreased. Contact hole technology presents significant challenges at various technology nodes in semiconductor integrated circuits. For example, contact holes are typically formed by etching semiconductor layers in narrow areas, especially at the bottom of trenches with high depth-to-width ratios. During the etching process, the top edges of the semiconductor device structure located on both sides of the trench are affected, leading to wear and tear at the top edges. This can easily result in device defects, ultimately causing a decrease in semiconductor device performance and a significant drop in yield. Summary of the Invention
[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.
[0004] This disclosure provides a method for forming a semiconductor structure and the semiconductor structure itself.
[0005] A first aspect of this disclosure provides a method for forming a semiconductor structure, the method comprising:
[0006] A substrate is provided, wherein the substrate includes a plurality of active regions;
[0007] Multiple bit line structures are formed on the substrate, the multiple bit line structures are spaced apart along a first direction, a groove is provided between two adjacent bit line structures, and each bit line structure extends along a second direction;
[0008] Perform at least one cycle process to form a plurality of capacitor contact holes between the plurality of said bit line structures, wherein the cycle process includes:
[0009] Multiple capping layers are formed, which conformally cover the top surface and part of the side surface of the bit line structure to cover the top corner of the bit line structure. There is a slit between two adjacent capping layers, and the slit is located in the groove.
[0010] The substrate is etched along the slits and the trenches to expose the active regions within the substrate;
[0011] Remove the plurality of the capping layers;
[0012] After performing at least one cycle of the process, a capacitor contact plug is formed in the capacitor contact hole.
[0013] The slit diameter gradually increases along the direction from the top surface to the bottom surface of the position line structure.
[0014] The diameter of the slit is 1 / 3 to 1 / 2 of the diameter of the groove.
[0015] The height of the capping layer covering the side surface of the bit line structure is 1 / 10 to 2 / 5 of the height of the bit line structure.
[0016] The ratio between the thickness of the capping layer covering the top surface of the bit line structure and the thickness of the capping layer covering the side surface of the bit line structure is (1-3):1.
[0017] In a single cycle process, the deposition pressure for forming the capping layer is greater than or equal to 3 mtorr and less than or equal to 40 mtorr, and the height of the capping layer covering the side surface of the bit line structure is inversely proportional to the deposition pressure for forming the capping layer in the single cycle process.
[0018] In a single cycle process, the deposition time for forming the capping layer is greater than or equal to 5 seconds and less than or equal to 20 seconds.
[0019] The forming method includes performing 4 to 10 cycle processes to form a plurality of capacitor contact holes between the plurality of bit line structures.
[0020] When multiple cycles are implemented, the deposition pressure for forming the capping layer remains constant between the multiple cycles.
[0021] When multiple cycles are implemented, the deposition pressure for forming the capping layer gradually decreases between the multiple cycles.
[0022] This involves repeating the process four times.
[0023] In the first cycle process, the deposition pressure for forming the capping layer is 30-40 mtorr;
[0024] In the second cycle process, the deposition pressure for forming the capping layer is 20-30 mtorr;
[0025] In the third cycle process, the deposition pressure for forming the capping layer is 10-20 mtorr;
[0026] In the fourth cycle, the deposition pressure for forming the capping layer is 3-10 mtorr.
[0027] The capping layer comprises carbon and short-chain polymers of carbon.
[0028] The method for forming multiple bit line structures on the substrate includes:
[0029] An initial conductive layer is deposited on the substrate, and the initial conductive layer is etched along the first direction to form a plurality of conductive layers spaced apart along the first direction, each of the conductive layers extending along a second direction;
[0030] A sidewall layer is formed on the surface of the conductive layer, and the trench is provided between adjacent sidewall layers;
[0031] A protective layer is formed on the surface of the sidewall layer and the trench to protect the sidewall layer and the substrate.
[0032] The etching selectivity ratio of the capping layer and the protective layer is greater than 10.
[0033] A second aspect of this disclosure provides a semiconductor structure prepared using the semiconductor structure formation method described in the first aspect.
[0034] The semiconductor structure formation method and semiconductor structure provided in this disclosure include a capping layer formed on top of each bit line structure to protect the top of the bit line structure. This avoids damage to the top of the bit line structure during the etching process of forming contact holes, prevents defects in the bit line structure, and improves the performance and yield of semiconductor devices.
[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.
[0037] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.
[0038] Figure 2 This is a schematic diagram illustrating the process of forming a semiconductor structure by providing a substrate, according to an exemplary embodiment.
[0039] Figure 3This is a schematic diagram showing the dielectric layer formed on a substrate during the formation of a semiconductor structure according to an exemplary embodiment.
[0040] Figure 4 This is a schematic diagram illustrating the formation of bit line contact holes during the formation of a semiconductor structure according to an exemplary embodiment.
[0041] Figure 5 This is a schematic diagram illustrating the formation of a conductive layer during the formation of a semiconductor structure according to an exemplary embodiment.
[0042] Figure 6 This is a top view of a substrate provided during the formation of a semiconductor structure according to an exemplary embodiment.
[0043] Figure 7 yes Figure 6 Cross-sectional view of AA.
[0044] Figure 8 This is a schematic diagram illustrating the formation of a protective layer during the formation of a semiconductor structure according to an exemplary embodiment.
[0045] Figure 9 A schematic diagram of the morphology of a capping layer formed during the formation of a semiconductor structure at a deposition pressure in the range of 30-40 millitor, according to an exemplary embodiment.
[0046] Figure 10 A schematic diagram of the morphology of a capping layer formed during the formation of a semiconductor structure at a deposition pressure in the range of 20-30 millitor, according to an exemplary embodiment.
[0047] Figure 11 A schematic diagram of the morphology of a capping layer formed during the formation of a semiconductor structure at a deposition pressure in the range of 10-20 millitor, according to an exemplary embodiment.
[0048] Figure 12 A schematic diagram of the morphology of a capping layer formed during the formation of a semiconductor structure at a deposition pressure in the range of 3-10 millitor, according to an exemplary embodiment.
[0049] Figure 13 A schematic diagram illustrating the process of forming a semiconductor structure after removing the capping layer, according to an exemplary embodiment.
[0050] Figure 14 A schematic diagram illustrating the formation of capacitor contact holes during the formation of a semiconductor structure according to an exemplary embodiment.
[0051] Figure 15 A schematic diagram illustrating the formation of a capacitive contact plug during the formation of a semiconductor structure according to an exemplary embodiment.
[0052] Figure 16 A flowchart illustrating a method for forming a semiconductor structure according to another exemplary embodiment.
[0053] Figure 17 A flowchart illustrating a method for forming a semiconductor structure according to another exemplary embodiment.
[0054] Figure label:
[0055] 100, Substrate; 120, Dielectric Layer; 20, Bit Line Structure; 200, Capping Layer; 201, Bit Line Contact Hole; 202, Conductive Layer; 203, Sidewall Layer; 220, Slit; 30, Active Region; 300, Trench; 310, Trench Wall; 40, Word Line Structure; 410, Initial Contact Hole; 400, Capacitor Contact Hole; 50, Shallow Trench Isolation Structure; 500, Protective Layer; 600, Capacitor Contact Plug. Detailed Implementation
[0056] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0057] This disclosure provides an exemplary embodiment of a method for forming a semiconductor structure. By forming multiple spaced bit lines on a semiconductor substrate and creating contact holes on the semiconductor substrate, the loss at the top of the bit lines can be improved or reduced, avoiding any impact or defects on the top morphology of the bit lines, thus preventing a decrease in semiconductor device performance and a significant drop in semiconductor device yield. Figure 1 As shown, Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 2-15 The diagram below illustrates the various stages of a semiconductor structure formation process. Figures 2-15 The methods for forming semiconductor structures are introduced.
[0058] This embodiment does not limit the semiconductor structure. The following description uses Dynamic Magnetic Random Access Memory (DRAM) as an example, but this embodiment is not limited to this; other semiconductor structures are also possible. It should be understood that the semiconductor structure formed in this embodiment does not constitute a complete memory; this embodiment is merely a process for forming the storage structure of a semiconductor memory.
[0059] Understandably, Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, containing multiple memory cells arranged in a matrix structure. Each memory cell mainly consists of a transistor and a capacitor controlled by the transistor, and the memory cells are electrically connected to each other via word lines and bit lines. Data is input from the bit lines and then transferred to the capacitor via the transistor, or data stored in the capacitor is output via the transistor and bit lines.
[0060] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure. Figures 2-15 The diagram below illustrates the various stages of a semiconductor structure formation process. Figures 2-15 A method for forming a semiconductor structure is described, which includes the following steps:
[0061] Step S110: Provide a substrate, which includes multiple active regions.
[0062] refer to Figure 2 The substrate 100 serves as a support component for the memory, supporting other components disposed thereon. The substrate 100 can be made of a semiconductor material, such as a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate. In this embodiment, the substrate 100 is a silicon substrate.
[0063] refer to Figure 2 and Figure 6 The substrate 100 can be doped with ions; for example, the substrate 100 can be a P-type doped substrate or an N-type doped substrate. Multiple active regions 30 are arrayed within the substrate 100, arranged at intervals along the first direction X and the third direction Z. Both the first direction X and the third direction Z are parallel to the top surface of the substrate 100, and there is a preset angle between them, such as 21 degrees, 45 degrees, or 60 degrees, which can be set according to actual design requirements.
[0064] refer to Figure 2 A shallow trench isolation structure 50 is also provided within the substrate 100, and the active region 30 is formed between the shallow trench isolation structures 50. (Reference) Figure 2 and Figure 6 The formation of multiple active regions 30 within the substrate 100 is described in detail below. First, a patterned mask layer (not shown) can be formed above the substrate 100. The patterned mask layer has multiple opening patterns, and the locations of these opening patterns on the substrate 100 correspond to the locations where the active regions 30 are formed. Using the patterned mask layer as a mask, the substrate 100 is etched along the multiple opening patterns to expose the pre-formed active region patterns. For DRAM (Dynamic Random Access Memory), the active region patterns are typically obliquely staggered strips (not shown). Then, the substrate 100 is further etched to form isolation trenches (not shown). Next, isolation material is filled into the isolation trenches to form shallow trench isolation structures 50. The shallow trench isolation structure 50 includes one or more isolation materials such as silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the shallow trench isolation structure 50 includes silicon oxide. Multiple independent regions are defined on the substrate 100 by the shallow trench isolation structures 50 to form the active regions 30.
[0065] In this embodiment, the formation of the active region is not limited to this; for example, other conventional methods for forming the active region can also be used. The formation of the patterned mask layer is a conventional process, and the patterning process includes, but is not limited to, pre-baking, exposure, development, and post-baking processes, specifically implemented through photolithography, which will not be elaborated further here.
[0066] For example, such as Figure 6 As shown, a word line structure 40 is also disposed on the substrate 100, extending in the first direction X. The substrate 100 also includes other memory structures besides the word line structure 40, the active region 30, and the shallow trench isolation structure 50, for the normal operation of the memory.
[0067] Step S120: A plurality of bit line structures are formed on the substrate. The plurality of bit line structures are spaced apart along a first direction. There is a groove between two adjacent bit line structures. Each bit line structure extends along a second direction.
[0068] For example, such as Figure 7 As shown, discrete bitline structures 20 are formed on the substrate 100. Multiple bitline structures 20 are arranged alternately and repeatedly along a first direction X. Each bitline structure 20 extends along a second direction Y, which is the direction from the top surface of the substrate 100 to the bottom surface of the substrate 100. The angle between the first direction X and the second direction Y is a right angle. (Reference) Figure 6The bit line structure 20 is located in the direction X parallel to the top surface of the substrate 100, and the bit line structure 20 is at a preset angle to the active region 30. On a plane parallel to the top surface of the substrate, the bit line structure 20 is perpendicular to the word line structure 40.
[0069] refer to Figure 7 In the first direction X, a groove 300 is provided between any two adjacent bit line structures 20, and each groove 300 extends along the extension direction of the bit line structure 20. For example, the depth of the groove 300 is denoted as H (based on the position shown in the figure), and the groove 300 has a high aspect ratio, for example, the aspect ratio of the groove 300 can be greater than or equal to 10, such as 12:1, 15:1, or 20:1.
[0070] Step S130: Perform at least one cycle process to form a plurality of capacitor contact holes between a plurality of bit line structures, wherein the cycle process includes: forming a plurality of capping layers, the capping layers conformally covering the top surface and part of the side surface of the bit line structure to cover the top corner of the bit line structure, a slit is provided between two adjacent capping layers, the slit being located in a trench; etching the substrate along the slit and the trench to expose the active region within the substrate; and removing the plurality of capping layers.
[0071] To prevent structural defects at the top of the bit line structure due to losses during the formation of capacitor contact holes, this embodiment employs a deposited capping layer to add a protective film layer to the top corners of the bit line structure during substrate etching. This reduces damage to the top corners of the bit line structure caused by the etching process, thereby avoiding adverse effects of the etching process on device performance.
[0072] Reference Figure 9 As shown, a capping layer 200 can be formed on the top of each bitline structure 20 through a deposition process. The capping layer 200 conformally covers the top surface of the bitline structure 20 and the portion of the side surface connected to the top surface, thereby covering the apex corner of the bitline structure 20 and protecting the top of the bitline structure 20 during the subsequent process of forming capacitor contact holes. The apex corner of the bitline structure 20 can be the connection point between the top surface and the side surface of the bitline structure 20, or within a predetermined range of the connection point between the top surface and the side surface of the bitline structure 20, such as... Figure 8 The area shown is 'a'.
[0073] refer to Figure 9In the process of forming the capping layer, certain process conditions, such as deposition pressure, ambient temperature, and deposition time, have a certain influence on the morphology and structure of the capping layer. During this process, the height of the capping layer covering the side surface of the bitline structure is inversely proportional to the deposition pressure in a single cycle. If the ambient temperature is too high (e.g., greater than 40°C) or the deposition pressure is too high (e.g., greater than 40 mTorr), the thickness of the capping layer 200 formed on the side surface of the bitline structure 20 will be too thick, causing blockage of the top opening of the trench 300 and hindering etching. If the gas cannot contact the substrate 100, it will affect the subsequent etching process of the capacitor contact holes. If the ambient temperature is too low (e.g., below 10°C) or the deposition pressure is too low, the ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness covering the side surface will be smaller. For example, if the deposition pressure is less than 3 mTorr, the thickness of the capping layer 200 at the top of the bit line structure 20 may be too thin. During the contact hole etching process, if the etching time is long, the capping layer 200 will not be able to protect the top of the bit line structure 20. Therefore, the morphology of the capping layer can be controlled by controlling one or more of the deposition pressure, ambient temperature, and deposition time in the process chamber to form a capping layer with suitable thickness and shape on the top of the bit line structure.
[0074] For example, in selecting the material for the capping layer, to facilitate subsequent removal, a material that is easy to remove can be chosen, and one that will not affect other structures during the removal process. For example, carbon and short-chain carbon polymers can be selected as the capping layer material. Here, carbon material refers to a material containing carbon, and short-chain carbon polymers are polymers whose macromolecular backbone is entirely composed of carbon atoms. For example, a short carbon chain can have 5 or fewer carbon atoms.
[0075] For example, refer to Figure 9 and Figure 14 The following example illustrates the process of forming multiple capacitor contact holes between multiple bitline structures using a single cyclic process. For instance, a substrate 100 is pre-placed within a reaction chamber. Carbon-containing gas is introduced into the reaction chamber through vents. During the introduction of the carbon-containing gas, the deposition pressure within the reaction chamber is simultaneously controlled within the range of 3 mTorr-40 mTorr to control the reaction products generated by the carbon-containing gas reacting with the reaction gas within the chamber. These reaction products contact the top surface of each bitline structure 20 and extend from the top surface of the bitline structure 20 to the side surface of the bitline structure 20. (Reference) Figure 9 The reaction products are concentrated on the top surface and part of the side surface of the bit line structure 20, forming a capping layer 200. The capping layer 200 covers the top surface and side surface of the bit line structure according to the morphology of the top of the bit line structure 20.
[0076] For example, the reaction gas in the reaction chamber may include fluoromethane (CH3F), helium (He), etc. During the deposition of the capping layer, the reaction gas reacts with carbon on the top surface of the dot line structure 20 to form carbon and carbon chain polymers such as carbon short-chain polymers as reaction products. Then the reaction products continue to diffuse downward along the side surface connected to the top surface of the dot line structure. Since the carbon chain polymer has a certain viscoelasticity, the formed capping layer can easily adhere to the top of the dot line structure.
[0077] For example, during the formation of the capping layer in a single cycle process, reference Figure 9 The thickness of the capping layer on the top surface of the bitline structure 20 is controlled within a ratio of (1-3):1 to the thickness of the capping layer on the side surface of the bitline structure 20. For example, it can be 1:1, 2:1, or 3:1 to prevent the capping layer with a poor morphology from failing to protect the top of the bitline structure. The thickness of the capping layer 200 covering the top surface of the bitline structure 20 can be the maximum distance from the top surface of the bitline structure 20 to the surface of the capping layer 200 in the second direction Y; the thickness of the capping layer 200 covering the side surface of the bitline structure 20 can be the maximum distance from the side surface of the bitline structure 20 to the surface of the capping layer 200 in the first direction X.
[0078] The temperature within the reaction chamber and the deposition pressure also have an impact. In some exemplary embodiments, during the formation of the capping layer in a single cycle process, the ambient temperature can be controlled within the range of 10°C to 40°C, thereby utilizing the temperature conditions within the reaction chamber to adjust and control the thickness of the top surface and the side surface of the capping layer covering the bit line structure.
[0079] In some exemplary embodiments, the thickness of the capping layer can increase uniformly with increasing deposition time during the formation of the capping layer. Therefore, the film thickness of the capping layer can be effectively adjusted by appropriately increasing or decreasing the deposition time. For example, in a single-cycle process, the deposition time of the capping layer can be controlled within the range of greater than or equal to 5 seconds and less than or equal to 20 seconds.
[0080] In this embodiment, during the formation process of the capping layer, the ratio of the thickness of the capping layer covering the top surface and the side surface of the bit line structure, as well as the height of the capping layer covering the side surface of the bit line structure, are adjusted by controlling one or more process conditions, including deposition pressure, ambient temperature, and deposition time, so as to control the morphology of the capping layer formed on the top of the bit line structure, thereby forming a capping layer that can effectively protect the top corner of the bit line structure.
[0081] In some exemplary embodiments, reference is made to Figure 9Furthermore, the height of the capping layer 200 covering the side surface near the apex corner of the bitline structure 20 can be controlled by adjusting process parameters such as deposition pressure, ambient temperature, and deposition time within the chamber. To effectively protect the apex corner of the bitline structure, the height of the capping layer 200 covering the side surface of the bitline structure 20 can be controlled to be 1 / 10 to 2 / 5 of the height of the bitline structure 20. For example, the height of the capping layer 200 on the side surface of the bitline structure 20 can be 1 / 10, 1 / 5, 3 / 10, or 2 / 5 of the height of the bitline structure 20. In this embodiment, the capping layer completely covers the side surface near the apex corner of the bitline structure, thus providing effective protection for the apex corner.
[0082] like Figure 9 As shown, the capping layer 200 has a certain height on the side surface of the bit line structure 20, such that the capping layers 200 on two adjacent bit line structures 20 are separated by the trench 300 (reference). Figure 7 A slit 220 is formed in the substrate so that subsequent etching gas can pass through the slit and contact the substrate 100 to etch the substrate 100.
[0083] refer to Figure 9 During deposition, the capping layer 200 extends from the top surface of the dot line structure 20 towards the side surface. As the deposition process progresses, the diameter of the slit 220 gradually increases along the direction from the top surface to the bottom surface of the dot line structure. For example, the diameter of the slit 220 can be in the range of 1 / 3 to 1 / 2 of the diameter of the trench 300. Figure 9 As shown, since the capping layer 200 forms a slit 220 in the trench 300, a dry etching process can be used to utilize the etching gas to contact the substrate 100 vertically downward along the slit 220 and the trench 300, thereby realizing a maskless dry etching process to etch the substrate 100 until the active region 30 in the substrate 100 is exposed. This eliminates the step of forming a mask layer, simplifies the process, and saves time and costs.
[0084] refer to Figure 9 , combined Figure 14 As shown, in step S130, the surface of the substrate 100 is etched along the slit 220 and the trench 300, and continues to extend into the substrate 100 to expose the active region 30 within the substrate 100. Then, an ashing process can be used to remove the capping layer 200 on top of each bit line structure 20, and a capacitor contact hole 400 is formed at the bottom of the trench 300 between any two adjacent bit line structures 20. Figure 14 As shown, capacitor contact hole 400 is a contact hole used for connection with other device structures such as capacitors.
[0085] For example, during the etching process of the substrate, the etching gas needs to be selected as a gas that hardly etches the capping layer. For example, the etching gas may include one or more of the following gases: tetrafluoromethane, octafluorocyclobutane, and argon.
[0086] In this embodiment, the process of removing the capping layer 200 using the ashing process will not cause damage to the top corner of the bit line structure 20, thereby ensuring that the top corner of the bit line structure 20 is not damaged.
[0087] Step S140: After performing at least one cycle of the process, a capacitor contact plug is formed in the capacitor contact hole.
[0088] like Figure 14 and 15 As shown, the trench 300 communicates with the capacitor contact hole 400 along the direction from the top surface of the bit line structure 20 to the bottom surface of the substrate 100. After removing the capping layer, conductive material can be filled into each capacitor contact hole 400 by a deposition process to form a plurality of capacitor contact plugs 600. The conductive material fills the capacitor contact hole 400 and the trench 300. The top surface of the capacitor contact plug 600 can be flush with the top surface of the bit line structure 20 or higher than the top surface of the bit line structure 20.
[0089] like Figure 14 and Figure 15 As shown, the capacitor contact plug 600 is in surface contact with the active region 30 exposed by the capacitor contact hole 400, so that the active region can form an electrical interconnect with the capacitor structure through the capacitor contact structure in subsequent processes.
[0090] The conductive material may be tungsten or cobalt, or at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a metal (e.g., tungsten, titanium, or tantalum).
[0091] like Figure 16 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure. Most of the content of the semiconductor structure forming method in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that this embodiment is another optional implementation of step S130 in the above embodiments.
[0092] In this embodiment, the method for forming the semiconductor structure includes:
[0093] Step S210: Provide a substrate, which includes multiple active regions.
[0094] Step S220: A plurality of bit line structures are formed on the substrate. The plurality of bit line structures are spaced apart along a first direction. There is a groove between two adjacent bit line structures. Each bit line structure extends along a second direction.
[0095] Step S230: Repeat multiple cycle processes to form multiple capacitor contact holes between multiple bit line structures, wherein the deposition pressure of the capping layer is constant between the multiple cycle processes.
[0096] Step S240: Form a capacitor contact plug inside the capacitor contact hole.
[0097] The implementation methods of steps S210-S220 in this embodiment are the same as those of steps S110-S120 in the above embodiment, and the implementation methods of step S240 in this embodiment are the same as those of step S140 in the above embodiment. Therefore, they will not be described again here.
[0098] During the formation of the capping layer, different process environments result in varying structural morphologies. This leads to differences in the thickness of the capping layer covering the top surface of the bitline structure and the ratio of its thickness covering the side surfaces. The morphology of the capping layer plays a decisive role in protecting the apex corners of the bitline structure, thus affecting its protective effect. For example, if an excessively thick capping layer is formed in a single process, the slit diameter between adjacent capping layers may be too small, blocking the top opening of the trench. Consequently, etching gas cannot reach the bottom of the substrate, hindering etching. Conversely, if the capping layer is too thin, the etching time during capacitor contact hole formation may be too long, rendering it ineffective in protecting the top of the bitline structure. Therefore, in this embodiment, multiple cyclic processes can be executed to form capping layers with well-defined morphologies each time. This approach aims to effectively protect the top of the bitline structure while minimizing the impact of the capping layer on substrate etching.
[0099] For example, in step S230, the process is described by performing 4 to 10 cycles to form multiple capacitor contact holes between multiple bit line structures, wherein the deposition pressure for forming the capping layer is constant in each cycle. For example, the deposition pressure is selected in the range of 3-10 mTorr, such as 7 mTorr. Figure 12 , Figure 13 and Figure 14As shown, performing the first cycle includes the following steps: controlling the process chamber under a deposition pressure of 7 mTorr, forming a capping layer 200 on top of each bitline structure 20, the capping layer 200 covering the apex corner of each bitline structure 20, wherein the ratio of the thickness of the capping layer 200 covering the top surface of the bitline structure 20 to the thickness of the capping layer 200 covering the side surface of the bitline structure 20 is approximately 1.1:1. (Reference) Figure 12 Under this deposition pressure, the overall thickness of the capping layer 200 is relatively uniform. For example... Figure 13 As shown, a slit 220 is provided between two adjacent capping layers. For example, the diameter of the slit 220 is half the diameter of the trench 300. The capping layer 200, while forming a protective layer at the apex of the bitline structure, maximizes the gap between the slits to allow etching gas to pass smoothly through the slit 220, thereby reducing the impact of the capping layer on the substrate etching. Then, the substrate 100 is etched vertically downwards along the slit 220 and the trench 3000 using an etching process to form an initial contact hole 410 with an initial morphological structure. Finally, the capping layer 200 is removed.
[0100] refer to Figure 13 Since the initial contact hole 410 formed in the first cycle process does not expose the active region 30 within the substrate 100, a second cycle process is sequentially executed according to the above procedure to further deepen the initial contact hole 410. If the initial contact hole 410 deepened by the second cycle process still does not expose the active region 30 within the substrate 100, a third cycle process is executed, exemplarily until the tenth cycle process, at which point the deepened initial contact hole 410 exposes the active region 30 within the substrate 100. Figure 14 As shown, a capacitor contact hole 400 with a target size is formed in the substrate 100, and the capacitor contact hole 400 exposes the active region 30.
[0101] In this embodiment, during the execution of multiple cycle processes, the deposition pressure in the process chamber can be controlled to be at the same constant value during each process of forming the capping layer, so that the morphology of the capping layer formed each time is consistent, thereby effectively protecting the top of the bit line structure during the etching of the substrate.
[0102] In some exemplary embodiments, during the formation of capacitor contact holes, the capping layer on the top surface of the bit line structure may be lost. Therefore, the deposition pressure can be increased to control the concentrated formation of the capping layer on the top surface of the bit line structure, thereby increasing the thickness of the capping layer covering the top surface of the bit line structure, so as to prevent the capping layer from exposing the top corner of the bit line structure during the etching process.
[0103] For example, in a single-cycle process, the deposition pressure for forming the capping layer is selected, for instance, within the range of 10-20 mtorr. Figure 11 As shown, in a single cycle process, the deposition pressure for forming the capping layer is controlled at 15 mTorr. The ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness of the capping layer 200 covering the side surface of the bit line structure 20 is approximately 2:1, which concentrates the capping layer on the top surface of the bit line structure, thereby increasing the thickness of the capping layer covering the top surface of the bit line structure.
[0104] In some exemplary embodiments, the deposition pressure for forming the capping layer in a single-cycle process can also be selected within the range of 20-40 mtorr. For example... Figure 9 As shown, in each cycle of the process, the process chamber is controlled to form a capping layer 200 under a deposition pressure of 30 mTorr. The thickness of the capping layer 200 covering the top surface of the bit line structure 20 is approximately 2.8:1, thereby further increasing the thickness of the capping layer covering the top surface of the bit line structure.
[0105] In this embodiment, by performing the cyclic process multiple times under the same deposition pressure to form the capping layer, the morphology of the capping layer formed each time can be made to be basically consistent. Furthermore, the morphology of the capping layer covering the top of the bit line structure can be controlled by adjusting the deposition pressure, thereby enabling the capping layer to effectively protect the top of the bit line structure.
[0106] Figure 17 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure. Most of the content of the semiconductor structure forming method in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that this embodiment is another optional implementation of step S230 in the above embodiments. In this embodiment, when implementing multiple cycle processes, the capping layer is formed by gradually reducing the deposition pressure between the multiple cycle processes.
[0107] In this embodiment, the method for forming the semiconductor structure includes:
[0108] Step S310: Provide a substrate, which includes multiple active regions.
[0109] Step S320: A plurality of bit line structures are formed on the substrate. The plurality of bit line structures are spaced apart along a first direction. There is a groove between two adjacent bit line structures. Each bit line structure extends along a second direction.
[0110] Step S330: Repeat multiple cycle processes to form multiple capacitor contact holes between multiple bit line structures, wherein, during the implementation of multiple cycle processes, the deposition pressure for forming the capping layer gradually decreases between multiple cycle processes.
[0111] Step S340: Form a capacitor contact plug inside the capacitor contact hole.
[0112] Steps S310-S320 in this embodiment are implemented in the same way as steps S110-S120 in the above embodiment, and step S340 in this embodiment is implemented in the same way as step S140 in the above embodiment. Therefore, they will not be described again here.
[0113] The following example illustrates the formation of a capping layer using a four-cycle process, with the deposition pressure gradually decreasing between cycles. Figures 9 to 12 As shown, the morphology of the capping layer 200 formed on top of the bitline structure 20 is illustrated under four deposition pressure ranges. For ease of explanation, four cycle process pressure ranges are defined, wherein, as... Figure 9 As shown, an exemplary morphological structure of a capping layer 200 formed when the deposition pressure is controlled within the range of 30-40 mtorr is illustrated. Figure 10 As shown, an exemplary morphological structure of a capping layer 200 formed when the deposition pressure is controlled within the range of 20-30 mtorr is illustrated. Figure 11 As shown, an exemplary morphological structure of a capping layer 200 formed when the deposition pressure is controlled within the range of 10-20 mtorr is illustrated. Figure 12 As shown, an exemplary morphological structure of a capping layer 200 formed when the deposition pressure is controlled within the range of 3-10 mtorr is illustrated.
[0114] like Figure 9 and Figure 13 As shown, the deposition pressure in the control process chamber is kept within the range of 30-40 mtorr, and the first cycle process is performed to form the capping layer 200 under this deposition pressure. Then, the substrate 100 is etched along the slit 220 and the trench 300 to form an initial contact hole 410 with an initial morphological structure within the substrate 100. The depth of the initial contact hole 410 is denoted as D1. The capping layer 200 is removed by an ashing process. The initial contact hole 410 formed in this process does not expose the active region within the substrate 100. In the first cycle process, the ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness of the capping layer 200 covering the side surface of the bit line structure 20 is denoted as A. The range of A can be 1-3, for example, 2.9 or 3.
[0115] Then, gradually reduce the deposition pressure, controlling it within the 20-30 mtorr range in the process chamber, and execute the second cycle of the process. Figure 10 and Figure 13 As shown, a capping layer 200 is formed on top of the bit line structure 20. In the second cycle, the ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness of the capping layer 200 covering the side surface of the bit line structure 20 is denoted as B. In the second cycle, the deposition pressure is reduced. As the deposition pressure decreases, the ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness of the capping layer 200 covering the side surface of the bit line structure 20 gradually decreases, making the value of B less than the value of A, for example, B is 2.5. Then, the initial contact hole 410 is further etched using an etching process to remove the capping layer 200. The initial contact hole 410 formed in this process still does not expose the active region within the substrate 100.
[0116] Next, the deposition pressure was further reduced, and the deposition pressure in the process chamber was controlled at 10-20 mtorr, and the third cycle of the process was executed. Figure 11 and Figure 13 As shown, a capping layer 200 is formed on top of the bit line structure 20. In the third cycle process, the ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness of the capping layer 200 covering the side surface of the bit line structure 20 is denoted as C. In this cycle process, the overall thickness of the capping layer 200 becomes thinner, and the overall thickness of the capping layer 200 is less than the overall thickness of the capping layer formed in the second cycle process. In this step, the ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness of the capping layer 200 covering the side surface of the bit line structure 20 is denoted as C. The value of C is less than the value of B, for example, C is 2.2. Then, the initial contact hole 410 is further etched using an etching process, and then the capping layer 200 is removed. The initial contact hole 410 formed in this process may not expose the active region in the substrate 100, or it may expose the active region in the substrate 100.
[0117] To ensure stable contact between the active region and the capacitor contact plug, the deposition pressure can be further reduced, controlling the deposition pressure in the process chamber to 3-10 mtorr, and performing the fourth cycle of the process. Figure 12 and Figure 13 As shown, a thinner capping layer 200 is formed on top of the bit line structure 20. In this cycle process, the ratio of the thickness of the capping layer 200 covering the top surface of the bit line structure 20 to the thickness of the capping layer 200 covering the side surface of the bit line structure 20 is denoted as D, where the value of D is less than the value of C, for example, D is 1.2. Then, the initial contact hole 410 is etched to form a capacitor contact hole 400, which exposes a portion of the surface of the active region within the substrate 100. The capping layer 200 is then removed. Finally, as shown... Figure 14 As shown, a capacitor contact hole 400 is formed that conforms to the target size.
[0118] In this embodiment, during the etching of capacitor contact holes, the deposition pressure of each capping layer can be gradually reduced according to the formation progress of the capacitor contact holes. By gradually reducing the deposition pressure, a thinner capping layer can be formed successively at the top corner of the bit line structure, resulting in a capping layer of suitable thickness. In the process of successively etching the substrate, this not only achieves the purpose of protecting the top corner of the bit line structure, but also saves process time and process steps.
[0119] This disclosure provides an exemplary embodiment of a method for forming a semiconductor structure. Most of the content of the semiconductor structure forming method in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that this embodiment is an optional implementation of forming multiple bit line structures on a substrate in the above embodiments.
[0120] The steps of forming multiple bitline structures on the substrate in this embodiment can be as follows:
[0121] An initial conductive layer is deposited on a substrate and etched along a first direction to form a plurality of conductive layers spaced apart along the first direction, each conductive layer extending along a second direction;
[0122] Sidewall layers are formed on the surface of the conductive layer, and grooves are formed between adjacent sidewall layers;
[0123] A protective layer is formed on the surface of the sidewall layer and the trench to protect the sidewall layer and the base.
[0124] Combination Figure 2 Zhihe Figure 7 As shown, a dielectric layer 120 is formed above the active region 30. The dielectric layer 120 is a single-layer film structure or a multi-layer film composite structure to form a flat top surface on the substrate 100. An initial conductive layer 130 is formed on the dielectric layer 120, and multiple opening patterns are formed along the first direction X. The dielectric layer 120 is etched along the opening patterns to extend into the substrate 100, exposing the top surface of the active region 30. The etching continues along the top surface of the active region 30 in a direction perpendicular to the bottom surface of the substrate 100 to form a bit line contact window 201. The bit line contact window 201 serves as the contact hole between the bit line structure formed in subsequent processes and the active region 30.
[0125] An initial conductive layer is deposited on the substrate 100 and etched along a first direction X to divide the initial conductive layer into a plurality of conductive layers 202 spaced apart along the first direction X, each conductive layer extending along a second direction Y; the second direction Y is the direction from the top surface of the substrate 100 to the bottom surface of the substrate 100. Finally, a sidewall layer 203 is deposited on the surface of the conductive layer 202, wherein the conductive layer 202 and the sidewall layer 203 form the main structure of the bit line structure 20, and the sidewall layer 203 is, for example, a silicon nitride material.
[0126] Exemplarily, the conductive layer includes a bit line contact layer, a metal layer, and a top dielectric layer (not shown) stacked sequentially. Exemplarily, the bit line contact layer is made of tungsten or polysilicon; the metal layer can be a single conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, or tungsten composites; the top dielectric layer is made of silicon nitride, silicon dioxide, or silicon oxynitride. The bit line contact layer also includes a bit line contact window (not shown), in a direction X parallel to the substrate, where only one of three consecutive bit line structures connects to an active region in the substrate through the bit line contact window. The bit line contact window is made of tungsten or polysilicon.
[0127] like Figure 7 As shown, the trench wall 310 of the trench 300 is formed by the exposed sidewall layer 203 of the bit line structure 20. In order to reduce the loss of etching gas to the sidewall layer 203 of the bit line structure 20 during the subsequent process of forming contact holes, combined with Figure 7 and Figure 8 As shown, a protective layer 500 can be formed on the bottom surface of the sidewall layer 203 and the trench 300 using a deposition process. The protective layer 500 covers the sidewalls of the bitline structure 20 and a portion of the surface of the substrate 100 exposed by the trench 300, thereby protecting the sidewall layer 203 of the bitline structure 20 and the surface of the substrate 100 from etching. Exemplarily, the protective layer can be one or more combinations of silicon dioxide, silicon nitride, and silicon oxynitride.
[0128] The protective layer 500 of the sidewall layer 203 covering the bit line structure 20 can also serve as a spacer sidewall, which can form electrical isolation for the sidewall layer 203 of the bit line structure 20 in subsequent processes.
[0129] For example, refer to Figure 9 and Figure 14 As shown, during the etching process at the bottom of the trench 300, etching gas can be used to etch the protective layer located on the bottom wall of the trench 300 and the bottom wall of the trench 300 until the active region 30 located within the substrate 100 is exposed. During each etching process along the bottom of the trench 300 towards the substrate 100, the etching gas also etches the trench wall 310 (in...) Figure 7 As shown in the figure, part of the protective layer 500 on the surface will be worn away, and part of the protective layer 500 will be retained. Due to the presence of this part of the protective layer, the sidewalls of the bit line structure can maintain their original appearance, thus improving the performance of the bit line structure.
[0130] In some exemplary embodiments, the material used to fabricate the capping layer can be different from the material used to fabricate the protective layer. For example, a material with a high etching selectivity relative to the protective layer material can be selected to minimize capping layer loss during subsequent etching processes, ensuring the covered portion remains intact. This effectively protects the top of the bitline structure, thus helping to maintain the top morphology of the bitline structure 20. For example, in subsequent etching processes, the etching selectivity of the capping layer relative to the protective layer can be controlled to be above 10.
[0131] like Figure 15 As shown, an exemplary embodiment of this disclosure provides a semiconductor structure, which is prepared by the semiconductor structure formation method provided in the above embodiment. The top of the bit line structure in the semiconductor structure has a complete morphological structure and no structural defects, thereby improving the performance of the semiconductor structure.
[0132] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0133] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.
[0134] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0135] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.
[0136] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
[0137] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.
[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, The method for forming the semiconductor structure includes: A substrate is provided, wherein the substrate includes a plurality of active regions; Multiple bit line structures are formed on the substrate, the multiple bit line structures are spaced apart along a first direction, a groove is provided between two adjacent bit line structures, and each bit line structure extends along a second direction; Perform at least one cycle process to form a plurality of capacitor contact holes between the plurality of said bit line structures, wherein the cycle process includes: Multiple capping layers are formed, which conformally cover the top surface and part of the side surface of the bit line structure to cover the top corner of the bit line structure. There is a slit between two adjacent capping layers, which is located in the groove. The diameter of the slit gradually increases in the direction from the top surface to the bottom surface of the bit line structure. The capping layer includes carbon and short-chain polymers of carbon. The substrate is etched along the slits and the trenches to expose the active regions within the substrate; Remove the plurality of the capping layers; After performing at least one cycle of the process, a capacitor contact plug is formed in the capacitor contact hole.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The diameter of the slit is 1 / 3 to 1 / 2 of the diameter of the groove.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, The height of the capping layer covering the side surface of the bit line structure is 1 / 10 to 2 / 5 of the height of the bit line structure.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, The ratio between the thickness of the capping layer covering the top surface of the bit line structure and the thickness of the capping layer covering the side surface of the bit line structure is (1-3):
1.
5. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The deposition pressure for forming the capping layer in a single cycle is greater than or equal to 3 mtorr and less than or equal to 40 mtorr, and the height of the capping layer covering the side surface of the bitline structure is inversely proportional to the deposition pressure for forming the capping layer in the single cycle.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, The deposition time for forming the capping layer in a single cycle process is greater than or equal to 5 seconds and less than or equal to 20 seconds.
7. The method for forming a semiconductor structure according to claim 5, characterized in that, The forming method includes performing 4 to 10 cycle processes to form a plurality of capacitor contact holes between the plurality of bit line structures.
8. The method for forming a semiconductor structure according to claim 7, characterized in that, When multiple cycles are implemented, the deposition pressure for forming the capping layer remains constant between the multiple cycles.
9. The method for forming a semiconductor structure according to claim 7, characterized in that, When multiple cycles are implemented, the deposition pressure for forming the capping layer gradually decreases between the multiple cycles.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The process is repeated four times, among which... In the first cycle process, the deposition pressure for forming the capping layer is 30-40 mtorr; In the second cycle process, the deposition pressure for forming the capping layer is 20-30 mtorr; In the third cycle process, the deposition pressure for forming the capping layer is 10-20 mtorr; In the fourth cycle, the deposition pressure for forming the capping layer is 3-10 mtorr.
11. The method for forming a semiconductor structure according to claim 1, characterized in that, A method for forming multiple bit line structures on the substrate includes: An initial conductive layer is deposited on the substrate, and the initial conductive layer is etched along the first direction to form a plurality of conductive layers spaced apart along the first direction, each of the conductive layers extending along a second direction; A sidewall layer is formed on the surface of the conductive layer, and the trench is provided between adjacent sidewall layers; A protective layer is formed on the surface of the sidewall layer and the trench to protect the sidewall layer and the substrate.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, The etching selectivity ratio of the capping layer and the protective layer is greater than 10.
13. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the semiconductor structure formation method as described in any one of claims 1 to 12.