Memory and storage systems

Abstract

The embodiment of the present disclosure provides a memory and a storage system, the memory comprises: a substrate; a control circuit layer located in the substrate; at least part of the control circuit of the memory is included in the control circuit layer; at least two storage structure layers; the at least two storage structure layers are sequentially stacked on the control circuit layer in a first direction; the first direction is perpendicular to the surface of the substrate; the storage structure layer is connected with the control circuit layer; the storage structure layer comprises: a plurality of storage units arranged in an array; the storage unit comprises a selection transistor and a storage structure connected with the selection transistor; the selection transistor comprises: a channel structure, the channel structure has at least two layers of nanosheets arranged in a stacked manner in the first direction; and a gate structure surrounding the channel structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a memory and a memory system. Background Technology

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. Among them, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers.

[0003] Random access memory (RAM) consists of a memory array composed of many repeating memory cells. Each memory cell includes a selection transistor and a memory structure connected to the selection transistor. Different states of the memory structure represent stored information, i.e., "0" or "1". To improve the storage capacity of memory, semiconductor devices are required to have higher storage density and smaller feature sizes. How to integrate more memory cells within a unit area and reduce the footprint of individual devices, as well as how to improve the electrical performance of memory, have become pressing problems for the industry. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory and a storage system.

[0005] In a first aspect, embodiments of this disclosure provide a memory, comprising: a substrate; a control circuit layer located within the substrate; the control circuit layer including at least a portion of the control circuitry of the memory; at least two memory structure layers; the at least two memory structure layers being sequentially stacked on the control circuit layer in a first direction; the first direction being perpendicular to the surface of the substrate; the memory structure layers being connected to the control circuit layer; the memory structure layers including: a plurality of memory cells arranged in an array; each memory cell including a selection transistor and a memory structure connected to the selection transistor; the selection transistor including: a channel structure having at least two nanosheets stacked in the first direction; and a gate structure surrounding the channel structure.

[0006] In some embodiments, at least two layers of the nanosheets overlap in projection onto the substrate.

[0007] In some embodiments, in the first direction, there is a gap between at least two layers of the nanosheets; the gate structure surrounds each layer of the nanosheets through the gap.

[0008] In some embodiments, the selection transistor further includes: a first source-drain structure and a second source-drain structure, respectively connected to both ends of the channel structure in a second direction; the second direction is parallel to the surface of the substrate; and the storage structure is connected to the first source-drain structure.

[0009] In some embodiments, the storage structure includes: a storage capacitor located above the first source-drain structure; the projection area of ​​the storage capacitor on the select transistor at least partially overlaps with the area where the select transistor is located; and a first connection structure connected between the storage capacitor and the first source-drain structure.

[0010] In some embodiments, the select transistors of two adjacent memory cells in the second direction share the same second source-drain structure; the two select transistors sharing the second source-drain structure are symmetrically arranged about the second source-drain structure.

[0011] In some embodiments, the volume of the second source / drain structure is larger than the volume of the first source / drain structure.

[0012] In some embodiments, the memory further includes: a first connection line located between two adjacent memory structure layers; and the second source-drain structures of two adjacent select transistors in the first direction connected to the same first connection line.

[0013] In some embodiments, the memory further includes: a bit line structure layer located between the bottommost memory structure layer and the control circuit layer; the bit line structure layer includes a plurality of parallel bit lines extending along a third direction; the third direction is parallel to the surface of the substrate; the third direction is parallel to the second direction or has an angle between the third direction and the second direction; each bit line connects a plurality of memory cells arranged along the third direction, wherein each group of memory cells is a plurality of memory cells stacked in a direction perpendicular to the surface of the substrate, connected by the first connection line.

[0014] In some embodiments, the storage structure layer includes: a plurality of storage blocks; each storage block has a plurality of storage cells; the control circuit layer includes: a plurality of control blocks connected to each of the storage blocks; wherein each bit line connects the control block and a plurality of sets of storage cells in the plurality of storage blocks.

[0015] In some embodiments, the region where the control block is located at least partially overlaps with the projection region of the storage block to which the control block is connected on the control circuit layer.

[0016] In some embodiments, the control block includes a first control block connected to the bit line.

[0017] In some embodiments, the gate structures of a plurality of memory cells located on the same straight line extending along a fourth direction in the memory block are interconnected and connected to the control block; the fourth direction is parallel to the surface of the substrate; and the fourth direction is not parallel to the third direction.

[0018] In some embodiments, the control block includes a second control block connected to the gate structure.

[0019] Secondly, embodiments of this disclosure provide a storage system, including: a memory as described in any of the above embodiments; and a storage controller.

[0020] In the memory provided in the embodiments of this disclosure, at least two memory structure layers are sequentially stacked on a control circuit layer. The channel structure of the selected transistor in the memory cell has at least two nanosheets stacked in a first direction, and the gate structure surrounds the channel structure. Thus, on the one hand, the stacked memory structure layers and control circuit layer occupy a smaller area, improving the integration density of the memory; on the other hand, the stacked at least two nanosheets increase the current when the selected transistor is turned on, which is beneficial for improving the electrical performance of the selected transistor. Attached Figure Description

[0021] Figure 1 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0022] Figure 2 A schematic diagram of another memory provided for an embodiment of this disclosure;

[0023] Figure 3 A schematic diagram of yet another type of memory provided in an embodiment of this disclosure;

[0024] Figure 4 A schematic diagram of another sensing amplifier circuit in a memory provided in an embodiment of this disclosure;

[0025] Figure 5 A schematic diagram of another sub-word line driving circuit in a memory provided in an embodiment of this disclosure;

[0026] Figure 6 This disclosure provides a schematic diagram of a storage system according to an embodiment. Detailed Implementation

[0027] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0028] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0029] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0030] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0032] like Figure 1As shown, this disclosure provides a memory 10, including: a substrate 100; a control circuit layer 110 located within the substrate; the control circuit layer 110 including at least a portion of the control circuitry of the memory 10; at least two memory structure layers 120; the at least two memory structure layers 120 being stacked sequentially on the control circuit layer 110 in a first direction; the first direction being perpendicular to the surface of the substrate 100; the memory structure layers 120 being connected to the control circuit layer 110; the memory structure layer 120 including: a plurality of memory cells 130 arranged in an array; each memory cell 130 including a selection transistor 131 and a memory structure 132 connected to the selection transistor 131; the selection transistor 131 including: a channel structure 133 having at least two nanosheets 134 stacked in the first direction; and a gate structure 135 surrounding the channel structure 133.

[0033] In this embodiment, the memory 10 may include, but is not limited to, DRAM, Static Random Access Memory (SRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Nano Random Access Memory (NRAM). The substrate 100 may be made of elemental semiconductor materials, such as silicon (Si) or germanium (Ge), or compound semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP). The substrate 100 may also be doped, or may include doped and undoped regions. It should be understood that, in order to clearly show each layer structure in the figures, the dimensional ratios of each layer structure may not conform to the actual structure. It is worth noting that the horizontal direction in this disclosure refers to the direction parallel to the surface of the substrate 100, including but not limited to the X and Y directions, while the vertical direction refers to the direction perpendicular to the surface of the substrate 100, such as the Z direction.

[0034] In some embodiments, the control circuitry and the memory cell array are located in the same plane parallel to the substrate surface, with the control circuitry positioned horizontally around the memory cell array. This results in a larger horizontal footprint and lower integration density for the memory. Understandably, to achieve higher storage density in this case, the size of the memory cells needs to be further reduced, leading to greater manufacturing complexity. Furthermore, due to the significant height difference between the control circuitry and the memory cell array in the vertical direction, and the fact that they are formed in the same process, the conductive connectors (Licon) in the control circuitry are relatively tall, resulting in higher contact resistance. This affects the transistor drive current, leading to poorer memory performance.

[0035] In the embodiments disclosed herein, such as Figure 1 As shown, the control circuit layer 110 is located in the substrate 100, and the control circuit layer 110 has at least a portion of the control circuitry for the memory 10. Exemplarily, the control circuit layer 110 includes, but is not limited to, a sub-word line driver (SWD), a sense amplifier (SA), a row decoder, a column decoder, a fuse repair circuit, a power supply circuit, and data input / output circuits. The control circuit layer 110 can be used for decoding, detecting the memory cell array, and controlling the memory cell array to perform operations such as writing and reading data.

[0036] At least two sequentially stacked memory structure layers 120 are located on the control circuit layer 110, meaning at least two memory structure layers 120 are located on the surface of the control circuit layer 110 away from the substrate 100, and are stacked along a first direction, which can be the Z direction. Each memory structure layer 120 may include multiple arrayed memory cells 130, each memory cell 130 being connected to the control circuit layer 110 via word lines, bit lines, and other connection structures. The memory cells 130 can perform data writing and reading operations according to control signals issued by the control circuit layer 110. Each memory cell 130 may include a selection transistor 131 and a memory structure 132 connected to the selection transistor 131. The selection transistor 131 controls the signal connection between the memory cell 130 and the control circuit layer 110. When writing or reading data to or from the memory cell 130, the selection transistor 131 needs to be switched to an on state to change or obtain the storage state of the storage structure 132. Different storage states of the storage structure 132 represent different data information. Storage structure 132 includes, but is not limited to, storage capacitors, magnetic tunnel junctions (MTJs), and GSTs (Geogens Injection Sequencers). x Sby Te z At least two memory structure layers 120 are stacked on the control circuit layer 110 in a direction perpendicular to the surface of the substrate 100, thereby forming a three-dimensional memory structure. This reduces the horizontal area occupied by the memory 10 without further reducing the size of the memory cells, which is beneficial for improving integration density. On the other hand, each memory structure layer 120 can be formed sequentially on the control circuit layer 110 without being limited by conductive plugs, shallow trench isolation (STI), metal silicide, or other process technologies. Therefore, it can save on the manufacturing cost of the memory 10 and ensure that each transistor in the control circuit and memory cell array has good performance.

[0037] In the embodiments disclosed herein, such as Figure 1 As shown, the selection transistor 131 includes a channel structure 133 and a gate structure 135 surrounding the channel structure 133. Exemplarily, the gate structure 135 may include a gate dielectric layer surrounding each nanosheet 134, and a gate electrode covering the gate dielectric layer. Thus, the gate structure 135 constitutes multiple Gate All Around (GAA) structures stacked in the Z direction to increase the control capability of the gate structure 135 over the channel structure 133. The channel structure 133 is composed of at least two nanosheets 134 stacked in the Z direction. Here, the nanosheets 134 refer to two-dimensional materials with a nanoscale layered structure, having a continuous microstructure, and a thickness that can be less than 10 nm. Increasing the width of the nanosheets can increase the current passing through them, while decreasing the width can reduce the power consumption of the device. Nanosheets 134 can be, but are not limited to, silicon, silicon-germanium (SiGe), and / or group III-V semiconductor materials, such as indium gallium arsenide (InGaAs), indium arsenide (InAs), or indium antimonide (InSb). Nanosheets 134 help reduce the occupied area of ​​the select transistor 131 while maintaining its performance. On the other hand, when the channel structure 133 is turned on, current flows through at least two nanosheets 134, increasing the effective width of the channel structure 133. This increases the drive current when the select transistor 131 is turned on, thereby improving the performance of the memory 10.

[0038] In some embodiments, such as Figure 2 As shown, at least two layers of the nanosheets 134 have overlapping projections on the substrate 100.

[0039] In this embodiment, the projections of each nanosheet 134 onto the substrate 100 coincide, meaning that the nanosheets 134 are not misaligned in the horizontal direction. This results in a smaller horizontal area occupied by the channel structure 133, which helps to further reduce the area occupied by the selection transistor 131.

[0040] In some embodiments, such as Figure 2 As shown, in the first direction, there is a gap between at least two layers of the nanosheets 134; the gate structure 135 surrounds each layer of the nanosheets 134 through the gap.

[0041] In this embodiment, gaps exist between adjacent nanosheets 134 in the Z direction, and the gate structure 135 passes through these gaps and covers each nanosheet 134, thereby forming a fully encircling gate structure to improve the control capability of the gate structure 135 over the channel structure 133. It is understood that the size of the gaps between adjacent nanosheets 134 can be adjusted to meet the performance requirements of the memory 10 for the selection transistors 131. The size of these gaps can be the distance between adjacent nanosheets 134 in the Z direction.

[0042] In some embodiments, such as Figure 2 As shown, the selection transistor 131 further includes: a first source-drain structure 136 and a second source-drain structure 137, which are respectively connected to the two ends of the channel structure 133 in a second direction; the second direction is parallel to the surface of the substrate 100; and the storage structure 132 is connected to the first source-drain structure 136.

[0043] In this embodiment, the first source / drain structure 136 and the second source / drain structure 137 are located at opposite ends of the channel structure 133 in a second direction, which can be the Y direction, i.e., the length direction of the channel structure 133. The first source / drain structure 136 and the second source / drain structure 137 can be doped semiconductor materials, such as doped Si or doped SiGe, and the doping type of the first source / drain structure 136 and the second source / drain structure 137 can be the same. The first source / drain structure 136 is also connected to the memory structure 132, while the second source / drain structure 137 can be connected to the bit lines in the memory 10. Thus, when the select transistor 131 is turned on, the bit lines can change or detect the state of the memory structure 132 via the select transistor 131 to perform write, read, or other operations on the memory cell 130.

[0044] In some embodiments, such as Figure 2As shown, the storage structure 132 includes: a storage capacitor 138 located above the first source-drain structure 136; the projection area of ​​the storage capacitor 138 on the selection transistor 131 at least partially overlaps with the area where the selection transistor 131 is located; and a first connection structure 139 connected between the storage capacitor 138 and the first source-drain structure 136.

[0045] In this embodiment, the storage structure 132 may include a storage capacitor 138 and a first connection structure 139. The storage capacitor 138 is located in the Z direction on the side of the first source / drain structure 136 away from the substrate 100, i.e., in... Figure 2 The storage capacitor 138 is located above the first source-drain structure 136. The projection of the storage capacitor 138 onto the select transistor 131 at least partially overlaps with the area where the select transistor 131 is located, thereby reducing the horizontal area occupied by the storage cell 130 and increasing the number of storage cells 130 per unit area in the storage structure layer. The storage capacitor 138 is connected to the first source-drain structure 136 through a first connection structure 139, that is, the first connection structure 139 can be a capacitive contact (Landing Pad), and the material of the first connection structure 139 includes, but is not limited to, conductive materials such as copper (Cu), tungsten (W), doped polycrystalline silicon, and metal silicide.

[0046] For example, the storage unit 130 in this embodiment may have a "1T1C" structure (one select transistor and one storage capacitor). The select transistor 131 is used to control the signal connection and disconnection between the control circuit and the storage unit 130. When writing data to and reading data from the storage unit 130, the select transistor 131 needs to be switched to the on state to realize the charge transfer between the storage capacitor 138 and the external circuit. The storage capacitor 138 stores data based on the stored charge. Since the potential of its electrodes differs depending on the charge stored in the storage capacitor 138, the reading and writing of binary data can be achieved by switching the storage state of the storage capacitor 138. For example, when the storage capacitor 138 is in a charged state, it represents the data "1", and when the storage capacitor 138 is in a discharged state (uncharged state), it represents the data "0". By detecting the voltage on the electrodes of the storage capacitor 138, its state can be determined as either charged or discharged (uncharged), thereby enabling data reading.

[0047] In some embodiments, such as Figure 2 As shown, the selection transistors 131 of two adjacent memory cells 130 in the second direction share the same second source-drain structure 137; the two selection transistors 131 sharing the second source-drain structure 137 are symmetrically arranged about the second source-drain structure 137.

[0048] In this embodiment of the present disclosure, the selection transistors 131 of two adjacent memory cells 130 in the Y direction can share the same second source-drain structure 137, and the two selection transistors 131 can be axially symmetrical about the shared second source-drain structure 137, which can reduce the area occupied by each memory cell 130; in addition, the bit lines connected to the second source-drain structure 137 can operate on the memory structure of two adjacent memory cells 130 at the same time, which improves the working efficiency of the memory 10.

[0049] It should be noted that the two selection transistors 131 here can also be centrally symmetrically distributed with the connection point of the shared second source-drain structure 137 as the center. Of course, in practical applications, other distribution positions can be designed according to specific requirements.

[0050] In some embodiments, such as Figure 2 As shown, the volume of the second source-drain structure 137 is larger than the volume of the first source-drain structure 136.

[0051] In this embodiment, the volume of the second source-drain structure 137 can be larger than the volume of the first source-drain structure 136. For example, in the Y direction, the width w2 of the second source-drain structure 137 can be larger than the width w1 of the first source-drain structure 136, while in the X and Z directions, their dimensions can be the same. It is understood that since two adjacent selection transistors 131 in the Y direction share the same second source-drain structure 137, the volume of the second source-drain structure 137 can be doubled to meet the performance requirements of the two selection transistors 131 sharing the second source-drain structure 137. Furthermore, the larger volume of the second source-drain structure 137 increases its own charge, thereby increasing the drive current of the selection transistor 131.

[0052] In some embodiments, such as Figure 2 As shown, the memory 10 further includes: a first connection line 121 located between two adjacent memory structure layers 120; the second source-drain structures 137 of two adjacent selection transistors 131 in the first direction are connected to the same first connection line 121.

[0053] In this embodiment, multiple first connection lines 121 may be provided between two adjacent memory structure layers 120 in the Z direction. The first connection lines 121 may extend along the Z direction, and the materials of the first connection lines 121 include, but are not limited to, conductive materials such as copper, tungsten, doped polysilicon, and metal silicides. The first connection lines 121 are used to connect the second source / drain structures 137 of two adjacent selection transistors 131 in the Z direction. It is understood that the second source / drain structures 137 of multiple selection transistors 131 located on the same straight line in the Z direction can be connected together by multiple first connection lines 121, thereby connecting to the same bit line. Thus, one bit line can operate on multiple memory cells 130 in different memory structure layers 120. In some embodiments, the first connection lines 121 may penetrate two or more memory structure layers 120 and connect multiple second source / drain structures 137 located on the same straight line in the Z direction. That is, the first connection lines 121 are not limited to connecting selection transistors in two adjacent memory structure layers 120.

[0054] In some embodiments, such as Figure 3 As shown, the memory 10 further includes: a bit line structure layer 140, located between the bottom storage structure layer 120 and the control circuit layer 110; the bit line structure layer 140 includes multiple parallel bit lines BL extending along a third direction; the third direction is parallel to the surface of the substrate 100; the third direction is parallel to the second direction or has an angle between the third direction and the second direction;

[0055] Each bit line BL connects multiple sets of memory cells 130 arranged along a third direction, wherein each set of memory cells 130 is a plurality of memory cells 130 stacked in a direction perpendicular to the surface of the substrate 100, connected by the first connection line 121.

[0056] In this embodiment, a bit line structure layer 140 is further provided between the bottommost storage structure layer 120 and the control circuit layer 110, and the bit line structure layer 140 has multiple bit lines BL extending along a third direction. This third direction can be the Y direction, or it can be other directions that form a certain angle with the Y direction.

[0057] At least two storage structure layers 120 have multiple groups of storage cells 130 arranged along the Y direction. Here, multiple storage cells 130 connected by multiple first connection lines 121 located on the same straight line in the Z direction constitute the same group of storage cells. That is, multiple storage cells 130 in each group of storage cells are located in different storage structure layers 120 and are stacked along the Z direction.

[0058] The same bit line BL can provide electrical connections to multiple sets of memory cells 130 arranged along the Y direction. For example, the selection transistors in two adjacent memory cells 130 in the Y direction in the same memory structure layer 120 are connected to the same first connection line 121, while multiple first connection lines 121 located on the same straight line in the Z direction are connected to the same bit line BL; the bit line BL is then connected to the control circuit layer 110 through a second connection line 142.

[0059] Since the storage structure layer 120 includes at least two layers, the storage cells 130 in this embodiment are arranged in a three-dimensional array on the substrate 100 and the control circuit layer 110. That is, the storage cells 130 connected by the bit line BL include a plurality of storage cells 130 on one surface.

[0060] Relative to the memory cells 130 connected on the same bit line BL, each memory cell 130 can be individually controlled by selecting the selection transistor of each memory cell 130.

[0061] The control circuit layer 110 may include circuitry and devices that connect to the bit line BL and perform read / write operations on each memory cell 130 via the bit line BL. Since the bit line BL extends along a first direction parallel to the surface of the substrate 100, a second connection line 142 perpendicular to the substrate is also required to connect the bit line BL and the control circuit layer 110.

[0062] In some embodiments, such as Figure 3 As shown, the storage structure layer 120 includes: a plurality of storage blocks 122; each storage block 122 has a plurality of storage cells 130; the control circuit layer 110 includes: a plurality of control blocks 111 corresponding to each of the storage blocks 122; wherein each bit line BL connects the control block 111 and a plurality of sets of storage cells 130 in the plurality of storage blocks 122.

[0063] In this embodiment, each storage structure layer 120 may include multiple storage blocks 122, each storage block 122 having multiple storage cells 130 arranged in an array. The storage block 122 may be a memory array tile (MAT). The storage block 122 may be connected to a control block 111 in the control circuit layer 110. The control block 111 can perform write and read operations on the multiple storage cells 130 in the storage block 122 through word lines, bit lines, and other connection structures. It is understood that the connection relationship between the control block 111 and the storage block 122 can be one-to-one, one-to-many, many-to-one, or many-to-many, etc. Figure 3 Only one control block 111 is shown as an example.

[0064] Each bit line BL can connect the control block 111 and multiple sets of memory cells 130 in multiple memory blocks 122. For example, the bit line BL is connected to the control block 111 via the second connection line 142 and to multiple sets of memory cells 130 via the first connection line 121.

[0065] It should be noted that multiple memory blocks 122 stacked in the Z direction can constitute a group of memory blocks 122, and the memory 10 can have multiple groups of memory blocks 122 in the Y direction. Each group of memory blocks can include multiple groups of memory cells 130. Here, multiple groups of memory cells 130 connected by a bit line BL can be located in the same group of memory blocks 122 or in multiple groups of memory blocks 122.

[0066] In some embodiments, such as Figure 3 As shown, the area where the control block 111 is located at least partially overlaps with the projection area of ​​the storage block 122 to which the control block 111 is connected on the control circuit layer 110. That is, at least a portion of the area of ​​each control block 111 is located below the storage block 122 to which it is connected, thereby facilitating wiring planning and improving the space utilization of each connection structure.

[0067] In some embodiments, such as Figure 4 As shown, the control block 111 includes a first control block connected to the bit line BL.

[0068] In this embodiment of the disclosure, the control block 111 may include a first control block connected to the bit line BL, wherein the first control block includes, but is not limited to, a first control block connected to, the bit line BL. Figure 4 The SA, also known as a sensitivity amplifier, is used to amplify small potential differences between the target bit line and the reference bit line during the reading and writing process of memory cell 130. Here, the target bit line can be the bit line BL connected to the selection transistor of the memory cell 130 currently being read or written, and the reference bit line can be any other bit line BL connected to the same SA as the target bit line. The memory cell 130 connected to the reference bit line does not participate in data reading or writing at this time. In this embodiment of the present disclosure, every two bit lines BL can be connected to the same SA. When reading or writing data to the memory cell 130 connected to the first bit line BL, this bit line is the target bit line, and the other bit line BL can be used as the reference bit line.

[0069] For example, when reading data from memory cell 130, the select transistor of memory cell 130 is turned on. At this time, the charge stored in memory cell 130 affects the potential of the target bit line it is connected to, thereby creating a small potential difference between the target bit line and the reference bit line. SA then amplifies this potential difference and reflects it on the target bit line and the reference bit line. In this way, data can be read by detecting the voltage difference between the target bit line and the reference bit line.

[0070] Here, bit line BL can be connected to SA in control block 111 via the second connection line 142 mentioned above.

[0071] In some embodiments, such as Figure 4 As shown, the bit line BL connecting two adjacent memory blocks 122 in the Y direction can be connected to the same SA. Thus, when one memory block 122 is in an active state, the bit line BL connected to the other memory block 122 serves as the reference bit line, while the bit line connected to the active memory block 122 serves as the target bit line of the SA. This allows the two memory blocks to alternately perform read and write operations, improving the efficiency of the SA and reducing its footprint.

[0072] In some embodiments, such as Figure 5 As shown, the gate structures 135 of the plurality of memory cells 130 located on the same straight line extending along the fourth direction in the memory block 122 are interconnected and connected to the control block 111; the fourth direction is parallel to the surface of the substrate 100; and the fourth direction is not parallel to the third direction.

[0073] In this embodiment, the gate structures 135 of multiple memory cells 130 located on the same straight line extending along a fourth direction in the memory block 122 are interconnected. This fourth direction can be the X direction. Thus, the interconnected gate structures 135 constitute the local word line in the memory block 122. A local word line can couple to the selection transistors 131 of multiple memory cells 130 located along its extending direction in the memory block 122. Based on the control signal issued by the control circuit layer 110, the multiple selection transistors 131 are turned on or off to complete operations such as data writing and reading. It is understood that the fourth direction has an angle with the third direction, meaning that the bit line BL and the projection of the word line onto the substrate intersect, to facilitate the wiring design of the memory 10.

[0074] In some embodiments, an opening is provided between two adjacent memory blocks 122 in the X direction, and the projections of the openings in the plurality of memory structure layers 120 onto the substrate 100 at least partially overlap, with a plurality of third connection lines 143 extending in the Z direction through the through opening. Thus, the gate structure 135 (i.e., local word line) connected in the memory block 122 can be connected to the control block 111 in the control circuit layer 110 through the third connection lines 143 passing through the plurality of memory structure layers 120, simplifying the wiring design of the memory 10.

[0075] In some embodiments, such as Figure 5 As shown, the control block 111 includes a second control block connected to the gate structure 135.

[0076] In this embodiment of the disclosure, the control block 111 may include a second control block connected to the gate structure 135, wherein the second control block includes, but is not limited to, a second control block connected to, the gate structure 135. Figure 5 The SWD in the memory block 122 can be used to drive the local word lines, i.e., the multiple gate structures 135 interconnected in the fourth direction, to provide strobe signals for each memory cell 130. In some embodiments, multiple local word lines can also be connected by a global word line for multiple memory blocks 122.

[0077] Understandably, an SWD can be connected to a local word line and used to turn on the select transistor 131 of each memory cell 130 connected to that local word line.

[0078] For the memory cell 130 to be read from or written to, i.e., the target memory cell, a drive signal is provided through the SWD corresponding to the target memory cell, and the multiple memory cells 130 connected to the local word line of the target memory cell are turned on through the local word line connected to it. At the same time, a corresponding data signal is provided to the bit line connected to the target memory cell, thereby achieving the purpose of performing independent read and write operations on the target memory cell.

[0079] like Figure 6 As shown, this disclosure also provides a storage system 20, including: a memory 10 as described in any of the above embodiments; and a storage controller 21. The storage system 20 can be any type of memory chip. The storage controller 21 can control the memory 10 to perform various operations based on signals sent by the host. It is understood that due to the use of stacked storage structure layers and control circuit layers, the storage system 20 has a high degree of integration; furthermore, the stacked at least two nanosheet layers increase the current when the selection transistor is turned on, which is beneficial to improving the electrical performance of the memory 10.

[0080] It should be noted that the features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0081] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0082] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0083] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0084] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0085] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0086] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: Substrate; A control circuit layer located within the substrate; the control circuit layer includes at least a portion of the control circuitry for the memory; At least two storage structure layers; The at least two storage structure layers are stacked sequentially on the control circuit layer in the first direction; The first direction is perpendicular to the surface of the substrate; The storage structure layer is connected to the control circuit layer; The memory structure layer includes: a plurality of memory cells arranged in an array; each memory cell includes a selection transistor and a memory structure connected to the selection transistor; The selection transistor includes: A channel structure having at least two layers of nanosheets stacked in a first direction; and the gate structure surrounding the channel structure; The selection transistor further includes: The first source / drain structure and the second source / drain structure are respectively connected to the two ends of the channel structure in the second direction; the second direction is parallel to the surface of the substrate. The storage structure is connected to the first source-drain structure; The storage structure includes: A storage capacitor is located above the first source-drain structure; the projection area of ​​the storage capacitor on the selection transistor at least partially overlaps with the area where the selection transistor is located. A first connection structure is connected between the storage capacitor and the first source-drain structure.

2. The memory according to claim 1, characterized in that, At least two layers of the nanosheets project onto the substrate.

3. The memory according to claim 1, characterized in that, In the first direction, there is a gap between at least two layers of the nanosheets; the gate structure surrounds each layer of the nanosheets through the gap.

4. The memory according to claim 1, characterized in that, The selection transistors of two adjacent memory cells in the second direction share the same second source-drain structure; the two selection transistors sharing the second source-drain structure are symmetrically arranged about the second source-drain structure.

5. The memory according to claim 4, characterized in that, The volume of the second source-drain structure is larger than the volume of the first source-drain structure.

6. The memory according to claim 1, characterized in that, Also includes: The first connection line is located between two adjacent storage structure layers; The second source-drain structures of two adjacent select transistors in the first direction are connected to the same first connection line.

7. The memory according to claim 6, characterized in that, Also includes: The bit line structure layer is located between the bottommost memory structure layer and the control circuit layer; the bit line structure layer includes multiple parallel bit lines extending in a third direction; The third direction is parallel to the surface of the substrate; the third direction is parallel to the second direction or there is an angle between the third direction and the second direction; Each bit line connects multiple groups of memory cells arranged along a third direction, wherein each group of memory cells is a stack of memory cells arranged in a direction perpendicular to the surface of the substrate, connected by the first connection line.

8. The memory according to claim 7, characterized in that, The storage structure layer includes: multiple storage blocks; each storage block has multiple storage units; The control circuit layer includes: a plurality of control blocks connected to each of the memory blocks; Each bit line connects the control block and multiple sets of memory cells in the multiple memory blocks.

9. The memory according to claim 8, characterized in that, The region where the control block is located at least partially overlaps with the projection region of the storage block connected to the control block on the control circuit layer.

10. The memory according to claim 8, characterized in that, The control block includes: The first control block connected to the bit line.

11. The memory according to claim 8, characterized in that, The gate structures of the plurality of memory cells located on the same straight line extending along a fourth direction in the memory block are interconnected and connected to the control block; the fourth direction is parallel to the surface of the substrate; and the fourth direction is not parallel to the third direction.

12. The memory according to claim 11, characterized in that, The control block includes: A second control block connected to the gate structure.

13. A storage system, characterized in that, include: The memory according to any one of claims 1 to 12; Storage controller.

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