Semiconductor structure and method of making the same, memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory. The method comprises: providing a stack structure alternately stacked by semiconductor layers and sacrificial layers; the stack structure comprises: a first stack region, and a second stack region connected to a first end of a plurality of first stack regions; the first stack regions are filled with insulating material; etching the sacrificial layers of the second stack region and part of the first stack region in a first direction to form a first multilayer gap; the semiconductor layers of the second stack region are used to form a plurality of stacked bit line structures; filling part of the first multilayer gap in the first stack region to form a first isolation layer; forming an opening in the insulating material adjacent to the first stack region and perpendicular to the surface direction of the stack structure; etching the first isolation layer from the opening to remove at least part of the first isolation layer; forming a word line structure extending perpendicular to the surface direction of the stack structure at the opening; and forming a plurality of stacked memory structures in each first stack region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent a binary bit (1 or 0). During DRAM development, as the size of the capacitors further decreased, bottlenecks began to emerge in vertical capacitor structures. To increase capacitor density, stacked capacitors were developed. The gate structure defined by bidirectional etching of the DRAM source and drain is prone to irregular shapes, while the performance and quality of DRAM devices are related to the regularity of the gate structure. Therefore, controlling the etching of the source and drain in DRAM devices to form a gate structure with the desired shape has become a pressing problem to be solved. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.

[0004] In a first aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising:

[0005] A stacked structure is provided, comprising alternating semiconductor layers and sacrificial layers; the stacked structure includes a plurality of first stacked regions extending along a first direction, and a second stacked region connected to a first end of the plurality of first stacked regions and extending along a second direction; wherein the first direction is perpendicular to the second direction; and an insulating material is filled between the first stacked regions.

[0006] The second stacked region and a portion of the sacrificial layer of the first stacked region are etched along the first direction to form a first multilayer void; the semiconductor layer of the second stacked region is used to form a plurality of stacked bit line structures;

[0007] The portion of the first multilayer void located in the first stacking area is filled to form a first isolation layer;

[0008] An opening perpendicular to the surface of the stacked structure is formed in the insulating material adjacent to the first stacked region;

[0009] The first isolation layer is etched from the opening to remove at least a portion of the first isolation layer;

[0010] A letter line structure extending in a direction perpendicular to the surface of the stacked structure is formed at the opening;

[0011] Multiple stacked storage structures are formed in the first stacking area.

[0012] In some embodiments, the etching selectivity ratio of the sacrificial layer material used in the sacrificial layer to the semiconductor material used in the semiconductor layer is greater than or equal to a first preset value.

[0013] In some embodiments, the sacrificial layer material is silicon germanide (SiGe), and the semiconductor material is silicon (Si).

[0014] In some embodiments, filling the portion of the first multilayer void located in the first stacked region to form a first isolation layer includes:

[0015] Along the first direction, a first isolation material, a second isolation material, and the first isolation material are sequentially filled into the first multi-layer gap to form the first isolation layer; wherein, the length of the first isolation layer along the first direction is greater than or equal to the length of the first multi-layer gap within the first stacking area.

[0016] In some embodiments, the etching selectivity ratio of the second isolation material to the first isolation material is greater than or equal to a second preset value.

[0017] In some embodiments, the step of sequentially filling the first multilayer voids with a first insulating material, a second insulating material, and the first insulating material to form the first insulating layer includes:

[0018] Fill the first layer of voids with a first insulating material;

[0019] The first isolation material is etched, while a portion of the first isolation material located in the first stacked area is retained;

[0020] Fill the first multi-layer voids with a second insulating material;

[0021] The second isolation material is etched, and a portion of the second isolation material located in the first stack region is retained; wherein, along the first direction, the length of the retained second isolation material is a predetermined gate length;

[0022] The first insulating material is then filled into the first multi-layer gaps again.

[0023] The first isolation material is etched, and the portion of the first isolation material located in the first stacked area and outside the second isolation material is retained.

[0024] In some embodiments, etching the first insulating layer from the opening to remove at least a portion of the first insulating layer includes:

[0025] The first insulating layer is etched from the opening to remove the second insulating material from the first insulating layer.

[0026] In some embodiments, forming a word line structure at the opening that extends in a direction perpendicular to the surface of the stacked structure includes:

[0027] A gate oxide layer is formed on the surface of each of the semiconductor layers within the opening;

[0028] A first conductive material is coated on the surface of the gate oxide layer as a gate conductive layer;

[0029] The word line structure is formed by filling the opening covered by the gate conductive layer with a second conductive material.

[0030] In some embodiments, the provision of the stacked structure consisting of alternating semiconductor layers and sacrificial layers includes:

[0031] Provide substrate;

[0032] Semiconductor materials and sacrificial layer materials are alternately stacked sequentially on the substrate;

[0033] The stacked semiconductor material and sacrificial layer material are etched along the first direction to form a plurality of first stacked regions extending along the first direction, and a second stacked region connected to the first end of the plurality of first stacked regions and extending along the second direction; the area outside the stacked structure is a groove formed by etching.

[0034] The insulating material is filled into the grooves formed after etching.

[0035] In some embodiments, the method further includes:

[0036] At the second end of the first stacked region, away from the second stacked region, the insulating material is etched to form a groove located between adjacent first stacked regions;

[0037] Fill the slot with insulating material;

[0038] Remove the insulating material from the side of the second end away from the first end, and etch a portion of the sacrificial layer in the first stacked region from the second end along the first direction to form a second multilayer void;

[0039] The isolation material is filled at the second end of the first stacked region where part of the sacrificial layer has been etched away to form a support structure.

[0040] In some embodiments, the plurality of storage structures stacked in each of the first stacking regions includes:

[0041] Remove the insulating material between the first stacked areas;

[0042] Remove the sacrificial layer in the first stacked region, leaving each semiconductor layer suspended;

[0043] The surface of the semiconductor layer is subjected to metal silicide treatment;

[0044] A first metal material is coated on the surface of the semiconductor layer after metal silicide treatment to form the lower electrode of the capacitor structure;

[0045] A dielectric layer is covered on the surface of the lower electrode;

[0046] A third metallic material is coated on the surface of the dielectric layer to form the upper electrode of the capacitor structure;

[0047] Polycrystalline silicon material is filled in the gaps between adjacent semiconductor layers where the upper electrode is formed and in the grooves between the first stacked regions.

[0048] In some embodiments, after forming a plurality of stacked capacitor structures, the method further includes:

[0049] Remove the insulating material at the second end of the first stacked area, and at the same time remove at least a portion of the first insulating layer on the side of the capacitor structure near the first end to form trenches at both ends of the capacitor structure.

[0050] The trench is filled with insulating material.

[0051] In some embodiments, after forming the first isolation layer, the method further includes:

[0052] In the second stack region, the semiconductor layer not covered by the first isolation layer is subjected to metallization along the second direction;

[0053] A second metallic material is coated on the surface of the semiconductor layer;

[0054] The second metal material at the connection between the semiconductor layers along the Z direction is etched to separate the second metal materials covered by the semiconductor layers from each other.

[0055] An insulating material is filled between the semiconductor layers covered with the second metal material and on the side of the second stacked region away from the first stacked region; wherein, the semiconductor layers covered with the second metal material are the bit line structure.

[0056] In some embodiments, the method further includes:

[0057] The bit line structure is processed to form a stepped structure with the length decreasing from bottom to top;

[0058] A bit line lead-out structure is formed on each of the stepped structures.

[0059] Secondly, embodiments of this disclosure also provide a semiconductor structure, which is formed as described in any of the above embodiments.

[0060] Thirdly, embodiments of this disclosure also provide a memory, including:

[0061] Semiconductor structures formed by the methods described in any of the above embodiments.

[0062] This embodiment of the disclosure uses a unidirectional etching process from the side. After forming the AA (Active Area) region, the intermediate layer is etched unidirectionally from one end and filled with different isolation materials to define the source, drain, and channel lengths and ranges of the transistor. This reduces the gate structure irregularities caused by bidirectional side etching of the source and drain. Attached Figure Description

[0063] Figures 1A to 1C This is a schematic diagram of a semiconductor structure formed by bidirectional etching in some embodiments;

[0064] Figure 2 This is a flowchart illustrating one method according to an embodiment of this application.

[0065] Figure 3 This is a schematic diagram of an alternating stacked structure consisting of a semiconductor layer and a sacrificial layer, as described in an embodiment of this application.

[0066] Figure 4 This is a schematic diagram of a semiconductor structure including a first multilayer void in an embodiment of this application;

[0067] Figure 5A This is a schematic diagram of a semiconductor structure including a first isolation layer in an embodiment of this application;

[0068] Figure 5B This is an enlarged schematic diagram of the first isolation layer in an embodiment of this application;

[0069] Figure 6 This is a schematic diagram of a semiconductor structure including an opening perpendicular to the surface direction of the stacked structure, according to an embodiment of this application.

[0070] Figure 7 This is a schematic diagram of a semiconductor structure with a through-hole and an opening, as described in an embodiment of this application.

[0071] Figure 8A This is a schematic diagram of a semiconductor structure including a word line structure in an embodiment of this application;

[0072] Figure 8B This is an enlarged schematic diagram of the word line structure in an embodiment of this application;

[0073] Figure 9 This is a schematic diagram of a semiconductor structure including a semiconductor pillar array in an embodiment of this application;

[0074] Figure 10 This is a schematic diagram of another stacked structure consisting of alternating semiconductor layers and sacrificial layers, as described in an embodiment of this application.

[0075] Figure 11 This is a schematic diagram of a semiconductor structure including a first stacked region and a second stacked region according to an embodiment of this application;

[0076] Figure 12 This is a schematic diagram of a semiconductor structure in which insulating material is filled between the first stacked regions in an embodiment of this application;

[0077] Figure 13 This is a schematic diagram of a semiconductor structure including a slot located between adjacent first stacked regions according to an embodiment of this application;

[0078] Figure 14 This is a schematic diagram of a semiconductor structure including a first support structure located between adjacent first stacked regions, according to an embodiment of this application.

[0079] Figure 15 This is a schematic diagram of a semiconductor structure including a second multilayer void in an embodiment of this application;

[0080] Figure 16 This is a schematic diagram of a semiconductor structure including a support structure in an embodiment of this application;

[0081] Figure 17 This is a schematic diagram of a semiconductor structure including a second opening in an embodiment of this application;

[0082] Figure 18A This is a schematic diagram of a semiconductor structure including a first multilayer void in an embodiment of this application;

[0083] Figure 18B This is an enlarged schematic diagram of the first multi-layered void in an embodiment of this application;

[0084] Figure 19 This is a schematic diagram of a semiconductor structure including a first isolation structure in an embodiment of this application;

[0085] Figure 20 This is a schematic diagram of a semiconductor structure including a first isolation portion according to an embodiment of this application;

[0086] Figure 21This is a schematic diagram of a semiconductor structure including a second isolation structure in an embodiment of this application;

[0087] Figure 22 This is a schematic diagram of a semiconductor structure including a second isolation portion according to an embodiment of this application;

[0088] Figure 23 This is a schematic diagram of a semiconductor structure including a third isolation structure in an embodiment of this application;

[0089] Figures 24A to 24B This is a schematic diagram of a semiconductor structure including a first isolation layer in an embodiment of this application;

[0090] Figure 25 This is a schematic diagram of a semiconductor structure including a first metal silicide structure in an embodiment of this application;

[0091] Figure 26 This is a schematic diagram of a semiconductor structure including a second metal material layer in an embodiment of this application;

[0092] Figure 27A and Figure 27B This is a schematic diagram of a semiconductor structure including a fourth metal structure in an embodiment of this application;

[0093] Figure 27C This is a schematic diagram of a semiconductor structure including a first bit line structure in an embodiment of this application;

[0094] Figure 28 This is a schematic diagram of a semiconductor structure including a fourth insulating structure in an embodiment of this application;

[0095] Figure 29 This is a schematic diagram of another semiconductor structure including an opening perpendicular to the surface direction of the stacked structure in an embodiment of this application;

[0096] Figure 30 This is a schematic diagram of another semiconductor structure including a through-hole located between the first isolation structure and the third isolation structure in an embodiment of this application;

[0097] Figures 31A to 31B This is a schematic diagram of a semiconductor structure including a gate oxide layer and a gate conductive layer in an embodiment of this application;

[0098] Figure 32 This is a schematic diagram of a semiconductor structure covered with a tungsten metal layer in an embodiment of this application;

[0099] Figure 33 This is a schematic diagram of a semiconductor structure including a word line structure in an embodiment of this application;

[0100] Figure 34This is a schematic diagram of a semiconductor structure including a semiconductor pillar array in an embodiment of this application;

[0101] Figure 35 This is a schematic diagram of a semiconductor structure including a metal silicide layer in an embodiment of this application;

[0102] Figure 36 This is a schematic diagram of a semiconductor structure including a first metal material layer in an embodiment of this application;

[0103] Figure 37 This is a schematic diagram of a semiconductor structure including a dielectric layer in an embodiment of this application;

[0104] Figure 38 This is a schematic diagram of a semiconductor structure including a polycrystalline silicon layer in an embodiment of this application;

[0105] Figure 39 This is a schematic diagram of a semiconductor structure covered with photoresist in an embodiment of this application;

[0106] Figure 40A This is a schematic diagram of a semiconductor structure including trenches located at both ends of the capacitor structure in an embodiment of this application;

[0107] Figure 40B This is a schematic diagram of a capacitor structure formed in an embodiment of this application;

[0108] Figure 41 This is a schematic diagram of a semiconductor structure formed in an embodiment of this application. Detailed Implementation

[0109] To facilitate understanding of this disclosure, exemplary embodiments thereof will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0110] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of actual embodiments, nor well-known functions and structures, may be described herein.

[0111] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0112] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0113] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0114] DRAM is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent a binary bit (1 or 0). During DRAM development, as the size of the capacitor further decreased, bottlenecks began to emerge in vertical capacitor structures. To increase capacitor density per unit area, stacked capacitors were developed. In some embodiments, DRAM devices can be formed by etching the source and drain terminals of the transistors into the channel region. First, as... Figure 1A As shown, the etched insulating structure 20 forms multiple trenches 10 to open both sides of the transistor source and drain regions, and the sacrificial layer below the arrow direction is removed by a wet etching process. Figure 1B As shown, for Figure 1A SiN is filled into the etched sacrificial layer. Since the etched sacrificial layer corresponds to the source and drain regions, and the etched sacrificial layer is irregular, the filled SiN is also irregular, resulting in irregular sacrificial layer in the transistor's gate region. Figure 1B As shown in the box. Figure 1CAs shown, after removing Figure 1B During the process of sacrificing the gate structure, due to Figure 1B The sacrificial layer removed during the process is irregular, resulting in an irregular gate structure that is subsequently formed.

[0115] The performance and quality of DRAM devices are related to the regularity of the gate structure. How to control the etching of the source and drain in DRAM devices to form a gate structure with the target shape has become an urgent problem to be solved.

[0116] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 2 As shown, the method includes:

[0117] Step S101: Provide a stacked structure consisting of alternating semiconductor layers and sacrificial layers; such as Figure 3 As shown, the stacking structure 300 includes a plurality of first stacking regions 320 extending along a first direction (i.e., the X direction), and a second stacking region 310 connected to the first end D1 of the plurality of first stacking regions 320 and extending along a second direction (i.e., the Y direction); wherein the first direction is perpendicular to or intersects the second direction; and the first stacking regions 320 are filled with insulating material.

[0118] Step S102: Etch the second stacked region 310 and a portion of the sacrificial layer of the first stacked region 320 along the first direction to form a sacrificial layer as shown in the figure. Figure 4 The first multilayer gap 510 is shown; the semiconductor layer of the second stacked region 310 is used to form a multilayer stacked bit line structure;

[0119] Step S103: Fill the portion of the first multi-layer gap 510 located in the first stacking area 320, forming as shown in the figure. Figures 5A to 5B The first isolation layer 600 is shown.

[0120] Step S104: Forming such in the insulating material adjacent to the first stacked region 320 Figure 6 The opening 730 shown is perpendicular to the surface of the stacked structure 300;

[0121] Step S105: Etch the first isolation layer from the opening 730, as shown. Figure 7 As shown, at least part of the first isolation layer is removed;

[0122] Step S106, as follows Figures 8A to 8B As shown, a word line structure 754 extending in a direction perpendicular to the surface of the stacked structure is formed at the opening 730;

[0123] Step S107: Form multiple stacked storage structures in the first stacking area 320.

[0124] First, execute step S101 and provide the following: Figure 3The semiconductor structure shown includes a stacked structure 300 and an insulating structure 410. The stacked structure 300 further includes alternately stacked semiconductor layers 101 and sacrificial layers 102. In some embodiments, the stacked structure 300 may be a superlattice structure, in which case both the semiconductor layers 101 and the sacrificial layers 102 are thin films with a thickness ranging from several to tens of atomic layers. The semiconductor layer 101 can be composed of P-type semiconductor materials (e.g., silicon (Si) or germanium (Ge)) or N-type semiconductor materials (e.g., indium phosphide (InP)). The composition of the sacrificial layer 102 is mainly determined by its etching selectivity ratio with that of the semiconductor layer 101. In some embodiments, if the etching selectivity ratio of the material used in the sacrificial layer 102 to that used in the semiconductor layer 101 is greater than or equal to a first preset value, where the first preset value is the minimum etching selectivity ratio (e.g., 10), then both the material used in the sacrificial layer 102 and the material used in the semiconductor layer 101 can be selected if the above conditions are met. In other words, the material of the sacrificial layer 102 can be selected based on the material of the semiconductor layer 101 and the minimum etching selectivity ratio. In this embodiment, the material of the semiconductor layer 101 can be silicon (Si), and the material of the sacrificial layer 102 can be silicon germanide (SiGe). Figure 3 As shown, the stacking structure 300 can be divided into a second stacking region 310 and multiple first stacking regions 320 along AA' in the Y direction. The second stacking region 310 extends along a second direction (i.e., the Y direction), and the first stacking regions 320 extend along a first direction (i.e., the X direction). In some embodiments, the X direction and the Y direction may intersect or be perpendicular. In this embodiment, the X direction and the Y direction are described as being perpendicular to each other. Each first stacking region 320 is connected to the second stacking region 310 at its first end D1 (the end closest to the second stacking region). Insulating material may also be filled between adjacent first stacking regions 320 to form an insulating structure 410. The insulating structure 410 can provide support for the stacking structure. The insulating structure 410 can be located on the side of the second stacking region 310 away from the first stacking region 320, between the first stacking regions 320, and on the side of the first stacking region 320 away from the second stacking region 310.

[0125] Continue with step S102, etching along the X direction as follows: Figure 3 The second stacked region 310 and the sacrificial layer 102 of part of the first stacked region 320, as shown, form as Figure 4The first multilayer void 510 is shown. In this embodiment, instead of etching the second stacked region 310 along the Z-direction from the upper surface of the stacked structure, the second stacked region 310 and a portion of the first stacked region 320 are etched along the X-direction to remove the sacrificial layer 102 in the second stacked region 310 and a portion of the sacrificial layer 102 in the first stacked region 320. This etching method includes, but is not limited to, dry etching and wet etching. In this embodiment, wet etching can be used, for example, one or more of hydrofluoric acid, nitric acid, hydrogen peroxide, ammonium hydroxide, etc., can be used to prepare the etching solution. The choice of etching solution is not limited to this; any etching solution with a high etching selectivity between the material used in the sacrificial layer 102 and the material used in the semiconductor layer 101 can be used in this embodiment. Figure 4 As shown, the semiconductor structure after performing step S102 has a first multilayer gap 510, and there are semiconductor layers 101 between adjacent first multilayer gaps 510, including all semiconductor layers 101 in the second stack region 310 and at least a portion of semiconductor layers 101 in the first stack region 320. The semiconductor layers 101 in the second stack region 310 can be used to form a bit line structure of multilayer stacking in the future.

[0126] Continue with step S103, fill as follows Figure 4 The first multilayer void 510 shown is located in a portion of the first stacked region 320, forming the first isolation layer 600 as shown in FIG. 5. The methods for filling the first multilayer void 510 include, but are not limited to, growth processes and deposition processes. The deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD), etc. Growth processes include, but are not limited to, in-situ steam generation (ISSG). The first multilayer void 510 can be filled with at least two insulating materials to form the first isolation layer 600. At least one insulating material is a low dielectric constant material (i.e., a dielectric constant lower than that of SiO2), for example, silicon nitride. The first isolation layer 600 can subsequently be used to isolate word line structures and capacitor structures, and can also be used to isolate the electrical connection between adjacent transistors on a semiconductor structure.

[0127] Continue with step S104, as follows Figure 5AAs shown, the first stacked region 320 is formed in the adjacent insulating material as follows Figure 6 An opening 730 perpendicular to the surface of the stacked structure is shown. On the insulating material on both sides of the first stacked region 320, a portion of the insulating material overlapping the first insulating layer in the X direction is etched. The etching method includes, but is not limited to, dry etching and wet etching, to form the opening 730 perpendicular to the surface of the stacked structure. That is, the opening 730 overlaps with a portion of the first insulating layer in the X direction, but does not overlap with either end of the first insulating layer. The length of the opening 730 in the X direction is less than the length of the first insulating layer in the X direction. The length and shape of the opening 730 can be defined by a mask. The cross-sectional shape of the opening 730 along the XY direction includes, but is not limited to, a circle, a square, and a rectangle. In some embodiments, the centerline of the opening 730 in the Y direction may overlap with the centerline of the first insulating layer in the Y direction.

[0128] Continue with step S105, etching the first isolation layer from the opening to remove at least a portion of the first isolation layer.

[0129] The first isolation layer may include multiple isolation materials, such as a first isolation material and a second isolation material. The first isolation layer may be a sandwich structure including a first isolation material, a second isolation material, and a third isolation material. Alternatively, it may be a structure in which the three materials are arranged sequentially. In this embodiment, the etching solution may be selected to have a higher etching selectivity for the second isolation material compared to the first and third isolation materials.

[0130] At least a portion of the first isolation layer is removed; specifically, etching solution can be poured into the opening to etch away the second isolation material in the first isolation layer. For example... Figure 7 As shown, a through hole 740 can be formed after removing at least part of the first isolation layer, and the through hole 740 is connected to the opening 730.

[0131] Continue with step S106, forming at the opening as shown Figures 8A to 8B The word line structure 754 shown extends perpendicular to the surface direction of the stacked structure 300.

[0132] The word line structure 754 includes a gate conductive layer 752, a gate oxide layer 751, and a word line 753. First, an oxide layer can be grown or deposited at the opening 730 as the gate oxide layer 751 using a growth or deposition process. In some embodiments, oxygen atoms can be introduced at the opening 730 at a high temperature, allowing them to bond with atoms (e.g., silicon atoms) in the stacked structure 300 to form a high-quality oxide film. In some embodiments, a deposition process, such as chemical vapor deposition (CVD), can also be used to form an oxide film as the gate oxide layer.

[0133] Then, one or more of a conductive material (e.g., tungsten), polysilicon, or metal silicide are filled into the opening 730 covered with the gate oxide layer 751 to form the gate conductive layer and word line.

[0134] Continue with step S107, forming multiple stacked storage structures in each first stacking area 320.

[0135] Etching is performed on the insulating material between the first stacked regions 320 to form Figure 9 The second groove 760 is shown. Specifically, the non-overlapping region (defined as the sixth interval X6) between the insulating material and the first isolation layer 600 between the first stacked regions 320 is etched. In the Z direction, the etching depth can be equal to the depth of the first stacked region 320, i.e., the substrate 100 is used as an etching barrier layer. In this way, the second groove 760 located between the first stacked regions 320 can be formed.

[0136] The sacrificial layer in the first stacked region 320 can then be removed by etching, such as... Figure 9 As shown, the semiconductor layer 101 in the first stacked region 320 is suspended, so that there is a semiconductor pillar array 770 formed by a plurality of mutually separated semiconductor layers 101 on both sides of the second groove 760.

[0137] Then, the memory structure continues to be formed between the suspended semiconductor layers 101.

[0138] In embodiments of this disclosure, the memory structure may include a capacitor structure, which may include a lower electrode, a dielectric layer, and an upper electrode. The capacitor structure is formed by depositing a first conductive material between suspended semiconductor layers to form the lower electrode, depositing a high-dielectric-constant material to form the dielectric layer, and depositing a second conductive material to form the upper electrode. The above is merely one example of forming a memory structure; the shapes of the memory structure include, but are not limited to, cylindrical capacitors, disc capacitors, rectangular capacitors, stacked capacitors, and various irregularly shaped capacitors.

[0139] This embodiment of the disclosure uses a unidirectional side etching process along the X direction. After forming the AA (Active Area) region, unidirectional etching is performed from the side, and isolation materials with different etching selectivity ratios are filled in. Based on the region of the semiconductor layer corresponding to different isolation materials, the length and range of the source, drain, and channel of the transistor are defined. This can reduce the gate structure irregularity problem caused by bidirectional side etching of the source and drain.

[0140] In some embodiments, step S103 involves filling the portion of the first multilayer void located in the first stacking region to form a first isolation layer, including:

[0141] Step S201: Along the first direction, fill the first multi-layer gap with the first isolation material, the second isolation material and the first isolation material in sequence to form the first isolation layer; wherein, the length of the first isolation layer along the first direction is equal to the length of the first multi-layer gap within the first stacking area.

[0142] In some embodiments, step S103 can be replaced by step S201.

[0143] like Figures 5A to 5B As shown, the first isolation layer 600 may be a sandwich structure composed of a first isolation portion 611 formed of a first isolation material, a second isolation portion 621 formed of a second isolation material, and a third isolation portion 631 formed of a first isolation material. Specifically, the forming steps include, along the X direction, towards... Figure 5A The first interval X1 of the first multi-layer void 510 is filled with a first insulating material. Continuing along the X direction, a second insulating material is filled into the second interval X2 of the first multi-layer void 510. Continuing along the X direction, a third insulating material is filled into the third interval X3 of the first multi-layer void. Therefore, the length of the first insulating layer 600 in the X direction is the sum of the distances between the first interval X1, the second interval X2, and the third interval X3. The length of the first insulating layer 600 in the X direction is equal to the length of the first multi-layer void within the first stacking area; that is, all the first multi-layer voids 510 within the first stacking area can be used to form the first insulating layer 600.

[0144] In some embodiments, the etching selectivity ratio of the second isolation material to the first and / or third isolation material is greater than or equal to a second preset value; in some embodiments, the second preset value may be 20. The second isolation material has a high etching selectivity ratio relative to the first isolation material, so that when the second isolation material is selectively removed, the first isolation material may not be removed, thereby achieving precise control of the gate length. The second isolation material refers to the material used to fill the middle portion of the first isolation layer 600. The first isolation material refers to the material used to fill both sides of the first isolation layer.

[0145] In some embodiments, the first isolation material and the third isolation material may be the same.

[0146] In some embodiments, step S201 involves sequentially filling the first multilayer voids with a first insulating material, a second insulating material, and another first insulating material to form a first insulating layer, including:

[0147] Step S301: Fill the first layer of voids with the first insulating material;

[0148] Step S302: Etch the first isolation material while retaining a portion of the first isolation material located in the first stacking region;

[0149] Step S303: Fill the first multi-layer voids with a second insulating material;

[0150] Step S304: Etch the second isolation material, and retain a portion of the second isolation material located in the first stack region; wherein, along the first direction, the length of the retained second isolation material is a predetermined gate length;

[0151] Step S305: Fill the first layer of voids with the first insulating material again;

[0152] Step S306: Etch the first isolation material, while retaining the portion of the first isolation material located in the first stacked area that is outside the second isolation material.

[0153] Step S201 can be further broken down into steps S301 to S306.

[0154] First, perform step S301, moving along the X direction towards... Figure 4 The first interval X1 of the first multilayer void 510 shown is filled with a first insulating material. The filling method includes, but is not limited to, growth processes and deposition processes. The first insulating material can be an insulating material, such as silicon nitride.

[0155] In some embodiments, if the filling range exceeds the first interval X1, step S302 can be performed to etch the first isolation material and retain the first isolation material located in the first stacked region within the first interval X1.

[0156] The etching method includes, but is not limited to, dry etching and wet etching, removing the first isolation material that exceeds the range of the first interval X1, and retaining the first isolation material located within the first interval X1 of the first stacking region.

[0157] Continue with step S303, along the X direction, fill the second interval X2 of the first multilayer void 510 with a second insulating material. The filling method includes, but is not limited to, growth processes and deposition processes. The second insulating material can be any insulating material different from the first insulating material. In particular, the second insulating material can be a material with an etching selectivity greater than that of the first insulating material, so as to facilitate the selective removal of the second insulating material in the future.

[0158] In some embodiments, if the filling range exceeds the second interval X2, step S304 can be performed to etch the second isolation material and retain the second isolation material located in the second interval X2 of the first stacking region.

[0159] The etching method includes, but is not limited to, dry etching and wet etching. The second isolation material extending beyond the second interval X2 is removed, leaving the second isolation material within the second interval X2 of the first stacked region. The length of the retained second isolation material is a predetermined gate length, because the gate of a transistor can be formed in the second interval X2 of the semiconductor layer in subsequent steps; therefore, the length of the second interval X2 is the predetermined gate length.

[0160] The embodiments of this disclosure define the gate length of the semiconductor layer by utilizing the length of the second isolation material in the first isolation layer, thereby achieving precise control of the gate length.

[0161] Then, step S305 is executed, and the first isolation material is filled again into the third interval X3 of the first multilayer void 510. The third interval X3 may be the remaining interval of the first multilayer void located in the first stacked region. The filling method includes, but is not limited to, growth processes and deposition processes, and the first isolation material may be any insulating material, such as silicon nitride.

[0162] In some embodiments, if the filling range exceeds the third interval X3, step S306 can be performed to etch the excess first isolation material, and the first isolation material located in the first stacking region in the third interval X3.

[0163] In some embodiments, step S105, etching the first isolation layer from the opening to remove at least a portion of the first isolation layer, includes:

[0164] Step S401, from Figure 6 The first isolation layer is etched at the opening 730 to remove the second isolation material in the first isolation layer 600.

[0165] In some embodiments, step S105 can be replaced by step S401.

[0166] When the first insulating layer 600 consists of a first insulating portion 611 composed of a first insulating material, a second insulating portion 621 composed of a second insulating material, and a third insulating portion 631 composed of a first insulating material, it can be considered a sandwich structure. Removing at least a portion of the first insulating layer 600 can be done by removing the second insulating portion 621 from the first insulating layer 600 to form a structure as shown below. Figure 7 The through hole 740 shown is connected to the opening 730.

[0167] In some embodiments, a wet etching process may be used to inject etching solution from the opening 730 to remove the second isolation portion 621 in the first isolation layer 600.

[0168] In some embodiments, step S106, forming a word line structure extending perpendicular to the surface direction of the stacked structure at the opening, includes:

[0169] Step S501: Form a gate oxide layer on the surface of each semiconductor layer within the opening;

[0170] Step S502: Cover the surface of the gate oxide layer with a first conductive material as a gate conductive layer;

[0171] Step S503: Fill the opening covered with the gate conductive layer with a second conductive material to form a word line structure.

[0172] In some embodiments, step S106 can be replaced by steps S501, S502 and S503.

[0173] The word line structure may include a gate oxide layer, a gate conductive layer, and word lines connecting multiple gates.

[0174] First, execute step S501, as follows: Figure 7 The surfaces of each semiconductor layer 101 within the opening 730 shown are formed Figure 8A The gate oxide layer 751 is shown.

[0175] For example, oxygen atoms can be introduced into the surface of each exposed semiconductor layer 101 at the opening 730 under high temperature conditions. The oxygen atoms combine with silicon atoms in the exposed semiconductor layer 101 to form a high-quality oxide film, namely the gate oxide 751. Alternatively, a deposition process, such as chemical vapor deposition (CVD), can be used to form an oxide film as the gate oxide layer 751.

[0176] The gate oxide layer 751 is composed of materials including, but not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrogen-doped oxides, etc. Then, step S502 is performed to cover the surface of the gate oxide layer 751 with a first conductive material using a growth process or a deposition process to form a gate conductive layer 752. The first conductive material can be a metal (e.g., TiN) or polysilicon.

[0177] Then, step S503 is performed, in which a second conductive material is filled into the opening 730 covered by the gate conductive layer 752 using a growth process or a deposition process to form a word line 753. The word line 753, the gate conductive layer 752, and the gate oxide layer 751 together form the word line structure 754.

[0178] The second conductive material includes, but is not limited to, metals (e.g., metal W) and polysilicon. The second conductive material can fill the opening 730 covering the gate conductive layer 752 to form... Figure 8A The word line 753 connecting multiple gates is shown. If the deposition height of the second conductive material exceeds the surface of the stacked structure, the excess portion of the second conductive material can be removed using CMP.

[0179] Figure 8B This is a partially enlarged schematic diagram of a word line structure 754, which consists of a gate oxide layer 751, a gate conductive layer 752, and a word line 753.

[0180] In some embodiments, step S101 provides a stacked structure consisting of alternating semiconductor layers and sacrificial layers, including:

[0181] Step S601: Provide a substrate;

[0182] Step S602: Semiconductor material and sacrificial layer material are alternately stacked on the substrate in sequence;

[0183] Step S603: Etch the stacked semiconductor material and sacrificial layer material along the first direction to form a plurality of first stacked regions extending along the first direction, and a second stacked region connected to the first end of the plurality of first stacked regions and extending along the second direction; the area outside the stacked structure is a groove formed by etching.

[0184] Step S604: Fill the groove formed after etching with the first insulating material.

[0185] In some embodiments, step S101 may include steps S601, S602, and S603.

[0186] First, step S601 is executed, providing a substrate, which may be a P-type semiconductor material substrate (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), an N-type semiconductor substrate (e.g., an indium phosphide (InP) substrate), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate), a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate, etc.

[0187] Then, step S602 is performed, where semiconductor materials and sacrificial layer materials are sequentially stacked on the substrate using a deposition or growth process to form a structure as shown in the figure. Figure 10 The diagram shows an alternating stack of a first semiconductor layer 201 and a first sacrificial layer 202 on a substrate 100. In some embodiments, the first half-layer 201 is made of the same material as the substrate 100.

[0188] In some embodiments, sputtering or atomic layer deposition may be used, and a target material for a semiconductor material (e.g., Si) and a target material for a sacrificial layer (e.g., SiGe) may be provided to form a first semiconductor layer 201 and a first sacrificial layer 202 of a superlattice structure.

[0189] Then, step S603 is performed: a layer of photoresist is applied to the upper surface (e.g., the first sacrificial layer 202) of the alternately stacked first semiconductor layer 201 and first sacrificial layer 202. A patterned mask is used to align the area to be removed, and then exposure is performed. This photoresist can be a negative photoresist, so the photoresist corresponding to the mask pattern is removed. Etching continues on the areas of the alternately stacked first semiconductor layer 201 and first sacrificial layer 202 not covered by photoresist. The substrate 100 can serve as an etching stop layer. This can form a structure such as... Figure 11 The stacked structure 300 shown includes a plurality of first stacked regions 320 extending along the X direction, and a second stacked region 310 connected to the first ends D1 of the plurality of first stacked regions 320 and extending along the Y direction. The plurality of first stacked regions 320 and second stacked regions 310 can form the stacked structure 300, and the area outside the stacked structure 300 is an etched groove 400.

[0190] In some embodiments, step S604 may be performed further, filling the groove 400 formed after etching with insulating material to form Figure 12 The insulation structure 410 is shown. The insulation structure 410 includes a first insulation structure 411 located on the negative X side of the second stacking region 310, a second insulation structure 412 on one or both sides of the first stacking region 320 in the Y direction, and a third insulation structure 413 on the positive X side of the second end D2 of the first stacking region 320.

[0191] The filling height of the insulating material can be flush with the upper surface of the stacked structure 300. In some embodiments, if the filling height of the insulating material exceeds the upper surface of the stacked structure 300, the excess insulating material can be removed using CMP (Chemical Mechanical Polishing). The support structure 410 formed by the insulating material can support several first stacked areas 320 and second stacked areas 310.

[0192] In some embodiments, the method further includes:

[0193] Step S701: At the second end of the first stacked region away from the second stacked region, an insulating material is etched to form a groove located between adjacent first stacked regions;

[0194] Step S702: Fill the groove with insulating material;

[0195] Step S703: Remove the insulating material on the side of the second end away from the first end, and etch part of the sacrificial layer in the first stacked area from the second end along the first direction to form a second multilayer void;

[0196] Step S704: Fill the second end of the first stacked region where part of the sacrificial layer has been etched away with an insulating material to form a support structure.

[0197] After completing step S604, you can continue to execute steps S701 through S704.

[0198] First, execute step S701, as follows: Figure 12 As shown, at the second end D2 of the first stacked region 320, which is away from the second stacked region 310, the insulating material in the fourth interval X4 is etched to form as shown. Figure 13 The slot 402 shown is located between adjacent first stacked regions 320. The first end of the fourth interval X4 overlaps with the second end D2 of the first stacked region 320, and the second end of the fourth interval X4 is located within the first stacked region 320. The etched insulating material is a portion of the insulating material in the second insulating structure 412. The width of the etched slot 402 in the Y direction is the distance between the two first stacked regions 320 in the Y direction, and the length of the etched slot in the X direction is the length of the fourth interval X4.

[0199] Then, step S702 is performed: filling the groove 402 with a separating material, which can be the first separating material, forming a shape as shown in the figure. Figure 14 The semiconductor structure shown includes a first support structure 420.

[0200] exist Figure 13 Multiple slots 402 are filled with a fourth insulating material through deposition or growth processes to form a structure like... Figure 14The first support structure 420 is shown in the diagram. The fourth insulating material includes, but is not limited to, SiN, SiCN, SiBN, and SiON. The upper surface of the first support structure 420 should be flush with the upper surface of the stacked structure. In some embodiments, if the upper surface of the first support structure 420 protrudes beyond the upper surface of the stacked structure, excess fourth insulating material can be removed using CMP (Continuous Metallurgical Processing).

[0201] Then proceed to step S703, remove... Figure 12 The insulating material on the side of the second end D2 away from the first stacking region 320 is removed, i.e., the third insulating structure 413 is removed, and a fourth insulating material is used as an etching stop layer to form a structure such as Figure 15 As shown in the first opening 401, continuing along the negative X direction, a portion of the sacrificial layer 102 in the first stacked region 320 is etched from the second end D2. Specifically, a portion of the sacrificial layer 102 located in the fifth interval X5 (one end of the fifth interval X5 is at the second end D2, and the other end of the fifth interval X5 is within the first stacked region) of the first stacked region 320 is removed to form a shape as shown in the image. Figure 15 The second multi-layer void 500 is shown.

[0202] Then, step S704 is performed, filling the second end D2 of the first stacked region 320 where part of the sacrificial layer 102 has been etched away with an isolation material. This isolation material can be a fifth isolation material, forming a structure as shown in the figure. Figure 16 The second support structure 421 shown is provided, and the first support structure 420 and the second support structure 421 together form the support structure 430.

[0203] The fourth and fifth isolation materials can be the same or different. In this embodiment, both the fourth and fifth isolation materials can be SiN. The second multilayer voids 500 are filled with the fifth isolation material, and the substrate 100 exposed on the side of the second end D2 of the first stacked region 320 away from the first stacked region is further filled with the fifth isolation material. This allows the fifth isolation material filled in steps S702 and S704 to be interconnected with the fourth isolation material, forming a single layer. Figure 16 The support structure 430 shown is used to prevent the semiconductor structure from collapsing in subsequent steps.

[0204] In some embodiments, step S107, forming a plurality of stacked storage structures in the first stacking region, includes:

[0205] After forming the word line structure, multiple stacked capacitor structures are formed using the semiconductor layer of the first stacked region.

[0206] In some embodiments, the memory structure includes a transistor and a capacitor structure; in other embodiments, the memory structure includes a capacitor structure.

[0207] The remaining sacrificial layers in the first stacked region are removed, leaving the semiconductor layers. Multiple stacked capacitor structures are formed based on the multiple semiconductor layers. Since N sacrificial layers are removed from each first stacked region, N stacked capacitor structures can be formed; the stacked structure in this embodiment includes M first stacked regions, which can be used to form N*M capacitor structures.

[0208] In some embodiments, step S107, forming a plurality of stacked storage structures in the first stacking region, includes:

[0209] Step S801: Remove the insulating material between the first stacked areas;

[0210] Step S802: Remove the sacrificial layer in the first stacked region to leave each semiconductor layer suspended;

[0211] Step S803: Perform metal silicide treatment on the surface of the semiconductor layer;

[0212] Step S804: Cover the surface of the semiconductor layer after metal silicide treatment with a first metal material to form the lower electrode of the capacitor structure;

[0213] Step S805: Cover the surface of the lower electrode with a dielectric layer;

[0214] Step S806: Cover the surface of the dielectric layer with a third metal material to form the upper electrode of the capacitor structure;

[0215] Step S807: Fill the gaps between the layers on which the upper electrode is formed and the grooves between the first stacked regions with polycrystalline silicon material.

[0216] In some embodiments, step S107 can be replaced by steps S801 to S807.

[0217] First, perform step S801 to remove... Figure 33 The insulating material located in the sixth interval X6 between the first stacked areas shown.

[0218] Specifically, it is possible Figure 33 The first stacked region 320 shown is coated with photoresist to form a photoresist layer. A patterned photomask (the pattern on the photomask is opaque and corresponds to the pattern on the insulating material) is aligned with the photoresist layer. When the photoresist is negative, the portion corresponding to the photoresist pattern on the photomask is removed, forming an opening in the photoresist layer. The size of this opening exactly covers the insulating material between the first stacked regions. Then, using a dry etching or wet etching process, the insulating material is removed with the substrate as the etching stop layer. After removing the insulating material, a layer is formed as shown... Figure 34 The multiple second grooves 760 are shown.

[0219] Continuing with step S802, the sacrificial layer 102 in the first stacked region 320 is removed, leaving each semiconductor layer 101 suspended. When the material of the semiconductor layer 101 is silicon, a silicon pillar array can be formed. Specifically, an etchant with a high etch selectivity for the sacrificial layer material can be used to remove the sacrificial layer 102 in the first stacked region 320, exposing the semiconductor layers 101 in the first stacked region 320. The semiconductor layers 101 are not connected to each other and are suspended. The capacitor structure is formed based on the semiconductor layers 101. The height between the semiconductor layers 101 (along the Z direction) and the length of the semiconductor layer 101 itself (along the Y direction) determine the size of the capacitor structure to a certain extent.

[0220] Continue with step S803, as follows Figure 34 The surface of the semiconductor layer 101 shown is subjected to metal silicide treatment, so that the surface silicon of the semiconductor layer is treated into metal silicide, forming a structure as shown in the figure. Figure 35 The diagram shows a metal silicide layer 780 covering the surface of the semiconductor layer. Metal silicides include, but are not limited to, titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, etc. On one hand, metal silicides can prevent the reaction between Si and oxygen in the semiconductor layer to form a dense oxide film; therefore, the metal silicide layer 780 can serve as a protective layer for the semiconductor layer. On the other hand, metal silicides have low resistivity, which can also be used to reduce the contact resistance of subsequently formed storage capacitors.

[0221] Continue with step S804, covering the surface of the semiconductor layer after metal silicide treatment with a first metal material to form a layer as shown in the image. Figure 36 The first metal material layer 790 shown is subsequently used to form the lower electrode of a stacked multilayer storage capacitor. The first metal material can be deposited on the surface of the semiconductor layer after metal silicide treatment (including the upper and lower surfaces parallel to the XY plane and the sidewalls in the YZ direction) using a growth process or a deposition process (e.g., atomic layer deposition).

[0222] In some embodiments, the first metallic material may also be deposited on all exposed surfaces of the semiconductor structure, such as the sidewalls (parallel to the YZ direction) of the first isolation layer connecting adjacent semiconductor layers, the substrate surface of the groove after the first insulating material has been removed, the upper surface of the support structure, and so on.

[0223] Subsequently, at least a portion of the sidewalls of the first isolation layer connecting adjacent semiconductor layers in the YZ direction can be removed, so that the first metal material covered by the adjacent semiconductor layers is not connected to each other, that is, the lower electrode of each capacitor is not connected to each other.

[0224] Then, step S805 is performed, using a growth process or deposition process (e.g., atomic layer deposition) to cover the surface of the first metal material layer with a layer such as... Figure 37The dielectric layer 791 is shown. The dielectric layer can be made of a high-k (dielectric constant) dielectric material, such as zirconium oxide (ZrOX) or hafnium oxide (HfO). x The dielectric layer 791 can be formed on the sidewall of the first isolation layer in the YZ direction, and the sidewall is connected to a plurality of semiconductor layers whose surfaces are covered by the dielectric layer 791. That is, the dielectric layers in the plurality of capacitors can be interconnected.

[0225] Then, step S806 is performed, using a growth process or deposition process (e.g., atomic layer deposition) to cover the surface of the dielectric layer 791 with a third metal material, forming the upper electrode of the capacitor structure. The third metal material covered in step S906 can also be formed on the sidewalls of the first isolation layer in the YZ direction, and these sidewalls are connected to multiple semiconductor layers whose surfaces are covered with the third metal material. That is, the upper electrodes of the multiple capacitors can be interconnected. The first metal material and the third metal material can be the same or different.

[0226] Then, step S807 is performed, using a growth process or deposition process to fill polycrystalline silicon material within the silicon pillar array covered with the upper electrode and within the second grooves covered with the upper electrode between each first stacked region, to form... Figure 38 The polycrystalline silicon layer 793 is shown. The height of the upper surface of the filled polycrystalline silicon material is flush with the height of the upper surface of the insulating material. In some embodiments, if the height of the upper surface of the filled polycrystalline silicon material exceeds the height of the upper surface of the insulating material, the excess polycrystalline silicon material can be removed by CMP. In this embodiment, the first metal material and dielectric layer material above the upper surface of the insulating material can also be removed by CMP to form a layer as shown. Figure 38 The semiconductor structure shown includes a polysilicon layer 793 connected to the upper electrode of a capacitor. The filled polysilicon material can serve as a common connection layer for the upper electrodes of multiple capacitors, connecting them to an external circuit.

[0227] In some embodiments, after forming the stacked plurality of capacitor structures, the method further includes:

[0228] Step S901, Remove Figure 38 The insulating material located at the second end D2 of the first stacking region 320 is removed, and at least a portion of the first insulating layer near the second end D2 of the first stacking region 320 is removed to form Figure 40AThe trenches 912 shown are located at both ends of the capacitor structure. This is because the sidewall S2 (along the YZ direction, perpendicular to the substrate surface) where the capacitor structure is combined with the second end D2 of the first stacked region 320 is deposited with a first metal material; the sidewall S3 (along the YZ direction, perpendicular to the substrate surface) where the capacitor structure is combined with the first isolation layer is also deposited with a first metal material. The first metal material connects the multiple capacitor structures between the semiconductor layers. At this time, part of the first metal material at the connection of the multiple capacitor structures can be removed, so that the lower plates of each capacitor structure are separated, thereby separating the capacitor structures. Specifically, it can be done as follows: Figure 38 The upper surface of the semiconductor structure shown is covered with a layer of photoresist. A patterned photomask is used to align the area to be removed, where the photomask pattern corresponds to the region where the isolation material at the second end D2 of the first stacked region 320 is located and the region where the first isolation material is located. Exposure is then performed. The photoresist can be a negative photoresist, in which case the photoresist corresponding to the photomask pattern is removed, such as... Figure 39 The remaining photoresist layer shown is the first photoresist layer 900. Figure 39 The semiconductor structure not covered by the first photoresist layer 900 is etched downwards to form a structure like... Figure 40A The trenches 912 shown at both ends of the capacitor structure include a first trench 910 and a second trench 911.

[0229] Step S902, in Figure 40A The trench 912 shown is filled with insulating material. Filling the trenches 912 at both ends of the capacitor structure with insulating material using a growth process or a deposition process can prevent leakage current generated by the capacitor structure in the semiconductor structure, and at the same time, can electrically isolate the capacitor structure from other structures (e.g., peripheral circuit areas).

[0230] In some embodiments, after forming the first isolation layer 600 as shown in 24A, the method further includes:

[0231] Step S1001: Along the second direction (i.e., the Y direction), metallization processing is performed on the semiconductor layer 101 not covered by the first isolation layer 600 in the second stacking region 310 to form... Figure 25 The formation of the first metal silicide structure 700;

[0232] Specifically, along the Y direction, the semiconductor layer 101 in the second stacked region 310 (where the sacrificial layer has been removed) undergoes a metal silicide treatment, causing the surface silicon of the semiconductor layer 101 to be treated as a metal silicide. Examples include titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, etc. The metal silicide can serve as a protective layer for the semiconductor layer 101. Due to its low resistivity, the metal silicide can also be used to reduce the contact resistance of subsequently formed bit lines.

[0233] Step S1002: Continue to cover the surface of the semiconductor layer with a second metal material to form a structure as shown in the figure. Figure 27A The second metal structure 711 is shown. Specifically, a second metal material can be deposited on the surface of a semiconductor layer covered with metal silicide (including the upper and lower surfaces parallel to the XY plane and the sidewalls in the YZ direction) using a growth process or deposition process (e.g., atomic layer deposition). This second metal structure 711 is used for subsequent formation of bit line structures. In some embodiments, when depositing the second metal material, it is also deposited on the upper surface of the semiconductor structure to form a structure such as... Figure 26 The second metal material layer 710 is shown in the figure. At this time, the excess second metal material covering the second stacked region of the semiconductor structure and the upper surface of the second insulating structure can be removed by a CMP process to form... Figure 27A As shown, the second metal structure 711 is located on the semiconductor layer of the second stacked region.

[0234] Step S1003: Etch a portion of the second metal material at the connection points between each semiconductor layer in the second stacked region along a third direction (i.e., the Z direction), separating the semiconductor layers from each other at the second metal material connections in the third direction; the third direction is perpendicular to the first and second directions. That is, remove at least a portion of the second metal material connecting adjacent semiconductor layers and covering the YZ sidewalls of the first isolation layer, thus separating the semiconductor layers covered by the second metal material from each other. Figure 27C As shown, in the second stacked region, a semiconductor layer covered with a second metal material can serve as a first bit line structure 712. Multiple first bit line structures 712 are stacked in the Z direction and separated from each other. The first bit line structure 712 can serve as a target bit line structure or as an intermediate structure for forming the final bit line structure.

[0235] Step S1004, in Figure 27C The semiconductor layers covered with the second metal material shown (i.e., the first line structure 712) and the side of the second stacked region away from the first stacked region are filled with insulating material to form a structure as shown. Figure 28 The fourth insulating structure 720 is shown.

[0236] Electrical isolation between adjacent first-line structures 712 is achieved by filling the spaces between them with insulating material. Support for multiple first-line structures 712 is provided by also filling the side of the second stacking region away from the first stacking region with insulating material.

[0237] In some embodiments, the method further includes:

[0238] Step S1101: Process the bit line structure to form a stepped structure with decreasing length from bottom to top; the bit line structure can then be further etched.

[0239] Step S1102: Form a lead-out structure on each step structure.

[0240] Bitline structures can be created using staircases. A staircase can be a structure whose length decreases from bottom to top along the Y direction. Specifically, the staircase can be etched by etching a first depth into a first section at the first end of the bitline structure, a second depth into a second section at the first end of the bitline structure, and so on, until all staircases are formed. The first depth is greater than the second depth, and the first section represents the length by which the bottommost bitline structure protrudes relative to the penultimate bitline structure.

[0241] In step S1102 above, a bit line lead-out structure is formed on each step structure. That is, on the steps with different lengths along the Y direction formed in step S1101, metal through holes are formed to connect to other wires as bit line lead-out structures.

[0242] This disclosure also provides a semiconductor structure formed as described in any of the above embodiments. It includes:

[0243] Several first stacking zones extending along a first direction;

[0244] A second stacking area is connected to the first end of a plurality of first stacking areas and extends along a second direction; the first direction is perpendicular to the second direction;

[0245] Each first stack area includes multiple stacked storage structures;

[0246] Each first stack region also includes word line structures located between multiple memory structures and the second stack region; the word line structures extend in a direction perpendicular to the surface of the stack structure;

[0247] The first isolation layer located on the sidewall of the word line structure;

[0248] The second stack region includes a bit line structure that extends along the second direction and is stacked in multiple layers.

[0249] This disclosure also provides a memory, including:

[0250] Semiconductor structures formed by any of the methods described in the above embodiments.

[0251] This disclosure also includes the following examples:

[0252] Step S601: Provide a substrate, the substrate material of which may be Si.

[0253] Step S602: Semiconductor material and sacrificial layer material are alternately stacked sequentially on the substrate. In this embodiment, the semiconductor material may be Si, and the sacrificial layer material may be SiGe. This forms a structure as shown in the diagram. Figure 10The semiconductor structure shown comprises, from bottom to top, a substrate 100, alternatingly stacked first sacrificial layers 201, and a first semiconductor layer 202. The upper surface S1 of this semiconductor structure may also be the upper surface of the uppermost first semiconductor layer 202. In other embodiments, the substrate material may be different from the semiconductor material of the semiconductor layers.

[0254] Step S603: Etch the stacked first sacrificial layer 201 and first semiconductor layer 202 along the X direction to form as shown. Figure 11 The stacked structure 300 shown can be divided along a cross-section AA' parallel to the Y direction into: a plurality of first stacked regions 320 extending along the X direction, each comprising alternately stacked sacrificial layers 102 and semiconductor layers 101; and a second stacked region 310 connected to a first end D1 of the plurality of first stacked regions 320 and extending along the Y direction, comprising alternately stacked sacrificial layers 102 and semiconductor layers 101. Here, the end of the first stacked region 320 connected to the second stacked region 320 in the X direction is called the first end D1, and the end of the first stacked region 320 away from the second stacked region 320 in the X direction is called the second end D2. The direction from the second end D2 to the first end D1 can also be defined as the negative X direction, and the direction from the first end D1 to the second end D2 as the positive X direction. The stacked structure 300 is located on the substrate 100, and the area outside the stacked structure 300 is defined as an etched groove 400. Figure 11 As shown, when viewed from the Z direction downwards, the area exposed by the substrate 100 (i.e. the substrate not covered by the stacked structure 300) can be the area where the groove 400 is located.

[0255] Step S604: Fill the groove 400 formed after etching with an insulating material, which may be an oxide, to form a... Figure 12 The semiconductor structure shown includes an insulating structure 410 formed of oxide located in the aforementioned recess 400. The insulating structure 410 includes a first insulating structure 411 located on the negative X-direction side of the second stacked region, a second insulating structure 412 on one or both sides of the first stacked region in the Y-direction, and a third insulating structure 413 on the positive X-direction side of the second end D2 of the first stacked region.

[0256] Step S701: At the second end D2 of the first stacked region 320 away from the second stacked region 310, etch the insulating material between the second ends D2 of the adjacent first stacked regions 320 to form as shown. Figure 13The slot 402 shown is located between adjacent first stacking areas 320. The length of the slot 402 in the X direction is X4, and the width of the slot 402 in the Y direction is the distance Y1 between the adjacent first stacking areas 320 in the Y direction. In this embodiment of the present disclosure, the thickness of the second insulating structure 412 in the Z direction may be greater than or equal to the depth of the slot 402 in the Z direction.

[0257] Step S702: Fill the groove 402 with a fourth insulating material, which may be SiN, to form a structure as shown in the figure. Figure 14 The semiconductor structure shown includes a first support structure 420 made of a fourth insulating material SiN located within a slot 402. The length of the first support structure 420 in the X direction is X4, and the length in the Y direction is Y1.

[0258] Step S703, Remove Figure 14 The insulating material on the side of the second end D2 of the first stacked region 320 away from the second stacked region 310 (i.e., removing the third insulating structure 413) is used to form a structure as shown. Figure 15 The first opening 401 is shown. After removing the third insulating structure 413, a portion of the sacrificial layer 102 in the first stacked region 320 is etched laterally along the negative X direction starting from the second end D2. The length of the removed sacrificial layer 102 in the X direction can be X5, thus forming a shape as shown. Figure 15 The second multilayer gap 500 shown is separated from the adjacent second multilayer gap 500 by a semiconductor layer 101.

[0259] Step S704, in Figure 15 The second end D2 of the first stacked region 320, where part of the sacrificial layer has been etched away (i.e., the second multilayer void 500), and the first opening 401 are filled with a fifth insulating material to form a second support structure 421. The fifth insulating material can be SiN. The second support structure 421 and the aforementioned first support structure 420 together form as shown in the figure. Figure 16 The support structure 430 is shown. The support structure 430 serves to support the first stacking region 320. In some embodiments, the fourth insulating material used in step S702 may be different from the fifth insulating material used in step S704.

[0260] Step S102, etch along the positive X direction as follows Figure 16 The second stacked region 310 and a portion of the first stacked region 320 are shown as sacrificial layers 102. Before performing step S102, the first isolation structure 411 can be removed by an etching process, with the sidewall of the second stacked region serving as an etching stop layer to form a structure as shown. Figure 17 The semiconductor structure shown includes the second opening 403. Then based on... Figure 17The semiconductor structure shown continues to execute step S102, laterally etching all sacrificial layers in the second stack 320 and the sacrificial layer of length L3 in the first stack region 310 along the positive X direction, forming as shown. Figures 18A to 18B The first multilayer gap 510 is shown. That is, the length L1 of the first multilayer gap 510 in the X direction is equal to the sum of the length L2 of the sacrificial layer of the second stacked region 310 in the X direction and the length L3 etched away in the first stacked region 320 in the X direction. Figure 18B for Figure 18A An enlarged schematic diagram of the first multi-layer void 510 in the middle.

[0261] Step S301, at least to Figure 18A The first multilayer void 510 shown is filled with a first insulating material, which may be SiN. In some embodiments, the first insulating material may also be used to fill the second opening 403 and the location of the first multilayer void 510, forming a structure as shown. Figure 19 The first isolation structure 610 is shown.

[0262] Step S302, along the positive X direction Figure 19 The portion of the first isolation structure 610 outside the first interval X1 is etched. The remaining first isolation structure 610, as shown in Figure 18, can be referred to as the first isolation portion 611. The length of the first isolation portion in the X direction is X1. The first isolation portion 611 contacts the semiconductor layer in the first stacked region 320 in the Z direction. The length X1 of the first isolation portion 611 can be used to define the length of the transistor source or drain. Figure 20 As shown, after step S302 is performed, the semiconductor structure still has a second opening 403 on the negative X-direction side of the second stacking region 310.

[0263] Step S303: Continue along the positive X direction towards Figure 20 The remaining spaces in the first multi-layer voids 510 that were not filled by the first insulating material are filled with the second insulating material, forming a structure as shown in the figure. Figure 21 The second isolation structure 620 is shown. The second isolation material can be a low dielectric constant material, that is, a dielectric with a relatively low dielectric constant (k) (lower than SiO2), including but not limited to inorganic porous materials (e.g., porous silicon oxide materials, porous silicon nitride materials, etc.) and organic porous materials (e.g., porous polyethylene materials, etc.). In embodiments of this disclosure, the second isolation material may be different from the first isolation material.

[0264] Step S304: Along the positive X direction, for Figure 21 The portion of the second isolation structure 620 located outside the second interval X2 is etched to form a shape as shown in the image. Figure 22 The second isolation section 621 is shown. Figure 22This is a partially enlarged view of the first multilayer void filled with the first isolation portion 611 and the second isolation portion 621. The second isolation portion 621 contacts the semiconductor layer in the first stacked region in the Z direction. The length X2 of the second isolation portion 621 in the X direction can be used to define the gate length of the transistor. In subsequent steps, the gate structure of the transistor can be fabricated by replacing the second isolation material with a gate material. Figure 22 As shown, after etching the second isolation structure 620, the second stacking region 310 still has a second opening 403 on the side along the negative X direction.

[0265] Step S305: Continue along the positive X direction towards Figure 22 The remaining portion of the first multi-layer voids 510 that was not filled by the first and second insulating materials is further filled with the first insulating material. The first insulating material also fills the second opening 403, forming a structure as described above. Figure 23 The semiconductor structure shown includes a third isolation structure 630, a second isolation portion 621, and a first isolation portion 611.

[0266] Step S306: Along the positive X direction, for Figure 23 The portion of the third isolation structure 630 located outside the third interval X3 is etched to form a shape like... Figure 24A The third isolation portion 631 shown has a length of X3 in the X direction. The third isolation portion 631 is in contact with the semiconductor layer in the first stacked region in the X direction. The length of the third isolation portion 631 in the X direction can be used to define the length of the source or drain of the transistor. For example, if the length X1 of the first isolation portion 611 in the X direction is used to define the source (or drain) of the transistor, then the length X3 of the third isolation portion 631 in the X direction is used to define the source (or drain) of the transistor. Subsequently, ion implantation of different concentrations can be performed on the semiconductor layer in the first stacked region that is in contact with the first isolation portion 611 and the second isolation portion in the Z direction to form the source and drain of the transistor.

[0267] After steps S301 to S306, the following is formed: Figure 24A , Figure 24B The first isolation layer 600 is shown. Wherein, Figure 24B for Figure 24A A partially enlarged view of the first isolation layer 600. The first isolation layer 600 includes a first isolation portion 611, a second isolation portion 621, and a third isolation portion 631. The first isolation layer 600 is located between the semiconductor layers of the first stacked region, and the first end d1 of the first isolation layer 600 overlaps with the first end D1 of the first stacked region 320 in the X direction.

[0268] Step S1001, along the X direction... Figure 24BThe semiconductor layer 101 in the second stacked region shown, which is not covered by the first isolation layer 600, is subjected to metal silicide treatment to form a first metal silicide structure 700.

[0269] At this point, the second stacked region 310 only includes the semiconductor layer 101. The semiconductor layer 101 located in the second stacked region is processed using a metal silicide process to form a structure as shown below. Figure 25 The diagram shows a metal silicide 700 covering the surface of the semiconductor layer 101 in the second stacked region 310. Specifically, a metal layer (e.g., Ti, Co, and NiPt) is first deposited on the surface of the semiconductor layer 101 in the second stacked region using a PVD process. Then, two rapid thermal annealing (RTA) processes and one selective wet etching process are performed, ultimately forming a first metal silicide structure 700 on the surface of the semiconductor layer 101 in the second stacked region. The metal silicides include, but are not limited to, TiSi2 (titanium silicide), CoSi2 (cobalt silicide), and nickel alloy (e.g., NiPt, NiAl, NiY) silicide films. In this embodiment, since the substrate is a Si substrate, metal silicides can also be formed simultaneously on the exposed surface of the Si substrate.

[0270] Step S1002, for Figure 25 The surface of the semiconductor layer 101, located in the second stacked structure and covered with metal silicide, is further covered with a second metal material, which can be TiN. In actual TiN deposition, TiN not only covers the surface of the first metal silicide structure 700, but also covers the surface of the semiconductor layer 101. Figure 25 The upper surface S1 of the semiconductor structure shown. Therefore, when looking down at the semiconductor structure from the Z direction, only the surface shown is visible. Figure 26 The second metal material layer 710 is shown. The second metal material layer 710 on areas not in the second stack region can be removed using a CMP process. For example... Figure 27A As shown, the second metal material layer 710 retained on the second stacking area can be referred to as the second metal structure 711.

[0271] Step S1003, Etching Figure 27B The second metal material at the junctions of the semiconductor layers in the Z direction separates the semiconductor layers covered by the second metal material from each other in the Z direction. In some embodiments, during the deposition of the second metal material, the second metal material is also deposited onto the sidewalls of the first isolation layer 600, so that adjacent semiconductor layers covered by the second metal material in the second stack region can be connected through the second metal material covered by the sidewalls of the first isolation layer 600.

[0272] A partial enlarged view of the second metal structure 711 in this embodiment is shown below. Figure 27BAs shown, it includes multiple stacked first line structures 712 and second metal material between adjacent first line structures 712. In this embodiment, a lateral etching process can be used to remove part or all of the second metal material between adjacent first line structures 712, such as... Figure 27C As shown, this ensures that the first bit line structures 712 are not connected to each other in the Z direction. The subsequent first bit line structures 712 can also undergo a step-processing technique to form target bit line structures, and each layer of target bit line structure can correspondingly control the memory cell located in the same layer.

[0273] Step S1004, in Figure 27C The semiconductor layers covered with the second metal material, as shown, are filled with an insulating material between them and along one side of the second stacked region in the negative X direction. This insulating material can be an oxide (e.g., silicon nitride). The semiconductor layers covered with the second metal material are the first line structures 712. That is, oxide is filled between the first line structures 712 and along one side of the second stacked region in the negative X direction to form a structure as shown... Figure 28 The fourth insulation structure 720 is shown. The fourth insulation structure 720 can not only electrically isolate the adjacent first line structure 712, but also provide support for the first line structure 712.

[0274] Step S104: Forming such in the insulating material adjacent to the first stacked region 320 Figure 29 The opening 730 shown is perpendicular to the surface of the stacked structure, and the insulating material can be an oxide. Specifically, the opening 730 can be formed by etching a portion of the oxide connected to the first stacked region 320 from the first surface S1 along the Z direction. In some embodiments, the coordinate axis range of the opening 730 in the X direction can be the same as the coordinate axis range of the second isolation portion 621 in the first isolation layer in the X direction, that is, the length of the second isolation portion 621 in the X direction is X2, and the width of the opening 730 in the X direction can also be X2. The plane containing the upper surface of the lowest semiconductor layer in the stacked structure can be used as the etching stop layer for the insulating material adjacent to the first stacked region 320, that is, the depth of the opening 730 can be equal to the thickness of the stacked structure in the Z direction minus the thickness of one semiconductor layer in the Z direction.

[0275] Step S401, from Figure 29 The first isolation layer is etched at the opening 730 to remove the second isolation portion 621 in the first isolation layer, the material used for the second isolation portion 621 including the second isolation material.

[0276] In this embodiment of the present disclosure, at least a portion of the first isolation layer can be removed by wet etching process through the filling of etching solution at the opening 730. This portion of the first isolation layer may be the aforementioned second isolation portion 621, to form as shown in the figure. Figure 30The semiconductor structure shown includes a plurality of vias 740 located between a first isolation portion 611 and a third isolation portion 631. The vias 740 are through-connected to the opening 730. Word line structures can subsequently be formed in the opening 730, and gate structures can be formed in the vias 740. A word line structure can be used to control multiple gate structures interconnected therewith, further controlling multiple transistors.

[0277] Step S501, in such Figure 30 A gate oxide layer is formed on the surface of each semiconductor layer 101 within the opening 730 shown.

[0278] For example, an atomic layer deposition process can be used to deposit a thin oxide film on the surface of the semiconductor 101 exposed by the via 740 and the opening 730 to form... Figure 31A Gate oxide layer 751 in the middle.

[0279] Step S502: Continue to cover the surface of the gate oxide layer 751 with a first metal material (e.g., TiN (titanium nitride)). Figure 31A The gate conductive layer 752 is formed by depositing a TiN layer on the thin film of the gate oxide layer 751 using a growth process or a deposition process. Specifically, in some embodiments, the gate conductive layer 752 may also cover the upper surface of the stacked structure to form a layer such as... Figure 31A The semiconductor structure shown. Figure 31A As shown, both the gate oxide layer 751 and the gate conductive layer 752 can be located in the via 740 and the opening 730. Figure 31B for Figure 31A A partial enlarged view of the through hole 740 and the opening 730.

[0280] Step S503: Fill the via 740 and opening 730 covered with gate conductive layer 752 with a second metal material to form Figure 33 The word line structure 753 is shown. Specifically, the openings 730 and vias 740, which are covered by the gate oxide layer 751 and the gate conductive layer 752, are further filled with a second metal material (e.g., tungsten W). In the actual filling process, the second metal material and the first metal material can be deposited in... Figure 30 On the upper surface of the semiconductor structure shown, a structure as shown is formed. Figure 32 The upper surface shown is a semiconductor structure with a 753 tungsten metal layer, which can be removed using CMP. Figure 32 The excess tungsten metal layer 753 and gate conductive layer 752 on the upper surface of the semiconductor structure shown are used to expose the opening 730 containing the word line structure. Figure 33As shown, the word line structure 754 within the opening 730 includes a gate oxide layer 751, a gate conductive layer 752, and a tungsten metal layer 753. The tungsten metal layer 753 is used to form the word line.

[0281] Step S801: Etching process can be used to remove... Figure 33 The insulating material located between the first stacking regions 320 and in the sixth interval X6. Specifically, it can be used as follows: Figure 33 The upper surface S1 of the semiconductor structure shown is covered with a layer of photoresist. A patterned mask is used to align the area to be removed (the pattern corresponds to the area of ​​insulating material located in the sixth interval X6 between the first stacked regions 320), and then exposure is performed. The photoresist can be a negative photoresist, so the photoresist corresponding to the mask pattern is removed, and etching continues on the areas not covered by photoresist. The substrate can serve as an etching stop layer.

[0282] Step S802: The sacrificial layer in the first stacked region can be removed using a wet etching process, leaving each semiconductor layer suspended, such as... Figure 34 As shown, a semiconductor pillar array (e.g., a silicon pillar array) 770 is formed on both sides of each second groove 760, arranged in the Z direction and stacked in the X direction.

[0283] Step S903: Perform metal silicide treatment on the surface of the semiconductor layer 101 in the first stacked region 320, that is, perform metal silicide treatment on the surface of the semiconductor pillar array 770. In some embodiments, a metal layer (e.g., Ti, Co, and NiPt) can be deposited first on the exposed surfaces of the silicon pillar array and the substrate silicon using a PVD process. Then, two rapid thermal annealing (RTA) processes and one selective wet etching process are performed to finally form a metal layer on the surface of the silicon pillar array. Figure 35 The metal silicide layer 780 shown is covering the silicon pillar array and the silicon substrate surface. The metal silicide includes, but is not limited to, thin films such as TiSi2, CoSi2 and NiPtSi.

[0284] Step S804: Using a deposition process, a first metal material is deposited onto the surface of the semiconductor layer after metal silicide treatment. The first metal material can be TiN, forming a structure as shown in the figure. Figure 34 The first metal material layer 790 shown can be further processed to serve as the lower electrode of a capacitor structure connected to a transistor.

[0285] Step S805: Using a deposition process, a dielectric material is coated onto the surface of the first metal material layer 790 to form a dielectric material as shown in the figure. Figure 37The dielectric layer 791 is shown. This dielectric material can be a high dielectric constant material, which refers to a material with a dielectric constant higher than that of SiO2. The higher the dielectric constant of the dielectric material, the greater the capacitance that the capacitor structure formed can store.

[0286] Step S806: A third metal material is deposited on the surface of the dielectric layer 791 using a deposition process. The third metal material may be TiN, forming the upper electrode of the capacitor structure.

[0287] At this point, a first metal layer 790, a dielectric layer 791, and a top electrode have been formed on all exposed surfaces of the silicon pillar array and the silicon substrate. The top electrodes between adjacent silicon pillars are not connected to each other. Then, step S807 is performed, filling the gaps between the silicon pillars covered with top electrodes and the grooves 760 between the first stacked regions covered with top electrodes with polysilicon material. In some embodiments, polysilicon material is also applied to the upper surface of the uppermost silicon pillar, where excess polysilicon material, dielectric material, and third metal material deposited on its upper surface can be removed by a CMP process. This forms a... Figure 38 The semiconductor structure shown. Figure 38 As shown, the semiconductor structure includes a polycrystalline silicon layer 793.

[0288] In order to use the first metal material layer as the lower electrode of the capacitor structure, the first metal material layer can be divided into multiple mutually separated lower electrodes, so that the first metal material layers contained in each capacitor structure are not electrically connected.

[0289] Step S901, Remove Figure 38 The insulating material located at the second end D2 of the first stacking region 320, i.e., the support structure 430, is removed, and at least a portion of the first insulating layer, i.e., the first insulating portion 611, near the second end D2 of the first stacking region 320 is removed to form Figure 40A The trenches 912 shown are located at both ends of the capacitor structure. In this embodiment, when the first metal material is deposited, the first metal material also covers the sidewall S3 of the first isolation structure 611. At this time, the portion of the first isolation layer 600 (or the first isolation portion 611) connected to the first metal material layer can be removed. In this embodiment, the first isolation portion 611 and the first metal material layer covering the surface S3 of the first isolation portion 611 can be removed. This makes the first metal material layers contained in each capacitor structure independent of each other.

[0290] The first metallic material also covers the exposed sidewall S2 of the support structure 430. Therefore, the first metallic material layer covering the support structure 430 and its sidewall S2 can be removed simultaneously. After step S1001, a structure as shown can be formed. Figure 40AThe trenches 912 shown are located at both ends of the capacitor structure. The trenches 912 include a first trench 910 and a second trench 911. Specifically, they can be... Figure 38 The semiconductor structure shown is covered with photoresist. A patterned photomask is used to align the areas to be removed, and then exposure is performed. This photoresist can be a negative photoresist; in this case, the photoresist corresponding to the photomask pattern is removed, and the remaining photoresist is as follows: Figure 39 As shown. Then, an etching process is used on the un-etched areas. Figure 39 The portion covered by the photoresist is removed to form a shape like... Figure 40A The semiconductor structure shown includes a capacitor structure as follows: Figure 40B As shown. The capacitor structure is located between silicon pillars covered with a metal silicide layer 780, and includes a lower electrode 794, a dielectric layer 791, and an upper electrode 792. The upper electrode 792 also has a polysilicon layer 793. The lower electrodes 794 of different capacitors are not connected to each other, and the upper electrodes 792 of different capacitors are connected together through the polysilicon layer 793.

[0291] Perform step S902: Fill the trench 912 with insulating material. Figure 40A The trench 912 shown is filled with an insulating material, such as an oxide, using a growth or deposition process. This insulating material wraps around the transistor, electrically isolating adjacent transistors to reduce leakage current.

[0292] In some embodiments, step S1101 may also be performed, and the following steps may be performed: Figure 41 The first bitline structure 712 shown is processed to form a stepped structure with lengths decreasing from bottom to top. Different depths and widths of etching can be applied to the first bitline structures located in different layers. For example, a deeper etching process can be applied to the first bitline structure in the lower layer, and a shallower etching process can be applied to the first bitline structure in the upper layer. The etching width along the Y direction for the first bitline structure in the lower layer is smaller than the etching width along the Y direction for the first bitline structure in the upper layer, thus forming a bitline structure with stepped lengths decreasing from bottom to top.

[0293] Step S1102: Form bit line lead-out structures on each step structure. Conductive material can be deposited on the surface of each step that is not covered by the previous step to form bit line lead-out structures on each step structure.

[0294] In this embodiment, a unidirectional side-etching method is used to form the support structure of the bottom frame of the memory structure. During the later formation of the memory structure, this support structure is etched, and the lower electrode material at the connection between the upper and lower memory structures is removed, thereby isolating the upper and lower capacitor structures from each other. After forming the AA region, a unidirectional side-etching method is used, and different isolation materials are filled to define the source, drain, and channel length and range of the transistor. The unidirectional side-etching process can avoid the gate structure irregularity problem caused by bidirectional side-etching. In this embodiment, metal silicide treatment is also applied to the Si layer connected to the capacitor structure and the bit line structure, thereby enhancing the conductivity of the connection between the capacitor structure and the bit line structure.

[0295] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0296] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0297] The above are merely embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A stacked structure is provided, comprising alternating semiconductor layers and sacrificial layers; the stacked structure includes a plurality of first stacked regions extending along a first direction, and a second stacked region connected to a first end of the plurality of first stacked regions and extending along a second direction; wherein the first direction intersects the second direction; and an insulating material is filled between the first stacked regions. The second stacked region and a portion of the sacrificial layer of the first stacked region are etched along the first direction to form a first multilayer void; the semiconductor layer of the second stacked region is used to form a plurality of stacked bit line structures; The portion of the first multilayer void located in the first stacking area is filled to form a first isolation layer; An opening perpendicular to the surface of the stacked structure is formed in the insulating material adjacent to the first stacked region; The first isolation layer is etched from the opening to remove at least a portion of the first isolation layer; A letter line structure extending in a direction perpendicular to the surface of the stacked structure is formed at the opening; Multiple stacked storage structures are formed in the first stacking area.

2. The method according to claim 1, characterized in that, The etching selectivity ratio of the sacrificial layer material used in the sacrificial layer to the semiconductor material used in the semiconductor layer is greater than or equal to a first preset value.

3. The method according to claim 2, characterized in that, The sacrificial layer material is silicon germanide (SiGe), and the semiconductor material is silicon (Si).

4. The method according to claim 1, characterized in that, The portion of the first multi-layer gap located in the first stacked area that is filled to form a first isolation layer includes: Along the first direction, a first isolation material, a second isolation material, and the first isolation material are sequentially filled into the first multi-layer gap to form the first isolation layer; wherein, the length of the first isolation layer along the first direction is greater than or equal to the length of the first multi-layer gap within the first stacking area.

5. The method according to claim 4, characterized in that, The etching selectivity ratio of the second isolation material to the first isolation material is greater than or equal to a second preset value.

6. The method according to claim 4, characterized in that, The step of sequentially filling the first multi-layer voids with a first insulating material, a second insulating material, and the first insulating material to form the first insulating layer includes: Fill the first layer of voids with a first insulating material; The first isolation material is etched, while a portion of the first isolation material located in the first stacked area is retained; Fill the first multi-layer voids with a second insulating material; The second isolation material is etched, and a portion of the second isolation material located in the first stack region is retained; wherein, along the first direction, the length of the retained second isolation material is a predetermined gate length; The first insulating material is then filled into the first multi-layer gaps again. The first isolation material is etched, and the portion of the first isolation material located in the first stacked area and outside the second isolation material is retained.

7. The method according to claim 6, characterized in that, Etching the first isolation layer from the opening to remove at least a portion of the first isolation layer includes: The first insulating layer is etched from the opening to remove the second insulating material from the first insulating layer.

8. The method according to claim 1, characterized in that, The formation of a word line structure at the opening, extending in a direction perpendicular to the surface of the stacked structure, includes: A gate oxide layer is formed on the surface of each of the semiconductor layers within the opening; A first conductive material is coated on the surface of the gate oxide layer as a gate conductive layer; The word line structure is formed by filling the opening covered by the gate conductive layer with a second conductive material.

9. The method according to claim 1, characterized in that, The provided stacked structure, consisting of alternating semiconductor layers and sacrificial layers, includes: Provide substrate; Semiconductor materials and sacrificial layer materials are alternately stacked sequentially on the substrate; The stacked semiconductor material and sacrificial layer material are etched along the first direction to form a plurality of first stacked regions extending along the first direction, and a second stacked region connected to the first end of the plurality of first stacked regions and extending along the second direction; the area outside the stacked structure is a groove formed by etching. The insulating material is filled into the grooves formed after etching.

10. The method according to claim 9, characterized in that, The method further includes: At the second end of the first stacked region, away from the second stacked region, the insulating material is etched to form a groove located between adjacent first stacked regions; Fill the slot with insulating material; Remove the insulating material from the side of the second end away from the first end, and etch a portion of the sacrificial layer in the first stacked region from the second end along the first direction to form a second multilayer void; The isolation material is filled at the second end of the first stacked region where part of the sacrificial layer has been etched away to form a support structure.

11. The method according to claim 10, characterized in that, The plurality of storage structures stacked in the first stacking region include: Remove the insulating material between the first stacked areas; Remove the sacrificial layer in the first stacked region, leaving each semiconductor layer suspended; The surface of the semiconductor layer is subjected to metal silicide treatment; A first metal material is coated on the surface of the semiconductor layer after metal silicide treatment to form the lower electrode of the capacitor structure; A dielectric layer is covered on the surface of the lower electrode; A third metallic material is coated on the surface of the dielectric layer to form the upper electrode of the capacitor structure; Polycrystalline silicon material is filled in the gaps between adjacent semiconductor layers where the upper electrode is formed and in the grooves between each first stacked region.

12. The method according to claim 11, characterized in that, After forming multiple stacked capacitor structures, the method further includes: Remove the insulating material at the second end of the first stacked area, and at the same time remove at least a portion of the first insulating layer on the side of the capacitor structure near the first end to form trenches at both ends of the capacitor structure. The trench is filled with insulating material.

13. The method according to claim 1, characterized in that, After forming the first isolation layer, the method further includes: In the second stack region, the semiconductor layer not covered by the first isolation layer is subjected to metallization along the second direction; A second metallic material is coated on the surface of the semiconductor layer; The second metal material at the connection between the semiconductor layers along a third direction is etched to separate the second metal materials covered by the semiconductor layers from each other; the third direction is perpendicular to the first direction and the second direction. An insulating material is filled between the semiconductor layers covered with the second metal material and on the side of the second stacked region away from the first stacked region; wherein, the semiconductor layers covered with the second metal material are the bit line structure.

14. The method according to claim 13, characterized in that, The method further includes: The bit line structure is processed to form a stepped structure with the length decreasing from bottom to top; A bit line lead-out structure is formed on each of the stepped structures.

15. A semiconductor structure, characterized in that, The semiconductor structure is formed by the method described in any one of claims 1 to 14.

16. A memory, characterized in that, include: The semiconductor structure formed by the method as described in any one of claims 1 to 14.

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