Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: providing a substrate, forming a first groove and a second groove in the substrate; the second groove comprises a bit line groove and an electrode groove which are arranged at intervals in a third direction; the first groove comprises a plurality of first sub-grooves arranged in a first direction; the bit line groove comprises a plurality of sub-bit line grooves arranged in the first direction; the electrode groove comprises a plurality of sub-electrode grooves arranged in the first direction; a word line protruding backward to the first groove is formed at the junction of adjacent first sub-grooves; a first source-drain layer is formed on the sidewall of the first sub-groove; a second source-drain layer protruding backward to the second groove is formed at the junction of adjacent sub-bit line grooves; and an electrode layer electrically connected to the substrate is formed in the electrode groove. The embodiment of the present disclosure can at least improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, and specifically relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a stored binary bit is 1 or 0.

[0003] 3D DRAM is a structure that stacks multiple layers of memory cells. It has a high degree of integration and a larger capacity per unit area, which helps to reduce the cost per unit area. However, the performance of 3D DRAM still needs to be improved. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, which at least helps to improve the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, wherein the method includes: providing a substrate; forming a first trench and a second trench in the substrate, wherein the depth direction of both trenches is a first direction, the arrangement direction of both trenches is a second direction, and the extension direction of both trenches is a third direction; the second trench includes bit line slots and electrode slots spaced apart in the third direction; the first trench includes a plurality of first sub-trenches arranged in the first direction, the bit line slots include a plurality of sub-bit line slots arranged in the first direction, and the electrode slots include a plurality of sub-electrode slots arranged in the first direction; forming word lines protruding away from the first trenches at the junctions of adjacent first sub-trenches; forming a first source / drain layer on the sidewall of the first sub-trench; forming a second source / drain layer protruding away from the second trench at the junctions of adjacent sub-bit line slots; and forming an electrode layer in the electrode slots, wherein the electrode layer is electrically connected to the substrate.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising: a substrate having a first trench and a second trench therein, wherein the depth direction of both trenches is a first direction, the arrangement direction of both trenches is a second direction, and the extension direction of both trenches is a third direction; the second trench includes bit line trenches and electrode trenches spaced apart in the third direction; the first trench includes a plurality of first sub-trenches arranged in the first direction, the bit line trenches include a plurality of sub-bit line trenches arranged in the first direction, and the electrode trenches include a plurality of sub-electrode trenches arranged in the first direction; a word line protruding away from the first trench is provided at the junction of adjacent first sub-trenches; a first source / drain layer is provided on the sidewall of the first sub-trench; a second source / drain layer protruding away from the second trench is provided at the junction of adjacent sub-bit line trenches; an electrode layer is provided in the electrode trench, and the electrode layer is electrically connected to the substrate.

[0007] The technical solution provided in this disclosure has at least the following advantages:

[0008] In this embodiment, a second trench is formed, including a bit line trench and an electrode trench, and an electrode layer electrically connected to the substrate is formed in the electrode trench. The electrode layer can draw out leakage charge in the substrate, avoiding an increase in substrate potential due to charge accumulation, thereby reducing the parasitic capacitance between the substrate and the first and second source / drain layers, and thus reducing leakage current. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0010] Figure 1(a), Figures 1(b) to 29(a) Figures 29(b) and 29(c) show schematic diagrams of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0011] Figures 30(a) to 30(c) Enlarged cross-sectional views of the semiconductor structure in different directions are shown. Detailed Implementation

[0012] As the background technology indicates, the performance of 3D DRAM still needs improvement. Analysis reveals that the main reason is the floating body effect in 3D DRAM. That is, because the substrate is suspended, leakage charge through the substrate cannot flow out, and the accumulated charge on the substrate leads to an increase in substrate potential, thereby increasing the parasitic capacitance between the transistor and the substrate. This results in significant leakage current when the transistor is turned on.

[0013] This disclosure provides a method for manufacturing a semiconductor structure. The method includes: forming bit line trenches and electrode trenches in a substrate, and forming an electrode layer electrically connected to the substrate in the electrode trenches. The electrode layer can draw out leakage charges in the substrate, avoid charge accumulation, thereby reducing the parasitic capacitance between the substrate and the transistor, and thus reducing leakage current.

[0014] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Figures 1(a) to 29(c) As shown, another embodiment of this disclosure provides a method for manufacturing a semiconductor structure. The following will describe in detail the method for manufacturing a semiconductor structure according to an embodiment of this application with reference to the accompanying drawings. It should be noted that, for ease of description and to clearly illustrate the steps of the semiconductor structure fabrication method, Figures 1(a) to 29(c) This is a partial structural diagram of a semiconductor structure.

[0015] refer to Figures 1(a) to 1(b) Figure 1(b) is a top view of the semiconductor structure shown in Figure 1(a). A substrate 1 is provided, and a first trench 2 is formed within the substrate 1. The depth direction of the first trench 2 is a first direction X, and the extension direction of the first trench 2 is a third direction Z. The first trench 2 includes a plurality of first sub-trenches 20 arranged in the first direction X, and the sidewalls of the first sub-trenches 20 are all convex. That is, the sidewalls of the first trench 2 are wavy. It should be noted that, for a more intuitive understanding, the first trench 2 is indicated by white filler blocks in Figure 1(b) and subsequent top views.

[0016] Specifically, the first trench 2 is formed using a Bosch process. The Bosch process involves alternating etching and passivation steps. First, isotropic etching is used to form a first sub-trench 20; a passivation layer is formed on the inner wall of the first sub-trench 20; the passivation layer at the bottom of the first sub-trench 20 is removed; and isotropic etching is used to form another first sub-trench 20. This etching and passivation process is repeated to form multiple first sub-trenches 20 to constitute the first trench 2.

[0017] In some embodiments, the substrate 1 can be made of monocrystalline silicon. Monocrystalline silicon offers material stability, and compared to indium gallium zinc oxide (IGZO) and alternating layers of silicon and germanium silicon, defects in monocrystalline silicon are easier to control, thus contributing to ensuring the performance of the semiconductor structure. Furthermore, based on monocrystalline silicon, the etching gas used in the Bosch process can be sulfur hexafluoride, and the passivation gas can be octafluorocyclobutane.

[0018] Furthermore, the substrate 1 may contain doped ions, and the type of doped ions in the substrate 1 may be opposite to the type of doped ions in the subsequently formed first source / drain layer 61 and second source / drain layer 62 (refer to FIG. 29(a)).

[0019] In some embodiments, the depth h of the first sub-trench 20 in the first direction X is 1 μm to 2 μm, which facilitates the subsequent formation of a first source / drain layer 61 of suitable size (refer to FIG. 29(a)). The protrusion s of the first sub-trench 20 toward the substrate 1 is approximately tens of nanometers, thereby facilitating the subsequent formation of the aperture 22 (refer to FIG. 29(a)). Figure 5 ).

[0020] refer to Figures 2(a) to 2(b) Figure 2(b) is a top view of the semiconductor structure shown in Figure 2(a). A second isolation film 21 is formed on the sidewall of the first trench 2. The second isolation film 21 located at the junction of adjacent first sub-trench 20 protrudes into the first sub-trench 20. That is, since the sidewall of the first trench 2 has a wavy shape, the second isolation film 21 formed on the sidewall of the first trench 2 also has a wavy shape.

[0021] For example, an isotropic deposition process or a thermal oxidation method is used to form a silicon oxide film as the second isolation film 21. In the second direction Y, the thickness of the second isolation film 21 can be 20 nm to 50 nm. It should be noted that when the thickness of the second isolation film 21 is within the above range, it facilitates the retention of the second isolation film 21 located on the sidewall of the first sub-trench 20 when removing the second isolation film 21 at the junction of adjacent first sub-trench 20s. That is, if the thickness of the second isolation film 21 is too large, it is difficult to expose the substrate 1 located at the junction of adjacent first sub-trench 20s; if the thickness of the second isolation film 21 is too small, it may be possible to remove all of the second isolation films 21 at the same time.

[0022] In addition, a portion of the second isolation film 21 may also cover the upper surface of the substrate 1, and this portion of the second isolation film 21 will be removed subsequently.

[0023] refer to Figures 3(a) to 3(b) Figure 3(b) is a top view of the semiconductor structure shown in Figure 3(a). Using the substrate 1 itself as a mask, a portion of the second isolation film 21 located at the junction of adjacent first sub-trench 20 is etched along the first direction X. That is, an anisotropic etching process is used to cut the protruding second isolation film 21 at the junction of adjacent first sub-trench 20 flat, thereby making the second isolation film 21 at this location thinner.

[0024] refer to Figure 4An isotropic etching process is used to remove the remaining second isolation film 21 located at the junction of adjacent first sub-trench 20, so as to expose the substrate 1 located at the junction of adjacent first sub-trench 20. The top view of the semiconductor structure does not change in this step, and can be referred to Figure 3(b).

[0025] In other words, after anisotropic etching, the second isolation film 21 at the junction of adjacent first sub-trench 20 is thinner than the second isolation film 21 on the sidewall of the first sub-trench 20; in the isotropic etching process, the second isolation film 21 at the junction of adjacent first sub-trench 20 will be removed more quickly, thereby exposing a certain width of substrate 1.

[0026] In the first direction X, the width L of the exposed substrate 1 at the junction of adjacent first sub-trench 20 is 20 nm to 50 nm. It should be noted that when the width of the exposed substrate 1 is within the above range, it is beneficial to form holes 22 of appropriate size in the future, that is, to avoid the inner diameter of the holes 22 being too small or the interconnection of adjacent holes 22.

[0027] refer to Figure 5 The substrate 1 exposed by the second isolation film 21 is etched to form holes 22. The top view of the semiconductor structure remains unchanged in this step, as shown in Figure 3(b).

[0028] For example, isotropic etching is performed on the exposed substrate 1 to further open the substrate 1 and form a hole 22. The depth of the hole 22 in the second direction Y can be 100 nm to 200 nm. It should be noted that if the depth of the hole 22 is too small, it may be difficult to provide sufficient filling space for the word line 32, thereby increasing the resistance of the word line 32; if the depth of the hole 22 is too large, defects such as pores may be generated in the word line 32. When the depth of the hole 22 is within the above range, it facilitates subsequent filling of the word line 32, ensures that the word line 32 has appropriate dimensions, reduces defects within the word line 32, and thus improves the performance of the semiconductor structure.

[0029] At this point, based on Figures 3(a) to 3(b) , Figure 4 as well as Figure 5 The steps shown can form a hole 22 protruding away from the first trench 2 at the junction of adjacent first sub-trenches 20. That is, the second isolation membrane 21 can serve as a mask layer for forming the hole 22, and is used to control the position and size of the hole 22.

[0030] refer to Figure 6A gate dielectric layer 31 is formed on the inner wall of the hole 22. The top view of the semiconductor structure remains unchanged during this step, as shown in Figure 3(b). For example, a thermal oxidation process is used to form silicon oxide on the inner wall of the hole 22 as the gate dielectric layer 31 of the transistor. In other embodiments, an atomic layer deposition process can be used to deposit a high dielectric constant material on the inner wall of the hole 22 as the gate dielectric layer 31.

[0031] refer to Figures 7(a) to 7(b) Figure 7(b) is a top view of the semiconductor structure shown in Figure 7(a), in which initial word lines 321 are formed on the sidewalls of the first trench 2 and within the holes 22. For example, tungsten and titanium nitride are deposited as the initial word lines 321 using an isotropic deposition process.

[0032] refer to Figures 8(a) to 8(b) Figure 8(b) is a top view of the semiconductor structure shown in Figure 8(a). An isotropic etching process is used to remove a portion of the initial word line 321 located on the sidewalls of the first trench 2 and within the hole 22. The remaining initial word line 321 within the hole 22 serves as the word line 32. The word line 32 serves as the gate of the transistor, and the gate dielectric layer 31 also covers the word line 32. Specifically, the gate dielectric layer 31 covers the side of the word line 32 away from the interior of the first trench 2.

[0033] At this point, based on Figures 7(a) to 7(b) as well as Figures 8(a) to 8(b) The steps shown can form a character line 32 protruding away from the first groove 2 at the junction of adjacent first sub-grooves 20, and the character line 32 extends along the third direction Z.

[0034] refer to Figures 9(a) to 9(b) Figure 9(b) is a top view of the semiconductor structure shown in Figure 9(a), in which an initial insulating layer 331 is formed within the hole 22 and on the sidewalls of the first sub-trench 20. For example, titanium nitride is deposited using an isotropic deposition process as the initial insulating layer 331 to seal the hole 22. The material of the initial insulating layer 331 can be different from the material of the second isolation film 21, thereby avoiding the removal of the insulating layer 331 during the subsequent removal of the second isolation film 21.

[0035] refer to Figures 10(a) to 10(b) Figure 10(b) is a top view of the semiconductor structure shown in Figure 10(a). Using the substrate 1 itself as a mask, the initial insulating layer 331 located on the sidewall of the first sub-trench 20 is etched along the first direction X. The remaining initial insulating layer 331 serves as the insulating layer 33. The sidewall of the insulating layer 33 is flush with the opening of the hole 22. The gate dielectric layer 31 also covers the surface of the insulating layer 33.

[0036] At this point, based on Figures 9(a) to 9(b) as well as Figures 10(a) to 10(b)The steps shown allow for the formation of an insulating layer 33 within the hole 22, located on the side of the word line 32 facing the first trench 2. It should be noted that the purpose of forming the insulating layer 33 is primarily twofold: first, to isolate the word line 32 from the subsequently formed capacitor plate 82 (refer to FIG. 29(a)) to prevent short circuits; second, the insulating layer 33 can be directly opposite the subsequently formed first source / drain layer 61 (refer to FIG. 29) in the first direction X, i.e., reducing the area of ​​direct contact between the word line 32 and the first source / drain layer 61, thereby reducing the risk of leakage.

[0037] refer to Figures 11(a) to 11(b) Figure 11(b) is a top view of the semiconductor structure shown in Figure 11(a). After forming the word line 32, the structure further includes filling the first trench 2 with a sacrificial layer 22. The sacrificial layer 22 can protect the first trench 2 from contamination in subsequent steps such as forming the second trench 5, the second source / drain layer 62, the metal silicide layer 63, and the bit line 64, thereby ensuring the performance of the semiconductor structure.

[0038] For example, silicon oxide is deposited in the first trench 2 as a sacrificial layer 22. After silicon oxide deposition, a planarization process can be performed to smooth the upper surface of the substrate 1 and the upper surface of the sacrificial layer 22. In some embodiments, the material of the sacrificial layer 22 can be the same as the material of the second isolation film 21, so that the sacrificial layer 22 and the second isolation film 21 can be removed using the same process step, thereby simplifying the manufacturing process.

[0039] refer to Figure 12 , Figure 12 In a top view, a portion of the substrate 1 and a portion of the sacrificial layer 22 are removed to form a plurality of spaced isolation trenches 4, which extend in the second direction Y and are arranged in the third direction Z.

[0040] For example, a mask is formed on the substrate 1 and the sacrificial layer 22, and the substrate 1 and the sacrificial layer 22 are etched using the mask. It should be noted that the word line 32 cannot be cut during the etching process. In other embodiments, the word line 32, as well as the insulating layer 33 and the gate dielectric layer 31 located on the surface of the word line 32, may also not be cut.

[0041] refer to Figure 13 , Figure 13 In a top view, multiple spaced first isolation structures 41 are formed; the multiple first isolation structures 41 extend along the second direction Y and are arranged in the third direction Z. The first isolation structures 41 cover multiple word lines 32, that is, the first isolation structures 41 do not truncate the word lines 32. In addition, the first isolation structures 41 also divide the sacrificial layer 22 into multiple parts.

[0042] For example, silicon nitride is filled into the isolation trench 4 to serve as an isolation structure 41. Subsequently, a planarization process is performed to grind the substrate 1, the sacrificial layer 22, and the upper surface of the isolation structure 41. In some embodiments, the material of the first isolation structure 41 may be different from the material of the sacrificial layer 22, thereby avoiding the consumption of the first isolation structure 41 during the subsequent removal of the sacrificial layer 22.

[0043] refer to Figures 14(a) to 14(b) Figure 14(b) is a top view, and Figure 14(a) is a cross-sectional view of Figure 14(b) along the A-A1 direction. After the first isolation structure 41 is formed, a second trench 5 is formed in the substrate 1. The depth direction of the second trench 5 is the first direction X. The first trench 2 and the second trench 5 are arranged in the second direction Y. The second trench 5 includes multiple second sub-trenches 50 arranged in the first direction X, and the sidewalls of the second sub-trenches 50 are convex. That is, the second trench 5 also has wavy sidewalls. The first isolation structure 41 also spans the first trench 2 and the second trench 5. The first isolation structure 41 divides the second trench 5 into multiple spaced bit line electrode grooves 54. It should be noted that, for a more intuitive understanding, the second trench 5 is indicated by white filler blocks in Figure 14(b) and the subsequent top views.

[0044] Specifically, the second groove 5 is formed using Bosch technology. For details on the specific formation process of the second groove 5, please refer to the detailed description of the first groove 2.

[0045] It should be noted that the material of the first isolation structure 41 and the substrate 1 may be different, so the first isolation structure 41 may not be removed during the process of etching the substrate 1 to form the second trench 5.

[0046] In other embodiments, a second trench 5 extending in the third direction Z can be formed first, followed by the formation of a first isolation structure 41 extending in the second direction Y, to divide the second trench 5 into multiple sections. For example, the first trench 2 and the second trench 5 can be formed in the same process step; then, sacrificial material is filled into the second trench 5; then, structures such as a second isolation membrane 21, a letter line 32, and an insulating layer 33 are formed in the first trench 2; then, the first isolation structure 41 is formed to span the first trench 2 and the second trench 5. Since the first trench 2 and the second trench 5 can be integrated in the same process step, the manufacturing process is simplified.

[0047] refer to Figures 15(a) to 15(b)Figure 15(b) is a top view, and Figure 15(a) is a cross-sectional view of Figure 15(b) along the A-A1 direction, forming an initial second isolation structure 531 that fills the second trench 5, i.e., the initial second isolation structure 531 fills the bit line electrode trench 54. In the third direction Z, the initial second isolation structure 531 and the first isolation structure 41 are alternately arranged. For example, silicon nitride is deposited in the second trench 5 as the initial second isolation structure 531, meaning the material of the initial second isolation structure 531 can be the same as the material of the first isolation structure 41.

[0048] refer to Figures 16(a) to 16(b) Figure 16(b) is a top view, and Figure 16(a) is a cross-sectional view of Figure 16(b) along the A-A1 and B-B1 directions. The initial second isolation structure 531 is graphically processed to form the second isolation structure 53. The second isolation structure 53 extends along the second direction Y and divides the bit line electrode groove 54 into bit line groove 541 and electrode groove 542. That is, the second groove 5 includes bit line grooves 541 and electrode grooves 542 spaced apart in the third direction Z. The bit line groove 541 includes a plurality of sub-bit line grooves 5410 arranged in the first direction X, and the electrode groove 542 includes a plurality of sub-electrode grooves 5420 arranged in the first direction X. The sidewalls of the sub-electrode grooves 5420 and the sub-bit line grooves 5410 are both convex.

[0049] refer to Figures 17(a) to 17(b) Figure 17(b) is a top view, and Figure 17(a) is a cross-sectional view of Figure 17(b) along the A-A1 and B-B1 directions. A first isolation membrane 511 is formed on the sidewalls of the bit line groove 541 and the electrode groove 542. The first isolation membrane 511 located at the junction of adjacent sub-bit line grooves 5410 protrudes towards the interior of the bit line groove 541; the first isolation membrane 511 located at the junction of adjacent sub-electrode grooves 5420 protrudes towards the interior of the electrode groove 542. That is, since the sidewalls of the bit line groove 541 and the electrode groove 542 have a wavy shape, the first isolation membrane 511 formed on the sidewalls of the bit line groove 541 and the electrode groove 542 also has a wavy shape.

[0050] For example, an isotropic deposition process is used to form a silicon nitride film as a first isolation film 511.

[0051] refer to Figures 18(a) to 18(b) Figure 18(b) is a top view, and Figure 18(a) is a cross-sectional view of Figure 18(b) along the A-A1 and B-B1 directions. Using the substrate 1 itself as a mask, a portion of the first isolation film 511 located at the junction of adjacent sub-position line slots 5410 and a portion of the first isolation film 511 located at the junction of adjacent sub-electrode slots 5420 are etched along the first direction X. That is, an anisotropic etching process is used to flatten the protruding first isolation film 511 at the junction of adjacent sub-position line slots 5410 and adjacent sub-electrode slots 5420.

[0052] refer to Figure 19 An isotropic etching process is used to remove the remaining first isolation film 511 at the junction of adjacent sub-position line slots 5410, exposing the substrate 1 at the junction of adjacent sub-position line slots 5410; and to remove the remaining first isolation film 511 at the junction of adjacent sub-electrode slots 5420, exposing the substrate 1 at the junction of adjacent sub-electrode slots 5420. The first isolation film 511 on the sidewalls of the sub-electrode slots 5420 and the sidewalls of the sub-position line slots 5410 serves as the first isolation layer 51. That is, in the isotropic etching process, the thinner first isolation film 511 at the junction of adjacent sub-position line slots 5410 and adjacent electronic electrode slots 5420 is removed more quickly, thereby exposing a certain width of the substrate 1. The top view of the semiconductor structure remains unchanged in this step, as shown in Figure 18(b).

[0053] At this point, based on Figures 17(a) to 17(b) , Figures 18(a) to 18(b) as well as Figure 19 The steps shown can form a first isolation layer 51 located on the sidewall of the sub-position line slot 5410 and the sidewall of the sub-electrode slot 5420. The first isolation layer 51 exposes the substrate 1 at the junction of adjacent sub-position line slots 5410 and exposes the substrate 1 on the sidewall of adjacent sub-electrode slots 5420.

[0054] refer to Figures 20(a) to 20(c) Figure 20(c) is a top view, Figure 20(a) is a cross-sectional view of Figure 20(c) along the A-A1 direction, and Figure 20(b) is a cross-sectional view of Figure 20(c) along the B-B1 direction. A first mask layer 55 is formed to fill the electrode trench 542, and the first mask layer 55 exposes the bit line trench 541. For example, photoresist is filled in the electrode trench 542 and the bit line trench 541 as an initial first mask layer. The initial first mask layer 55 is photolithographically processed to remove the initial first mask layer in the bit line trench 541, and the remaining initial first mask layer serves as the first mask layer 55. A portion of the first mask layer 55 is also located on the upper surface of the substrate 1.

[0055] Referring again to FIG20(a), a second source / drain layer 62 protruding away from the second trench 5 is formed at the junction of adjacent sub-slots 5410. The second source / drain layer 62 is also in contact with the gate dielectric layer 31. For example, after forming the first isolation layer 51, the substrate 1 at the junction of adjacent sub-slots 5410 is plasma-doped to form the second source / drain layer 62. That is, the first isolation layer 51 can serve as a mask for forming the second source / drain layer 62, controlling the position and size of the second source / drain layer 62 and preventing interconnection between adjacent second source / drain layers 62 in the first direction X. The dopant ions of the second source / drain layer 62 can be n-type ions.

[0056] The second source / drain layer 62 and the word line 32 are both located between the first trench 2 and the second trench 5, and the second source / drain layer 62 is disposed opposite to the word line 32. The second source / drain layer 62 is also in contact with the gate dielectric layer 31.

[0057] A first isolation structure 41 and a second isolation structure 53 are provided between adjacent second source / drain layers 62 in the third direction Z. Therefore, adjacent second source / drain layers 62 in the third direction Z are mutually isolated. A first isolation layer 51 is provided between adjacent second source / drain layers 62 in the first direction X. Therefore, adjacent second source / drain layers 62 in the first direction X are also mutually isolated.

[0058] refer to Figure 21 A portion of the second source / drain layer 62 near the interior of the second trench 5 is removed to form a contact port 52. For example, using the first mask layer 55 as a mask, isotropic etching is employed to remove the portion of the second source / drain layer 62 exposed by the first isolation layer 51, thereby increasing the exposed area of ​​the second source / drain layer 62. The top view and cross-sectional view along the B-B1 direction of the semiconductor structure remain unchanged in this step, as shown in Figure 20(c).

[0059] refer to Figures 22(a) to 22(c) Figure 22(c) is a top view, Figure 22(a) is a cross-sectional view of Figure 22(c) along the A-A1 direction, and Figure 22(b) is a cross-sectional view of Figure 22(c) along the B-B1 direction. The first mask layer 55 is removed to form a second mask layer 56 filling the bit line trench 541, exposing the electrode trench 542. For example, after cleaning the old photoresist, new photoresist is filled into the bit line trench 541 and the electrode trench 542 as an initial second mask layer. The initial second mask layer is then photolithographically processed to remove the initial second mask layer located within the electrode trench 542, leaving the remaining initial second mask layer as the second mask layer 56. A portion of the second mask layer 56 is also located on the upper surface of the substrate 1.

[0060] Referring again to Figure 22(b), the substrate 1 at the junction of adjacent sub-electrode trenches 5420 is heavily doped to form a heavily doped layer 71. For example, p-shaped dopant ions are implanted into the substrate 1 using plasma doping to form the heavily doped layer 71. That is, the type of dopant ions in the heavily doped layer 71 can be the same as the type of dopant ions in the substrate 1. This provides a rapid outflow channel for charge within the substrate 1, preventing charge accumulation within the substrate 1.

[0061] In the second direction Y, the doping depth of the heavily doped layer 71 is less than the doping depth of the second source / drain layer 62. That is, the smaller doping depth of the heavily doped layer 71 can prevent the second source / drain layer 62 from contacting the heavily doped layer 71, and also prevent the heavily doped layer 71 from contacting the gate dielectric layer 31, thereby avoiding leakage or short circuit problems.

[0062] It should be noted that since the first isolation layer 51 on the sidewalls of the sub-position groove 5410 and the sub-electrode groove 5420 is formed in the same process step, the manufacturing process is simpler. In some other embodiments, the first isolation layer 51 may be formed only on the sidewall of the sub-position groove 5410 and not on the sidewall of the sub-electrode groove 5420. This exposes the entire sidewall of the electrode groove 542, allowing a heavily doped layer 71 to be formed on the entire sidewall of the electrode groove 542. This increases the contact area between the heavily doped layer 71 and the substrate 1, thereby increasing the charge outflow rate within the substrate 1.

[0063] refer to Figures 23(a) to 23(c) Figure 23(c) is a top view, Figure 23(a) is a cross-sectional view of Figure 23(c) along the A-A1 direction, and Figure 23(b) is a cross-sectional view of Figure 23(c) along the B-B1 direction. The second mask layer 56 is removed, exposing the bit groove 541.

[0064] Referring again to FIG23(a), a second metal silicide layer 63 is formed on the side of the second source / drain layer 62 facing the interior of the bit line groove 541. The second metal silicide layer 63 is also located within the contact port 52. For example, a metal layer is first deposited within the contact port 52, and the metal layer is annealed to react with the second source / drain layer 62 to generate the second metal silicide layer 63.

[0065] It should be noted that the contact port 52 can increase the contact area between the second metal silicide layer 63 and the second source / drain layer 62, thereby reducing the contact resistance. In some embodiments, the second metal silicide layer 63 may only adhere to the inner wall of the contact port 52 without completely filling it; that is, the subsequently formed bit line 64 may also fill the contact port 52, which helps to increase the filling space of the bit line 64 and the contact area between the bit line 64 and the second metal silicide layer 63. In other embodiments, the second metal silicide layer 63 may also completely fill the contact port 52.

[0066] Referring to FIG23(b), a first metal silicide layer 72 is formed on the side of the heavily doped layer 71 facing the interior of the electrode trench 542. For example, a metal layer is formed on the sidewall of the heavily doped layer 71, and a high-temperature annealing process is performed to cause the metal layer to react with the heavily doped layer 71, thereby generating the first metal silicide layer 72.

[0067] In some embodiments, a first metal silicide layer 72 and a second metal silicide layer 63 can be formed simultaneously, thereby simplifying the manufacturing process and reducing production costs. The first metal silicide layer 72 can be located between the heavily doped layer 71 and the subsequently formed conductive layer 73, thereby reducing the contact resistance between the subsequently formed conductive layer 73 and the heavily doped layer 71; the second metal silicide layer 63 can be located between the subsequently formed bit line 64 and the second source / drain layer 62, thereby reducing the contact resistance between the formed bit line 64 and the second source / drain layer 62, and thus improving the electrical performance of the semiconductor structure. In other embodiments, the first metal silicide layer 72 and the second metal silicide layer 63 may not be formed.

[0068] refer to Figures 24(a) to 24(c) Figure 24(c) is a top view, Figure 24(a) is a cross-sectional view of Figure 24(c) along the A-A1 direction, and Figure 24(b) is a cross-sectional view of Figure 24(c) along the B-B1 direction. Bit lines 64 are formed to fill the bit line trench 541 and are connected to the second metal silicide layer 63, i.e., bit lines 64 are electrically connected to the second source / drain layer 62. A conductive layer 73 is formed to fill the electrode trench 542 and is electrically connected to the heavily doped layer 71.

[0069] For example, tungsten and titanium nitride metal material layers are simultaneously deposited in the bit line groove 541 and the electrode groove 542. The metal material layer in the bit line groove 541 serves as the bit line 64, and the metal material layer in the electrode groove 542 serves as the conductive layer 73. Since the bit line 64 and the conductive layer 73 can be formed in the same process step, the manufacturing process is simpler. After depositing the metal material layers, the metal material layers can be polished and ground smooth.

[0070] Depend on Figures 24(a) to 24(c) It is known that bit lines 64 extend along the first direction X, and each bit line 64 is electrically connected to multiple second source / drain layers 62 in the first direction X. A first isolation structure 41 and a second isolation structure 53 are provided between two adjacent bit lines 64 in the third direction Z. The conductive layer 73 extends along the first direction X, and also provides a first isolation structure 41 and a second isolation structure 53 between two adjacent bit lines 64 in the third direction Z. That is, bit lines 64 can be parallel to the conductive layer 73, and the two are alternately arranged in the third direction Z.

[0071] At this point, based on Figures 22(a) to 22(c) , Figures 23(a) to 23(c) and Figures 24(a) to 24(c) The steps shown allow for the formation of an electrode layer 7 within the electrode trench 542, with the electrode layer 7 electrically connected to the substrate 1. The electrode layer 7 includes a first metal silicide layer 72, a conductive layer 73, and a heavily doped layer 71. In other embodiments, the electrode layer 7 may include the conductive layer 73 and the heavily doped layer 71, or the electrode layer 7 may consist solely of the conductive layer 73.

[0072] refer to Figures 25(a) to 25(c) Figure 25(c) is a top view, Figure 25(a) is a cross-sectional view of Figure 25(c) along the A-A1 direction, and Figure 25(b) is a cross-sectional view of Figure 25(c) along the B-B1 direction. Part of the bit line 64 and part of the conductive layer 73 are etched back, and a third insulating film 52 is formed to seal the top of the bit line groove 541 and the electrode groove 542. The third insulating film 52 protects the bit line 64 and the conductive layer 73 from contamination and oxidation.

[0073] refer to Figures 26(a) to 26(b) Figure 26(b) is a top view, and Figure 26(a) is a cross-sectional view of Figure 26(b) along the A-A1 direction. The sacrificial layer 22 and the second isolation film 21 located on the sidewall of the first sub-trench 20 are removed, thereby exposing the sidewall of the first sub-trench 20. For example, a wet etching process is used to remove the sacrificial layer 22 and the second isolation film 21.

[0074] refer to Figures 27(a) to 27(b) A first source / drain layer 61 is formed on the sidewall of the first sub-trench 20. The top view of the semiconductor structure remains unchanged in this step, as shown in FIG26(b). FIG27(a) is a cross-sectional view of FIG26(b) along the A-A1 direction, and FIG27(b) is a cross-sectional view of FIG26(b) along the B-B1 direction. The first source / drain layer 61 is also in contact with the gate dielectric layer 31. Furthermore, a first isolation structure 41 is provided between adjacent first source / drain layers 61 in the third direction Z to prevent mutual interference between adjacent first source / drain layers 61. Additionally, an insulating layer 33 is provided between adjacent first source / drain layers 61 in the first direction X.

[0075] Specifically, the sidewalls of the first sub-trench 20 are doped to form a first source / drain layer 61. For example, n-type dopant ions are implanted into the substrate 1 exposed within the first trench 2 using a plasma doping process. It should be noted that the first source / drain layer 61 has a shallow doping depth in the second direction Y, which allows the first source / drain layer 61 to be offset from the word line 32 in the first direction X, avoiding or reducing the overlap area between them, thereby preventing leakage between the first source / drain layer 61 and the word line 32.

[0076] refer to Figures 28(a) to 28(b) Figure 28(b) is a top view, and Figure 28(a) is a cross-sectional view of Figure 28(b) along the A-A1 direction. A dielectric layer 81 is formed on the sidewall of the first trench 2, and the dielectric layer 81 also covers the first source / drain layer 61. For example, a high dielectric constant material is deposited as the dielectric layer 81. A high dielectric constant material is beneficial for improving capacitance.

[0077] Continue to refer to Figures 28(a) to 28(b)Multiple capacitor plates 82 are formed at intervals within the first trench 2, and the capacitor plates 82 are also covered by a dielectric layer 81; the multiple capacitor plates 82 are arranged in the third direction Z and extend in the first direction X. The capacitor plates 82 arranged adjacently in the third direction Z are separated by a first isolation structure 41.

[0078] In other words, the first source / drain layer 61, the capacitor plate 82, and the dielectric layer 81 constitute a capacitor, which is connected to the transistor formed by the first source / drain layer 61, the second source / drain layer 62, and the word line 32. It is understandable that since the first source / drain layer 61 also serves as a capacitor plate, it is advantageous to eliminate the need for an electrical connection structure between the first source / drain layer 61 and the capacitor, thus simplifying the manufacturing process.

[0079] For example, the first trench 2 is filled with metals such as tungsten and titanium nitride as capacitor plates 82, and then the capacitor plates 82 and the upper surface of the substrate 1 are polished.

[0080] refer to Figures 29(a) to 29(c) The capacitor plate 82 is etched back, and a fourth isolation film 23 is deposited to seal the top of the first trench 2. The fourth isolation film 23 can protect the capacitor plate 82. For example, the material of the fourth isolation film 23 can be silicon nitride.

[0081] At this point, based on Figures 1(a) to 29(c) The steps shown can complete the front-end manufacturing of 3D DRAM. It is worth noting that performing the process steps in the aforementioned order helps reduce contamination of the semiconductor structure and reduces impurity residue. In other embodiments, the order of the process steps can also be adjusted. For example, a second trench 5 can be formed first, and then divided into bit line trenches 541 and electrode trenches 542. Subsequently, a second source / drain layer 62, a second metal silicide layer 63, and bit lines 64 are formed based on the wavy bit line trenches 541, and an electrode layer 7 is formed within the electrode trenches 542. Then, a first trench 2 is formed, and word lines 32, dielectric layers 81, and capacitor plates 82 are formed based on the wavy first trench 2. Alternatively, the first trench 2, word lines 32, first source / drain layers 61, dielectric layers 81, and capacitor plates 82 can be formed first, followed by the formation of the second trench 5, second source / drain layers 62, and bit lines 64.

[0082] In summary, the embodiments of this disclosure employ Bosch processes to form a first trench 2 and a second trench 5 with a wavy shape. Word lines 32 and a first source / drain layer 61 are formed based on the wavy first trench 2, and a second source / drain layer 62 is formed based on the wavy second trench 5. Therefore, transistors can be formed within the silicon substrate 1, avoiding the use of IGZO and Superlattice technologies, which produce transistors with numerous defects. Consequently, the method of the embodiments of this disclosure helps reduce defects within the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0083] Furthermore, an electrode layer 7 electrically connected to the substrate 1 is formed, and the electrode layer 7 can be connected to a power source in the peripheral region. This prevents charge accumulation within the substrate 1, thereby avoiding the floating body effect and improving the performance of the semiconductor structure. Additionally, the electrode layer 7 may also include a heavily doped layer 71 and a first metal silicide layer 72 to guide rapid charge outflow.

[0084] This disclosure provides a semiconductor structure according to one embodiment. This semiconductor structure can be manufactured using the manufacturing method provided in the foregoing embodiments. For a detailed description of this semiconductor structure, please refer to the foregoing embodiments. Further details will not be repeated here.

[0085] refer to Figures 29(a) to 29(c) as well as Figures 30(a) to 30(c) Figure 30(a) is a partial enlarged view of Figure 29(a), Figure 30(b) is a partial enlarged view of Figure 29(b), and Figure 30(c) is a partial cross-sectional enlarged view of the semiconductor structure, with the cross-section perpendicular to the first direction X. The semiconductor structure includes: a substrate 1, which has a first trench 2 and a second trench 5, both of which have a depth direction of a first direction X, an arrangement direction of a second direction Y, and an extension direction of a third direction Z; the second trench 5 includes bit line trenches 541 and electrode trenches 542 spaced apart in the third direction Z; the first trench 2 includes a plurality of first sub-trenches 20 arranged in the first direction X, the bit line trenches 541 include a plurality of sub-bit line trenches 5410 arranged in the first direction X, and the electrode trenches 542 include a plurality of sub-electrode trenches 5420 arranged in the first direction X; a word line 32 protruding away from the first trench 2 is provided at the junction of adjacent first sub-trenches 20; a first source / drain layer 61 is provided on the sidewall of the first sub-trench 20; a second source / drain layer 62 protruding away from the second trench 5 is provided at the junction of adjacent sub-bit line trenches 5410; and an electrode layer 7 is provided in the electrode trench 542, and the electrode layer 7 is electrically connected to the substrate 1.

[0086] The semiconductor structure will now be described in detail. First, it should be noted that the semiconductor structure has a first direction X, a second direction Y, and a third direction Z, and these three directions are not identical. For example, the first direction X is perpendicular to the second direction Y and the third direction Z, and the second direction Y is perpendicular to the third direction Z. In some embodiments, the semiconductor structure can be a Dynamic Random Access Memory (DRAM).

[0087] The semiconductor structure also includes a gate dielectric layer 31, which covers the side of the word line 32 away from the interior of the first trench 2, and is in contact with the first source / drain layer 61 and the second source / drain layer 62. That is, the first source / drain layer 61, the second source / drain layer 62, the word line 32, and the gate dielectric layer 31 can be used to form a transistor.

[0088] The semiconductor structure also includes: a plurality of capacitor plates 82 filling the first trench 2; the plurality of capacitor plates 82 are spaced apart in the third direction Z and extend along the first direction X. The semiconductor structure also includes: a dielectric layer 81 located on the sidewall of the first trench 2, the dielectric layer 81 further covering the first source / drain layer 61 and located between the first source / drain layer 61 and the capacitor plates 82. That is, the first source / drain layer 61, the dielectric layer 81 and the capacitor plates 82 constitute a capacitor. The capacitor and the transistor can form a basic memory cell.

[0089] Referring to Figure 30(a), when an enable voltage is supplied to word line 32, two channels are formed, meaning current flows between the first source / drain layer 61 and the second source / drain layer 62 on both the upper and lower sides of word line 32. When the transistor is turned on, the capacitor can store or release charge.

[0090] Referring again to Figure 30(a), since the upper and lower transistors share a first source-drain layer 61, adjacent transistors can be switched off simultaneously to prevent read / write errors. In some embodiments, the transistors include an isolation transistor and active transistors, which are alternately arranged in the first direction X. A normally off voltage is supplied to the isolation transistor to isolate the two active transistors. In other words, an isolation transistor is provided between the two active transistors, thereby increasing the distance between the active transistors, and the isolation transistor is in a normally off state, thus isolating the two active transistors and preventing mutual interference between adjacent active transistors.

[0091] Referring to FIG. 29(b), the electrode trench 542 includes a plurality of sub-electrode trenches 5420 arranged in the second direction Y. Referring to FIG. 29(b) and FIG. 30(b), the electrode layer 7 includes an electrically connected heavily doped layer 71 and a conductive layer 73, wherein the heavily doped layer 71 is located at least within the substrate 1 at the junction of adjacent sub-electrode trenches 5420, and the conductive layer 73 fills the electrode trench 542. In some embodiments, the heavily doped layer 71 may also cover the entire sidewall of the electrode trench 542. In addition, the electrode layer 7 may also include a first metal silicide layer 72, which is located between the conductive layer 73 and the heavily doped layer 71.

[0092] To more clearly illustrate the first groove 2 and the second groove 5, Figures 29(a) to 29(c) Only one first trench 2 and one second trench 5 are shown in the diagram. In other embodiments, there may be multiple first trenches 2 and multiple second trenches 5, and the first trenches 2 and the second trenches 5 may be arranged alternately in the second direction Y, which is beneficial to increasing the number of transistors and capacitors, thereby increasing the storage capacity.

[0093] In some embodiments, reference Figures 29(a) to 29(c) Multiple first source-drain layers 61 are spaced apart in the third direction Z; multiple second source-drain layers 62 are spaced apart in the third direction Z; and word lines 32 extend along the third direction Z. That is, multiple transistors can be arranged in the third direction Z, and word lines 32 can serve as the gates of the multiple transistors arranged in the third direction Z. Furthermore, both the first source-drain layers 61 and the second source-drain layers 62 can extend in the third direction Z, meaning both can be columnar structures in the third direction Z.

[0094] The semiconductor structure also includes multiple bit lines 64 filling the second trench 5. These bit lines 64 are spaced apart in the third direction Z and extend along the first direction X. The bit lines 64 are electrically connected to the second source / drain layers 62. In other words, the bit lines 64 are electrically connected to the multiple second source / drain layers 62 arranged in the first direction X. The bit lines 64 are also electrically connected to peripheral circuitry and are used to read stored data from memory cells or write data to memory cells.

[0095] Furthermore, referring to FIG29(c), the semiconductor structure also includes a plurality of spaced-apart first isolation structures 41, which extend along the second direction Y and are arranged in the third direction Z; the first isolation structures 41 span the first trench 2 and the second trench 5, and cover a plurality of word lines 32. That is, the first isolation structures 41 are used to isolate a plurality of transistors arranged in the third direction Z, but do not truncate the word lines 32. Specifically, there are first isolation structures 41 between adjacent first source-drain layers 61 in the third direction Z, and there are first isolation structures 41 between adjacent second source-drain layers 62 in the third direction Z. In addition, the first isolation structures 41 are also used to isolate adjacent capacitor plates 82 in the third direction Z.

[0096] In some embodiments, the semiconductor structure further includes a second isolation structure 53 extending along a second direction Y. A first isolation structure 41 divides the second trench 5 into a plurality of bit line electrode trenches 54 arranged in a third direction Z, and the second isolation structure 53 divides the bit line electrode trenches 54 into bit line trenches 541 and electrode trenches 542. This achieves isolation between the bit line 64 and the electrode layer 7.

[0097] In summary, the semiconductor structure provided in this disclosure has 3D stacked transistors and capacitors, which constitute a memory cell. In the first direction X, interference between adjacent memory cells can be avoided by not simultaneously activating them. In the third direction Z, adjacent memory cells are separated by a first isolation structure 41. Additionally, the semiconductor structure includes an electrode layer 7 electrically connected to the substrate 1 to avoid a floating body effect. The electrode layer 7 is disposed parallel to the bit line 64, and the two are alternately arranged in the third direction Z, and separated by a second isolation structure 53.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided in which a first trench and a second trench are formed, wherein the depth direction of both trenches is the first direction, the arrangement direction of both trenches is the second direction, and the extension direction of both trenches is the third direction. The second trench includes bit line grooves and electrode grooves spaced apart in the third direction; the first trench includes a plurality of first sub-grooves arranged in the first direction, the bit line groove includes a plurality of sub-bit line grooves arranged in the first direction, and the electrode groove includes a plurality of sub-electrode grooves arranged in the first direction. A letter line protruding away from the first groove is formed at the junction of adjacent first sub-grooves; A first source / drain layer is formed on the sidewall of the first sub-trench; A second source / drain layer protruding away from the second trench is formed at the junction of adjacent sub-position grooves; An electrode layer is formed within the electrode groove, and the electrode layer is electrically connected to the substrate.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The electrode groove includes a plurality of sub-electrode grooves arranged in the first direction, and the sidewalls of the sub-electrode grooves are convex. The steps for forming the electrode layer include: The substrate at least at the junction of adjacent sub-electrode trenches is heavily doped to form a heavily doped layer; A conductive layer is formed to fill the electrode trench, the conductive layer being electrically connected to the heavily doped layer, and the two constituting the electrode layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Before forming the electrode layer and the first source / drain layer, the method further includes: forming a first isolation layer located on the sidewall of the sub-position slot and the sidewall of the sub-electrode slot, wherein the first isolation layer exposes the substrate at the junction of adjacent sub-position slots and exposes the substrate on the sidewall of adjacent sub-electrode slots.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, The method for forming the first isolation layer includes: A first isolation membrane is formed on the sidewall of the bit line groove and the electrode groove; the first isolation membrane located at the junction of adjacent sub-bit line grooves protrudes toward the interior of the bit line groove; the first isolation membrane located at the junction of adjacent sub-electrode grooves protrudes toward the interior of the electrode groove. Using the substrate itself as a mask, a portion of the first isolation film located at the junction of adjacent sub-electrode slots and a portion of the first isolation film located at the junction of adjacent sub-electrode slots are etched along the first direction. An isotropic etching process is used to remove the remaining first isolation film at the junction of adjacent sub-position line slots to expose the substrate at the junction of adjacent sub-position line slots; and to remove the remaining first isolation film at the junction of adjacent sub-electrode slots to expose the substrate at the junction of adjacent sub-electrode slots; the first isolation film on the sidewall of the sub-electrode slot and the sidewall of the sub-position line slot serves as the first isolation layer.

5. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, After the first isolation layer is formed, the substrate at the junction of adjacent sub-slots is doped to form the second source / drain layer.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The doping depth of the heavily doped layer is less than the doping depth of the second source / drain layer.

7. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Also includes: A first metal silicide layer is formed between the conductive layer and the heavily doped layer; The first metal silicide layer, the conductive layer, and the heavily doped layer constitute the electrode layer.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Also includes: A second metal silicide layer is formed on the side of the second source / drain layer facing the inside of the bit groove; A bit line is formed to fill the bit line groove, and the bit line is connected to the second metal silicide layer.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The sidewall of the first sub-groove is convex. Before forming the word line, the method further includes: forming a hole protruding away from the first groove at the junction of adjacent first sub-grooves; A gate dielectric layer is formed on the inner wall of the hole, the gate dielectric layer covers the word line and is in contact with the first source / drain layer and the second source / drain layer.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, After forming the word line, the method further includes: forming an insulating layer inside the hole, the insulating layer being located on the side of the word line near the first trench; the gate dielectric layer also covering the surface of the insulating layer.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, The steps for forming the hole include: A second isolation membrane is formed on the sidewall of the first trench, and the second isolation membrane located at the junction of adjacent first sub-trenches protrudes toward the interior of the first sub-trench; Using the substrate itself as a mask, a portion of the second isolation film located at the junction of adjacent first sub-trenches is etched along the first direction; An isotropic etching process is used to remove the remaining second isolation film located at the junction of adjacent first sub-trenches, so as to expose the substrate located at the junction of the adjacent first sub-trenches.

12. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps of forming the first trench, the bit line trench, and the electrode trench include: The first and second trenches are formed using Bosch technology; Multiple first isolation structures are formed at intervals, and the multiple first isolation structures extend along a second direction and are arranged in the third direction; The first isolation structure spans the first trench and the second trench; the first isolation structure divides the second trench into a plurality of spaced bit line electrode trenches; the first isolation structure covers a plurality of word lines, and has the first isolation structure between the first source / drain layers adjacent to each other in the third direction, and has the first isolation structure between the second source / drain layers adjacent to each other in the third direction. A second isolation structure is formed extending along the second direction, the second isolation structure dividing the bit line electrode groove into a bit line groove and an electrode groove.

13. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Also includes: A dielectric layer is formed on the sidewall of the first trench, and the dielectric layer also covers the first source / drain layer; After forming the dielectric layer, the method further includes: forming a plurality of spaced capacitor plates in the first trench, wherein the plurality of capacitor plates are arranged in the third direction and extend in the first direction.

14. A semiconductor structure, characterized in that, include: The substrate has a first trench and a second trench, both of which have a depth direction in the first direction, an arrangement direction in the second direction, and an extension direction in the third direction. The second trench includes bit line grooves and electrode grooves spaced apart in the third direction; the first trench includes a plurality of first sub-grooves arranged in the first direction, the bit line groove includes a plurality of sub-bit line grooves arranged in the first direction, and the electrode groove includes a plurality of sub-electrode grooves arranged in the first direction. The junction of adjacent first sub-grooves has a character line protruding away from the first groove; The sidewall of the first sub-trench has a first source / drain layer; The junction of adjacent sub-slots has a second source / drain layer that protrudes away from the second trench; The electrode groove has an electrode layer, and the electrode layer is electrically connected to the substrate.

15. The semiconductor structure according to claim 14, characterized in that, The electrode groove includes a plurality of sub-electrode grooves arranged in the second direction; The electrode layer includes an electrically connected heavily doped layer and a conductive layer, wherein the heavily doped layer is located at least within the substrate at the junction of adjacent sub-electrode trenches, and the conductive layer fills the electrode trenches.

16. The semiconductor structure according to claim 14, characterized in that, Also includes: A dielectric layer located on the sidewall of the first trench, the dielectric layer also covering the first source / drain layer; The first trench has a plurality of spaced capacitor plates, which are arranged in the third direction and extend in the first direction. The semiconductor structure further includes bit lines filling the bit line slots.

17. The semiconductor structure according to claim 14, characterized in that, Also includes: A plurality of first isolation structures are spaced apart, and the plurality of first isolation structures extend along a second direction and are arranged in the third direction; The first isolation structure spans the first trench and the second trench; The first isolation structure covers multiple word lines, and the first isolation structure is present between the first source / drain layers adjacent to each other in the third direction, and between the second source / drain layers adjacent to each other in the third direction; The first source / drain layer extends upward on the third party, and the second source / drain layer extends upward on the third party.

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